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Psoc® 6 MCU: Psoc 63 with BLE Datasheet Programmable System-On-Chip (Psoc®)

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Psoc® 6 MCU: Psoc 63 with BLE Datasheet Programmable System-On-Chip (Psoc®) PSoC® 6 MCU: PSoC 63 with BLE Datasheet Programmable System-on-Chip (PSoC®) General Description PSoC® is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with Arm® Cortex™ CPUs (single and multi-core). The PSoC 63 product family, based on an ultra low-power 40-nm platform, is a combi- nation of a dual-core microcontroller with low-power Flash technology and digital programmable logic, high-performance analog-to-digital and digital-to-analog conversion, low-power comparators, and standard communication and timing peripherals. The PSoC 63 family provides wireless connectivity with BLE 5.0 compliance. Features 32-bit Dual Core CPU Subsystem Low-Power 1.7-V to 3.6-V Operation ■ 150-MHz Arm Cortex-M4F CPU with single-cycle multiply ■ Active, Low-power Active, Sleep, Low-power Sleep, Deep (Floating Point and Memory Protection Unit) Sleep, and Hibernate modes for fine-grained power ■ 100-MHz Cortex M0+ CPU with single-cycle multiply and MPU. management ■ User-selectable core logic operation at either 1.1 V or 0.9 V ■ Deep Sleep mode current with 64-KB SRAM retention is 7 µA ■ Inter-processor communication supported in hardware with 3.3-V external supply and internal buck ■ ■ 8 KB 4-way set-associative Instruction Caches for the M4 and On-chip Single-In Multiple Out (SIMO) DC-DC Buck converter, M0+ CPUs respectively <1 µA quiescent current ■ ■ Active CPU power consumption slope with 1.1-V core operation Backup domain with 64 bytes of memory and Real-Time-Clock for the Cortex M4 is 40 µA/MHz and 20 µA/MHz for the Cortex Flexible Clocking Options M0+, both at 3.3-V chip supply voltage with the internal buck regulator ■ On-chip crystal oscillators (High-speed, 4 to 33 MHz, and ■ Active CPU power consumption slope with 0.9-V core operation Watch crystal, 32 kHz) for the Cortex M4 is 22 µA/MHz and 15 µA/MHz for the Cortex ■ Phase Locked Loop (PLL) for multiplying clock frequencies M0+, both at 3.3-V chip supply voltage with the internal buck regulator ■ 8 MHz Internal Main Oscillator (IMO) with 2% accuracy ■ Two DMA controllers with 16 channels each ■ Ultra low-power 32 kHz Internal Low-speed Oscillator (ILO) Flash Memory Sub-system with ±10% accuracy ■ 1 MB Application Flash with 32-KB EEPROM area and 32-KB ■ Frequency Locked Loop (FLL) for multiplying IMO frequency Secure Flash ■ 128-bit wide Flash accesses reduce power Serial Communication ■ SRAM with Selectable Retention Granularity ■ Nine independent run-time reconfigurable serial communi- ■ 288-KB integrated SRAM cation blocks (SCBs), each is software configurable as I2C, ■ 32-KB retention boundaries (can retain 32 KB to 288 KB in SPI, or UART 32-KB increments) Timing and Pulse-Width Modulation ■ One-Time-Programmable (OTP) E-Fuse memory for validation and security ■ Thirty-two Timer/Counter Pulse-Width Modulator (TCPWM) blocks Bluetooth Low Energy (Bluetooth Smart) BT 5.0 Subsystem ■ Center-aligned, Edge, and Pseudo-random modes ■ 2.4-GHz RF transceiver with 50- antenna drive ■ Comparator-based triggering of Kill signals ■ Digital PHY Up to 78 Programmable GPIOs ■ Link Layer engine supporting master and slave modes ■ Programmable output power: up to 4 dBm ■ Drive modes, strengths, and slew rates are programmable ■ RX sensitivity: –95 dBm ■ Six overvoltage tolerant (OVT) pins ■ RSSI: 4-dB resolution ■ 5.7 mA TX (0 dBm) and 6.7 mA RX (2 Mbps) current with 3.3-V Packages battery and internal SIMO Buck converter ■ 116-BGA and 104-MCSP packages with PSoC 6 and BLE ■ Link Layer engine supports four connections simultaneously Radio ■ Supports 2 Mbps LE data rate Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 002-18787 Rev. *G Revised July 17, 2018 PSoC® 6 MCU: PSoC 63 with BLE Datasheet Audio Subsystem Energy Profiler ■ I2S Interface; up to 192 kilosamples (ksps) Word Clock ■ Block that provides history of time spent in different power ■ Two PDM channels for stereo digital microphones modes ■ Allows software energy profiling to observe and optimize QSPI Interface energy consumption ■ Execute-In-Place (XIP) from external Quad SPI Flash ■ On-the-fly encryption and decryption PSoC Creator Design Environment ■ ■ 4-KB QSPI cache for greater XIP performance with lower power Integrated Development Environment provides schematic design entry and build (with analog and digital automatic ■ Supports 1, 2, 4, and Dual-Quad interfaces routing) and code development and debugging Programmable Analog ■ Applications Programming Interface (API Component) for all fixed-function and programmable peripherals ■ 12-bit 1 Msps SAR ADC with differential and single-ended modes and Sequencer with signal averaging ■ Bluetooth Smart Component (BLE4.2 compliant protocol stack) with Application level function calls and Profiles ■ One 12-bit voltage mode DAC with < 5-µs settling time ■ Two opamps with low-power operation modes Industry-Standard Tool Compatibility ■ Two low-power comparators that operate in Deep Sleep and ■ After schematic entry, development can be done with Hibernate modes. Arm-based industry-standard development tools ■ Built-in temp sensor connected to ADC ■ Configure in PSoC Creator and export to Arm/Keil or IAR IDEs for code development and debugging Programmable Digital ■ Supports industry standard Arm Trace Emulation Trace Module ■ 12 programmable logic blocks, each with 8 Macrocells and an 8-bit data path (called universal digital blocks or UDBs) Security Built into Platform Architecture ■ Usable as drag-and-drop Boolean primitives (gates, registers), ■ or as Verilog programmable blocks Multi-faceted secure architecture based on ROM-based root of trust ■ Cypress-provided peripheral component library using UDBs to implement functions such as Communication peripherals (for ■ Secure Boot uninterruptible until system protection attributes example, LIN, UART, SPI, I2C, S/PDIF and other protocols), are established Waveform Generators, Pseudo-Random Sequence (PRS) ■ generation, and many other functions. Authentication during boot using hardware hashing ■ Smart I/O (Programmable I/O) blocks enable Boolean ■ Step-wise authentication of execution images operations on signals coming from, and going to, GPIO pins ■ Secure execution of code in execute-only mode for protected ■ Two ports with Smart_IO blocks, capability are provided; these routines are available during Deep Sleep ■ All Debug and Test ingress paths can be disabled Capacitive Sensing ■ Cypress Capacitive Sigma-Delta (CSD) provides best-in-class Cryptography Accelerators SNR, liquid tolerance, and proximity sensing ■ Hardware acceleration for Symmetric and Asymmetric ■ Mutual Capacitance sensing (Cypress CSX) with dynamic cryptographic methods (AES, 3DES, RSA, and ECC) and Hash usage of both Self and Mutual sensing functions (SHA-512, SHA-256) ■ Wake on Touch with very low current ■ True Random Number Generator (TRNG) function ■ Cypress-supplied software component makes capacitive sensing design fast and easy ■ Automatic hardware tuning (SmartSense™) Document Number: 002-18787 Rev. *G Page 2 of 63 PSoC® 6 MCU: PSoC 63 with BLE Datasheet More Information Cypress provides a wealth of data at www.cypress.com to help you select the right PSoC device and quickly and effectively integrate it into your design. The following is an abbreviated list of resources for PSoC 6 MCU: ■ Overview: PSoC Portfolio, PSoC Roadmap ■ Code Examples provides PSoC Creator example projects for different product features and usage. ■ Product Selectors: PSoC 6 MCU Page ■ Technical Reference Manuals (TRMs) provide detailed ■ Application Notes cover a broad range of topics, from basic descriptions of PSoC 6 MCU architecture and registers. to advanced level, and include the following: ❐ AN210781: Getting Started with PSoC 6 MCU BLE ■ Development Tools ❐ AN218241: PSoC 6 MCU Hardware Design Considerations ❐ CY8CKIT-062-Wi-Fi-/BT supports the PSoC 62 series MCU ❐ AN213924: PSoC 6 MCU Bootloader Guide with WiFi and Bluetooth connectivity. ❐ AN215656: PSoC 6 MCU Dual-Core CPU System Design ❐ CY8CKIT-062-BLE supports the PSoC 63 series MCU with Bluetooth Low-Energy (BLE) connectivity. ❐ AN219434: Importing PSoC Creator Code into an IDE ❐ AN219528: PSoC 6 MCU Power Reduction Techniques ■ Training Videos: Visit www.cypress.com/training for a wide ❐ AN221111: PSoC 6 MCU: Creating a Secure System variety of video training resources on PSoC Creator PSoC Creator PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables you to design hardware and firmware systems concurrently, based on PSoC 6 MCU. As shown below, with PSoC Creator, you can: 1. Explore the library of 200+ Components in PSoC Creator 4. Co-design your application firmware and hardware in the 2. Drag and drop Component icons to complete your hardware PSoC Creator IDE or build project for 3rd party IDE system design in the main design workspace 5. Prototype your solution with the PSoC 6 Pioneer Kits.If a 3. Configure Components using the Component Configuration design change is needed, PSoC Creator and Components Tools and the Component datasheets enable you to make changes on the fly without the need for hardware revisions. Figure 1. PSoC Creator Schematic Entry and Components Document Number: 002-18787 Rev. *G Page 3 of 63 PSoC® 6 MCU: PSoC 63 with BLE Datasheet Contents Blocks and Functionality ................................................. 5 Analog Peripherals.................................................... 31 Functional Definition.......................................................
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