Field-Programmable Soc Devices Programmable Logic Design Fall 2001 By: Maziar Gudarzi

1st Edition

Fall 2001

Field-Programmable SoC Devices Programmable Logic Design Fall 2001 By: Maziar Gudarzi

Triscend E5 CSoC Figure PSoC-2

Notes Triscend has been the pioneer in commercially providing Programmable SoC devices. First introduced in 1999, E5 chips are equipped with industry-standard 8032-compatible processor; and hence, ideal for control-dominated applications. Other features include: • Performance accelerated 8051 microcontroller core (10 MIPS at 40 MHz) • Binary and source code compatible with other 8051 variants • Standalone operation from a single external memory (code + configuration) • Up to 64Kbytes of on-chip, dedicated system RAM • Up to 3200 Configurable System Logic (CSL) cells (up to 40,000 "ASIC" gates) • Power-down and power-management modes (low power mode consumption under 100 µA) • Compliant to the "CSI Socket" interface, allowing soft peripherals to be used on other CSoC Families • Two dedicated DMA Channels • On-chip breakpoint unit provides sophisticated debugging capability • Offers real-time debugging for hw-sw co-verification

The E5 CSoC Device Family and Availability Device CSL Cells* System RAM User I/O Packages Samples TE502 256 8Kx8 92 128LQFP Production TE505 512 16Kx8 124 128LQFP, 208QFP Production TE512 1152 32Kx8 188 128LQFP, 208QFP Production TE520 2048 40Kx8 252 208QFP, 484BGA Production

Triscend A7 CSoC Figure PSoC-3

Notes Industry’s first 32-bit Programmable SoC device, is based on ARM7TDMI RISC processor. Other features: • High-performance, 32-bit ARM7TDMI™ Processor Core • Memory Interface Unit o Flexible, glue-less interface to external memories (ROM, EEPROM, FLASH, SRAM, and SDRAM) o 8-bit, 16-bit and 32-bit support o Up to 2 external SDRAM banks o Automatic support for self-refresh, auto-refresh and initialization of SDRAM • 4-channel DMA controller • In-system debug/breakpoint unit • Power-down and power-management modes • CSL cells can be configured as memory, including true dual-port operation The A7 CSoC Device Family Device CSL Cells* PIO Packages TA7S05 512 123 208QFP, 324BGA TA7S12 1152 187 208QFP, 324BGA TA7S20 2048 252 208QFP, 324BGA TA7S32 3200 316 208QFP, 324BGA

Atmel FPSLIC Figure PSoC-4

Notes Introduced in 1999, as Triscend E5, is equipped with Atmel’s own 20 MIPS, 8-bit RISC processor. FPSLIC Secure (AT94S) chips integrate configuration memory in the programmable SoC device to provide more security. Software tool provides hw-sw co-simulation capability.

SIDSA FIPSOC Figure PSoC-5

Notes An Spanish company, conducting various research projects in this field, specially on EDA tools for programmable SoC. Each member of the FIPSOC product family features: • Single Chip Programmable Analog, Digital & 8051: • Each analog block consists of o 4 differential analog channels each with 3 OpAmps with programmable gain (up to 65dB), offset and CMRR (max 70dB). o 4 comparators with programmable references. • The conversion block consists of 4 DACs (configured as 8 to 10 bits) which via successive approximation can be independently configured as ADCs up to 800 k samples/s. • Programmable digital logic, up to 40MHz, 5ns LUT to LUT delay, RAM based high granularity FPGA. • 8051 uC core, 6k embedded RAM for data and program, 48MHz clock, 2MHz instruction rate. • Optimized internal interface between 8051 and analog & digital blocks.

Cypress PSoC Figure PSoC-6

Notes Based on Cypress’s own 8-bit processor, main advantage is availability of several analog blocks and MAC (Multiply and Accumulate) modules on chip.

Key Features 8C25122A 8C26233A 8C26443A 8C26643A Operating Frequency 93.7kHz - 24MHz 93.7kHz - 24MHz 93.7kHz - 24MHz 93.7kHz - 24MHz Operating Voltage 3.0 - 5.5V 3.0 - 5.5V 3.0 - 5.5V 3.0 - 5.5V Program Memory (kilobytes) 4 8 16 16 Data Memory (Bytes) 128 256 256 256 Digital PSoC Blocks 8 8 8 8 Analog PSoC Blocks 12 12 12 12 I/O Pins 6 16 24 40/44 External Switch Mode Pump No Yes Yes Yes Available Packages 8 PDIP 20 PDIP 28 PDIP 48 PDIP 20 SOIC 28 SOIC 48 SSOP 20 SSOP 28 SSOP 44 TQFP

QuickLogic QuickMIPS Figure PSoC-7

- Based on well-known 32-bit MIPS RISC processor - Processor core runs at 133 to 175MHz, when built in 0.25 and 0.15 micron processes respectively - The FPGA block (called “High-performance programmable fabric” by QuickLogic) offers more than 400,000 gates, consisting of - 2000 logic cells - 83 Kbits of dual-port SRAM - 18 Embedded Computational Unit (ECU) - Contains Configurable Logic Analysis Module (CLAM™) functioning as on-chip logic analyzer to debug hardware implemented on the FPGA part

Notes

Altera Excalibur Figure Nios Family PSoC-8

Notes

Soft-core processor is embedded on an Apex20K FPGA, taking only 2% (according to Altera announcements) of the FPGA logic capacity.

Compiler is GNUPro C compiler, and Quartus is used to design and implement the hardware portion.

Altera Excalibur Figure ARM-Based Family PSoC-9

Notes

• This family of devices is announced, but not yet available. • Industry-standard ARM922T 32-bit RISC processor core operating at up to 200 MHz o Memory management unit (MMU) included • Builds upon features of the APEX 20KE family of PLDs, with up to 1,000,000 gates o Harvard cache architecture with separate 8-Kbyte instruction and 8- Kbyte data caches o Internal single-port SRAM up to 256 Kbytes - Internal dual-port SRAM up to 128 Kbytes o External SDRAM 133-MHz data rate (PC133) interface up to 512 Mbytes External dual data rate (DDR) 266-MHz data rate (PC266) interface up to 512 Mbytes o External flash memory in 4 banks of up to 32 Mbytes each o Several on-chip peripherals including ETM9 embedded trace module, interrupt controller, UART, timer, and watchdog timer

Xilinx Figure Virtex II-PowerPC Based PSoC-10

- Joint work from IBM and Xilinx - Embeds IBM PowerPC processor cores in Xilinx Virtex II FPGAs - First chips will be manufactured in IBM fabs for Xilinx, to use IBM advanced manufacturing technology including copper wires.

Notes