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(12) United States Patent (10) Patent No.: US 6,480,952 B2 Gorishek, IV Et Al

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(12) United States Patent (10) Patent No.: US 6,480,952 B2 Gorishek, IV Et Al USOO648.0952B2 (12) United States Patent (10) Patent No.: US 6,480,952 B2 Gorishek, IV et al. (45) Date of Patent: Nov. 12, 2002 (54) EMULATION COPROCESSOR EP O 455 345 11/1991 EP O 617 376 9/1994 (75) Inventors: Frank J. Gorishek, IV; Charles R. EP O 671 685 A2 2/1995 EP O 817 O96 1/1998 Boswell, Jr., both of Austin, TX (US) GB 2 278 214 11/1994 (73) Assignee: Advanced Micro Devices, Inc., WO 93/16437 8/1993 Sunnyvale, CA (US) OTHER PUBLICATIONS Notice: Subject to any disclaimer, the term of this BYTE Magazine, “Why the 615 Matters", Linley Gwennap, patent is extended or adjusted under 35 1995, pp. 198-200. U.S.C. 154(b) by 0 days. BYTE Magazine, “An Alpha in PC Clothing”, Tom Thomp son, Feb. 1996, pp. 1-6. (21) Appl. No.: 09/085,187 BYTE Magazine, “Alpha Learns to Do Windows', Selinda (22) Filed: May 26, 1998 Chiquoine, Oct. 1996, pp. 1-3. (65) Prior Publication Data (List continued on next page.) Primary Examiner Daniel H. Pan US 2002/0013892 A1 Jan. 31, 2002 (74) Attorney, Agent, or Firm-Conley, Rose & Tayon, PC; (51) Int. Cl............................ G06F 9/455; G06F 9/54; Lawrence J. Merkel G06F 13/38 (52) U.S. Cl. ......................... 712/227; 712/36; 712/209; (57) ABSTRACT 703/26; 703/27; 709/319; 709/328 A computer System employing a host processor and an (58) Field of Search .......................... 712/41, 208, 233, emulation coprocessor. The host processor includes hard 712/23, 36, 31, 209, 212, 34, 227; 711/119, ware configured to execute instructions defined by a host 121-143, 146; 709/208,330, 329, 328, instruction Set architecture, while the emulation coprocessor 319; 710/127, 128, 129, 101, 137, 130, includes hardware configured to execute instructions defined 5,55, 131, 150; 703/23, 26, 27, 29; 361/183; by a different instruction set architecture from the host 717/5 instruction set architecture (“the foreign instruction set architecture”). The host processor core executes operating (56) References Cited System code as well as application programs which are U.S. PATENT DOCUMENTS coded in the host instruction Set architecture. Upon initiation of a foreign application program, the host processor core 4,799,150 A 1/1989 Bui ............................ 710/130 4.954,949 A 9/1990 Rubin ........................ 710/101 communicates with the emulation coprocessor core to cause 5,077,657 A 12/1991 Cooper et al. ................ 703/26 the emulation coprocessor core to execute the foreign appli 5,574,927. A 11/1996 Scantlin ....................... 71.2/41 cation program. Accordingly, application programs coded 5,638,525 A 6/1997 Hammond et al. ... 712/209 according to the foreign instruction Set architecture can be 5,659,709 A 8/1997 Quach .............. ... 711/146 executed directly in hardware. The computer System may be 5,666,519 A * 9/1997 Hayden ....................... 703/23 characterized as a heterogeneous multiprocessing System. 5,717,898 A 2/1998 Kagan et al. .. ... 711/145 While the emulation coprocessor is executing the foreign 5,764,934. A 6/1998 Fisch et al. ................. 710/129 application program, the host processor may execute oper (List continued on next page.) ating System routines unrelated to the foreign application program or may execute a host application program. FOREIGN PATENT DOCUMENTS EP O 230 353 7/1987 20 Claims, 15 Drawing Sheets as HostProcessor Registers? Core 43 E. Registers Coprocessor Core E. Fyne || Fun Fun. E. F. Fr. Fyn. | A-6.Fetch A DecodeA 30 N-7AFetch Decode . 20. ; - - - - - - aka -- am -w- - - Al--------| - - - - - w y Instruction Cache Cache 44 Data Cache (DCache) 48 Memory Management Unit (MMU) 42 Busterface Unit 40 Backside 2 34 Enterface to L2Cache 38 US 6,480,952 B2 Page 2 U.S. PATENT DOCUMENTS Readwx86, “Win32 x86 Emulation on Risc (Wx86)”, pp.2. 5,802,373 A * 9/1998 Yates et al. .................... 717/5 AMD Tech Law “Intel Reveals how Merced with be 5,819,105 A 10/1998 Moriarty et al. ............... 710/5 x86-Compatible”, Alexander Wolfe, Santa Clara, CA, May 5,802,577 A 6/1999 Bhat et al. ..... ... 711/146 8, 1998, pp. 2. 5,909,559 A 6/1999 So ............ ... 710/127 5,923,892 A 7/1999 Levy ........................... 712/31 AMD, “AMD5, 86 TM Processor”, Technical Reference 5,925,123 A 7/1999 Tremblay et al. ........... 712/212 Manual, Chpts. 1 & 2, pp. 1-1 to 1-3 and 2-1 to 2-12. 6,026,238 A 2/2000 Bond et al. ................. 709/528 “Press Release”, Undated: Jun. 25, 1997, downloaded from: 6,275,938 B1 8/2001 Bond et al. ................. 713/200 digital.com/info/PROOUM and www.zdnet.com/cshopper/ 6,308.255 B1 10/2001 Gorisheck, IV, et al. ... 712/209 content/9704/cshp0039.html on Dec. 11, 1997, (7 sheets). OTHER PUBLICATIONS Digital, “Digital FX32”, Updated: Sep. 26, 1997, down Microsoft Windows NT Workstation, “Windows(r) x86 loaded from digital.com/semiconductor/amt/fx32/fx Technology Preview”, Microsoft Corporation, 1997, pp. 1. white.html on Jan. 26, 1998, pp. 1-4. AMD, “AMD-K6 Processor Data Sheet”, Chpt. 1 & 2, Mar. Orange Micro, Inc., “Product Information', downloaded 1998, pp. 1–20. from orangemicro.com.page2.html on Aug. 4, 1998, (6 Digital Equipment Corp., Maynard Massachusetts, “Digital sheets). Semiconductor 21172 Core Logic Chipset, Technical Ref erence Manual, Apr. 1996, pp. 1-1 to 1-7. * cited by examiner U.S. Patent Nov. 12, 2002 Sheet 2 of 15 US 6,480,952 B2 66 HOSt PrOCeSSOr Core 48 FunC. FunC. FunC. FunC, FunC. FunC. Unit Unit Unit Unit Unit Unit 62C 62B 62A 72C 72B 72A 64 Fetch/DeCode 70 Instruction Cache (Cache) 44 Data Cache (DCache) 4 Memory Management Unit (MMU) 42 BuS Interface Unit 40 Backside L2 CPUBUS 34 Interface 52 - to L2 Cache 38 FIG 2 U.S. Patent Nov. 12, 2002 Sheet 4 of 15 US 6,480,952 B2 Begin: Create PrOCeSS 100 Examine File Format 102 -YeS Host Code? 104 NO Execute PrOCeSS On 106 HOSt PrOCeSSOr / Foreign COde Executable by Emulation Coprocessor? 108 Invoke Emulation Coprocessor Interface Code Display Unsupported Application MeSSage End: Create PrOCeSS FIG. 4 U.S. Patent Nov. 12, 2002 Sheet 5 of 15 US 6,480,952 B2 Begin: Invoke Emulation Interface 120 Establish PrOCeSS Context and Start Emulation Coprocessor 122 Transition to HOSt COde Detected? NO YeS 128 PrOCeSS Exit NO Detected? 124 Collect Context Information and Call Yes HOSt COde 130 126 Send Destroy Process Message to O/S Provide Context Information Upon Exit of Host Code End: Invoke Emulation interface a FIG. 5 U.S. Patent US 6,480,952 B2 U.S. Patent Nov. 12, 2002 Sheet 7 of 15 US 6,480,952 B2 L2 Cache 38 to Bus Bridge 12 FIG. 7 U.S. Patent Nov. 12, 2002 Sheet 8 of 15 US 6,480,952 B2 Start: Request Received 160 HOst Yes PrOCeSSOr Request? Emulation No (Emulation Yes Interface Coprocessor Request) Command? Route Request to 164 168 Emulation RouteRequest to HOSt PrOCeSSOr Coprocessor mulation Interface Yes No Command? NO 172 Host NO Processor Fulfill Yes Request? 166 174 ROute Data to RouteRequest to Emulation CPUBUS 34 CoproceSSOr End: Request Received FIG. 8 U.S. Patent Nov. 12, 2002 Sheet 9 of 15 US 6,480,952 B2 ZG|JOSS000ICH|SOH |-----———) U.S. Patent US 6,480,952 B2 U.S. Patent US 6,480,952 B2 79 U.S. Patent US 6,480,952 B2 9SnOW U.S. Patent Nov. 12, 2002 Sheet 13 of 15 US 6,480,952 B2 to/from PCI BuS 24 PC Interface Emulation Coprocessor 15 FIG. 13 U.S. Patent Nov. 12, 2002 Sheet 14 of 15 US 6,480,952 B2 970Z OZOZ 0903 O96ed |06ed EZOZ 0902 E900 |SS900): O96ed |96ed OVOZ WWOZ WZOZ 8900 0903 0SS90OJE O96ed |96ed Z?fied ?SITSS900)); U.S. Patent Nov. 12, 2002 Sheet 15 of 15 US 6,480,952 B2 Do Nothing 230 222 u1 Predefined Illegal Op? NO Send Exception Message 246 Select Ready Task 240 Return to Selected Task US 6,480,952 B2 1 2 EMULATION COPROCESSOR computer System. Generally, an instruction Set architecture defines the instructions which execute upon the processors, BACKGROUND OF THE INVENTION as well as processor resources directly used by the instruc 1. Field of the Invention tions (such as registers, etc.). The application program is This invention is related to the field of processors for generally compiled into a Set of instructions defined by the computer Systems and, more particularly, to Supporting instruction Set architecture, and hence the operating System multiple instruction Set architectures within a computer does not insulate the application program from this feature System. of the computer System hardware. 2. Description of the Related Art AS described above, a computer System must Support a Computer Systems have become an important productiv large number of different types of application programs to be ity tool in many environments. Nearly all lines of work useful to a large base of customers. Processors employing benefit from a computer System to carry out many tasks newly developed instruction Set architectures face a daunt which are central to that work. For example, managerial ing task of enticing application developers to develop appli professionals use computer Systems for managing databases cations designed for the new instruction Set architecture. of busineSS-critical data, creating and managing documents, 15 However, without the application programs, the instruction etc. Engineering professionals use computer Systems for Set architecture and the processors designed therefor will researching, designing, and verifying products. Manufactur often achieve only limited market acceptance, at best.
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