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Central Processing Units for PLC Implementation in Virtex-4 FPGA

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Central Processing Units for PLC Implementation in Virtex-4 FPGA Preprints of the 18th IFAC World Congress Milano (Italy) August 28 - September 2, 2011 Central Processing Units for PLC implementation in Virtex-4 FPGA M. Chmiel*, J. Mocha**, E. Hrynkiewicz***, A. Milik**** Institute of Electronics, Silesian University of Technology, Gliwice * (e-mail: [email protected]), ** (e-mail:[email protected]) *** (e-mail:[email protected]), **** (e-mail:[email protected]) Abstract: The paper presents an approach to the design and construction of central processing units for programmable logic controllers implemented in a FPGA development platform. Presented units are optimised for minimum response- and throughput time. The CPU structure is based on bit-word architecture and two types of control data exchange methods: with handshaking – control data are passed through the two flip-flop units with acknowledgement; without handshaking – control data are passed through the dual port RAM. Third unit – simple one processor – built to compare with the above two. The paper presents specific timers/counters hardware construction solution. Additionally it presents implementation results which show how many FPGA circuit resources are used to implement presented units. Keywords: Programmable Logic Controller (PLC), Central Processing Unit, Throughput Time, Concurrent Programs, Field Programmable Logic Array (FPGA). independent tasks are often determined by their analogue or 1. INTRODUCTION binary nature, as well as process set of signals and control One of the main parameters (features) of Programmable conditions. This observation leads to the conclusion: bit-word Logic Controller (PLC) is scan time – execution time of one structure of PLC CPU well matches typical processed data. thousand control commands. Due to this fact designing and The CPU structure is oftentimes optimised for very fast logic construction of the CPU should have an architecture that operations and for execution of complicated arithmetic enables fast control program execution. It is a very important operation (including floating point). To benefit from task. The most of developed CPUs of PLCs delivered by described architecture both processors must work in parallel well-known manufacturers are constructed as multiprocessor as independent as possible. To make it possible, two units. Particular processor in such units executes the processors must be equipped with specific hardware and commissioned for it tasks. In this way one can obtain a unit, software solutions. which make possible concurrent operation of a few The most effective and natural approach to the problem of processors. For such CPU the main problem to solve is the task assignment is partitioning along the operation type (bit way of task assignment to particular processors and finding or word). The tasks operating on discrete input/outputs are a structure of CPU be able to execute of such task assigned in executed by a bit-processor (Getko, 1983). Nowadays such practice as it was shown by (Michel, 1990). The other processors may be implemented in programmable structures important problem inseparable from hardware are like CPLDs or FPGAs. It brings the positive effects in user programmatic tools. Those tools should enable easy and program execution time (the controller speed-up). On the efficient creation of control algorithm. The programming other hand a word-processor is built on the base of a standard toolbox should take benefits from all aspects of microprocessor or embedded microcontroller. It is used for multiprocessor unit. word data processing in control of analogue objects, numeric Apart from instruction execution time, the access time to data processing and operating system maintenance of the internal (markers, counters, timers), and external (inputs and PLC (networking, diagnostics, control loop) (Donandt, 1989; outputs) resources is a very important parameter. Another Aramaki et al., 1997). parameter which characterises PLC is throughput time. It is As it was mentioned above an efficient and most promising defined as the response time to the change of object signals. platform for control unit implementation is a platform based From the point of view of the object, this parameter is most on programmable logic devices. This platform may be based important, which describes the quality of control that is on Field Programmable Logic (FPL), especially Field directly derived from the central processing unit and Programmable Gate Arrays (FPGAs). System architects are programmatic toolbox (Chmiel, 2008). offered powerful tools which ensure acceptable financial and PLCs control mainly process of a binary nature. In some time outlays in comparison to effects. The FPL enables easy cases they are used for mixed control containing analogue prototyping, testing and evaluating different solutions. signals (Koo et al., 1998). There are a lot of objects where control can form independent tasks. The boundaries of Copyright by the 7860 International Federation of Automatic Control (IFAC) Preprints of the 18th IFAC World Congress Milano (Italy) August 28 - September 2, 2011 2. FPGA PLATFORM - HARWADRE AND SOFTWARE Programmer writes a program in form of instructions SOLUTION sequence. Compiler checks the syntax and splits the sequence of instructions into two streams. Those streams are later Large density FPGA devices offer a platform that enables compiled separately for each processor and written to the using different approaches to construct a PLC CPU. The CPU program memories of the particular processor. can be constructed from off the shelf CPU IP-Cores. It can be F F cores that are compatible with standard microprocessors or Bit b bB Byte Fb Procesor WRFbB RDFbB Procesor microcontrollers. An alternative is to design your own CPU Program Instruction FbB Instruction Program EMPTYF READYF TRF bB bB READ_FbB from the scratch. This can be designed to satisfy requirements Memory bB Memory of the application. Those requirements reflect on the Byte Procesor F F instruction set and interface operation. This approach is much bB B FB Standard RDFBb WRFBb Program more laborious but results seem to be more optimal. Instruction FBb Instruction READYF EMPTYF Memory TFBb Bb Bb WRITE_FBb The authors have decided to use a development board with Bit Bit Byte Byte Procesor Procesor a Xilinx Virtex-4 (Xilinx, 2006) to perform experiments. Data Processor Processor Data Virtex-4 logic resources are sufficient to implement and Memory Memory evaluate dedicated PLC CPU (processors and required Bit Byte peripherals) implemented in FPGA structures. It must be In/Out In/Out mentioned that implemented central processing units work in Modules Modules classical manner. The central processing unit executes instructions in serial-cyclic manner, in opposite to parallel Fig. 1. CPU with exchange flip-flop register block (Chmiel specific hardware processing of ladder diagram which is and Hrynkiewicz, 2008). possible in reconfigurable logic devices (Ichikawa et Bit Processor Exchange Memory Byte Processor al., 2006). RAM 1' RAM 1 In prior research works the comparison of basic structures were carried out (Chmiel et al., 2010). Three different Upadate memory Update memory state - UPDB structures were designed. VHDL hardware description state - UPD language was used for the design (Skahill, 2004). RAM 2 RAM 2' There following structures were evaluated: dual processor where one processor waits for the results Fig. 2. CPU with exchange memory (BlockRAM) (Chmiel et from the other; al., 2010). dual processor with fully asynchronous operation From the point of view of experiments, possibility of execution (no synchronisation between processors – no introducing new commands is very important. The process of waiting for each other); developing new commands influences the processor single processor executes bit and word instructions. hardware. This is because each new command means that new functionality must be modelled in a hardware description Ideas presented in (Chmiel and Hrynkiewicz, 2005; Chmiel et language. Finally the new structure has to be synthese and al., 2005) were used to build bit-word structure of CPU. implemented in the target architecture. Different ideas of concurrent execution of instructions, as well as the processor’s synchronisation mechanism based on The assembler program is able to process macros. Macros common data dependencies are presented in cited papers. The enable creating sequences of instructions that perform units with fully concurrent operating processors were used in specific operation (e.g. configuring I/O units or timer/counter experiments. Information between processors was exchanged units). Using macros simplified writing the programs and in two alternative ways: increase the level of abstraction. by means of flags written to the flip-flops equipped with 3. PROCESSORS STRUCTURES a handshake mechanism; one flag is written by each processor and made available for opposite one for reading For experimental and evaluation purposes, three structures of (Fig. 1); central processing unit have been designed, described in by means of exchange memory, which was implemented VHDL and finally implemented. Two dedicated processors in dual port RAM (Fig. 2). One side has full access to the have been designed: for bit operations and for word memory while opposite one is granted only reading. operations. The third processor has been developed as a general processor equipped with word and bit operations. It In order to exploit specific features of designed units, has not been equipped
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