Bit-Level Partial Evaluation of Synchronous Circuits Sarah Thompson Alan Mycroft Computer Laboratory Computer Laboratory University of Cambridge University of Cambridge
[email protected] [email protected] ABSTRACT Table 1: Rewrite Rules for Combinational PE Partial evaluation has been known for some time to be very effective when applied to software; in this paper we demonstrate that it can also be usefully applied to hard- a ∧ a → a a ∨ a → a ware. We present a bit-level algorithm that supports the a ∧ false → false a ∧ true → a partial evaluation of synchronous digital circuits. Full PE a ∨ false → a a ∨ true → true of combinational logic is noted to be equivalent to Boolean minimisation. A loop unrolling technique, supporting both ¬false → true ¬true → false partial and full unrolling, is described. Experimental results are given, showing that partial evaluation of a simple micro- processor against a ROM image is equivalent to compiling Section 3 this is extended to encompass loop unrolling of the ROM program directly into low level hardware. synchronous circuits. Section 4 introduces HarPE, the hard- ware description language and partial evaluator used to sup- 1. INTRODUCTION port the experimental work leading to the results described in Section 4. Partial evaluation [12, 14, 13] is a long-established tech- nique that, when applied to software, is known to be very powerful; apart from its usefulness in automatically creating 2. PE OF COMBINATIONIAL CIRCUITS (usually faster) specialised versions of generic programs, its The simplest form of hardware partial evaluation is al- ability to transform interpreters into compilers is particu- ready well known to hardware engineers, though under a larly noteworthy.