Intel-Based Electronic Classroom Student Computing Station Based on the Intel® Celeron™ Processor and Intel® 810 Chipset

Reference Configuration

August 2000

Order Number: 273292-002 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Celeron™ and Pentium® II processors, 810 Chipset, and 82559 ethernet controller may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

Copyright© Intel Corporation, 2000 *Other brands and names are the property of their respective owners.

Application Note Intel-Based Electronic Classroom Student Computing Station

Contents

1.0 Introduction ...... 5 1.1 Purpose ...... 5 1.2 Terminology...... 5 1.3 Revision History ...... 5 2.0 Intel-Based Electronic Classroom Environment Overview ...... 6

3.0 Intel-Based Electronic Classroom Setup and Operating Environment...... 7 3.1 Intel-Based Electronic Classroom Configuration...... 8 3.1.1 Network Environment ...... 8 3.1.2 Teacher Station Management System ...... 9 3.1.3 Multimedia Teaching Software ...... 9 3.1.4 Application Software...... 10 3.1.5 Remote Booting Intel-Based Electronic Classroom Student Computing Stations from Server ...... 10 4.0 Recommended Motherboard Configuration for Intel-Based Electronic Classroom Student Computing Stations...... 11

5.0 Design Consideration of Intel-Based Electronic Classroom Student Computing Station Hardware ...... 13 5.1 Intel® Celeron™ Processor ...... 13 5.1.1 Design Notes for the Intel® Celeron™ Processor ...... 13 5.2 Intel® 810 Chipset ...... 14 5.2.1 The Intel® 82810 Graphics Memory Controller Hub (GMCH0) ...... 15 5.2.1.1 Design Notes for the Intel® 82810 GMCH0...... 15 5.2.2 The Intel® 82801 I/O Controller Hub (ICH)...... 16 5.2.2.1 Design Notes for the Intel® 82801 ICH...... 16 5.3 IDE Connectors...... 17 5.4 AC’97 2.1 Compliant Components...... 17 5.4.1 Design Notes for AC’97 Devices ...... 18 5.5 Audio/Modem Riser Card (AMR)...... 18 5.5.1 Design Notes for the Audio/Modem Riser Card ...... 18 5.6 PCI ...... 19 5.7 Network Controller — Intel® 82559 Fast Ethernet Controller...... 19 5.7.1 Design Note for the Intel® 82559 Fast Ethernet Controller ...... 19 5.7.2 Wired for Management...... 21 5.7.2.1 Instrumentation...... 21 5.7.2.2 Remote Service Boot ...... 22 5.7.2.3 Remote Wake-Up...... 22 5.7.2.4 Power Management ...... 22 5.8 Low Pin Count (LPC) Interface...... 22 6.0 Conclusion...... 23

A References ...... 25 B Intel-Based Electronic Classroom Schematics ...... 27

Application Note 3 Intel-Based Electronic Classroom Student Computing Station

Figures

1 Typical Intel-Based Electronic Classroom Setup ...... 7 2 Building Block of the Intel-Based Electronic Classroom Student Computing Station Motherboard ...... 12 3 Topology for Single Processor Designs with Single End Termination (SET)...... 13 4 Placement of Termination Resistor ...... 20 5 Trace Geometry ...... 20 6 Cover Sheet Schematic ...... 28 7 Block Diagram...... 29 8 370-Pin Socket (Part 1)...... 30 9 370-Pin Socket (Part 2)...... 31 10 GTL Terminal Schematic ...... 32 11 Clock Synthesizer Schematic...... 33 12 82810, Part 1: Host Interface Schematic ...... 34 13 82810, Part 2: System Memory and Hub Interface Schematic ...... 35 14 82810, Part 3: Graphics Schematic ...... 36 15 System Memory Schematic ...... 37 16 82810AA, Part 1 Schematic ...... 38 17 82810AA, Part 2 Schematic ...... 39 18 Firmware Hub (FWH) Schematic ...... 40 19 Super I/O Schematic ...... 41 20 PCI Connector Schematic...... 42 21 ATA/33 IDE Connectors Schematic ...... 43 22 USB Connectors Schematic...... 44 23 Parallel Port Header Schematic ...... 45 24 Serial Port/Com Headers Schematic ...... 46 25 Keyboard/Mouse Ports, Floppy Disk Header, Game Post Header Schematic ... 47 26 Video Connectors Schematic...... 48 27 Audio Riser Schematic...... 49 28 LAN Schematic ...... 50 29 LAN Schematic ...... 51 30 Voltage Regulators...... 52 31 Processor Voltage Regulator Schematic ...... 53 32 System Schematic ...... 54 33 System: Power Connector and Reset Control Schematic...... 55 34 Pull-Up Resistors and Unused Gates Schematic...... 56 35 730-Pin Socket Decoupling Schematic ...... 57 36 DRAM, Chipset and Bulk Power Decoupling Schematic ...... 58 37 Revision History Schematic ...... 59 Tables

1 Intel-Based Electronic Classroom Hardware Descriptions and Recommended Configuration ...... 8 2 AC’97 Configuration Combinations ...... 17

4 Application Note Intel-Based Electronic Classroom Student Computing Station

1.0 Introduction

1.1 Purpose

This application note describes how Intel® architecture processors, chipsets, and other components can be used in designs for Intel-based electronic classroom student computing stations. An Intel-based electronic classroom is an educational setting in which a network of computers is used as a primary teaching, learning, and assessment tool. A typical Intel-based electronic classroom contains an instructor’s system that broadcasts application software to, and often receives data from, student computing stations. The student computing stations can be configured and administered at the server level.

Intel architecture components are well-suited for Intel-based electronic classroom systems. Using PC-based building blocks in these designs provides flexibility, upgradability, ease of administration, and high performance for graphic-intensive and internet applications. In addition, Intel architecture processors are compatible with a wide variety of operating system and off-the-shelf application software. This application note describes a typical Intel-based electronic classroom network and provides a reference design for Intel architecture-based electronic classroom student computing stations.

Schematics for the reference design are provided in Appendix B of this document.

1.2 Terminology

The following terms are used in this document.

Term Definition

Intel-Based An electronic teaching and learning environment that uses dedicated, connected student Electronic computing stations to implement a specific educational curriculum Classroom Remote boot A client operating system boot up from a server in a network environment TCO Total cost of ownership ISV Independent software vendor WfM Intel’s Wired for Management initiative

1.3 Revision History

Revision Date Notes

001 October 15, 1999 Initial version.

Application Note 5 Intel-Based Electronic Classroom Student Computing Station

2.0 Intel-Based Electronic Classroom Environment Overview

An Intel-based electronic classroom is a teaching and learning environment that uses a server-client system in the classroom to implement the curriculum. Teaching and learning is done using a teacher station, student computing stations, and specific educational software applications and content. With this modern educational technology, educators can deliver intuitive online courses, training, demonstrations, and examinations. They can also incorporate access to the Internet and intranet to enrich the educational experience.

An Intel-based electronic classroom LAN environment can consist of up to 60 student computing stations, a teacher station, and a network server. In an Intel-based electronic classroom, every student computing station is administered centrally. These student computing stations have high reliability and security, and low maintenance costs. The student computing stations have a subset of a PC feature set: they typically have a different motherboard configuration (described in Section 4.0) and are configured without a CD-ROM drive or hard disk. This solution provides a greater access to the necessary technology while simplifying maintenance and reducing the total cost of ownership.

In schools, PCs can be used in teacher offices as productivity tools for administration and development of teaching materials. These materials may then be used in Intel-based electronic classrooms to teach subjects such as computer skills, languages, sciences, and mathematics. The teacher uses the teacher station in the Intel-based electronic classroom to guide students through the lesson, while each student follows the lesson on his/her own student computing station. The students can also use their student computing stations independently to practice lesson materials and learn other application software.

Desirable features of Intel-based electronic classroom student computing stations include the following: • Ease of management and maintenance Primary and secondary schools typically do not have a full time Information Technology (IT) staff to manage the Intel-based electronic classroom. Most IT administration is done by teachers and student volunteers. Hence, the student computing stations used in the Intel-based electronic classroom must be easy to manage. Intel-based electronic classroom student computing stations can be configured without CD-ROM and floppy drives. This further simplifies the management of these student computing stations by preventing students from erasing files or corrupting the operating system and applications. • Low total cost of ownership (TCO) Schools have limited budgets for setting up Intel-based electronic classrooms. Therefore, a key consideration is affordability in terms of initial capital and ongoing maintenance costs, including the costs of off-the-shelf educational applications and teaching content. • Software availability and compatibility Establishing a productive Intel-based electronic classroom depends on the availability of system-compatible, off-the-shelf applications and teaching materials. It is important that schools have tools to develop customized content to meet the particular needs of their students. • Product life cycle support Schools use Intel-based electronic classroom student computing stations for several years before considering an upgrade. Therefore, replacement parts should be available for this duration.

6 Application Note Intel-Based Electronic Classroom Student Computing Station

3.0 Intel-Based Electronic Classroom Setup and Operating Environment

A typical Intel-based electronic classroom setup is depicted in Figure 1. Figure 1. Typical Intel-Based Electronic Classroom Setup

Home Internet PC

School Network

15 - 60 Student Computing Stations Server

Intel-Based Electronic Classroom Teacher Station

A7490-02

The student and teacher stations are linked together in a LAN environment via a network hub or switch device. The LAN network enables the remote boot for diskless student computing stations and file sharing among all the student computing stations. The broadcasting capability is implemented through software using the existing LAN infrastructure. This solution reduces overall system cost, simplifies wiring and upgrade requirements, and enables the use of higher performance processors.

The components of a typical Intel-based electronic classroom and their recommended configuration are described in Table 1.

Application Note 7 Intel-Based Electronic Classroom Student Computing Station

Table 1. Intel-Based Electronic Classroom Hardware Descriptions and Recommended Configuration

Quantity Item Recommended Configuration (units) Intel® Pentium® III processor, 64 -128 Mbyte SDRAM, Intel® 440BX AGPset, Hard-disk, Teacher Station 1 Intel® Network Card, Video Capture Card Student Computing Intel® Celeron™ processor 433 MHz or better (in 370-pin PPGA) and Intel® 810 chipset, 15 - 60 Station 32 Mbyte SDRAM, Intel Network Card integrated on board, Hard-disk (optional) Pentium III processor, 128 Mbyte SDRAM, Intel® L440GX motherboard, SCSI Hard-disk, Server 1 Intel Network Card Switch 1-3 Intel Express 510T, 24 10/100Mbit Switching Port Router 1 Intel Express 9500 Router for Internet connection Multimedia teaching From ISVs. Based on TCP/IP or IPX network protocol. Intel® LANSchool software site is a 1 Software basic reference: http://www.intel.com/network/products/lanschool.htm

3.1 Intel-Based Electronic Classroom Configuration

The configuration of the Intel-based electronic classroom depends on the size of the classroom, the network design, and the use of the multimedia broadcasting software. The following describes an example configuration that consists of five main parts: • Network environment • Teacher Station management system • Multimedia broadcasting software • Application and education software • Intel-based electronic classroom student computing stations that remote boot from server

The following sections describe each component of the example Intel-based electronic classroom.

3.1.1 Network Environment

The network can be set-up using Windows* NT 4.0 or Novell Netware* on the server. The teacher station and student computing stations run on Windows 95/98 operating systems. The Intel-based electronic classroom student computing stations boot up remotely from a server that is connected in a LAN environment.

8 Application Note Intel-Based Electronic Classroom Student Computing Station

3.1.2 Teacher Station Management System

The teacher station in this example can perform the following functions: • Broadcasting the teacher station screen All teaching materials, including presentation, animations, and movies can be broadcast to the student computing stations. • Controlling student computing stations remotely The teacher can control, reset, and lock the student computing stations or receive the display from a particular Intel-based electronic classroom student computing station. • Providing online help The teacher can provide help through the network when students have difficulty with their assignment. The students would also be able to request assistance through the network.

3.1.3 Multimedia Teaching Software

The multimedia teaching software utilizes a standard LAN network interface through TCP/IP protocol and typically offers the following features: • Screen broadcasting — Each computing station (teacher’s and student’s) can broadcast its screen to some or all students. Only one screen can be broadcast at a time. — The teacher can lock each student’s keyboard and mouse and can broadcast any student’s screen to the class. — All graphics formats, such as MPEG and VCD can be broadcast in real time. • Audio/voice communication — The teacher’s voice can be broadcast to one, several, or all students. — Conferencing is supported in teacher-student, student-student, or other combinations. — The voice can be input through MIC or Line In on the sound card. • Remote access — The teacher can view any student’s screen remotely. • Grouping — Student computing stations can be grouped in any combination for discussion (screen/audio). • Question — Students can submit questions through MIC or keyboard (using a special function key). — Two way or multi-way online questioning is supported, as in a “chat” mode. • Remote reset — The teacher can reset any or all Intel-based electronic classroom student computing stations if an error occurs in the system. • Examinations can be administered and completed online.

Application Note 9 Intel-Based Electronic Classroom Student Computing Station

3.1.4 Application Software

Typically, application software, such as word processing and spreadsheet programs, and instructor-developed materials are taught in Intel-based electronic classrooms. In some Intel-based electronic classrooms, students are assessed using on-line examinations.

3.1.5 Remote Booting Intel-Based Electronic Classroom Student Computing Stations from Server

During the remote boot process, the Intel-based electronic classroom student computing stations contact the server (using Preboot Execution Environment in the boot ROM of the network interface), install a boot image, and boot the operating system that is pre-configured on the server. Various operating systems can be remote booted from the server, including Windows 95/98 or Linux*.

The setup is optimized through the availability of the Preboot Execution Environment (PXE) compliant boot ROM. PXE allows the server to set up each student computing station with a specific IP address using the Dynamic Host Communication Protocol (DHCP). The boot ROM then downloads the boot image from the server using the Trivial File Transfer (TFT) protocol. This boot image program then configures the student computing stations and boots the pre-configured operating system. If the Intel-based electronic classroom student computing station’s operating system or applications are damaged, they can be recovered by downloading the new image from server when the system restarts. This reduces the total cost of maintenance. Refer to section Section 5.7.2.2, “Remote Service Boot” on page 22 for more information.

10 Application Note Intel-Based Electronic Classroom Student Computing Station

4.0 Recommended Motherboard Configuration for Intel-Based Electronic Classroom Student Computing Stations

The motherboard of this reference design for Intel-based electronic classroom student computing stations is a highly integrated design that incorporates many features on the board. It is recommended that system designers use an LPX form factor or Flex ATX design. The LPX form factor enables the student computing stations to have a very slim casing, which is desirable for small Intel-based electronic classroom environments. Flex ATX helps reduce board size and cost. The components listed below provide an example of a motherboard design based on the Celeron processor and Intel 810 chipset.

Main Components of Reference Motherboard for the Intel-Based Electronic Classroom Student Computing Station: • Intel® Celeron™ processor 300A/366/433 MHz in 370-pin PPGA • Intel® 810 Chipset • Two DIMM sockets that support up to 512 Mbyte (128 Mbit technology) SDRAM • Two IDE interfaces • One floppy disk interface • COM 1 and COM 2 serials ports and a parallel port • PS/2 mouse and keyboard connectors • Intel® Flash BIOS • Super I/O* and USB ports • 1 X PCI 2.2-compliant PCI slot

Peripherals on Intel-Based Electronic Classroom Student Computing Station:

Integrated audio in chipset • Audio Codec ’97 2.1 extensions compliant • Stereo line level output • One audio out, audio in, and MIC jack

Integrated Graphics • 3-D graphics with texturing and visual enhancements up to 1024x768x16 @85 Hz refresh • 2-D graphics up to 1600x1200x8 @85 Hz refresh • RGB output

PCI-based 10/100 Mbps Network card • Intel® 82559-based card recommended • One RJ-45 port • Boot ROM which contains Intel® Preboot Execution Environment (PXE)

Application Note 11 Intel-Based Electronic Classroom Student Computing Station

Figure 2. Building Block of the Intel-Based Electronic Classroom Student Computing Station Motherboard

Intel® Celeron™ Processor

System Bus [66 MHz] Intel® 810 Chipset

Display I/F Monitor SDRAM Memory 82810 100 MHz 241 BGA

GD82559

2 IDE Port/ Ultra AT A66 Intel Network Controller Support 10/100 Mbit One RJ-45 port SMBus One Flash boot ROM 82801AA

USB USB 241 BGA PCI 33 1 PCI REQ/GNT

Low Pin 82802AB Count Interface 4Mb

AC'97 Riser COM1 & COM 2 Serial Ports AC'97 2.1 Parallel Port Super IO* PS/2 Mouse Floppy Disk Interface Keyboard Connectors

A7493-01

12 Application Note Intel-Based Electronic Classroom Student Computing Station

5.0 Design Consideration of Intel-Based Electronic Classroom Student Computing Station Hardware

5.1 Intel® Celeron™ Processor

This reference configuration supports the Intel Celeron processor at 300, 366 MHz and 433 MHz inaPlasticPinGridArray(PPGA)package.

The Intel Celeron processor PPGA package implements a Dynamic Execution micro-architecture and executes MMX™ media technology instructions for enhanced media and communication performance. The Intel Celeron processor PPGA is based on the P6 family processor core and is provided in a PPGA package for use in low cost systems in the value PC and Intel-based electronic classroom student computing station market segments. The Intel Celeron processor PPGA utilizes the AGTL+ system bus used by the Pentium® II processor with support limited to single-processor systems. The Intel Celeron processor PPGA includes an integrated 128 Kbyte second level cache with separate 16 Kbyte instruction and 16 Kbyte data level-one caches. The second level cache is capable of caching 4 Gbytes of system memory.

5.1.1 Design Notes for the Intel® Celeron™ Processor

The schematics use a Single Ended Termination (SET) network topology in which the termination resistors are located at only the PPGA (processor) side to reduce the system cost, solution space, and ringing effect. In the SET topology, the termination should be placed close to the processor either on the motherboard or on the processor substrate. No termination is present at the chipset end of the network. Figure 3. Topology for Single Processor Designs with Single End Termination (SET)

VTT

L2†† Intel® 810 Chipset L1† 370-Pin Socket

† - 1.9"

A7494-01

Application Note 13 Intel-Based Electronic Classroom Student Computing Station

5.2 Intel® 810 Chipset

Intel has developed technology that enhances the performance and value of Intel Celeron processor-powered systems. Built on the strong foundation of Intel 440BX AGPset technology, the Intel 810 chipset provides next generation features and great graphics performance at a lower cost.

The Intel 810 chipset contains three core components: 1. Host Controller — Graphics and Memory Controller Hub (GMCH0) The GMCH0 (82810) provides the interconnect between the SDRAM and the rest of the system logic: — 421 Mini BGA — Integrated Graphics controller — 230 MHz RAMDAC — Support for Intel Celeron processors with a 66 MHz system bus. — 100 MHz SDRAM interface supporting 64/256/512 Mbyte with 16/64/128 Mbit SDRAM technology — Downstream hub interface for access to the ICH 2. I/O Controller Hub — 82810AA (ICH) The I/O Controller Hub provides the I/O subsystem with access to the rest of the system: — 421 Mini BGA — Upstream hub interface for access to the GMCH0 — PCI 2.2-compliant interface (6 PCI Req/Grant Pairs for 82801AA ICH) — Bus Master IDE controller; supports either Ultra ATA/33 or Ultra ATA/66 (82801AA) — USB controller — SMBus controller — FWH interface — LPC interface — AC’97 2.1 interface — Integrated System Management Controller — Alert-on-LAN (82801AA ICH only) — Interrupt controller 3. 82802 Firmware Hub (FWH) The 82802 FWH component is a key element to enabling a new security and manageability infrastructure for the PC platform. The device operates under the FWH interface and protocol. The hardware features of this device include: — An integrated hardware Random Number Generator (RNG) — Register-based locking — Hardware-based locking — 5GPIs

14 Application Note Intel-Based Electronic Classroom Student Computing Station

5.2.1 The Intel® 82810 Graphics Memory Controller Hub (GMCH0)

The Intel 810 chipset provides a rich and robust 2-D and 3-D graphics using an integrated chipset design that utilizes second-generation graphics technology. At the core of the 810 chipset is a memory controller with built-in graphics technology. The Intel 810 chip optimizes system memory arbitration, similar to AGP technology, resulting in a more responsive and cost-effective system.

The 82810 Graphics Memory Controller Hub (GMCH0) features Intel graphics technology and software drivers and uses Direct AGP (integrated AGP) to create vivid 2-D and 3-D effects and images. The 82810 chip features integrated Hardware Motion Compensation to improve soft DVD video quality and a digital video out port that enables connection to traditional TVs or the new space-saving digital flat panel displays.

Intel Dynamic Video Memory Technology (DVMT) is an architecture that offers breakthrough performance for the Value PC segment through efficient memory utilization and Direct AGP. The system OS uses the Intel software drivers and intelligent memory arbiter to support richer graphics applications.

The System Manageability Bus allows networking equipment to monitor the 810-chipset platform. Using ACPI specifications, the system manageability function enables low-power sleep mode and conserves energy when the system is idle.

5.2.1.1 Design Notes for the Intel® 82810 GMCH0

The GMCH ball assignment and ICH ball assignment have been optimized to simplify hub interface routing. It is recommended that the hub interface signals are routed directly from the GMCH0 to the ICH on the top signal layer. The hub interface has two signal groups: • Data Signals: HL[10:0] • Strobe Signals: HL_STB, HL_STB# (differential strobe pair)

There are no pull-ups or pull-downs required on the hub interface.

Hub interface data signals should be routed with a trace width of 5 mils and a trace spacing of 20 mils. These signals can be routed with a trace width of 5 mils and a trace spacing of 15 mils for navigation around components or mounting holes. To break out of the GMCH0 and the ICH, the hub interface data signals can be routed with a trace width of 5 mils and a trace spacing of 5 mils. The signals should be separated to a trace width of 5 mils and a trace spacing of 20 mils within 0.3” of the GMCH0/ICH components. The maximum trace length for the hub interface data signals is 7”. These signals should each be matched within ±0.1” of the HL_STB and HL_STB# signals.

Due to their differential nature, the hub interface strobe signals should be 5 mils wide and routed 20 mils apart. This strobe pair should be a minimum of 20 mils from any adjacent signals. The maximum length for the strobe signals is 7” and the two strobes should be the same length. Additionally, the trace length for each data signal should be matched to the trace length of the strobes with ±0.1”.

HREF is the hub interface reference voltage. It is 0.5 * 1.8 V = 0.9 V ±2%. It can be generated locally, or a single HREF divider can be used. Each divider consists of a DC element and an AC element. The resistors in the DC element should be equal in value and rated at 1% tolerance. The value of these resistors must be chosen to ensure that the reference voltage tolerance is maintained over the entire input leakage specification. The resistors in the AC element of the resistor divider should be no greater than 80 Ω and the capacitors should be 500 pF. Additionally, the reference voltage should be bypassed to ground at each component with a 0.1 uF capacitor.

Application Note 15 Intel-Based Electronic Classroom Student Computing Station

5.2.2 The Intel® 82801 I/O Controller Hub (ICH)

The 82801 I/O Controller Hub (ICH) employs the Intel Accelerated Hub Architecture to make a direct connection from the graphics and memory to the integrated AC97 controller, the IDE controllers, dual USB ports, and PCI add-in cards.

The Accelerated Hub Architecture provides twice the bandwidth of the PCI bus at 266 MB per second. This allows a wider flow of rich information from the I/O controller to the memory controller, with optimized arbitration rules allowing more functions to run concurrently, enabling more life-like audio and video.

The Integrated Audio-Codec 97 controller enables software audio and modem by using the processor to run sound and modem software. By reusing existing system resources, this feature adds flexibility, improves sound quality, and lowers the system BOM cost by eliminating components.

The 82802 Firmware Hub (FWH) stores system BIOS and video BIOS, eliminating a redundant nonvolatile memory component. In addition, the 82802 contains a hardware Random Number Generator (RNG). The Intel RNG provides truly random numbers to enable fundamental security building blocks supporting stronger encryption, digital signing, and security protocols.

5.2.2.1 Design Notes for the Intel® 82801 ICH

• ICH Placement: The ICH should be placed within 8” of the ATA connector(s). There are no minimum length requirements for this spacing. • Capacitance: The capacitance of each pin of the IDE connector on the host should be below 25 pF when the cables are disconnected from the host. • Series Termination: There is no need for series termination resistors on the data and control signals since series termination is integrated into these signal lines on the ICH. • A1KΩ pull-up to 5 V is required on PIORDY and SIORDY. • A 470 Ω pull-down resistor is required on pin 28 of each connector. • A5.6KΩ pull-down resistor is required on PDREQ and SDREQ. • Support Cable Select (CSEL) is a PC99 requirement. The state of the cable select pin determines the master/slave configuration of the hard drive at the end of the cable. • Primary IDE connector uses IRQ14 and the secondary IDE connector uses IRQ15. Ω • IRQ14andIRQ15eachneedan8.2K pull-up resistor to VCC. • Due to the elimination of the ISA bus from the ICH, PCI_RST# should be connected to pin 1 of the IDE connectors as the IDE reset signal. Due to high loading, the PCI_RST# signal should be buffered. • There is no internal pull up or down on PDD7 or SDD7 of the ICH. Devices should not have a pull-up resistor on DD7. It is recommended that a host have a 10 KΩ pull-down resistor on PDD7 and SDD7 to allow the host to recognize the absence of a device at power-up (as required by the ATA-4 specification). • If no IDE is implemented with the ICH, the input signals (xDREQ and xIORDY) can be grounded and the output signals left as no connects.

16 Application Note Intel-Based Electronic Classroom Student Computing Station

5.3 IDE Connectors

The 82801AA ICH supports Ultra ATA/66 and ATA/33 devices The ATA/66 cable is an 80-conductor cable; however the 40-pin connectors used on motherboards for 40-conductor cables do not change as a result of this new cable. The wires in the cable alternate: ground, signal, ground, signal, etc. All the ground wires are tied together at the connectors on the cable (and they are tied to the ground on the motherboard through the ground pins in the 40-pin connector). This cable conforms to the Small Form Factor Specification SFF-8049. This specification can be obtained from the Small Form Factor Committee. To determine if ATA/66 mode can be enabled, the Intel 810 chipset using the ICH requires the system BIOS to attempt to determine the cable type used in the system.

If only one IDE is implemented with the ICH, the input signals (xDREQ and xIORDY) can be grounded and the output signals left as no connects. This can be implemented to reduce the board space and cost.

5.4 AC’97 2.1 Compliant Components

The ICH implements an Audio Codec '97 (AC’97) 2.1 compliant digital controller. Any codec attached to the ICH AC-link should also be AC’97 2.1 compliant. Contact your preferred codec vendor for information on AC’97 2.1 compliant products. The AC’97 2.1 specification is available on the Intel web-site: http://developer.intel.com/pc-supp/platform/ac97/index.htm

The ICH supports the following combinations of codecs:

Table 2. AC’97 Configuration Combinations

Primary Secondary

Audio (AC) None Modem (MC) None Audio (AC) Modem (MC) Audio/Modem (AMC) None

The ICH does not support two codecs of the same type on the link. For example, if an AMC is on the link, it must be the only codec. If an AC is on the link, another AC cannot be present.

Application Note 17 Intel-Based Electronic Classroom Student Computing Station

5.4.1 Design Notes for AC’97 Devices

• Special consideration must be given for the ground return paths for the analog signals. If isolated ground planes are used, pin B2 on the AMR connector should be used as an isolated ground pin and should be connected to an isolated ground plane to reduce noise in the analog circuits. The AMR designer and motherboard designer should jointly address any EMI issues when implementing isolated grounds. • Digital signals routed in the vicinity of the analog audio signals must not cross the power plane split lines. Analog and digital signals should be located as far as possible from each other. • Partition the board with all analog components grouped together in one area and all digital components in the other. • Separate analog and digital ground planes should be provided, with the digital components over the digital ground plane, and the analog components, including the analog power regulators, over the analog ground plane. The split between the planes must be a minimum of 0.05” wide. • Keep digital signal traces, especially the clock, as far way from analog input and voltage reference pins as possible. • Do not completely isolate the analog/audio ground plane from the rest of the board ground plane. There should be a single point (¼” to ½”wide) where the analog/isolated ground plane connects to the main ground plane. The split between the planes must be a minimum of 0.05”wide. • Any signals entering or leaving the analog area must cross the ground split in the area where the analog ground is attached to the main motherboard ground (i.e., there should not be any signals crossing the split/gap between the ground planes). Doing so will cause a ground loop.

5.5 Audio/Modem Riser Card (AMR)

Intel is developing a common connector specification known as the Audio/Modem Riser (AMR). This specification defines a mechanism for allowing OEM plug-in card options. The AMR specification is available on the Intel developer website: http://developer.intel.com/pc-supp/platform/ac97/index.htm

The AMR specification provides a mechanism for AC’97 codecs to be on a riser card. This is important for modem codecs as it helps ease international certification of the modem.

For the Intel-based electronic classroom student computing station, the audio codec is integrated on the motherboard to avoid compatibility issues and robustness. A modem codec is optional for electronics classroom.

5.5.1 Design Notes for the Audio/Modem Riser Card

• Only one primary codec can be present on the link. A maximum of two present codecs can be supportedinanICHplatform. • As the Intel-based electronic classroom student computing station motherboard implements an active primary codec (audio) on the motherboard and provides an AMR connector, it must tie PRI_DN# to ground. The PRI_DN# pin is provided to indicate that a primary codec is present on the motherboard.

18 Application Note Intel-Based Electronic Classroom Student Computing Station

5.6 PCI

The ICH provides a PCI bus interface that is compliant with the PCI Local Bus Specification, Revision 2.2. The implementation is optimized for high-performance data streaming when the ICH is acting as either the target or the initiator on the PCI bus. For more information on the PCI Bus interface, please refer to the PCI Local Bus Specification, Revision 2.2. The 82801AA ICH supports 6 PCI bus masters (excluding ICH), by providing 6 REQ#/GNT# pairs. The PCI network controller (GD82559) is integrated on board; therefore, an extra PCI slot is expandable for a PCI network broadcasting card (if implemented).

5.7 Network Controller — Intel® 82559 Fast Ethernet Controller

The 82559 10/100 Mbps Fast Ethernet controller with an integrated 10/100 Mbps physical layer device is Intel’s leading solution for PCI board LAN designs. It is designed for use in Network Interface Cards (NICs), PC LAN On Motherboard (LOM) designs, embedded systems, and networking system products. The 82559 combines a low power and small package design which is ideal for power- and space-constrained environments. It is compliant with Advanced Configuration and Power Interface (ACPI) 1.20A-based power management and with the Wired for Management (WfM) 2.0 Baseline specification.

The 82559 is an integrated IEEE 802.3 10BASE-T and 100BASE-TX compatible PHY. It provides a glueless 32-bit PCI master interface and supports a 128 Kbyte Flash interface. The package is a thin BGA with a small footprint (15 mm X 15 mm).

The 82559 supports the Intel Preboot Execution Environment (PXE) driver, which allows a new or existing system to boot over the network and download software or an image, including the operating system, stored on a server. The 82559 provides for operating system independent network booting, automating the setting up and configuration of new systems. If the operating system or applications software is damaged, the system can be recovered by downloading the original image from server again, reducing the total cost of maintenance.

5.7.1 Design Note for the Intel® 82559 Fast Ethernet Controller

The differential transmit signal pair (TDP/TDN) is terminated with a 100 W (1%) resistor, and the differential receive signal pair (RDP/RDN) is terminated with a 120 W (1%) resistor. These termination resistors should be placed as close to the PHY as possible. These resistors terminate the entire impedance seen at the termination source (for example, the PHY), including the wire impedance reflected through the transformer. Figure 4 depicts the placement of the termination resistors.

Application Note 19 Intel-Based Electronic Classroom Student Computing Station

Figure 4. Placement of Termination Resistor

R RJ-45 82559 Magnetics Module R PCI Interface

Place termination resistors as close to the 82559 as possible.

A7495-01

The key factors in controlling trace EMI radiation are the trace length and the ratio of trace-width to trace-height above the ground plane. To minimize trace inductance, high-speed signals, such as the clock, and signal layers that are close to a ground plane or power plane should be as short and as wide as is practical. As shown in Figure 5, this ratio is ideally somewhere between 1:1 and 3:1. To maintain the impedance of a trace, the width of the trace should be modified when changing from one board layer to another if the two layers are not equidistant from a power or ground plane. Figure 5. Trace Geometry

W W 1 < < 3 H H Ground

A7496-01

NOTE: W= Trace Width, H= Height Above Ground Plane

20 Application Note Intel-Based Electronic Classroom Student Computing Station

5.7.2 Wired for Management

Wired for Management (WfM) is an Intel initiative to improve the manageability of desktop, mobile, server and embedded systems. The goal of WfM is to reduce the total cost of ownership (TCO) through improved manageability in the following four technology areas: • Instrumentation • Remote Service Boot • Remote Wake-Up • Power Management

Manageability features in each of these four technology areas combine to form the Wired for Management Baseline Specification. A copy of the Wired for Management Baseline Specification, Version 2.0 can be obtained from: http://developer.intel.com/ial/wfm/wfmspecs.htm

An on-line Design Guide is available at: http://developer.intel.com/ial/WfM/design/index.htm

Future versions of the specification will be available at this site.

In the Intel-based electronic classroom reference configuration, the NIC is WfM compliant, particularly in the Remote Service Boot features needed to support the student computing stations’ remote boot from the server.

5.7.2.1 Instrumentation

A component's instrumentation consists of code that maintains attributes with up-to-the-minute values and adjusts the component's operational characteristics based on these values. By providing instrumentation, the platform provides accurate data to management applications, so those applications can make the best decisions for managing a system or product. The WfM 2.0 Baseline requires that compliant desktop and mobile platforms utilize the DMI Version 2.00 Management Interface (MI) and Component Interface (CI) application programming interfaces and host a DMI v2.00 Service Provider, as defined by the DMTF. Intel's DMI 2.0 Service Provider Software Development Kit (SDK) provides a DMI Service Provider and binaries that support DMI Version 2.00. This kit is available at the following URL: http://developer.intel.com/ial/WfM/tools/sdk/index.htm

® Intel® LANDesk Client Manager product includes the Service Provider and component instrumentation. Information regarding this product can be found at: http://developer.intel.com/ial/WfM/tools/ldcm/index.htm

The WfM Baseline Instrumentation specification identifies specific DMI standard groups, including event generation groups, that must be instrumented for a Baseline-compliant platform. This specification provides support for the SMBIOS revision 2.0 specification that along with appropriate component instrumentation will supply some of the required data in the specified DMI 2.0 groups.

Application Note 21 Intel-Based Electronic Classroom Student Computing Station

5.7.2.2 Remote Service Boot

The WfM Baseline specifies the protocols by which a client requests and downloads an executable image from a server and the minimum requirements on the client execution environment when the downloaded image is executed. The Baseline specification includes a set of APIs for the particular network controller used. The code supporting the Preboot eXecution Environment (PXE) and the network controller is provided on the EtherExpress™ PRO/100 WfM adapters Option ROM. Two implementation options are available: • NICwithOptionROMandWakeonLANHeader • LAN on Motherboard implementation. For this option, the Preboot execution environment and the network controller code must be incorporated into the system BIOS.

In addition, the BIOS must provide the _SYSID_ and _UUID_ data structures. The details of the BIOS requirements can be obtained from the Intel web site: http://developer.intel.com/ial/WfM/design/pxedt/index.htm

5.7.2.3 Remote Wake-Up

If a student computing station supports a reduced power state, it is possible to bring the system to a fully powered state in which all power management interfaces are available. Typically, the LAN adapter recognizes a special packet as a signal to wake up the system. The system BIOS must enable the wake event and provide wake up status. The details of the BIOS requirements can be obtained from the Intel web site: http://developer.intel.com/ial/WfM/design/rwudt/index.htm

5.7.2.4 Power Management

WfM Baseline compliant systems have four distinct power states: Working, Sleeping, Soft Off, and Mechanical Off. A user accessible switch that will send a soft off request to the system usually provides Soft Off. A second optional “override” switch located in a less obvious place (or removal of the power cord) stops current flow forcing the platform into the mechanical off state without OS consent. Note that a second “override” switch is required for legal reasons in some jurisdictions (for example, some European countries). The BIOS may support the power management requirement either through the APM revision 1.2 or ACPI revision 1.0 specifications. See Intel's web site for additional information: http://developer.intel.com/ial/WfM/design/pmdt/index.htm.

5.8 Low Pin Count (LPC) Interface

In the Intel 810 chipset platform, the Super I/O* (SIO) component has migrated to the Low Pin Count (LPC) interface. Migration to the LPC interface allows for lower cost Super I/O designs. The LPC Super I/O component requires the same feature set as traditional Super I/O components. It should include a keyboard and mouse controller, a floppy disk controller, and serial and parallel ports. In addition to the Super I/O features, an integrated game port is recommended because the AC’97 interface does not provide support for a game port. In systems that have ISA audio, the game port typically existed on the audio card. The fifteen pin game port connector provides for two joysticks and a two-wire MPU-401 MIDI interface. Consult your preferred Super I/O vendor for a comprehensive list of devices offered and features supported.

22 Application Note Intel-Based Electronic Classroom Student Computing Station

6.0 Conclusion

Traditional teaching media such as projector, video player, audio recorder, and black board are being replaced in the Intel-based electronic classroom by new computer-based teaching media. Audio, video and 2-D/3-D graphics can be introduced in the Intel-based electronic classroom. The classroom can be connected to the Internet by using modem or Intel router.

Intel provides the building blocks for Intel-based electronic classroom systems that feature manageability, ease of maintenance, compatibility with operating systems and application software, and long life cycle support for the Intel components. The recommended motherboard configuration is designed to optimize the performance of the overall system, reducing board space, power consumption, and the total cost of ownership.

Application Note 23

Intel-Based Electronic Classroom Student Computing Station

Appendix A References

Document Order Number / URL

Intel Documents and Resources

Order Number 290657 Intel® 810 Chipset Design Guide http://developer.intel.com/design/chipsets/designex/290657.htm Intel® 82810 Chipset: Intel 82810/82810-DC100 Graphics Order Number 290656 and Memory Controller Hub (GMCH) datasheet http://developer.intel.com/design/chipsets/datashts/290656.htm Intel® 82801AA (ICH) and Intel 82801AB (ICH0) I/O Order Number 290655 Controller Hub datasheet http://developer.intel.com/design/chipsets/datashts/290655.htm Order Number 290658 Intel® 82801 FirmWare Hub (FWH) datasheet http://developer.intel.com/design/chipsets/datashts/290658.htm Order Number 243658 Intel® Celeron™ Processor datasheet http://developer.intel.com/design/celeron/datashts/243658.htm Order Number 243733 VRM 8.2 DC-DC Converter Design Guidelines http://developer.intel.com/design/pentiumii/xeon/designgd/243773 .htm Order Number 243330 AP-585 Pentium® II Processor GTL+ Guidelines http://developer.intel.com/design/pentiumii/applnots/243330.htm Order Number AP-587: Slot 1 Processor Power Distribution Guidelines http://developer.intel.com/design/celeron/applnots/243332.htm Order Number 243341 Pentium® II Processor Developer's Manual http://developer.intel.com/design/PentiumII/manuals/243502.htm Pentium® II Processor at 350 MHz, 400 MHz and 450 MHz Order Number 243657 datasheet http://developer.intel.com/design/PentiumII/datashts/243657.htm Intel® 82559 Fast Ethernet Multifunction PCI Controller http://developer.intel.com/design/network/82559.htm Order Number 739073 AP-39982559PrintedCircuitBoardDesign http://developer.intel.com/design/network/applnots/739073.htm Order Number 718213 AP-392 82559 LAN on Motherboard (LOM) Design Guide http://developer.intel.com/design/network/applnots/718213.htm Intel® Networking LANSchool software site http://www.intel.com/network/products/lanschool.htm AC’97 Specifications on Intel web site http://developer.intel.com/pc-supp/platform/ac97/index.htm Wired for Management specifications and information http://developer.intel.com/ial/wfm/index.htm

Non-Intel Documents and Resources

PCI Local Bus Specification, Revision 2.2 http://www.pcisig.com/ Universal Serial Bus Specification, Revision 1.0 http://www.usb.org/

Application Note 25

Intel-Based Electronic Classroom Student Computing Station

Appendix B Intel-Based Electronic Classroom Schematics

Application Note 27 A Intel® Celeron™ Processor And Intel® 810 Based Electronic Classroom Student Computing Station Hardware Schematics

** Please note these schematics are subject to change.

THESE SCHEMATICS ARE PROVIDED "AS IS" WITH NO WARRANTIES TITLE PAGE WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS Cover Sheet 1 FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING Block Diagram 2 OUT OF PROPOSAL, SPECIFICATION OR SAMPLES. 370PGA Socket 3 , 4 GTL Termination 5 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or Clock Synthesizer 6 otherwise, to any intellectual property rights is granted by this 82810 7 , 8 , 9 document. Except as provided in Intel's Terms and Conditions System Memory 10 of Sale for such products, Intel assumes no liability 82801AA 11,12 whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products 82802AB (FWH) 13 including liability or warranties relating to fitness for a Super I/O 14 particular purpose, merchantability, or infringement of any PCI Connectors 15 patent, copyright or other intellectual property right. Intel A A ATA 33/66 IDE Connectors 16 products are not intended for use in medical, life saving or life sustaining applications. USB Connectors 17 18 Parallel Port Intel may make changes to specifications and Serial Ports 19 product descriptions at any time, without Kybrd / Mse / F. Disk / Gme Connectors 20 notice. Graphics Connectors 21 The Intel (r) Celeron (tm) processor and Intel (r) 810 chipset 22 may contain design defects or errors known as errata which AC'97 Riser Connector may cause the product to deviate from published LAN (82559) 23,24 specifications. Current characterized errata are available on Voltage Regulators 25 request. VRM 8.4 26 Copyright (c) Intel Corporation 2000 System 27,28 29 * Other brands and names are the property of their respective Pullup Resistors and Unused Gates owners. Decoupling 30 Revision History 31 Electronic Classroom Student Computing Station Ref Schematic Rev COVER SHEET 0.1

INTEL CORPORATION Last Revision Date: APPLIED COMPUTING PRO DUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 Sheet: 1 of 33

A A

Block Diagram

VRM 370-Pin Socket Processor Clock PG. 26 PG. 3-4 PG. 6 ADDR CTRL DATA

Term ADDR CTRL DATA PG. 5

One 82810 DIMM Module PG. 7-9 PG. 10 PCI CONN1 PCI

IDE Primary PG. 16 A Ultra DMA 33/66 A PCI CNTRL IDE Secondary PG. 16 82801AA PCI ADDR/DATA USB Port 1 PG. 17 PG. 11-12 15 PG. USB USB Port 2 PG. 17 LPC Bus AUDIO/MODEM RISER AC'97 Link PCI CNTRL LAN PG. 22 PCI ADDR/DATA PG. 23-24 SIO PG. 14 82802AB

PG. 13

Keyboard Floppy Parallel Game Port Mouse Serial 1

Electronic Clasroom Student Computing Station Ref. Schematic REV BLOCK DIAGRAM 0.1

INTEL CORPORATION Last Revision Date: APPLIED COMPUTING PRO DUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 Sheet: 2 of 33

A A 370PGA Socket Part 1 VCCVID

X2A AJ21 D20 F22 AM24 AJ25 D24 F26 AM28 AJ29 D28 AK34 F30 B30 AM32 AH32 Z32 V32 R32 B26 C3 AK2 AF2 AB2 T2 P2 K2 F4 E5 AM4 AE5 AA5 W5 S5 N5 J5 F2 AJ5 D6 B6 AM8 AJ9 E9 B10 AM12 AJ13 E13 B14 AM16 AJ17 E17 B18 AM20

5,7 HD#[63:0] HD#0 W1 HD#0 HD#1 T4 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 HA#[31:3] 5,7 HD#1 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 AK8 HA#3 HD#2 N1 HA#3 HD#2 AH12 HA#4 HD#3 M6 HA#4 HD#3 AH8 HA#5 HD#4 U1 HA#5 HD#4 AN9 HA#6 HD#5 S3 HA#6 HD#5 AL15 HA#7 HD#6 T6 HA#7 HD#6 AH10 HA#8 HD#7 J1 HA#8 HD#7 AL9 HA#9 HD#8 S1 HA#9 HD#8 AH6 HA#10 HD#9 P6 HA#10 HD#9 AK10 HA#11 HD#10 Q3 HA#11 HD#10 AN5 HA#12 HD#11 M4 HA#12 HD#11 AL7 HA#13 HD#12 Q1 HA#13 HD#12 AK14 HA#14 HD#13 L1 HA#14 HD#13 AL5 HA#15 HD#14 N3 HA#15 HD#14 AN7 HA#16 HD#15 U3 HA#16 HD#15 AE1 HA#17 HD#16 H4 HA#17 HD#16 Z6 HA#18 HD#17 R4 HA#18 HD#17 AG3 HA#19 HD#18 P4 HA#19 HD#18 AC3 HA#20 HD#19 H6 HA#20 HD#19 AJ1 HA#21 HD#20 L3 HA#21 HD#20 AE3 HA#22 HD#21 G1 HA#22 HD#21 AB6 HA#23 HD#22 F8 HA#23 HD#22 370-Pin Socket AB4 HA#24 HD#23 G3 HA#24 HD#23 AF6 HA#25 HD#24 K6 HA#25 HD#24 Y3 HA#26 HD#25 E3 HA#26 HD#25 AA1 HA#27 HD#26 E1 HA#27 HD#26 Part 1 AK6 HA#28 HD#27 F12 HA#28 HD#27 Z4 HA#29 HD#28 A5 HA#29 HD#28 AA3 HA#30 HD#29 A3 HA#30 HD#29 AD4 HA#31 A HD#30 J3 HA#31 A HD#30 VID[3:0] HD#31 26 C5 HD#31 VID0 AL35 VID0 HD#32 F6 HD#32 VID1 AM36 VID1 HD#33 C1 HD#33 VID2 AL37 VID2 HD#34 C7 HD#34 VID3 AJ37 VID3 HD#35 B2 HD#35 AH26 RS#0 RS#[2:0] 5,7 HD#36 C9 RS#0 HD#36 AH22 RS#1 HD#37 A9 RS#1 HD#37 AK28 RS#2 HD#38 RS#2 D8 HD#38 HD#39 HREQ#[4:0] 5,7 D10 HD#39 REQ#0 AK18 HREQ#0 HD#40 C15 HD#40 REQ#1 AH16 HREQ#1 HD#41 D14 HD#41 REQ#2 AH18 HREQ#2 HD#42 D12 HD#42 REQ#3 AL19 HREQ#3 HD#43 A7 HD#43 REQ#4 AL17 HREQ#4 HD#44 A11 HD#44 AH20 HD#45 C11 RSRVD1 HD#45 AH4 HD#46 A21 RSRVD2 HD#46 A29 HD#47 A15 RSRVD3 HD#47 A31 HD#48 A17 RSRVD4 HD#48 A33 HD#49 C13 RSRVD5 HD#49 AA33 HD#50 C25 RSRVD6 HD#50 AA35 HD#51 A13 RSRVD7 HD#51 AC1 HD#52 D16 RSRVD8 HD#52 AC37 HD#53 A23 RSRVD9 HD#53 AF4 HD#54 C21 RSRVD10 HD#54 AK16 HD#55 C19 RSRVD11 HD#55 AK24 HD#56 C27 RSRVD12 HD#56 AK30 HD#57 A19 RSRVD13 HD#57 AL11 Electronic Classroom Student Computing Station Ref. Schematic REV. HD#58 C23 RSRVD14 HD#58 AL13 HD#59 C17 RSRVD15 0.1 HD#59 AL21 370-PIN SOCKET (PART 1) HD#60 A25 RSRVD16 HD#60 AN11 HD#61 A27 RSRVD17 HD#61 AN13 HD#62 RSRVD18 E25 HD#62 INTEL CORPORATION Last Revision Date: HD#63 F16 HD#63 APPLIED COMPUTING PRO DUCTS DIVISION GND1 GND2 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 GND49 GND50 GND3 GND4 GND5 GND6 GND7 GND8 GND9

AM2 AM34 AH2 AD2 Z2 V2 M2 D18 H2 D2 AL3 AK4 AG5 AC5 Y5 U5 Q5 L5 G5 D4 B4 AM6 AJ7 E7 B8 AM10 AJ11 E11 B12 AM14 AJ15 E15 B16 AM18 AJ19 E19 F20 B20 AM22 AJ23 D22 F24 B24 AM26 AJ27 D26 F28 B28 AM30 D30 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 Sheet: 3 of 33

A A 370PGA Socket Part 2 VCC2_5

VCC2_5 ITP Test Port Option 29 VCMOS VTT1_5 R9A

VCMOS 4N677 VCMOS 4N329 220 VTT1_5 VCCVID 8 7 6 5 RP2A GTLREF

R8A R7A 1 2 1K 150 4N642 J2A 330 4N937 JP1A

ITP30RA 1 2 3 4 X2B AB36 AD36 Z36 E33 F18 K4 R6 V6 AD6 AK12 AK22 M32 H32 AF34 AB34 X34 T34 P34 K34 F34 B34 AH36 B22 V36 R36 H36 D36 D32 AD32 AH24 F14 K32 AA37 Y35 R1A ITP_RST 1 2 5,7 CPURST# JP5 is a Test Option Only. 240 R2A R_DBRST# 3 4 28 DBRESET# V1_5 V2_5

R_TCK 0K 5 6 VREF0 VREF1 VREF2 VREF3 VREF4 VREF5 VREF6 VREF7 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC75 VCC74

R_TMS TDI V_CMOS 7 8 AN35 TDI BNR# AH14 BNR# 5,7 ITP_PON TDO 9 10 AN37 TDO BPRI# AN17 BPRI# 5,7 TRST# 11 12 TRST# AN33 TRDY# AN25 HTRDY# 5,7 R_TCK R3A TCK 13 14 AL33 TCK DEFER# AN19 DEFER# 5,7 R_TMS R4A 47 TMS 15 16 AK32 TMS LOCK# AK20 HLOCK# 5,7 17 18 R_ITPRDY# 47 AN27 ITPREQ# J37 DRDY# DRDY# 5,7 19 20 PREQ# AL23 A35 HITM# HITM# 5,7 21 22 R21A PRDY# AL25 ITPRDY# HIT# HIT# 5,7 23 24 ITPRDY# 5 G33 AL27 240 BP2# DBSY# DBSY# 5,7 25 26 E37 BP3# ADS# AN31 HADS# 5,7 27 28 C35 BPM0# FLUSH# AE37 29 30 E35 6 ITPCLK BPM1# BSEL# AJ33 FREQSEL 6,9 AN15 RSRVD19 BR0# AN29 BR0# 5 AN21 RSRVD20 370-Pin Socket AL31 THRMDP AN23 RSRVD21 THRMDN AL29 B36 RSRVD22 THERMTRIP# AH28 C29 RSRVD23 C31 RSRVD24 A20M# AE33 A20M# 11,29 C33 Part 2 AG35 RSRVD25 STPCLK# STPCLK# 11,29 E23 AH30 A RSRVD26 SLP# CPUSLP# 11, 29 A E29 RSRVD27 SMI# AJ35 SMI# 11, 29 E31 RSRVD28 LINT0/INTR M36 INTR 11, 29 F10 RSRVD29 LINT1/NMI L37 NMI 11, 29 VTT1_5 GTLREF Generation Circuit G35 RSRVD30 INIT# AG33 INIT# 11,13,29 G37 RSRVD31 FERR# AC35 FERR# 11,29 Use 0603 Packages and distribute VCCVID L33 RSRVD32 IGNNE# AG37 IGNNE# 11,29 within 500 mils of Mendocino R102A N33 RSRVD33 IERR# AE35 1% GTLREF Inputs (1 cap for every 2 inputs). N35 75 RSRVD34 W33 PLL1 C123A L22A N37 PLL1 RSRVD35 U33 PLL2 2 1 4N606 GTLREF VCCVID Q33 PLL2 RSRVD36 + 4.7UH Q35 RSRVD37 33UF 20% Q37 S37 R104A RSRVD38 RSRVD40 C206A C209A C204A C207A 1% S33 RSRVD39 RSRVD41 U35 150 U37 J35 RSRVD42 0.1UF 0.1UF APICD011,29 0.1UF 0.1UF PICD0 RSRVD43 V4 APICD111,29 L35 PICD1 VCC3_3 4N949 RSRVD44 W3 6 APICCLK_CPU J33 PICCLK RSRVD45 W35 R171A 6 CPUHCLK W37 BCLK RSRVD46 X6 Y1 220 AK26 RSRVD47 29 PWRGOOD PWRGOOD E21 CPURST# RSRVD48 VCCDET 9 X4 RESET# VCMOS Decoupling RSRVD49 E27 SLEWCTRL 29 R76A EDGCTRL 4N639 AG1 EDGCTRL RSRVD50 R2 51 S35 C37 RSRVD51 RTTCRTL 29 VCMOS CPUPRES# Place 0603 Package RSRVD52 X2 Near VCMOS Processor Pin. GND51 GND52 GND53 GND54 GND55 GND56 GND57 GND58 GND59 GND60 GND61 GND62 GND63 GND64 GND65 GND66 GND67 GND68 GND69 GND70 GND71 GND72 GND73 GND74 GND75 GND76 GND77 GND78 GND79 GND80 C6A M34 H34 D34 AK36 AF36 X36 T36 P36 K36 F36 A37 AC33 AJ3 AL1 AN3 Y37 AJ31 Y33 AF32 AB32 X32 T32 P32 F32 B32 AH34 AD34 Z34 V34 R34

4N101 0.1UF

Do not stuff C114 Electronic Classroom Student Computing Station Ref. Schematic Rev C114A R5A 0.5 18PF 680 370-PIN SOCKET (PART 2) Place site w / in 0.5" Last Revision Date: of clock pin (W37) 4N859 INTEL CORPORATION

APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 Sheet: CHANDLER, AZ 85226 4 of 33

A A GTL Termination

VTT1_5 VTT1_5 VTT1_5 VTT1_5

RP19A 1 8 HA#17 HA#[31:3] 3,7 2 7 HA#22 RP22A RP38A 3 6 HA#31 HD#[63:0] 3,7 RP6A 5N208 1 8 HD#15 1 8 HD#54 4 5 HA#19 1 8 BPRI# 4,7 2 7 HD#1 2 7 HD#55 2 7 56 HREQ#4 3,7 3 6 HD#0 3 6 HD#52 3 6 4 5 HD#6 4 5 HD#40 RP18A HLOCK# 4,7 HA#18 4 5 1 8 RS#1 3,7 56 56 2 7 HA#21 56 RP23A RP33A 3 6 HA#25 RP9A 1 8 HD#8 1 8 HD#56 4 5 HA#10 1 8 HTRDY# 4,7 2 7 HD#5 2 7 HD#61 2 7 HD#9 HD#62 56 RS#0 3,7 3 6 3 6 3 6 4 5 HD#4 4 5 HD#46 RP8A DRDY# 4,7 1 8 HA#15 4 5 DBSY# 4,7 56 56 HA#12 2 7 56 3 6 HA#3 RP35A RP32A RP5A 1 8 HD#16 1 8 HD#60 4 5 HA#6 1 8 HITM# 4,7 2 7 HD#23 2 7 HD#50 2 7 HD#21 HD#53 56 HIT# 4,7 3 6 3 6 3 6 4 5 HD#24 4 5 HD#58 RP20A RS#2 3,7 HA#30 4 5 HADS# 4,7 1 8 56 56 2 7 HA#24 56 3 6 HA#20 RP24A RP36A RP10A 1 8 HD#3 1 8 HD#57 4 5 HA#23 1 8 HREQ#0 3,7 2 7 HD#12 2 7 HD#63 2 7 56 DEFER# 4,7 3 6 HD#10 3 6 HD#59 3 6 4 5 HD#17 4 5 HD#48 RP12A HREQ#3 3,7 A 5N369 4 5 A 1 8 HA#28 HREQ#2 3,7 56 56 HA#13 2 7 56 3 6 HA#16 RP26A RP39A RP3A 1 8 HD#30 1 8 HD#47 4 5 HA#5 1 8 ITPRDY# 4 2 7 HD#7 2 7 HD#27 2 7 HD#11 HD#44 56 3 6 3 6 3 6 4 5 HD#20 4 5 HD#45 RP7A HA#9 4 5 BR0# 4 1 8 56 56 2 7 HA#11 5N395 56 HA#7 RP25A RP37A 3 6 1 8 HD#13 1 8 HD#49 4 5 HREQ#1 3,7 2 7 HD#18 2 7 HD#51 56 3 6 HD#14 3 6 HD#41 4 5 HD#2 4 5 HD#42 RP11A 1 8 HA#8 56 56 5N58 2 7 HA#4 RP43A RP40A 3 6 BNR# 4,7 1 8 HD#31 1 8 HD#36 HA#14 4 5 2 7 HD#32 2 7 HD#22 HD#25 HD#43 56 3 6 3 6 4 5 HD#26 4 5 HD#34 RP21A 1 8 CPURST# 4,7 56 56 2 7 HA#26 3 6 HA#29 RP41A RP42A 1 8 HD#29 1 8 HD#39 HA#27 4 5 2 7 HD#19 2 7 HD#37 56 3 6 HD#35 5N250 3 6 HD#38 4 5 HD#33 4 5 HD#28

56 56 Electronic Classroom Student Computing Station Ref. Schematic REV.

GTL TERMINATION 0.5

INTEL CORPORATION Last Revision Date:

APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 Sheet: 5 of 33

A A

Clock Synthesizer VCC3_3 L17A USBV3 1 2 C55A C50A 1 +

VCC3_3 22UF 0.1UF

2 VCC3_3 L13A L16A Notes: 1 2 1 2 - Place all dec oupling caps as close to VCC/GND pins as possible PCIV3 MEMV3 C158A C38A C37A C39A C40A C386A C388A C385A C387A C60A C63A C64A C61A C48A 1 1 - PCI_0/ICH pin has to go to the ICH. + + (This clock cannot be turned off through SMBus) 22UF 0.1UF .001UF 0.1UF .001UF .1UF .001UF .001UF .1UF .001UF 0.1UF .001UF 0.1UF 22UF - CPU_ITP pin has to go to the ITP. It is the only 2 2 CPU CLK that can be shut off thr ough the SMBUS interface.

R41A

8.2K U1A C51A 2 9 10 21 27 33 38 44 SEL1_PU

Y1A 12PF 2

VDD3_3[0] VDD3_3[1] VDD3_3[2] VDD3_3[3] VDD3_3[4] VDD3_3[5] VDD3_3[6] VDD3_3[7] R34A XTAL_IN 3 XTAL_IN APIC_0 55 APIC_0 APICCLK_CPU 4 XTAL APIC 33 R25A APIC_1 54 APIC_1 APICCLK_ICH 11 R184A 33 C49A 1 14.318MHZ SIO_CLK14 REF R32A 14 XTAL_OUT 4 CPU_0_152 10 XTAL_OUT CPU_0 R35A CPUHCLK 4 50 33 R48A 12PF CPU CPU_1 R26A GMCHHCLK 7 REFCLK CPU_2 33 12 ICH_CLK14 1 REF0 CPU_2/ITP 49 ITPCLK 4 10 33 R42A R36A MEMCLK0 MEMCLK[7:0] 10 12 ICH_3V66 3V66_0 7 3V66_0 SDRAM_0 46 DRAM_0 R49A 22 3V66 R27A 22 MEMCLK1 8 GMCH_3V66 3V66_1 8 3V66_1 SDRAM_1 45 DRAM_1 22 22 R37A MEMCLK2 SDRAM_2 43 DRAM_2 A R43A R28A A PCI_0 11 CK_Whitney 42 DRAM_3 22 MEMCLK3 11 PCLK_0/ICH R50A PCI_0/ICH SDRAM_3 R38A 33 PCI_1 12 40 DRAM_4 22 MEMCLK4 14 PCLK_1 R44A PCI_1 SDRAM_4 R29A 33 PCI_2 13 ICS9250-10 39 DRAM_5 22 MEMCLK5 15 PCLK_2 PCI_2 SDRAM_5 R39A 33 15 37 DRAM_6 22 MEMCLK6 PCI_3 PCI Memory SDRAM_6 R30A 16 36 DRAM_7 22 MEMCLK7 R51A PCI_4 SDRAM_7 PCI_5 18 22 24 PCLK_5 PCI_5 R40A VCC3_3 33 R46A 13 PCLK_6 PCI_6 19 PCI_6 DCLK 34 DCLK DCLK_WR 8 33 20 22 PCI_7 VCC2_5

2 32 R53A PWRDWN# CK_PW RDN# 24,27 L18A 12 USBCLK USB_0 25 USB_0 SCLK 31 CK_SMBCLK 20 R47A 33 USB 2 9 DOTCLK USB_1 26 USB_1 SDATA 30 CK_SMBDATA 20 22 L15A SEL1 29

1 28 L_CKVDDA SEL0 FREQSEL 4,9

C52A C53A 1 22 VDD_A 51 .001UF VDD2_5[0] 0.1UF L_VCC2_5 VDD2_5[1] 53 23 VSS_A C46A C47A C56A 1 VSS2_5[1] 56 + VSS2_5[0] 48 .001UF 0.1UF 4.7UF 2 VSS3_3[0] VSS3_3[1] VSS3_3[2] VSS3_3[3] VSS3_3[4] VSS3_3[5] VSS3_3[6] VSS3_3[7] 24 35 41 47 5 6 14 17

Minimize Stub Length from JP6A CLK14 trace to JP1A.

JP1 Electronic Classroom Student Computing Station Ref. Schematic Rev . 0.5 APIC Clk Strap JP6A CLOCK SYNTHESIZER R23A 16 MHz in 10K 33 MHz out INTEL CORPORATION Last Revision Date:

APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 Sheet: 6 of 33

A A 82810, PART 1: HOST INTERFACE VCC1_8 VTT1_5

U2A V16 V15 V14 V10 V9 V8 V7 F17 F16 F14 F10 F8 F7 B20 P6 U18 V17 Y5 HD#0 HD#[63:0] 3,5 R80A HD0# HD#1 75 HD1# W5 1% HD#2 HD2# W8

VCC1_8[0] VCC1_8[1] VCC1_8[2] AA6 HD#3 GMCHGTLREF M5 HD3# GTLREFA AB6 HD#4 W13 VCC_CORE[0] VCC_CORE[1] VCC_CORE[2] VCC_CORE[3] VCC_CORE[4] VCC_CORE[5] VCC_CORE[6] VCC_CORE[7] VCC_CORE[8] VCC_CORE[9] HD4# GTLREFB VCC_CORE[10] VCC_CORE[11] VCC_CORE[12] VCC_CORE[13] Y6 HD#5 C166A C167A HD5# R81A AA5 HD#6 150 V6 HD6# 6 GMCHHCLK HTCLK AA9 HD#7 1% 0.1UF .001UF M2 HD7# 11,13,14,15,16,23 PCIRST# RESETB V5 HD#8 AB4 HD8# 4,5 CPURST# CPURST# AC7 HD#9 P5 HD9# 4,5 HLOCK# HLOCK# AB7 HD#10 R3 HD10# 4,5 DEFER# DEFER# AC8 HD#11 N3 HD11# 4,5 HADS# ADS# AA7 HD#12 T3 INTEL 82810 HD12# 4,5 BNR# BNR# Y8 HD#13 T1 HD13# 4,5 BPRI# BPRI# W7 HD#14 M4 HD14# 4,5 DBSY# DBSY# AC6 HD#15 N1 PART1 HD15# 4,5 DRDY# DRDY# W9 HD#16 P1 HD16# 4,5 HIT# HIT# AC9 HD#17 R1 HD17# 4,5 HITM# HITM# HOST INTERFACE Y7 HD#18 N4 HD18# 4,5 HTRDY# HTRDY# HD#19 HD19# AA10 AB8 HD#20 HA#[31:3]3,5 HA#3 U5 HD20# HA3# AC10 HD#21 HA#4 U1 HD21# HA4# AB13 HD#22 HA#5 V4 HD22# HA5# AB10 HD#23 HA#6 V1 HD23# HA6# AB9 HD#24 HA#7 T4 HD24# HA7# AB11 HD#25 HA#8 U2 HD25# HA8# Y10 HD#26 HA#9 U3 HD26# HA9# AB16 HD#27 HA#10 W1 HD27# HA10# AB12 HD#28 HA#11 U4 HD28# HA11# Y11 HD#29 HA#12 W3 HD29# HA12# Y9 HD#30 HA#13 W4 HD30# HA13# AC12 HD#31 HA#14 T5 HD31# A HA14# W11 HD#32 A HA#15 W2 HD32# HA15# AC11 HD#33 HA#16 V2 HD33# HA16# W12 HD#34 HA#17 AC2 HD34# HA17# AA11 HD#35 HA#18 AA2 HD35# HA18# AA13 HD#36 HA#19 Y3 HD36# HA19# Y13 HD#37 HA#20 AB3 HD37# HA20# Y12 HD#38 HA#21 AA1 HD38# HA21# AC14 HD#39 HA#22 AB2 HD39# HA22# AA15 HD#40 HA#23 AC3 HD40# HA23# AC15 HD#41 HA#24 AA3 HD41# HA24# Y14 HD#42 HA#25 Y2 HD42# HA25# AC13 HD#43 HA#26 AB5 HD43# HA26# AA14 HD#44 HA#27 AC4 HD44# HA27# AB14 HD#45 HA#28 Y1 HD45# HA28# Y17 HD#46 HA#29 AC5 HD46# HA29# Y15 HD#47 HA#30 Y4 HD47# HA30# AC17 HD#48 HA#31 AB1 HD48# HA31# HD#49 HD49# AC16 AA18 HD#50 3,5 HREQ#[4:0] HREQ#0 R4 HD50# HREQ0# AB15 HD#51 HREQ#1 T2 HD51# HREQ1# W15 HD#52 HREQ#2 P4 HD52# HREQ2# AB18 HD#53 HREQ#3 R2 HD53# HREQ3# W17 HD#54 HREQ#4 R5 HD54# HREQ4# HD#55 HD55# AA17 3,5 RS#[2:0] W18 HD#56 RS#0 N5 HD56# RS0# W16 HD#57 RS#1 P2 HD57# RS1# AC19 HD#58 RS#2 N2 HD58# RS2# HD#59 HD59# Y16 Electronic Classroom Student Computing Station Ref. Schematic Rev . HD#60 HD60# AB19 HD#61 0.5 HD61# Y18 82810 ,PART 1: HOST INTERFACE HD#62 HD62# AC18 AB17 HD#63 VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] HD63#VSS[23] INTEL CORPORATION Last Revision Date: Y22 V18 N22 J22 Y19 C19 E22 K14 K13 K12 K11 K10 L14 L13 L12 L11 L10 M14 M13 M12 M11 M10 N14 N13 Do not Stuff C398 APPLIED COMPUTING PRODUCTS DIVISION C161A 5000 W CHANDLER BLVD. CH6-236 18PF CHANDLER, AZ 85226 Place site w/in 0.5" Sheet: of clock ball (V6) 7 of 33

A A 82810, PART 2: SYSTEM MEMORY

VCC3_3 AND HUB INTERFACE VCC1_8 VCC3_3SBY

Place Resistor as Close R82A U2B 40 D4 C11 C7 C15 L3 G3 F15 F9 K6 F6 B2 L21 G21 F18 J18 R18 as possible to GMCH SM_MD0 SM_MD[63:0] 10 1% SMD0 E17 10 SM_MAA[11:0] C16 SM_MD1 SM_MAA0 C9 SMD1 SMAA0 D15 SM_MD2 SM_MAA1 E7 SMD2 SMAA1 SM_MD3 VCC3_3[0] VCC3_3[1] VCC3_3[2] VCC3_3[3] VCC3_3[4] VCC3_3[5] VCC3_3[6] VCC3_3[7] VCC3_3[8] VCC3_3[9] SMD3 D17 VCC3_3[10] VCC3_3[11] VCC3_3[13] VCC3_3[14] VCC3_3[15] SM_MAA2 A9 VCC3_3[12] SMAA2 C17 SM_MD4 SM_MAA3 RP70A D7 SMD4 SMAA3 A17 SM_MD5 SM_MAA4 1 8 B8 SMD5 SMAA4 A16 SM_MD6 SM_MAA5 2 7 A8 SMD6 SMAA5 B16 SM_MD7 SM_MAA6 3 6 B7 SMD7 SMAA6 A15 SM_MD8 SM_MAA7 4 5 A7 SMD8 SMAA7 C14 SM_MD9 SM_MAA8 D6 SMD9 Place HUBREF Generation SMAA8 B14 SM_MD10 SM_MAA9 10 C6 SMD10 Circuit in middle of SMAA9 INTEL 82810 A14 SM_MD11 SM_MAA10 D5 SMD11 VCC1_8 SMAA10 D13 SM_MD12 GMCH and ICH. SM_MAA11 A5 SMD12 SMAA11 C13 SM_MD13 C300A RP77A SMD13 A13 SM_MD14 HUBREF_CV 1 8 B6 SMD14 SMAB4# PART 2 A12 SM_MD15 2 7 A6 SMD15 470PF SMAB5# E1 SM_MD16 R177A 3 6 B4 SMD16 R130A SMAB6# F2 SM_MD17 56 301 4 5 A4 SMD17 SMAB7# SM_MD18 1% SYSTEM MEMORY SMD18 G4 10 G1 SM_MD19 10 SM_DQM[7:0] SM_DQM0 C10 SMD19 HUBREF 11 SDQM0 D3 SM_MD20 SM_DQM1 A10 SMD20 SDQM1 H2 SM_MD21 SM_DQM2 B1 SMD21 R176A R131A SDQM2 AND H1 SM_MD22 SM_DQM3 D1 SMD22 56 301 SDQM3 J4 SM_MD23 1% SM_DQM4 B10 SMD23 C299A SDQM4 J1 SM_MD24 SM_DQM5 D9 SMD24 HUBREF_CG SDQM5 K2 SM_MD25 SM_DQM6 C1 HUB INTERFACE SMD25 470PF SDQM6 K1 SM_MD26 SM_DQM7 D2 SMD26 SDQM7 SM_MD27 SMD27 K3 L1 SM_MD28 10 SM_BS[1:0] SM_BS0 C5 SMD28 SBS0 L2 SM_MD29 SM_BS1 E5 SMD29 SBS1 SM_MD30 SMD30 M3 A K4 SM_MD31 A SM_CS#[3:0] SM_CS#0 C4 SMD31 10 SCS0# D16 SM_MD32 SM_CS#1 C3 SMD32 SCS1# E15 SM_MD33 SM_CS#2 B3 SMD33 SCS2# D14 SM_MD34 SM_CS#3 C2 SMD34 SCS3# SM_MD35 SMD35 E14 E13 SM_MD36 D8 SMD36 10 SM_RAS# SRAS# E12 SM_MD37 A11 SMD37 10 SM_CAS# SCAS# D12 SM_MD38 B11 SMD38 10 SM_WE# SWE# SM_MD39 SMD39 B15 B12 SM_MD40 10 SM_CKE[1:0] SM_CKE0 A3 SMD40 SCKE0 C12 SM_MD41 SM_CKE1 A2 SMD41 R31A SCKE1 D11 SM_MD42 SCLK E6 SMD42 6 DCLK_WR SCLK D10 SM_MD43 0K SMD43 E10 SM_MD44 D19 SMD44 C168A 6 GMCH_3V66 HLCLK E9 SM_MD45 HL0 C21 SMD45 HL0 E8 SM_MD46 22PF 11 HL[10:0] HL1 B23 SMD46 HL1 C8 SM_MD47 HL2 B22 SMD47 HL2 F3 SM_MD48 HL3 A23 SMD48 HL3 F1 SM_MD49 HL4 B19 SMD49 HL4 G2 SM_MD50 HL5 B18 SMD50 HL5 H3 SM_MD51 HL6 C18 SMD51 HL6 HUB I/F E4 SM_MD52 HL7 A18 SMD52 HL7 E3 SM_MD53 HL8 A22 SMD53 HL8 F4 SM_MD54 HL9 C20 SMD54 HL9 J3 SM_MD55 HL10 A19 SMD55 HL10 F5 SM_MD56 HUBREF D20 SMD56 HUBREF G5 SM_MD57 A21 SMD57 11 HLSTB HLSTB H5 SM_MD58 A20 SMD58 Electronic Classroom Student Computing Station Ref. Schematic Rev . 11 HLSTB# HLSTB# SM_MD59 SMD59 H4

GHCOMP D18 HCOMP SM_MD60 SMD60 H6 82810, PART 2: SYSTEM MEMORY AND HUB INTERFACE 0.5 SM_MD61 SMD61 J5 SM_MD62 SMD62 K5 C241A L5 SM_MD63 Last Revision Date: Place C241A as close VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] SMD63VSS[44] VSS[45] INTEL CORPORATION as possible to GMCH 0.1UF N12 N11 N10 P14 P13 P12 P11 P10 AC1 AA4 AA8 AA12 AA16 W6 W10 W14 V3 R6 P3 M1 L4 J2 C236A APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 18PF CHANDLER, AZ 85226 Sheet: 8 of 33

A A JP16 82810, PART 3 VCC1_8 VCC1_8 L24A VCCDACA 68NH-0.3A + 1

C217A Use Surface Mount Caps C216A C222A U2C placed close as possible to 2 U6 E19 AC20 AB23 AB21 33UF power pins with short, 0.1UF 0.01UF GMCH RESET STRAPS wide direct connections L20 LCS# VCCBA VCCHA VCCDA LTVDATA0 Y21 P21 VCCDACA1 VCCDACA2 FREQSEL 4,6 LDQM0 Y20 R23 LTVDATA1 VCC3_3 VCCDET 4 LDQM1 W23 C23 LTVDATA2 LDQM2 W22 F20 LTVDATA3 LDQM3 W21 RP46A LTVDATA4 RP48A K19 V23 8 7 6 5 8 7 6 5 LRAS# VIDEO DIGITAL OUT LTVDATA5 K20 LCAS# LTVDATA6 U23 J19 LWE# INTERFACE LTVDATA7 U22 10K 10K LTVDATA8 U21 M19 LMA0

1 2 3 4 T23 1 2 3 4 P19 LTVDATA9 LMA1 T22 P20 LTVDATA10 JP16A LMA2 T21 DC_MD31 N19 LTVDATA11 GRS_PU26 LMA3 INTEL 82810 V19 GRS_PU31 GRS_PU28 GRS_PU30 J21 BLANK# LMA4 U20 H19 TVCLKIN/SL_STALL JP15A LMA5 CLKOUT0 V21 DC_MD30 H20 LMA6 VCC3_3SBY PART3 CLKOUT1 V22 H18 LMA7 TVVSYNC V20 DC_MD29 G19 LMA8 TVHSYNC U19 JP14A F19 LMA9 DC_MD28 R62A M20 LMA10 LTVCL T19 R64A L19 LMA11 LTVDA T20 DC_MD27 4.7K M22 LMD0 4.7K JP13A M21 LMD1 DC_MD26 L23 LMD2 L22 LMD3 K21 LMD4 K23 LMD5 A A R19 LMD6 R20 LMD7 R22 LMD8 R21 LMD9 P23 LMD10 P22 LMD11 N23 Function Jumper Comment LMD12 N21 LMD13 JP16 XOR IN = XOR Tree N20 LMD14 *OUT = Normal M23 LMD15 Tri-state JP15 IN = Tri-state Mode F23 LMD16 *OUT = Normal E20 LMD17 E21 System N/A Reads System LMD18 W19 Bus Freq. Bus Freq. E23 DISPLAY CACHE DDCDA 3VDDCDA 21 LMD19 W20 D22 DDCCL 3VDDCCL IOQ Depth JP14 IN = IOQ Depth of 1 LMD20 21 D23 *Out = IOQ Depth of 4 LMD21 AA21 D21 DCLKREF DOTCLK 6 DOTCLK Detects type of LMD22 VCORE N/A IWASTE Y23 Processor I/O Buffers C22 Detect LMD23 AA23 IREFPD H21 IREF C379A RESVD JP13 TBD LMD24 Do not Stuff C379A H22 18PF LMD25 AA20 H23 VSYNC CRT_ VSYNC 21 Place site w / in 0.5" LMD26 GRAPHICS INTERFACE AB20 of clock ball ( AA21). G20 HSYNC CRT_HSYNC 21 LMD27 AC21 G22 RED VID_RED 21 LMD28 AC22 G23 GREEN VID_GREEN 21 LMD29 AC23 BLUE VID_BLUE 21 F21 LMD30 F22 LMD31 R127A Place as close as R_LTCLK K22 R125A LTCLK 174 Possible to GMCH Electronic Classroom Student Computing Station Ref. Schematic Rev . 22 1% and via straight to R128A VSS plane. 0.5 RCLK J20 LRCLK 82810, PART 3: GRAPHICS 0K J23 R129A LOCLK OCLK_FB OCLK 33 INTEL CORPORATION Last Revision Date: Place R70A within 0.5" of the GMCH Ball. VSSDA VSSDACA VSSHA VSSBA VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] APPLIED COMPUTING PRODUCTS DIVISION

T6 E18 J6 G6 E2 A1 B5 B9 E11 B13 E16 B17 B21 G18 K18 P18 T18 AA19 AA22 AB22 5000 W CHANDLER BLVD. CH6-236 C238A CHANDLER, AZ 85226 Sheet: 22PF Do Not Populate C238 9 of 33

A A

SYSTEM MEMORY

8 SM_MD[63:0] SM_MD0 SM_MD44 SM_MD4 SM_MD1 SM_MD3 SM_MD7 SM_MD2 SM_MD10 SM_MD5 SM_MD11 SM_MD9 SM_MD8 SM_MD14 SM_MD15 SM_MD13 SM_MD17 SM_MD12 SM_MD20 SM_MD21 SM_MD16 SM_MD22 SM_MD19 SM_MD18 SM_MD24 SM_MD23 SM_MD25 SM_MD26 SM_MD27 SM_MD29 SM_MD28 SM_MD30 SM_MD31 SM_MD35 SM_MD36 SM_MD33 SM_MD34 SM_MD32 SM_MD39 SM_MD37 SM_MD38 SM_MD40 SM_MD41 SM_MD42 SM_MD48 SM_MD45 SM_MD43 SM_MD46 SM_MD47 SM_MD50 SM_MD49 SM_MD52 SM_MD56 SM_MD51 SM_MD57 SM_MD54 SM_MD58 SM_MD55 SM_MD53 SM_MD59 SM_MD60 SM_MD62 SM_MD63 SM_MD61 SM_MD6 2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 55 56 57 58 60 65 66 67 69 70 71 72 74 75 76 77 86 87 88 89 91 92 93 94 95 97 98 99 100 101 103 104 139 140 141 142 144 149 150 151 153 154 155 156 158 159 160 161 21 22 52 53 105 106 136 137

VCC3_3SBY DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ53 DQ56 DQ57 DQ58 DQ59 DQ60 DQ63 DQ44 DQ45 DQ54 DQ55 DQ61 DQ62 DQ52 ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7

168 VCC17 VSS18 162 157 VCC16 VSS17 152 143 VCC15 VSS16 148 133 VCC14 VSS15 138 84 VCC13 VSS14 127 73 VCC12 VSS13 116 59 VCC11 VSS12 107 49 VCC10 VSS11 96 124 VCC9 DIMM SOCKET VSS10 85 110 VCC8 VSS9 78 102 VCC7 VSS8 68 90 VCC6 168 PIN VSS7 64 41 VCC5 VSS6 54 A 40 VCC4 VSS5 43 A 26 VCC3 VSS4 32 18 VCC2 VSS3 23 6 VCC1 VSS2 12 VSS1 1

J11A CLK1 CLK2 CLK3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 BA0 BA1 S0# S1# S2# S3# CAS# WE# RAS# CKE0 CKE1 SMBDATA SMBCLK REGE SA0 SA1 SA2 DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7 WP NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 CLK0 165 166 167 81 24 25 31 44 48 50 51 61 62 80 108 109 134 135 145 146 164 42 125 79 163 33 117 34 118 35 119 36 120 37 121 38 123 126 132 122 39 28 29 46 47 112 113 130 131 30 114 45 129 27 111 115 128 63 82 83 147

VCC3_3SBY R63A

2.2K SM_BS0 SM_BS1 SM_DQM0 SM_DQM1 SM_DQM2 SM_DQM3 SM_DQM4 SM_DQM5 SM_DQM6 SM_DQM7 SM_CKE0 SM_CKE1 MEMCLK0 MEMCLK1 MEMCLK2 MEMCLK3 SM_CS#0 SM_CS#1 SM_MAA0 SM_MAA1 SM_MAA2 SM_MAA3 SM_MAA4 SM_MAA5 SM_MAA6 SM_MAA7 SM_MAA8 SM_MAA9 SM_MAA10 SM_MAA11

6 MEMCLK[7:0]

8 SM_MAA[11:0]

8 SM_BS[1:0]

8 SM_DQM[7:0]

8 SM_CS#[3:0] 8 SM_WE# Electronic Classroom Student Computing Station Ref. Schematic REV 8 SM_CAS# 8 SM_RAS# SYSTEM MEMORY 0.5

8 SM_CKE[1:0] 12,21,24,29 SMBDATA INTEL CORPORATION Last Revision Date: 12,21,24,29 SMBCLK APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 Sheet: 10 of 33

A A 82801AA , Part 1 VCC3_3 VCC1_8

U14A E3 G5 P6 T7 U10 R13 T16 M14 C11 C8 A5 E6 E5 D16 N5 N13 E13 G13 H14 K14 G15 L15 H16 J16

AD[31:0]15,23 VCC3_3_1 VCC3_3_2 VCC3_3_3 VCC3_3_4 VCC3_3_5 VCC3_3_6 VCC3_3_7 VCC3_3_8 VCC3_3_9 VCC1_8_1 VCC1_8_2 VCC1_8_3 VCC1_8_4 VCC1_8_5 VCC1_8_6 VCC1_8_7 VCC3_3_10 VCC3_3_11 VCC3_3_12 VCC3_3_14 VCC3_3_15 VCC3_3_16 VCC3_3_17 AD0 VCC3_3_13 AD0 G2 A20M# F13 A20M# 4,29 AD1 AD1 G4 CPUSLP# E12 CPUSLP# 4,29 AD2 AD2 F2 FERR# F15 FERR# 4,29 AD3 F3 B17 AD3 IGNNE# IGNNE# 4,29 AD4 F4 E15 AD4 INIT# INIT# 4,13,29 AD5 F5 E14 AD5 INTR INTR 4,29 AD6 AD6 E1 NMICPU B16 NMI 4,29 AD7 AD7 E2 SMI# F14 SMI# 4,29 AD8 AD8 D1 STPCLK# A17 STPCLK# 4,29 AD9 AD9 D3 RCIN# A15 RCIN# 14,29 AD10 AD10 E4 A20GATE B15 A20GATE 14,29 AD11 AD11 C2 AD12 HL0 HL[10:0] 8 AD12 C1 82801AA HL0 D17 AD13 HL1 AD13 B1 HL1 E17 AD14 HL2 AD14 D4 HL2 F17 VCC1_8 AD15 HL3 AD15 C3 HL3 G16 AD16 HL4 AD16 A4 HL4 J15 AD17 PART 1 HL5 AD17 B4 HL5 K16 AD18 HL6 AD18 C5 HL6 K17 R182A Place R189 AD19 HUB I/F HL7 40 AD19 C6 HL7 L17 as close as AD20 HL8 1% possible to ICH0. AD20 B5 HL8 H15 AD21 HL9 AD21 E7 PCI HL9 J17 AD22 HL10 AD22 A6 HL10 J14 AD23 AD23 B6 HLSTB G17 HLSTB 8 AD24 AD24 D7 HLSTB# H17 HLSTB# 8 AD25 IHCOMP_PU AD25 B8 HCOMP M17 AD26 AD26 A7 HUBREF J13 HUBREF 8 A AD27 A AD27 A8 AD28 C302A AD28 B7 PIRQ#A D10 PIRQ#A 15,23,29 AD29 C9 A10 AD29 PIRQ#B PIRQ#B 15,29 Place C172 as close AD30 0.1UF AD30 D8 PIRQ#C B10 PIRQ#C 15,29 as possible to ICH0. AD31 C7 C10 AD31 PIRQ#D PIRQ#D 15,29

15,23 C_BE#[3:0] C_BE#0 C_BE#0 D2 IRQ14 P11 IRQ14 16,29 C_BE#1 B2 INTERRUPTS N14 C_BE#1 IRQ15 IRQ15 16,29 C_BE#2 C_BE#2 A3 APICCLK C16 APICCLK_ICH 6 C_BE#3 C_BE#3 D6 APICD1 C17 APICD1 4,29 APICD0 E16 APICD0 4,29 6 PCLK_0/ICH PCICLK C14 SERIRQ R4 SERIRQ 14,29 B3 15,23,29 FRAME# FRAME# 15,23,29 DEVSEL# DEVSEL# D9 REQ#0 A14 PREQ#0 15,29 A2 B13 15,23,29 IRDY# IRDY# REQ#1 PREQ#1 29 15,23,29 TRDY# TRDY# C4 REQ#2 B12 PREQ#2 29 STOP#15,23,29 STOP# D5 REQ#3 D12 PREQ#3 23,29 J5 7,13,14,15,16,23 PCIRST# PCIRST# PCI A13 B9 GNT#0 PGNT#0 15,29 PLOCK#15,29 PLOCK# C13 A9 GNT#1 PGNT#1 29 15,23 PAR PAR A12 A1 GNT#2 PGNT#2 29 SERR#15,23,29 SERR# C12 VCC3_3 K1 GNT#3 PGNT#3 23,29 15,23 PCI_PME# PME# R174A A11 RESV0PU N6 RESV[0] 29 PCPCI_REQ#A REQ#A/GPIO0 B11 RESV1PU R175A 8.2K P5 RESV[1] GNT#A/GPIO16 RESV2PD 8.2K RESV[2] F16 29 REQ#B/GPIO1 REQ#B/GPIO1 P4 PC/PCI 29 GNT#B/GPIO17 R5 GNT#B/GPIO17 R181A 0K Electronic Classroom Student Computing Station Ref. Schematic REV For Test/Debug 0.5 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 Don't Stuff R181A ICH0, PART 1 R2 G3 H8 J8 K8 H9 J9 K9 H10 J10 K10 G14 K15 INTEL CORPORATION Last Revision Date:

APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 Sheet: 11 of 33

A A

82801AA , Part 2 VCC3_3 VCC5 VCC3SBY

VCC3_3SBY ICH5VREF VCC3_3SBY VRTC A R203 CR11A R173A CR13A C290A C294A 1K 10K SLP_S5# U14B BAT17 A C R85 1.0UF 0.1UF C G1 N1 L1 C15 R206A BAT17 10K

1K 29 THERM# D14 THRM# 5VREF

C349A VCCRTC SLP_S3#25,28 K3 VCCSUS2 VCCSUS1 1.0UF SLP_S3/GPIO24 JP20A Config. K2 SLP_S5 N12 16 J3 PDCS#1 PDCS#1 1 - 2 Normal 24,25,28 PWROK PWROK L14 27 M2 SDCS#1 SDCS#1 16 2 - 3 Clear CMOS PWRBTN# PWRBTN# U13 19 L3 PDCS#3 PDCS#3 16 VBATC ICH_RI# RI# L16 F1 SDCS#3 SDCS#3 16 R219A JP20A 24,28 RSMRST# RSMRST# VBATC_DLY 1 24 L4 SUS_STAT# SUSSTAT#/GPIO25 R12 PDA0 PDA[2:0] 16 8.2K 2 RTCRST# PDA0

C T12 PDA1 CR14A 3 10,21,24,29 J1 PDA1 1 C364A + SMBDATA SMBDATA P12 PDA2 J2 PDA2 BAT17 JP24_PD 10,21,24,29 SMBCLK SMBCLK SDA0 SDA[2:0] 16 2.2UF SYSTEM SDA0 M16

A M1 2 29 SMBALERT# SMBALERT#/GPIO11 SDA1 R216A SDA1 M15 1K SDA2 R202A SDA2 L13 R_VBIAS 29 INTRUDER# J4 INTRUDER#/GPIO10 1K U6 U11 C347A 6 ICH_CLK14 CLK14 PDDREQ PDREQ 16 6 USBCLK U2 CLK48 SDDREQ P17 SDREQ 16 0.047UF 6 ICH_3V66 A16 CLK66 PDDACK# U12 PDDACK# 16 INTEL 82801AA (ICH) M13 VBIAS H2 SDDACK# SDDACK# 16 VBIAS R11 RTCX1 H3 PDIOR# PDIOR# 16 RTCX1 N16 RTCX2 H4 SDIOR# SDIOR# 16 R197A RTCX2 T11 RTCRST# PDIOW# PDIOW# 16 R220A H1 VBAT RTCRST# PART 2 10M SDIOW# N15 SDIOW# 16 N11 10M T1 PIORDY PIORDY 16 22 AC_RST# AC_RST# SIORDY N17 SIORDY 16 22 AC_SYNC T3 AC_SYNC Y3A AC_BITCLK R3 AC_BITCLK PDD[15:0] 16 + 22 R10 PDD0 X3 T2 PDD0 1 2 AC_SDOUT22 AC_SDOUT AC97 N9 PDD1 U1 PDD1 AC_SDIN022,29 AC_SDIN0 R9 PDD2 P3 PDD2 32.768KHZ AC_SDIN122,29 AC_SDIN1/GPIO9 U9 PDD3 U3 IDE PDD3 27 ICH_SPKR SPKR R8 PDD4 A Socketed C346A C366A PDD4 A U8 PDD5 3vdc Lithium 12PF 12PF D11 PDD5 LPC_SMI#14,29 GPIO5 R7 PDD6 equivalent to 14,29 E11 PDD6 LPC_PME# GPIO6 U7 PDD7 Rayovac BR2325 E9 PDD7 15,29 GPIO7 GPIO7 P7 PDD8 N4 PDD8 29 GPIO12 GPIO12 N7 PDD9 L2 PDD9 29 GPIO13 GPIO13 T8 PDD10 B14 PDD10 JP17A Strap Speaker 29 GPIO21 GPIO21 P8 PDD11 D13 GPIO PDD11 29 GPIO22 GPIO22 T9 PDD12 IN No Reboot on 2nd watchdog timeout D15 PDD12 27 GPIO23_FPLED GPIO23 P9 PDD13 OUT Reboot on 2nd watchdog timeout K4 PDD13 27 GPIO26_FPLED GPIO26 T10 PDD14 M5 PDD14 24 GPIO27 GPIO27 PDD15 JP18A Strap AC_SDOUT PDD15 P10 24 GPIO28 L5 GPIO28 IN Force CPU freq. strap to safe mode (1111) P15 SDD0 SDD[15:0] 16 R6 SDD0 OUT Use CPU freq. strap setting in ICH/0 register. LAD0/FWH013,14 LAD0/FWH0 R16 SDD1 U5 SDD1 LAD1/FWH113,14 LAD1/FWH1 T17 SDD2 T5 SDD2 LAD2/FWH213,14 LAD2/FWH2 U16 SDD3 T4 SDD3 VCC3_3 LAD3/FWH313,14 LAD3/FWH3 LPC U15 SDD4 JP17A U4 SDD4 LFRAME#/FWH413,14 LFRAME#/FWH4 R14 SDD5 ICH_SPKR T6 SDD5 LDRQ#014 LDRQ#0 P13 SDD6 N3 SDD6 JP13_PD LDRQ#129 LDRQ#1/GPIO8 T13 SDD7 R187A SDD7 U14 SDD8 10K 16 R1 SDD8 R209A USBP1P USBP1P T14 SDD9 16 P2 SDD9 10K Minimize Stub Length USBP1N USBP1N P14 SDD10 to Jumpers P1 SDD10 16 USBP0P USBP0P T15 SDD11 N2 USB SDD11 JP18A 16 USBP0N USBP0N U17 SDD12 M4 SDD12 JP14_PU OC#1 R15 SDD13 M3 SDD13 AC_SDOUT OC#016 OC#0 SDD14 SDD14 R17 SDD15 SDD15 P16

C293A Electronic Classroom Student Computing Station Ref. Schematic REV 18PF 82801AA, PART 2 0.5

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A A FirmWare Hub (82802AB) Socket NOTE: This is a Socketed Implementation

VCC3_3 VCC3_3

C211A C355A C361A C259A

0.1UF 0.1UF 0.1UF 0.1UF

VCC3_3 Distribute close to each power pin. X4A 40PIN_TSOP_SKT

1 NC1 GNDA 40 2 IC VCCA 39 3 38 C353A C36A NC3 FWH4 LFRAME#/FWH4 12,14 4 NC4 INIT# 37 INIT# 4,11,29 0.1UF 0.1UF 5 NC5 RFU36 36 6 NC6 RFU35 35 7 FGPI4 RFU34 34 8 NC8 RFU33 33 6 PCLK_6 9 CLK RFU32 32 10 VCC10 VCC31 31 R218A R_VPP 11 VPP GND30 30 0K 12 RST# GND29 29 A 7,11,14,15,16,23 PCIRST# A 13 NC13 FWH3 28 LAD3/FWH3 12,14 14 NC14 FWH2 27 LAD2/FWH2 12,14 15 FGPI3 FWH1 26 LAD1/FWH1 12,14 VCC3_3 16 FGPI2 FWH0 25 LAD0/FWH0 12,14 FWH_ID0 S66DETECT16 17 FGPI1 ID0 24 VCC3_3 FWH_ID1 P66DETECT16 18 FGPI0 ID1 23 FWH_ID2 19 WP# ID2 22 20 21 FWH_ID3 JP21A TBL# ID3

R222A WPROT IC_PD FGPI4_PD FGPI3_PD FGPI2_PD JP21A CONFIG 4.7K IN Unlocked 4 3 2 1 TBLK_LCK 4 3 2 1 OUT Locked Default 0K 8.2K RP63A RP64A

R223A RP64A for 5 6 7 8 5 6 7 8 4.7K Test/Debug

Notes:

VPP and WP# are tied to 3.3v in this configruation Write Protection is register based Electronic Classroom Student Computing Station Ref. Schematic REV with the exception of the Boot Block. FIRMWARE HUB (FWH) 0.5

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A A

VCC3_3 Super I/O VCC3_3 VCC5

R183A 4.7K U15A 44 18 53 65 93

VTR Decoupling 24 VREF VCC1 VCC2 VCC3 66 LFRAME#/FWH412,13 LFRAME# INIT# PAR_INIT# 18 VCC3_3 VCC5 LAD3/FWH312,13 23 LAD3 SLCTIN# 67 SLCTIN# 18 LAD2/FWH212,13 22 LAD2 PDR7 PDR[7:0] 18 Place near LAD1/FWH112,13 21 LAD1 PD7 75 PDR6 VREF pin LAD0/FWH012,13 20 LAD0 PD6 74 1 LPC I/F PDR5 C99A

25 73 + C229A LDRQ#012 LDRQ# PD5 C297A C323A C246A 26 72 PDR4 C287A 7,11,13,15,16,23 PCIRST# LRESET# PD4 PDR3 2 SUSSTAT_PU 27 LPCPD# PARALLEL POR T I/F PD3 71 2.2UF 0.1UF 0.1UF 0.1UF PDR2 0.1UF 0.1UF LPC_PME#12,29 17 PME# PD2 70 PDR1 SERIRQ11,29 30 SERIRQ PD1 69 29 68 PDR0 6 PCLK_1 PCI_CLKSIO PD0 Place 1 0.1UF cap near each power pin SLCT# 77 SLCT# 18 19 KDAT 56 KDAT PE 78 PE 18 19 KCLK 57 KCLK LPC47B27X BUSY 79 BUSY 18 MDAT19 58 MDAT ACK# 80 ACK# 18 19 MCLK 59 MCLK KYBD/MSE I/F ERROR# 81 ERROR# 18 11,29 RCIN# 63 KBDRST ALF# 82 ALF# 18 A20GATE11,29 64 A20GATE STROBE# 83 STROBE# 18

27 IRRX 61 IRRX2/GP34 FAN2/GP32 54 PWM2 27 INFRARED I/F 27 IRTX 62 IRTX2/GP35 FAN1/GP33 55 PWM1 27

84 28 SIO_GP43 C356A C371A 19 RXD#0 RXD1 FDC_PP/DDRC/GP43 19 TXD0 85 TXD1 470PF 470PF 19 DSR#0 86 DSR1# RTS#019 87 RTS1# 88 SERIAL PORT 1 Test/Debug Header 19 CTS#0 CTS1# Unused GPIOs DTR#019 89 DTR1# J23A 90 1 2 A 19 RI#0 RI1# A 19 DCD#0 91 DCD1# 3 4 5 6

19 RXD#1 95 RXD2_IRRX 19 TXD1 96 TXD2_IRTX 19 DSR#1 97 DSR2# 19 RTS#1 98 RTS2# SERIAL PORT 2 SIO_GP60 19 CTS#1 99 CTS2# GP60/LED1 48 SIO_GP61 19 DTR#1 100 DTR2# GP61/LED2 49 RI#119 92 RI2# GP27/IO_SMI# 50 LPC_SMI# 12,29 19 DCD#1 94 DCD2# GP30/FAN_TACH2 51 TACH2 27 GP31/FAN_TACH1 52 TACH1 27 DRVDEN#120 2 DRVDEN1 GP25/MIDI_IN 46 MIDI_IN 20 20 DRVDEN#0 1 DRVDEN0 GP26/MIDI_OUT 47 MIDI_OUT 20 MTR#020 3 MTR0# 20 DS#0 5 DS0# GP10/J1B1 32 J1BUTTON1 20 DIR#20 8 DIR# GP11/J1B2 33 J1BUTTON2 20 20 STEP# 9 STEP# GP12/J2B1 34 J2BUTTON1 20 20 WDATA# 10 WDATA# GP13/J2B2 35 J2BUTTON2 20 FDC I/F 20 WGATE# 11 WGATE# GP14/J1X 36 JOY1X 20 20 HDSEL# 12 HDSEL# GP15/J1Y 37 JOY1Y 20 20 INDEX# 13 INDEX# GP16/J2X 38 JOY2X 20 TRK#020 14 TRK0# GP17/J2Y 39 JOY2Y 20 15 41 20 WRTPRT# WRTPRT# GP20/P17 KEYLOCK# 27 SIO_GP21 20 RDATA# 16 RDATA# GP21/P16 42 SIO_GP22 20 DSKCHG# 4 DSKCHG# GP22/P12 43

SYSOPT REV. 6 CLKI32 CLOCKS GP24/SYSOPT 45 Pulldown on SYSOPT for IO Electronic Classroom Student Computing Station Ref. Schematic 19 address of 0x02E Schematics 6 SIO_CLK14 CLOCKI SUPER I/O 0.5 R180A GND1 GND2 GND3 GND4 AVSS 4.7K Last Revision Date: 7 31 60 76 40 INTEL CORPORATION

APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 Sheet: 14 of 33

A A PCI Connector 0

VCC3_3SBY (DEV Ah) VCC3_3 VCC12- VCC5 VCC5 J17A VCC12 VCC3_3 PCI3_CON B1 A1 B2 A2 B3 A3 PTMS 29 B4 A4 PTDI 29 B5 A5 B6 A6 PIRQ#A 11,23,29 PIRQ#B 11,29 B7 A7 PIRQ#C 11,29 PIRQ#D B8 A8 11,29 B9 A9 B10 A10 B11 A11 B12 A12 B13 A13 B14 A14 B15 A15 PCIRST# 7,11,13,14,16,23 PCLK_2 B16 A16 6 B17 A17 PREQ#0 PGNT#0 11,29 11,29 B18 A18 AD[31:0] B19 A19 PCI_PME# 11,23 11,23 AD31 B20 A20 AD30 AD[31:0] AD29 B21 A21 11,23 B22 A22 AD28 AD27 B23 A23 AD26 AD25 B24 A24 C_BE#[3:0] B25 A25 AD24 R168A 11,23 C_BE#3 R_AD16 B26 A26 AD16 11,23 AD23 B27 A27 100 B28 A28 AD22 AD21 B29 A29 AD20 AD19 B30 A30 B31 A31 AD18

A AD17 B32 A32 AD16 A C_BE#2 B33 A33 B34 A34 FRAME# 11,23,29 11,23,29 IRDY# B35 A35 B36 A36 TRDY# 11,23,29 DEVSEL#11,23,29 B37 A37 B38 A38 STOP# 11,23,29 B39 A39 11,29 PLOCK# B40 A40 23 PERR# SDONEP1 29 B41 A41 SBOP1 29 B42 A42 11,23,29 SERR# B43 A43 PAR 11,23 C_BE#1 B44 A44 AD15 AD14 B45 A45 B46 A46 AD13 AD12 B47 A47 AD11 AD10 B48 A48 B49 A49 AD9 key

AD8 B52 A52 C_BE#0 11,23 AD7 B53 A53 B54 A54 AD6 AD5 B55 A55 AD4 AD3 B56 A56 B57 A57 AD2 AD1 B58 A58 AD0 B59 A59 29 PU1_ACK64# B60 A60 PU1_REQ64# 29 Electronic Classroom Student Computing Station Ref. Schematic REV B61 A61 B62 A62 PCI Connector 0.5

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A A ATA33/66 IDE CONNECTORS

VCC5 VCC5

R133A PRIMARY 1K R100A SECONDARY IDE CONN. 1K IDE CONN.

12 PDD[15:0] 12 SDD[15:0] J15A J12A R140A R139A R_RSTP# R_RSTS# 1 2 16 PCIRST_BUF# 1 2 16 PCIRST_BUF# 33 PDD7 3 4 PDD8 33 SDD7 3 4 SDD8 PDD6 5 6 PDD9 SDD6 5 6 SDD9 PDD5 7 8 PDD10 SDD5 7 8 SDD10 PDD4 9 10 PDD11 SDD4 9 10 SDD11 PDD3 11 12 PDD12 SDD3 11 12 SDD12 PDD2 13 14 PDD13 SDD2 13 14 SDD13 PDD1 15 16 PDD14 SDD1 15 16 SDD14 PDD0 17 18 PDD15 SDD0 17 18 SDD15 19 20 19 20 12 PDREQ 21 22 12 SDREQ 21 22 For Host side 80-c onductor Cable Detection: For Host side 80-c onductor Cable Detection: 23 24 12 SDIOW# 23 24 12 PDIOW# Populate R96A and R221A, Depopulate C187A Populate R95A and R94A, Depopulate C186A 25 26 25 26 12 PDIOR# For Drive side 80-c onductor Cable Detection: 12 SDIOR# For Drive side 80-c onductor Cable Detection: PRI_SD1 PIORDY12 27 28 PRI_PD1 Populate C187A, Depopulate R96A and R221A SIORDY12 27 28 Populate C186A, Depopulate R95A and R94A 29 30 12 PDDACK# 29 30 12 SDDACK# 31 32 31 32 11,29 IRQ14 R96A 11,29 IRQ15 R95A PDA1 R_P66DET SDA1 33 34 R_S66DET 33 34 P66DETECT 13 S66DETECT 13 PDA0 35 36 0K SDA0 35 36 0K 37 38 12 PDCS#1 37 38 PDCS#3 12 12 SDCS#1 SDCS#3 12 27 IDEACTP# 39 40 27 IDEACTS# 39 40

PDA2 SDA2 A 12 PDA[2:0] 12 SDA[2:0] A

C186A R94A C187A R134A R137A R132A

R135A R138A R101A R221A 15K 15K 470 470 10K 5.6K 10K 5.6K 0.047UF 0.047UF

VCC3_3 VCC3_3

14 R141A 8.2K U11C PCIRST_BUF# 7,11,13,14,15,23 PCIRST# 5 OA 6 16

SN74LVC07A REV. GND VCC Electronic Classroom Student Computing Station Ref. Schematic 0.1 7 ULTRA ATA/33 IDE CONNECTORS

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A A USB Connectors

VCC3_3 VCC5 R149A POLYSWITCH RUSB250 22 AC97_USB- 2 0K F3A R148A 2.5A 22 AC97_USB+ R147A 1 Do Not Stuff 0K A330K L23A USBV5 1 2 + 1

22 AC97_OC# C12A R72A C202A

470K 2 68UF R146A 0.1UF Place R204A, R205A, C348A, and C359A 0K within 1" of ICH0 USBV0 Do Not Stuff R204A R13A R_USBP0N USBD0N OC#012 12 USBP0N 15 R205A 0K R15A R_USBP0P USBD0P C124A R201A 12 USBP0P 15 0K 560K .001UF USBG0 R11A R14A

C348A C359A 15K 15K 2 C15A 47PF 47PF L11A 470PF J3A

USB-CON2 1 1 VCC0 GND 9 2 DATA0- 3 DATA0+ GND 12 4 GND0 2 - USB Stack ed L9A 5 1 2 VCC1 6 11 A DATA1- GND A

C9A 7 DATA1+ + 1 8 10 C201A GND1 GND 2 68UF 0.1UF Place R211A, R214A, C358A, and C357A

within 1" of ICH0 C8A C13A C98A USBV1 C16A R214A USBD1N 47PF 47PF 47PF

12 USBP1N 47PF 15 R211A USBD1P Place CAPs as close as 12 USBP1P 15 possible to c onnector. USBG1

C358A C357A R12A R63A 2 C14A L10A 47PF 47PF 15K 15K 470PF 1

REV. Electronic Classroom Student Computing Station Ref. Schematic USB CONNECTORS 0.1

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A A Parallel Port Header

VCC5 CR1A

A C PARV5

1N4148 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5

R224A RP28A RP17A RP13A RP14A 2.2K 2.2K 2.2K 2.2K 2.2K 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4

ERROR#14

RP16A SLCTIN#14 1 8 R_SLCTIN# R_PARINIT# PAR_INIT#14 2 7 R_ALF# 14 ALF# 3 6 4 5 R_STROBE# A 14 STROBE# A 33 RP15A J5A 14 PDR[7:0] PDR0 1 8 R_PDR0 1 2 PDR1 2 7 R_PDR1 3 4 PDR2 3 6 R_PDR2 5 6 PDR3 4 5 R_PDR3 7 8 33 9 10 RP27A PDR4 1 8 R_PDR4 11 12 PDR5 2 7 R_PDR5 13 14 PDR6 3 6 R_PDR6 15 16 PDR7 4 5 R_PDR7 17 18 33 19 20 21 22 14 ACK# 23 24 25 26

14 BUSY

14 PE NOTE: J5A is pinned out for IDC (Flow C91A C93A C88A C96A C92A 180PF 180PF 180PF 180PF 180PF 180PF 180PF 180PF 180PF C197A C194A C192A 14 SLCT# C189A Through) ribbon cable connector. C97A C89A C90A C94A C95A 180PF 180PF 180PF 180PF C196A 180PF 180PF C190A 180PF C193A 180PF

Electronic Classroom Student Computing Station Ref. Schematic REV. PARALLEL PORT HEADER 0.5

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APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 Sheet: 18 of 33

A A

Serial Port/COM Headers VCC12- VCC5 VCC12

U17A COM1 HEADER

GD75232 20 VCC VCC12 1 19 2 DCD#0_C DCD#014 RY0 RA0 18 3 RXD#0_C 14 RXD#0 RY1 RA1 J21A DSR#0_C DSR#014 17 RY2 RA2 4 1 2 DTR#0_C 14 DTR#0 16 DA0 DY0 5 3 4 TXD#0_C 14 TXD0 15 DA1 DY1 6 5 6 CTS#0_C CTS#014 14 RY3 RA3 7 7 8 RTS#0_C RTS#014 13 DA2 DY2 8 9 10 12 9 RI#0_C 14 RI#0 RY4 RA4 11 GND VCC-12 10 VCC3_3SBY Place Close to Header COM1 and COM2 are 2x5 pin 100PF 100PF 100PF 100PF Headers for a cabled port. C368A C325A C329A C327A R230A 10K 100PF 100PF 100PF 100PF C328A C330A C326A C369A

ICH_RI#12 Q10A D

R227A CR15A NOTE: J19A and J21A are pinned out NOTE: If Wake from S3 on G ICHRI#_C RI#_CR_C 3 1 for IDC (Flow Through) ribbon cable 2N7002LT1 connector. Serial Modem is not s upported 47K do not stuff CR14A and Q2A. 2 S

R229A C374A BAT54C 47K 1.0UF

A 2nd COM Header Option A VCC12- VCC12 VCC5 If not populated at all, remove CR14 and short RI#0_C to RI#CR U16A COM2 HEADER

GD75232 20 VCC VCC12 1 DCD#1_C DCD#114 19 RY0 RA0 2 RXD#1_C 14 RXD#1 18 RY1 RA1 3 J19A DSR#1_C DSR#114 17 RY2 RA2 4 1 2 DTR#1_C 14 DTR#1 16 DA0 DY0 5 3 4 TXD#1_C 14 TXD1 15 DA1 DY1 6 5 6 CTS#1_C CTS#114 14 RY3 RA3 7 7 8 RTS#1_C RTS#114 13 DA2 DY2 8 9 10 RI#1_C RI#114 12 RY4 RA4 9 11 GND VCC-12 10

Place Close to Header 100PF 100PF 100PF 100PF C315A C311A C316A C314A C309A 100PF 100PF C313A 100PF C312A 100PF C310A

REV. Electronic Classroom Student Computing Station Ref. Schematic SERIAL PORT/ COM HEADERS 0.5

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A A KEYBOARD/MOUSE PORTS FLOPPY DISK HEADER

VCC5

VCC5 F2A L3A 1 2 PS2V5_F 1 2 RP31A 1 8 1.25A 2 7 PS2V5 3 6 4 5 8 7 6 5 1K RP1A 4.7K STACKED PS2 CO NNECTOR R143A 1K 1 2 3 4 J1A J14A L5A 2 1 1 2 L_KDAT 1 DRVDEN#014 14 KDAT 4 3 2 6 5 3 14 DRVDEN#1 8 7 L4A 4 14 INDEX# 10 9 1 2 L_KCLK Mse 5 PS/2 KybdPS/2 MTR#014 14 KCLK 12 11 6 14 13 L7A 14 DS#0 16 15 1 2 L_MDAT 7 MDAT14 18 17 8 17 PS2GND DIR#14 20 19 9 16 14 STEP# 22 21 L6A 10 15 14 WDATA# 24 23 1 2 L_MCLK 11 14 14 WGATE# 14 MCLK 26 25 12 13 TRK#014 WRTPRT#14 28 27 30 29 C1A C3A C4A C5A C2A 14 RDATA# 32 31 2 14 HDSEL# 34 33 L1A 14 DSKCHG# 0.1UF 470PF 470PF 470PF 470PF PS2_PD 1 2

L2A A A 1

GAME PORT HEADER

RP29A VCC5 R_JOY1X 1 8 JOY1X 14 R_JOY1Y 2 7 JOY1Y 14 R_JOY2Y 3 6 JOY2Y 14 R_JOY2X 4 5 JOY2X 14 NOTE: J7A is pinned out for IDC (Flow Through) ribbon cable connector. 2.2K C199A VCC5 C198A C191A C195A 1 3 5 7 9 11 13 15 0.01UF 0.01UF 0.01UF 0.01UF J7A

VCC5 8 7 6 5 2 4 6 8 10 12 14 16 RP30A

1K 1 2 3 4 R89A R178A 14 4.7K 4.7K J1BUTTON1 J1BUTTON2 14 J2BUTTON2 14 REV. J2BUTTON1 14 Electronic Classroom Student Computing Station Ref. Schematic R88A 0.5 MIDI_OUT14 R_MIDIOUT KEYBOARD/MOUSE PORTS, FLOPPY DISK HEADER, GAME R179A 47 C79A PORT HEADER C178A C179A C182A MIDI_IN14 R_MIDIIN 47 INTEL CORPORATION Last Revision Date: 47PF 47PF 47PF 47PF C177A C176A APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 470PF 470PF CHANDLER, AZ 85226 Sheet: 20 of 33

A A Video Connectors VGA Connector VCC5 VCC1_8

CR10A 2 2 F1A BLM31A700S is rated at 2.5A 1 3 70Ohms at 100MHz 1 L21A R65A R74A BAT54S CRT5V_F 9 VID_RED 1 2 1K 1K BLM11B750S Place R66A,R67A, & R69A Close to VGA R69A C111A Connector 75 C109A 2 1% L12A VCC1_8 3.3PF 3.3PF J6A CR9A 6 6 2 1 L_RED 1 111 1 3 MONOPU 11 BAT54S L20A 7 9 VID_GREEN 1 2 L_GREEN 2 BLM11B750S 12 8 R67A C106A L_BLUE 3 75 C105A L_HSYNC 13 1%

3.3PF 3.3PF FUSE_5 9 MON2PU 4 L_VSYNC 14 5VDDCDA 10 10 5 5 15 R71A 5VHSYNC 15 VCC5 0K C119A CR5A C122A 2 3.3PF 1 3 3.3PF Do Not Stuff C331 and C332 BAT54S 5VDDCCL A A R64A 5VVSYNC 5V to 3.3V Translation / Isolation VCC5 0K VCC5

CR6A C102A C100A CR4A 2 QS4_3V C A 3.3PF 3.3PF C116A C208A C101A 1 3 C112A

8 7 6 5 BAT54S Do Not Stuff C333 and C334 10PF R115A 10PF C227A RP34A 10PF 10PF 4.7K L19A 9 VID_BLUE 1 2 2.2K 0.1UF BLM11B750S U6A 1 2 3 4 VCC1_8 QST3384 R66A CR8A C104A VCC 24 75 C103A 5VDDCDA 1% 9 3VDDCDA 3 1A1 1B1 2 2 3.3PF 4 5 5VDDCCL 3.3PF 9 3VDDCCL 1A2 1B2 1 3 5VHSYNC 9 CRT_HSYNC 7 1A3 1B3 6 5VVSYNC 9 CRT_ VSYNC 8 1B41A4 9 BAT54S 11 1B51A5 10 14 2A1 2B1 15 17 2A2 2B2 16 QSSDA R119A 6 CK_SMBDATA 18 2A3 2B3 19 SMBDATA 10,12,24,29 QSSCL R120A 0K 6 CK_SMBCLK 21 2A4 2B4 20 SMBCLK 10,12,24,29 0K 22 2A5 2B5 23 1 BEA# GND 12 13 BEB# REV. Electronic Classroom Student Computing Station Ref. Schematic VIDEO CONNECTORS 0.5

R59A INTEL CORPORATION Last Revision Date: 2.2K R58A APPLIED COMPUTING PRODUCTS DIVISION 2.2K Do Not Populate 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 Sheet: 21 of 33

A A AUDIO RISER

VCC12 VCC5 VCC5 VCC12- VCC3_3 VCC3_3SBY

J18A

AUDIO_MUTE#B1 AUDIO_PWRDWN A1 GND[0] B2 MONO_PHONE A2 B3 A3 27 AC97SPKR MONO_OUT/PC_BEEP RESV[5] RESV[1] B4 RESV[6] A4 RESV[2] B5 RESV[7] A5 PRIMARY_DN# B6 GND[7] A6 -12V B7 +5VDUAL/5VSBY A7 GND[1] B8 USB_OC A8 AC97_OC# 16 B9 +12V GND[8] A9 GND[2] B10 AC'97_RISERUSB+ A10 AC97_USB+ 16 B11 +5VD USB- A11 AC97_USB- 16

KEY KEY

KEY AMR_CONNECTOR KEY GND[3] B12 GND[9] A12 A RESV[3] B13 S/P_DIF_IN A13 A RESV[4] B14 GND[10] A14 B15 +3.3VD +3VDUAL/3VSBYA15 GND[4] B16 GND[11] A16 AC_SDOUT12 AC97_SDATA_OUTB17 AC97_SYNC A17 AC_SYNC 12 12 AC_RST# AC97_RESET# B18 GND[12] A18 AC97_SDATA_IN3 B19 AC97_SDATA_IN1 A19 AC_SDIN1 12,29 GND[5] B20 GND[13] A20 B21 A21 AC97_SDATA_IN2 AC97_SDATA_IN0 AC_SDIN0 12,29 GND[6] B22 GND[14] A22 AC97_MSTRCLK B23 AC97_BITCLK A23 AC_BITCLK 12

REV. Electronic Classroom Student Computing Station Ref. Schematic 0.5 AC'97 RISER CONNECTOR

INTEL CORPORATION Last Revision Date:

APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 Sheet: 22 of 33

A A

VCC5 VCC3_3SBY VCC3_3SBY VCC3_3SBY VCC3_3SBY LAN R159A 4.7K VCC3_3SBY 5% U13A G13 K13 N8 P12 A11 A3 A7 E1 K3 N6 P2 E12 G5 G6 H5 H6 H7 H8 J5 J6 J7 J8 J9 J10 J11 K4 K5 K6 K7 K8 K9 K10 K11 L4 L5 L9 L10

AD[31:0]11,15 AD0 N7 AD0 AD1 M7 AD1 VCC[0] VCC[1] VCC[2] VCC[3] VCC[4] VCC[5] VCC[6] VCC[7] VCC[8] VCC[9] VCCPT AD2 P6 VCC[10] VCC[11] VCC[12] VCC[13] VCC[14] VCC[15] VCC[16] VCC[17] VCC[18] VCC[19] VCC[20] VCC[21] VCC[22] VCC[23] VCC[24] VCC[25] A12 VCCPL[0] VCCPL[1] VCCPL[2] VCCPL[3] AD2 VCCPP[0] VCCPP[1] VCCPP[2] VCCPP[3] VCCPP[4] VCCPP[5] LILED LILED 24 LAN Decoupling AD3 P5 C11 AD3 ACTLED ACTLED 24 AD4 N5 B11 VCC3_3SBY Distribute aroung Power AD4 SPEEDLED SPEEDLED 24 AD5 M5 C13 Pins Close to 82559. AD5 TDP TDP 24 AD6 P4 C14 AD6 TDN TDN 24 AD7 N4 E13 AD7 RDP RDP 24 AD8 P3 E14 AD8 RDN RDN 24 C184A C261A C165A AD9 N3 AD9 SMBALRT# B10 AD10 N2 AD10 CSTSCHG C5 AD11 0.1UF 0.1UF 0.1UF M1 AD11 PME# A6 PCI_PME# 11,15 AD12 M2 J13 AD12 FLA0/PCIMODE# R164A AD13 LANAPWR M3 AD13 FLA1/AUXPWR J12 AD14 3K VCC3_3SBY L1 AD14 FLA2 K14 AD15 L2 AD15 FLA3 L14 AD16 K1 AD16 FLA4 L13 AD17 E3 AD17 FLA5 L12 AD18 D1 M14

C334A C180A AD18 FLA6 C257A AD19 D2 AD19 FLA7 M13 AD20 D3 AD20 FLA8/IOCHRDY N14 VCC3_3SBY 0.1UF 0.1UF 0.1UF AD21 C1 AD21 82559 FLA9/MRST P13 AD22 B1 AD22 FLA10/MRING# N13 AD23 B2 M12 U18A VCC3_3SBY AD23 FLA11/MINT AD24 8 B4 AD24 FLA12/MCNTSM# M11 93C46 Place C68A/C255A AD25 EEDI A5 AD25 FLA13/EEDI P10 3 EEDI Close to Ball A10 AD26 EEDO VCC B5 AD26 FLA14/EEDO N10 4 EEDO NC2 7

1 1 AD27 EESK C68A B6 M10 2 6 + + AD27 FLA15/EESK EESK NC1 C255A AD28 C6 AD28 FLA16 P9 1 EECS GND

2 2 AD29 C7 AD29 FLD0 F14

4.7UF 4.7UF AD30 A8 AD30 FLD1 F13 5 AD31 B8 AD31 FLD2 F12 FLD3 G12 11,15 C_BE#[3:0] C_BE#0 M4 C/BE0# FLD4 H14 R162A A C_BE#1 FLD5_PD A L3 C/BE1# FLD5 H13 C_BE#2 FLD6_PD 619 R163A F3 C/BE2# FLD6 H12 C_BE#3 619 C4 C/BE3# FLD7 J14 Do Not Stuff EECS EECS P7 FRAME#11,15,29 F2 FRAME# FLCS# N9 11,15,29 IRDY# F1 IRDY# FLOE# M8 G3 M9 11,15,29 TRDY# TRDY# FLWE# R154A LANCL KRUN DEVSEL#11,15,29 H3 DEVSEL# CLKRUN# C8 LAN_TEST 62K R152A STOP#11,15,29 H1 STOP# TEST A13 4.7K PAR11,15 J1 PAR TEXEC D13 PIRQ#A11,15,29 H2 INTA# TCK D14 15 PERR# J2 PERR# TI D12 A2 B12 SERR#11,15,29 R153A SERR# TO R156A R_LANIDS A4 B14 RBIAS10 AD2011,15 IDSEL RBIAS10 R155A 100 RBIAS100 549 PREQ#311,29 C3 REQ# RBIAS100 B13 J3 C12 619 11,29 PGNT#3 GNT# VREF 7,11,13,14,15,16 PCIRST# C2 RST# NC11 D10 6 PCLK_5 G1 CLK NC10 G4 NC9 A14 24 LAN_ISOLATE# B9 ISOLATE# NC8 J4 24 LAN_RST# A9 ALTRST# NC7 L7 NC6 P1 24 L_SMBCLK A10 SMBCLK NC5 D9 24 L_SMBD C9 SMBD NC4 L8 NC3 P14 VIO G2 VIO NC2 H4 NC1 A1 LAN_XTAL1 N11 X1 REV. Electronic Classroom Student Computing Station Ref. Schematic

Y2A 2 LAN_XTAL2 P11 X2 LAN 0.5 VSSPL[0] VSSPL[1] VSSPL[2] VSSPL[3] VSSPT VSSPP[0] VSSPP[1] VSSPP[2] VSSPP[3] VSSPP[4] VSSPP[5] VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] G10 G11 H9 H10 H11 L6 L11 G14 K12 P8 N12 C10 B3 B7 E2 K2 M6 N1 D4 D5 D6 D7 D8 D11 E4 E5 E6 E7 E8 E9 E10 E11 F4 F5 F6 F7 F8 F9 F10 F11 G7 G8 G9 25MHZ C331A C269A C265A 1 INTEL CORPORATION Last Revision Date: 22PF 22PF 0.1UF APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 Sheet: 23 of 33

A A

LAN

VCC3_3SBY

VCC3_3SBY

R108A R144A R145A 330 330 330 R111A 330 JP11_PU JP12_PU JP7_PU J9A JP7A

ACT_CR JP11A JP12A R112A 10 RJMAG 23 TDP TD+ 15 LI_CR ACTLED 12 LA1 23 TDN TD- 330 9 16 LILED 23 RDP RD+ LC1 7 23 RDN RD- 23 LILED RJ-45 13 5 LA2 ACTLED23 R157A R158A R160A R161A RJ-4 23 SPEEDLED Place Termination near 82559 SPEEDLED 50 50 50 50 6 RJ-5 LC2 14 3 RJ-7 4 RJ-8 RD_PDTD_PD TXC RXC TDC RDC SHLD1 SHLD2 1 2 17 18 11 8 C268A C266A TDC RDC Do Not Stuff 0.1UF 0.1UF VCC3_3SBY RXC_PD TXC_PD RJ45_PD RJ78_PD

R215A R107A R110A R106A R109A C213A C212A 4.7K 75 75 75 75 JP8A 0.1UF 0.1UF A 1 A Do Not Stuff 10,12,21,29 SMBCLK R151A 2 JP8_SMBC L_SMBCLK 23 RJMAG_CONN 3 0K 12 GPIO27

C210A Select JP8A/JP9A Default Config: Note: Chassis Ground, Do Not Stuff 470PF-1500V use plane for this signal For EST Testing ICH0 1-2 Default VCC3_3SBY ICH 2-3

Note: Chassis Ground, R186A use plane for this signal 4.7K JP9A

10,12,21,29 1 SMBDATA R150A 2 JP9_SMBD L_SMBD 23 12 GPIO28 3 0K

R210A 12 SUS_STAT# 0K LAN_ISOLATE# 23 R198A 12,25,28 PWROK 0K Do Not Stuff R198A LAN DI SABLE - JP10A NORMAL 1-2 Default 2-3 REV. DISABLE Electronic Classroom Student Computing Station Ref. Schematic JP10A LAN 0.5 RSMRST#12,28 1 2 LAN_RST# 23 3 INTEL CORPORATION Last Revision Date:

APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 Sheet: Note: This circuit is for debug purpose only. CHANDLER, AZ 85226 24 of 33

A A Voltage Regulators

V3SB VCC3_3 VCC3_3SBY 1N5822 VCC 3.3V Standby VOLTAGE SWITCH A C + + + + 1 1 CR2A 1 1 This generates 3.3V Standby Power which is C174A C75A C173A C375A 47UF 47UF NDS356AP 1200uF 1200uF on in S0,S1,S3,S4,&S5. It passes 3.3V from 2 2 2 2 S D the ATX supply in S0/S1, and 3.3VSB (generate d by VR4 below) in S3/S4/S5. VTT 1.5V VOLTAGE REGULATOR Q5A

G Do Not Populate VCC12 NDS356AP VCC3_3 VR5A VTT1_5 S D LT1587-1_5 VOUT 2 R61A 3 VIN 4.7K ADJ 1 Q6A

VCC5SBY G + + 1 1 C43A C270A C225A VCC5SBY Q9A SI4410DY

VCC3_3SBY R87A 2 2 PLANE_CTL1 4 5 1.0UF 100UF

10K 100UF

14 3 6 C U4A U5A Q7A 2 7 14 R83A 32 12,28 1 1 8 SLP_S3# A 3 PCTL_IN 1 2 PLANE_CTL0 V_GQ6 B 2 Y 1 12,24,28 PWROK B 7 0K

74LS132 SN74LVC07A MMBT3904LT1 GND VCC E

7 SN74LVC07Ahas 5V input and output tolerance. Q8A SI4410DY 4 5 3 6 2 7 1 8

A A

VCC 3.3VSB Regulat or VCC 1.8 VOLTAGE REGULATOR VCC 2.5 VOLTAGE REGULATOR VCC1_8 VCC2_5 VCC5SBY V3SB VCC3_3 VCC5

VR2A VR3A VR4A LT1587ADJ LT1587ADJ LT1117-3_3 R55A R56A 2 VOUT 301 2 240 3 1% VOUT 3 IN OUT 2 VIN 3 1% 1 VR1_ADJ VIN

ADJ + GND Place C260A at the 1 VR5_ADJ 1 Place C76A at ADJ C74A + +

1 1 Regulator C59A C57A + 1 C159A +

1 the Regulator 1 C71A R54A C76A C65A

130 R57A 2 2 2 1% 240 22UF 2 2 1.0UF 100UF

100UF 1% 22UF 100UF 0.1UF

REV. Electronic Classroom Student Computing Station Ref. Schematic 0.5 VOLTAGE REGULATORS

INTEL CORPORATION Last Revision Date:

APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 Sheet: 25 of 33

A A Processor Voltage Regulator

VCC3_3 VCC5 VCC5 VCC12

R33A R18A R22A 220 5.6K

L8A 5.1 1.0UH-6.8A

VRM_PWRGD 28 5VIN C21A

1.0UF C7A 1 1 1 1 1 + + C30A C26A C22A C29A + + C27A + R17A

10K 2 2 2 2 2 10UF 0.1UF 1200UF 1200UF 1200UF 1200UF

C20A R20A 2.7K Q2A Q1A

0.01UF 5 6 7 8 5 6 7 8 PV12 D4 D3 D2 D1 D4 D3 D2 D1

VR1A Place CAPs 5 2 Close to FETs SI4410DY 3 VID[3:0] RP4A OUTEN 19 7 IMAX SI4410DY OUTEN IMAX G1 S3 S2 S1 G1 S3 S2 S1 VID0 4 5 R_VID0 18 VCC 13 C24A C25A VID0 PVCC PWRGD VCCVID VID1 R_VID1 4 3 2 1 4 3 2 1 1.0UF 1.0UF 3 6 17 VID1 FAULT# 12 FAULT#_PU VID2 R_VID2 2 7 16 VID2 G1 20 G1 L14A VID3 R_VID3 R19A 1 8 15 VID3 IFB 8 L_VCCVIDR_VCCVID 20 14 1 G2 0.8UH-20A 0K VID4 G2 Q4A Q3A 11 VFB_PD VFB 5 6 7 8 5 6 7 8 COMP SS SGND GND SENSE D4 D3 D2 D1 D4 D3 D2 D1

The LTC1753 incorporates internal pull-ups on VID[4:0]. LTC1753 10 9 4 3 6

If your VR IC does not incorporate these, they must VRCOMP_PD SI4410DY

SS_PD SI4410DY A go on the motherboard. A G1 S3 S2 S1 G1 S3 S2 S1 R16A JP2A JP3A JP4A JP5A 4 3 2 1 4 3 2 1 8.2K

R_VRCOMP C35A C19A C18A C17A 220PF VID Override Jumpers 0.1UF 150PF 0.01UF

C147A 1 1 1 1 1 C58A C28A C54A C31A + + + + + 0.1UF C128A Do Not Stuff C147A 2 2 2 2 2 2700UF 2700UF 2700UF 2700UF 2700UF

Refer to VR supplier for layout guildlines.

REV. Electronic Classroom Student Computing Station Ref. Schematic 0.5 VRM 8.4

INTEL CORPORATION Last Revision Date:

APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 Sheet: 26 of 33

A A

SYSTEM VCC3_3 VCC5

VCC3_3SBY 16V

R217A 1 No stuff. + ICH has internal pullup and de bounce on PWRBTN# R226A For test only 100K C292A 1M 2 10UF C279A R225A 12 PWRBTN# J20A 0K 14 IRRX 0.1UF C370A 1 1.0UF 2 No stuff. 14 IRTX R212A R_IRTX 3 For test only SW2 R213A 82 4 INFRARED 1 2 4.7K 5 VCC3_3 KEY VCC3_3 3 4 6 7 VCC5 VCC3_3 VCC5 PBTN_IN 8 9 POWER SW. R228A 10 R136A R93A R231A U11B 14 11 10K 10K 470 10K SN74LVC07A 12 13 KEY 3 4 14 IDE_ACTIVE 14 H.D. LED 16 IDEACTP# OA 15 VCC5 GND VCC 16 KEY 1 2 16 IDEACTS# OA FP_PD 17 7 U11A 18 R232A KEY POWER LED

GNDSN74LVC07A VCC PWRLED 19

7 220 20 KEY 21 14 KEYLOCK# 22 KEYLOCK 23 24 KEY 25 SPEAKER 22 AC97SPKR R233A VCC5 SPKR_IN R_SPKRIN 26 JP22A 68 VCC3_3 1 Q11A C FNT_PNL_CONN A R234A A 2 R235A 32 12 ICH_SPKR SP1A 3 SPKR SPKR_Q1G B 68 1 + C378A C373A C258A 1 POS 2.2K 2N3904 SPKR_NEG 2 NEG 5 6 7 8 E RP62A 0.1UF 470PF 470PF 4.7K FAN Headers Speaker Circuit 4 3 2 1

VCC3_3SBY VCC12 VCC3_3SBY

VCC12 VCC3_3SBY

C23A

C363A 330 R98A R97A VCC3_3SBY 330 0.1UF 0.1UF VCC3_3SBY J26A J24A R188A On-Board LED indicates the 1 1 14 U5B U5C 14 330 Standby Well is on to prevent 2 2 GP26LED Hot-Swapping Memory. 12 GPIO23_FPLED 3 4 1 2 6 5 GPIO26_FPLED 12 3 3 7 GP23LED 7 For Debug Only SN74LVC07A SN74LVC07A TACH214 CR3A TACH114 V3SBLED

VCC12 2 VCC12 CR12A 4.7K R172A 1

C362A C365A REV. 0.1UF Electronic Classroom Student Computing Station Ref. Schematic J27A J25A 0.1UF SYSTEM 0.5 1 1 2 2 3 3 INTEL CORPORATION Last Revision Date:

14 PWM1 14 PWM2 APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 Sheet: 27 of 33

A A SYSTEM Power Connector and Reset Control

ITP RESET CIRCUIT - FOR DEBUG ONLY

VCC3_3SBY VCC3_3SBY

Power Good Circuit R99A 240

U10A 4 DBRESET# VCC5SBY VCC5 SN74LVC08A 14 VCC5SBY 1 VCC5- 3 DBRST VCC12 APOK_ST 2 VCC2_5 VCC12- VCC3_3 VCC3_3SBY 7 U12A 14 U12B 14

1 2 ST23 3 4 VCC3_3SBY R90A R62A J4A 74LVC14A 74LVC14A 0K 7 7 4.7K U3A 14 R10A U3C 14 11 3_3V11 3_3V1 1 SN74LVC06A has 330 12 2 74LVC14A is 5V i nput 5V input tolerance -12V 3_3V2 tolerant 13 3 1 2 GND13 GND3 AO PWRGOOD 4 5 6 5VPSON 14 4 VCC5SBY 12,25 SLP_S3# AO PS_0N ATX 5V4 15 GND15 GND5 5 DBRPOK SN74LVC06A GND VCC

SN74LVC06A U4B 14 16 GND16 5V6 6 SN74LVC 06A is 5V output GND VCC 17 7 74LS132 7 tolerance GND17 GND7 R91A R92A VCC3_3SBY 7 18 8 ATX_PWOK DBRPOK_DLY 4 -5V PW_OK A 6 PWROK# 19 9 5 Y 5V19 5VSB 0K 0K B VCC3_3SBY C183A 20 5V20 12V 10 Do not stuff 1.0UF GND VCC 14 Do not stuff 7 U3B R200A 4.7K

220 Ohm Pull-up to 3.3V is on VRM Sheet 3 4 AO PWROK 12,24,25 26 VRM_PWRGD A SN74LVC06A A GND VCC R199A

7 1M Do Not Stuff Reset Button For Debug Only SW1

1 2 R24A 3 4 RST_PD 22 JP23A Resume Reset Circuitry + 1 1 2 C45A C185A Schmitt Trigger Logic 0.01UF 10UF

2 using a 22msec delay Place JP23A near front panal header (J20) VCC3_3SBY VCC3_3SBY VCC3_3SBY

U12C 74LVC14A

R142A 14 U12D 14 CLOCK POWERDOWN CONTROL V3RSMRST 5 6 ST69 9 8 RSMRST# 12,24 R86A 22K SLP_S3# 74LVC14A 7 7 8.2K R196A C264A 1M VCC3_3SBY 1.0UF Do Not Stuff CK_PW RDN# 6,25 For Debug Only U10B 14 DBRPOK 4 R84A 6 CK_PWRD 5 0K SN74LVC08A 7 REV. Do not stuff R84A - For debug only. Electronic Classroom Student Computing Station Ref. Schematic If R84A is populated, R86A must 0.5 be de-populated. SYSTEM: POWER CONNECTOR AND RESET CONTROL

INTEL CORPORATION Last Revision Date:

APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 Sheet: 28 of 33

A A PULL-UP RESISTORS AND UNUSED GATES

PCI BUS 82801AA CPU RP59A VCC5 2 VCC5 3 SERR#11,15,23 RP47A VCC3_3SBY 4 VCMOS 4 1 8 PLOCK#11,15 15 SDONEP1 11,15,23 STOP# 5 2 7 11,15,23 6 2.7K 1 3 6 DEVSEL# 15 SBOP1 RP61A 11,15,23 TRDY# 7 4 5 R73A 12 SMBALERT# 1 8 8 4,11 APICD0 11,15,23 IRDY# 5.6K 2 7 9 LDRQ#112 150 FRAME#11,15,23 3 6 R6A 10 12 GPIO12 VCC5 4 5 4,11 APICD1 12 GPIO13 150 9 PULLUP/DOWN RESISTOR PAK RP58A 4.7K 1 8 RP60A 2 7 RP45A 10,12,21,24 SMBDATA 1 8 3 6 11,15 PIRQ#D 2 PTDI15 2 7 3 VCC5 4 5 11,15 PIRQ#C 15 PTMS 10,12,21,24 SMBCLK 3 6 4 PIRQ#B11,15 5.6K INTRUDER#12 4 5 5 VCMOS PIRQ#A11,15,23 4.7K PREQ#311,23 6 2.7K 1 VCC5 VCC3_3 11 PREQ#2 7 RP51A 11 PREQ#1 8 RP56A RP50A 15 PU1_ACK64# 1 8 9 1 8 1 8 PREQ#011,15 2 7 11 REQ#B/GPIO1 4,11 NMI 10 15 PU1_REQ64# 3 6 2 7 CPUSLP#4,11 2 7 3 6 3 6 9 PULLUP/DOWN 4 5 11 GNT#B/GPIO17 STPCLK#4,11 RESISTOR PAK 11,14 4 5 4 5 2.7K SERIRQ 4,11 SMI# 8.2K 330 VCC3_3 RP57A RP52A RP49A 1 8 11,15 PGNT#0 11 PCPCI_REQ#A 1 8 4,11 INTR 1 8 2 7 11 PGNT#1 THERM#12 2 7 4,11,13 INIT# 2 7 3 6 PGNT#211 11,14 RCIN# 3 6 4,11 IGNNE# 3 6 4 5 11,23 PGNT#3 A20GATE11,14 4 5 A20M#4,11 4 5 A 8.2K 8.2K 330 A RP53A LPC_SMI#12,14 1 8 12 GPIO7 2 7 R169 3 6 4,11 FERR# 4 5 330 UNUSED GATES 8.2K VCC3_3SBY RP54A VCC3_3SBY VCC3_3SBY VCC3_3 1 8 2 7 14 U10C 14 12 GPIO22 9 3 6 U12E LPC_PME#12,14 U3E 14 8

14 10 12 GPIO21 4 5 11 10 SN74LVC08A 11 AO 10 7 8.2K For Future Compatibility Upgrade U11D 74LVC14A 7 9 8 U10D R68A OA SN74LVC06A 14 VCC5 GND VCC 14 U12F 12 4 RTTCTRL 11 RP55A 110 1%

GND VCC 13 12 13

7 1 8 SN74LVC07A SN74LVC08A 2 7

7 R70A 7 74LVC14A 14 7 11,16 IRQ14 3 6 4 SLEWCTRL 110 1% U3F VCC5SBY 4 5 14 IRQ15 VCC3_3SBY 11,16 13 12 8.2K

U11E AO 14 U5D SN74LVC06A 14 U4C 11 OA 10 GND VCC 9 8 9 A Y 8 7 10 SN74LVC07A 7 B GND VCC 74LS132 R166A

GND VCC 12,22 7 SN74LVC07A AC_SDIN0 10K 7

14 REV. U5E R170A 14 Electronic Classroom Student Computing Station Ref. Schematic 14 AC_SDIN112,22 0.5 U3D PULL-UP RESISTORS AND UNUSED GATES U11F 11 10 10K 9 8 7 14 13 12 AO U4D OA SN74LVC07A 12 INTEL CORPORATION Last Revision Date: SN74LVC06A A 11 SN74LVC07A Y GND VCC

GND VCC U5F 14 13 B 74LS132 7

7 13 12 GND VCC APPLIED COMPUTING PRODUCTS DIVISION 7 5000 W CHANDLER BLVD. CH6-236 7 SN74LVC07A CHANDLER, AZ 85226 Sheet: 29 of 33

A A 370-pin Socket Decoupling

VCCVID Decoupling Place in 370 PGA Socket Cavity

Bulk Decoupling VCCVID 1206 Packages

C125A C152A C136A C117A C110A C115A C153A C146A C126A C139A C155A C140A

4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF

VCCVID High Frequency Decoupling 0805 Package

C121A C142A C118A C113A C120A C149A C145A C107A C154A C156A C148A C135A C132A C137A C138A C151A C108A C141A C143A C134A

1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF

A A

VTT Decoupling 0603 Package placed within 200mils of VTT Termination R-packs One Capacitor for every 2 R-Packs

VTT1_5

C384A 1 + C33A C34A C129A C11A C32A C133A C144A C150A C157A C218A C220A C219A C205A C221A C42A 22 UF

2 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF

Electronic Classroom Student Computing Station Ref. Schematic REV. 0.5 370-PIN SOCKET DECOUPLING

INTEL CORPORATION Last Revision Date:

APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 Sheet: 30 of 33

A A

DRAM, CHIPSET, and BULK POWER DECOUPLING

82810 Decoupling 82801AA Decoupling Distribute near the 1.8V Distribute near the VCCSUS power pins of the power pins of the 82801AA 3.3V Plane Decoupling: 82801A A 82801A A Place 1 .1uF/.01uF pair in each corner, VCC1_8 VCC3_3SBY VCC3_3 and 2 on opposite sides close to component VCC1_8 if they fit. + 1

C130A C239A C382A C215A C381A 1 C44A C163A C319A C307A C295A C296A C10A C345A C332A C308A C304A C41A C305A C289A C263A C303A C171A + C67A C372A

10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.1UF 0.1UF 0.1UF 0.1UF 2 2 2.2UF

82810 Core Plane De coupling: Place 1 .1uF/.01uF pair in each corner, and 2 on opposite sides close to component if they fit.

VCC1_8

C131A C164A C242A C237A C214A C233A C380A C383A System Memory Decoupling Bulk Power Decoupling 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF

VCC3_3 VCC5 VCC12 VCC5- VCC12-

DIMM0 Decoupling: 1 C62A C333A C321A C367A 2 1 + C360A C80A C70A + C81A 2 VCC3_3SBY 1

C86A C87A C66A C72A C324A C85A 22UF + C82A C83A C317A

Distribute near DIMM0 Power Pins. 22UF 0.1UF 0.1UF 0.1UF 0.1UF + 0.1UF 0.1UF +

0.1UF 2 0.1UF 0.1UF 22UF 0.1UF 0.1UF 1 2 0.1UF 22UF A C69A A 1 2 0.1UF 0.1UF 22UF C84A + 1 C260A C245A C248A C254A C181A C175A 82810 3.3V IO Decoupling: C162A

VCC3_3 Place 3 near System Memory Quadrant 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 2 and 3 near Display Cache Quadrant 22UF

C234A C343A C341A C350A C278A C288A 3 VOLT Decoupling 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF

VCC3_3

C352A C298A C283A C291A C354A C285A C339A C160A C250A C78A C340A C318A C172A C376A C320A C240A C256A C127A C338A C322A

0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF

Electronic Classroom Student Computing Station Ref. Schematic REV. 0.5 DRAM, CHIPSET AND BULK POWER DECOUPLING

INTEL CORPORATION Last Revision Date:

APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 Sheet: 31 of 33

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Electronic Classroom Student Computing Station Ref. Schematic REV. 0.5 REVISION HISTORY

INTEL CORPORATION Last Revision Date:

APPLIED COMPUTING PRODUCTS DIVISION 5000 W CHANDLER BLVD. CH6-236 CHANDLER, AZ 85226 Sheet: 32 of 33

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