Analysis and Identification of Speed-Independent Circuits on an Event Model

Formal Methods in System Design, 4: 33-75 (1994) © 1994 Kluwer Academic Publishers Analysis and Identification of Speed-Independent Circuits on an Event Model M. KISHINEVSKY R&D Coop TRASSA, St. Petersburg, Russia, and Technical University of Denmark, Lyngby, Denmark A. KONDRATYEV, A. TAUBIN, AND V. VARSHAVSKY R&D Coop TRASSA, St. Petersburg, Russia, and The University of Aizu, Japan Received January 17, 1992; revised June 22, 1993 Abstract. The object of this article is the analysis of asynchronous circuits for speed independence or delay insensitivity. The circuits are specified as a netlist of logic functions describing the components. The analysis is based on a derivation of an event specification of the circuit behavior in a form of a signal graph. Signal graphs can be viewed either as a formalization of timing diagrams, or as a signal interpreted version of marked graphs (a subclass of Petri nets). The main advantage of this method is that a state explosion is avoided. A restoration of an event specification of a circuit also helps to solve the behavior identification problem, i.e., to compare the obtained specification with the desired specification. We illustrate the method by means of some examples. Keywords: speed-independent circuits, delay-insensitive circuits, event models, signal graph, analysis, identification, verification 1. Introduction Speed-independent and delay-insensitive circuits seem to be very promising in a number of VLSI applications, for example, in hardware interfacing. Such circuits, which do not use clocks for the ordering of operations, have well-known advantages. They are more robust, they have self-checking properties with respect to stuck-at faults, and they are potentially faster than synchronous circuits in highly parallel and iterative computations, since their correct operation does not depend on worst-case delays of the components [1-3]. The design of these circuits appears to be an intellectual problem requiring skill and experience. In a top-down approach, we start the design from a formal specification and proceed to develop a logic circuit, which implements this specification. Such an approach requires verification of the initial specification followed by a formal method of synthesis [3-6]. Another, bottom-up, approach consists of generating standard library modules, which can be used as building blocks for large-scale circuits [2, 7]. In the top-down design, analysis methods are used for performance evaluation [8] and for dynamic modeling of the circuits. Even if methods of formal design are correct by construction, we still need tools to browse through alternative 34 KlSHINEVSKY, A. KONDRATYEV, A. TAUBIN, AND V. VARSHAVSKY solutions and to choose the best one. In the bottom-up approach, analysis is a kernel of a design method: there is no guarantee that the circuit implementation we have arrived at is correct in both the functional and dynamic sense. The purpose of this article is to present a method of analysis that can be used both in the bottom-up and the top-down design. In [9] we gave a brief discussion of this method. Objects of analysis are asynchronous circuits, specified by netlists of logic functions of components. Analysis problems can be divided in two parts: first, to test the circuit with respect to speed independence and delay insensitivity, and second, to perform behavior identification, i.e., to construct and check "all circuit behaviors" in order to recognize whether the circuit operates as requested. The problem of identification can be decomposed into two independent sub-problems: reconstructing a behavior specification from a netlist of circuit components, and matching this specification with the desired one. In the present article, we check the distributivity property to ensure the cor rectness of circuits. We formally define the distributivity property in section 2.3. This property is sufficient to guarantee the speed independence of a circuit behavior [10]. Distributive circuits are the most popular in a design [2, 8], since both analysis and synthesis of such circuits are much easier than in the general case of speed-independent circuits. It was proved in [2] that any distributive circuit can be implemented without hazards using the minimal basis of NAND gates or, dually, NOR gates. To implement nondistributive speed-independent circuits, one needs either a basis of complex AND-OR-NOT gates or a basis of NAND and NOR gates together. The distributivity property is a necessary but not a sufficient condition for the circuit to be delay insensitive. To test for delay insensitivity, we explicitly introduce auxiliary "WIRE"-components (Le., buffers) into all wire connections that have to be checked. The behavior of distributive circuits can be specified with an event-based model, called signal graphs, with only one type of causal relations (AND type): an event can occur only if all its predecessors have occurred. Distributive circuits do not include circuits with OR-causal relations between signal transitions. Any circuit with an OR gate (or, dually, AND gate) has an OR-causal relation, and, hence, is not distributive, if concurrent transitions of the type 0 --t 1(1 --t 0) can occur at the inputs of the gate. A small example of a circuit with an OR-causal relation is given in figure 2. The parallel compression circuit (Figures 4.6 and 11.2 in [2]) used to perform a code membership test for a double-rail 4-phase communication is a practical example of a nondistributive speed-independent circuit. Circuits with a nondeterministic choice, like the arbiters, are also excluded. In subsection 8.2 we give an example of the SELECT element, where the internal implementation of the circuit is not distributive, and not even speed independent, but its behavior at the external terminals appears distributive. This can be viewed as a useful technique for dealing with the limitations of the class of distributive circuits, based on hiding a non distributive behavior inside circuit modules. ANALYSIS AND IDENTIFICATION OF SPEED-INDEPENDENT CIRCUITS 35 The summary of the results of the article is as follows. 1. We present an efficient algorithm that, given a circuit and an initial state, verifies whether a circuit is distributive and extracts a signal graph specifying a circuit behavior. 2. The algorithm considers signal transitions instead of states. In principle, a distributivity test and an identification of a circuit behavior can be solved in a straightforward manner by derivation of the whole set of global states of a circuit. However, such a straightforward procedure is not suitable for practical use due to the exponential complexity. A partial ordering of the signal transitions leads to an. algorithm in which a state explosion is avoided. 3. The partial ordering of signal transitions is based on properties of distributive circuits that were introduced by D. Muller [10]. We show how Muller's ideas of cumulative states help in a derivation of the partial ordering of signal transitions used in our algorithm. 4. In particular, we introduce a notion of "basic cumulative states" and show that for any given signal there is a unique sequence of basic states with one state for each signal transition. In other words, for a distributive circuit the sequence of possible basic states for any particular signal is totally ordered. The ordering or concurrency of transitions of two different signals can be determined by comparing their basic cumulative states. 5. We show that there are three major factors that allow us to reduce the search space for basic states and corresponding signal transitions down to a polynomial size, namely: a real interconnection between the circuit gates, a "maximal parallelism strategy" for generation of signal transitions, and the concurrency between transitions. Unlike previous analysis techniques based on a search for all operational states of a circuit, this algorithm searches for all so-called "active sets of signal transitions." These active sets of transitions correspond to those "noninertial" states of a circuit, in which either new signal transitions or distributivity errors can be expected. The method proposed depends exponentially on the extremely small parameter-the number of concurrent signal transitions at the inputs of one circuit gate. Therefore the number of active sets and noninertial states is typically a linear function of the number of signal transitions. 6. Based on the notion of active sets we derive conditions for the generation of a new signal transition and for the simultaneous distributivity test. A criterion to halt the process of analysis and to fold an extracted acyclic signal graph into a cyclic one is given. The organization of this article is as follows. In section 2, we define the low-level model of asynchronous circuits, called the Muller model, together with the related binary state model, called a transition diagram, and the integer state model, called a cumulative transition diagram. We then define classes of semimodular and distributive circuits and show that 36 KISHINEVSKY, A. KONDRATYEV, A. TAUBIN, AND V. VARSHAVSKY for both of these a "local criterion" of correctness does exist in terms of global states of a circuit. In this section we mainly review the work of D. Muller [10] and ourselves [2]. Section 3 defines an event model called signal graphs and describes its prop erties. Section 4 defines basic states of a circuit and presents their unique properties. A one-to-one correspondence does exist between so-called basic states and signal transitions of a distributive circuit. The key pieces of the algorithm are derived in sections 5 and 6. In section 5 we show major factors that allow us to reduce the search space for basic states down to a polynomial size. We define active sets of signal transitions and give a criterion for the generation of signal transitions (subsection 5.3), as well as criteria to test for distributivity simultaneously with the generation of a new signal transition (subsection 5.4).

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