Memristor-Based Memory: the Sneak Paths Problem and Solutions

Memristor-based memory: The sneak paths problem and solutions

Item Type Article

Authors Zidan, Mohammed A.; Fahmy, Hossam A.H.; Hussain, Muhammad Mustafa; Salama, Khaled N.

Citation Zidan MA, Fahmy HAH, Hussain MM, Salama KN (2013) Memristor-based memory: The sneak paths problem and solutions. Microelectronics Journal 44: 176-183. doi:10.1016/ j.mejo.2012.10.001.

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DOI 10.1016/j.mejo.2012.10.001

Publisher Elsevier BV

Journal Microelectronics Journal

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Link to Item http://hdl.handle.net/10754/250453 Memristor-based Memory: The Sneak Paths Problem and Solutions

Mohammed Aﬀan Zidana, Hossam Aly Hassan Fahmyb, Muhammad Mustafa Hussaina, Khaled Nabil Salamaa

aElectrical Engineering, King Abdullah University of Science and Technology (KAUST), Thuwal 23955-6900, Saudi Arabia bElectronics and Communication Department, Faculty of Engineering, Cairo University, Cairo, Egypt

Abstract In this paper, we investigate the read operation of memristor-based memories. We analyze the sneak paths problem and provide a noise margin metric to compare the various solutions proposed in the literature. We also analyze the power consumption associated with these solutions. Moreover, we study the eﬀect of the aspect ratio of the memory array on the sneak paths. Finally, we introduce a new technique for solving the sneak paths problem by gating the memory cell using a three-terminal memistor device. Keywords: Nanotechnology, Memory, Memory Array, Memristor, Sneak Paths

1. Introduction One of the main challenges facing the memristor at the circuit and architecture level is the sneak paths problem. In this paper ff Memristors (memory resistors) o er a promising alternative we introduce a new way to analyze the sneak paths using nor- to conventional memory devices. According to the Interna- malized noise margins. Our analysis is based on simulations for tional Technology Road-map for Semiconductors (ITRS), cur- different memory array sizes, data sets, and architectures using rent memory technologies (DRAM, SRAM, and NAND Flash) the models presented in [17]. Moreover, we study the effect of will soon be facing design challenges related to their contin- the aspect ratio of the memory array on the sneak paths. Finally, ued scaling-down [1]. Memristors are considered to be a very a new method is introduce for solving the sneak paths based on good candidate for future memory devices when compared to a new gating technique by using three-terminal memistor device other emerging technologies such as Magnetoresistive RAM as a gate for the memristor memory cell. / (MRAM) and Phase Change RAM (PCM PCRAM) [2]. The The following section discusses the main concept of the main advantage these emerging technologies share is the prop- memristor-based memory. The Section 3 describes the sneak erty of retaining data after bias removal. Moreover, memristor- paths analysis, and Section 4 summarized the main solutions based memories have many unique advantages including very for the sneak paths that have been described in the literature. high density compared to other memory technologies and hard Then, the new proposed solution is given in Section 5. disk drives. The memristor is a nonlinear resistor which changes its state relative to the net charge (or net electric flux) passing through 2. Memristor-Based Memory its two terminals. It saves its state after an electrical bias is removed. The memristor (M), which was described by Chua Memristor-based memories are fabricated as a high-density in 1971 [3], is generally thought of as the fourth of the two- crossbar architecture. Memristor devices are located at each terminal basic passive elements, alongside the resistor (R), ca- intersection between two bars, as shown in Fig. 1. Typical pacitor (C), and inductor (L). The first reported passive imple- memristor-based memories do not use transistors for cell gat- mentation of the memristor was the TiO2-based device intro- ing. The advantage of these devices is that they have a retain- duced by HP in 2008 [4]. Recently, devices based on different able memory and a very high density compared to other storage materials have been introduced [5–9]. In addition, several models for memristors has been introduced [10–16]. Since the first reported use of the memristor, it received a significant of at- tention in the research community. In addition to be used as a memory element [2, 17–26], the memristor has found many applications in oscillators [27–30], logic and arithmetic circuits [31, 32], programmable analog circuits [33, 34], and in modeling and emulation of natural phenomena [35, 36].

Email addresses: [email protected] (Mohammed Aﬀan Figure 1: A simple memristor-based memory array showing Zidan), [email protected] (Hossam Aly Hassan Fahmy), how a memristor device is located at the intersection between [email protected] (Muhammad Mustafa Hussain), [email protected] (Khaled Nabil Salama) two bars of the array.

Preprint submitted to Microelectronics Journal October 29, 2012 Table 1: Detailed comparison between memristor-based memory, traditional memories, and other emerging memories according to the 2011 ITRS report [1]. The abbreviations used are: T – transistor, C – capacitor, R – resistor, and D – diode. The bold font indicates the best value per row.

Traditional Memories Other Emerging Technologies Redox DRAM SRAM NOR Flash NAND Flash FeRAM MRAM PCRAM Including Memristor Cell Element 1T1C 6T 1T 1T 1T1C 1(2)T1R 1T(D)1R (1D)(1T)1R Feature Size (nm) 36-65 45 90 22 180 65 45 9 Density (Gbit/cm2) 0.8 - 13 0.4 1.2 52 0.14 1.2 12 154 - 309 Read Time (ns) 2-10 0.2 15 100 45 35 12 <50 Write Time (ns) 2-10 0.2 107 106 65 35 100 0.3 Retention Time 4-64 ms N/A 10 years 10 years 10 years >10 years >10 years >10 years systems. of finding a needle in a haystack. Moreover, the reading oper- Table 1 shows a detailed comparison between memristor- ation itself could be destructive to the cell data, depending on based memory, traditional memories, and other emerging mem- the device properties. ories. The memristor memory is 4x as dense as the hard disk drive (HDD) [37], and 23x as dense as DRAM. As a result, 2.3. Multilevel Memory memristor-based memories are a good candidate for replacing Multilevel memory is one promising application for the both the permanent and running storages, therefore approaching memristor device. Using such a technique would enormously the ideal model of having one flat memory instead of memory increase the density of memristor-based memory, but would hierarchy. The current reading and writing speeds are slower also reduce the noise margin significantly. The current pro- than DRAM and SRAM, but are very fast compared to flash posed techniques for building binary memristor-based memory memories, as shown in Table 1. These numbers show that mem- suffer from many problems that could be fatal for the multi- ristors could easily replace flash memories, while further speed level memory. Some researchers believe 1M is insufficient for enhancement is required for replacing CMOS memories. HP building multilevel memory, and that 1M1T (one memristor and Labs are currently reporting a fast switching time of less than one transistor) or 1M1D (one memristor and one diode) are 2ns [38]. Recently, Elpida Memory Inc., reported the develop- needed [42]. We believe that addressing the current challenges ment of a high-speed non-volatile resistance memory [39]. It is facing the binary memristor-based memory will directly solve to be noted that any resistor with a hysteresis curve is consid- the multilevel memory problems. ered a memristor [40]. HP Labs expects to come up with their memristor-based memory chip replacing flash and solid-state drives (SSD) in 2013 [41]. 3. Sneak Paths Analysis Sneak paths are undesired paths for current, parallel to the 2.1. Writing Operation intended path. The source of the sneak paths is the fact that the crossbar architecture is based on the memristor as the only Data are stored in the memristor in the form of its resistance memory element, without gating. Fig. 2a shows an array with value, where each of the limiting resistances Ro f f and Ron are a simple voltage divider and its equivalent circuit. The figure assigned to the two Boolean values ‘0’ and ‘1’. Ro f f and Ron are shows the ideal case in which the current flows from the source the maximum and minimum resistances of the device, respec- to the ground passing through only the desired cell at the inter- tively. Writing one of these values is simply done by passing section between the activated column and row. Unfortunately current through the cell of interest until the memristor’s resis- this is not the real case as shown in Fig. 2b. The current flows tance saturates. The saturation value (Ron or Ro f f ) depends on through many sneak paths beside the desired one. These paths the direction of the writing current. Even this simple writing act as an unknown parallel resistance to the desired cell resis- operation could consume considerable of energy, depending on tance as shown in Fig. 2b. What makes the sneak paths problem the values of the memristor’s resistances. harder to solve is the fact that the paths depend on the content of the memory. This is due to the fact that the current will sneak 2.2. Reading Operation with more intensity through the paths with smaller resistance, which is memory content dependent. While writing to the memristor is a straightforward opera- The added resistance of the sneak paths significantly narrows tion, reading is more challenging. In the memristor memory the noise margin and reduces the maximum possible size of a array, we are trying to sense a cell resistance merged in a com- memristor array. To study the effect of the sneak paths on the plete resistive structure. This could be compared to the problem noise margin, we simulate memristor-based memory arrays of 2 VR VR VR VR

RM RM RSP

Vo Vo

R RL L V V o o Memristor RL RL Desired Path Sneak Path

(a) (b)

Figure 2: The reading current path through a memristor memory array and the equivalent circuit for (a) the ideal case where the current flows only through the target cell and (b) an example of a real case where current sneaks through different undesired paths. The green lines show the desired path and the red ones show the effective sneak paths.

different sizes and with different data sets. The sets are selected where a and kx are constants. The reported feasible values −1 −8 to reflect both the worst and best cases for the memory content. in [17] for the constants are a = 3 and kon = 10 A and −11 The worst case for the sneak paths is a memory full of “ones” ko f f = 10 A for the ON and OFF states of the device respec- since the effect of the sneak paths becomes more dominant as tively. their resistance decreases. On the other hand the “all zeros” In conventional CMOS circuits, there are two regions defined case is the best case condition since all the sneak paths are made for accepted values of ONEs and ZEROs [43], as shown in of Ro f f resistances in series. In addition to the previous cases, Fig. 4. For typical CMOS circuits, the prefect ONE has the checkered cases typical of real data and interleaved rows (or value of VOH = Vdd and the perfect ZERO is VOL = GND. columns) are also used. These cases are considered as normal However, the circuit can tolerate shift in values of the input of test cases since ones and zeros are present in equal numbers and certain bounds called noise margins. are uniformly distributed. The simulation result is independent In the case of memristor memory sensing, the value detected of the location of the cell in the array if we neglect the rows’ for ONE or ZERO depends on the severity of the sneak-path and columns’ pad resistances. We can interpret the array as a noise. For a given data pattern stored in the memory, the differ- complete sphere, since connecting the terminals of each row or ence between voltages values representing ONE and ZERO at column will not introduce any change to the equivalent circuit the target cell is a perfect measure for the sneak-path effect. as shown in Fig. 3. Hence all the cell locations are equivalent We define a total noise margin as the region between the ON from the sneak paths point of view. All the simulations were and the OFF states, such that: made on Cadence Virtuoso 6 with a reading voltage (VR) of . Ω ’1V’ and a load resistance (RL) of 19 76M . ∆ = VOne − VZero (2) As our basic building block, we used the model in [17] for the memristor as a memory cell, such that: where VOne and VZero are values for the sensing circuit output (voltage divider) in the case of ONE and ZERO stored in the = IM kx sinh(aV) (1) desires cell. This value is proportional to the noise margin such that is equal to twice the margin if no guard region is assigned.

VOH NMH

≡ Grading Region NML VOL

Figure 4: Traditinal CMOS noise margines, where Voh and Vol are the maximum and the minimum voltage outputs of the cir- Figure 3: Two equivalent arrays from the sneak paths point of cuit respectively. NMH abbreviates Noise Margin High and view. NML abbreviates Noise Margin Low.

3 ﬀ To study the e ect of the array size on the sneak-paths we de- All Zeros Checkered Interleaved All Ones ﬁned a normalized value, where the ∆ is compared to its best case, as: 1 0.8 ∆Array ∆′ = (3)

∆Device ' 0.6 Δ where ∆Device is the case of one device used (the best case) while 0.4 ∆ ∆ Array is for the array case. Array is highly dependent on the 0.2 data stored in the memory as shown later. 0 4 16 64 256 1024 4096 16384 3.1. Floating Array Array Size The basic structure for a memory array is to leave the un- (a) Floating terminals used array terminals floating. Simulation results for the float- ′ ing memristor array are shown in Fig. 5a. The figure shows ∆ All Zeros Checkered Interleaved All Ones versus the array size for four different data sets. The simulations show that the noise margins of both the “all ones” and the 1 “interleaved” cases almost vanish at a very small array size of 0.8 4kbit. At the array size of 16kbit, ∆′ reaches a negligible value

' 0.6 of 0.00145 and 0.00323 for the “all ones” and the “interleaved” Δ cases respectively. This shows how the sneak paths affect the 0.4 noise margins and consequently limit the maximum capacity of 0.2 the array. On the other hand, the noise margin for the best case condition is almost unaffected by the array size. The reason 0 3 4 16 64 256 1024 4096 16384 for this is that the large Ro f f /Ron (ko f f /kon) ratio of 10 makes Array Size sneak paths of resistances Ro f f in series ineffective. (b) Grounded columns 3.2. Grounded Array All Zeros Checkered Interleaved All Ones Grounding the unselected rows and columns might be considered as a mean of preventing sneak paths. In [20] the equiv- 1 alent circuits for all the possibilities of grounding the floating 0.8 terminals are given. None of the four possibilities of: 1) float-

' 0.6 ing rows and columns, 2) floating rows and grounded columns, Δ 3) grounded rows and floating columns, and 4) grounded rows 0.4 and columns, could solve the sneak paths problem. The idea 0.2 behind grounding the floating terminals is to provide paths for the sneaking current to the ground rather than the sense cir- 0 cuit. However, part of the current will still find its path to the 4 16 64 256 1024 4096 16384 ground through the load resistance. Effectively grounding rows Array Size or columns or both will move part of the unknown resistance (c) Grounded rows of the sneak paths so that it is parallel to the total resistance of All Zeros Checkered Interleaved All Ones the equivalent circuit instead of RM, which does not solve the problem. 1 While grounding the array’s floating terminals does not solve the sneak paths problem, it does marginally improve the noise 0.8 ′ ∆ margin. Fig. 5b-d shows the simulation results for versus the ' 0.6 array size for the grounded terminals cases. For the grounded Δ rows and columns case, the simulations show that the noise 0.4 margin still vanishes as the array size increases but at a slower 0.2 rate than in the floating terminals case. At an array size of ′ 0 16kbit, ∆ reaches a negligible values of 0.052 and 0.096 for the 4 16 64 256 1024 4096 16384 “all ones” and the “interleaved” cases respectively, but on the Array Size other hand these values are higher than for the floating terminals (d) Grounded rows and columns case. The two cases of grounding either columns or rows show slightly better results. This is due to fact that grounding both Figure 5: Noise margins (∆′) versus the array size containing rows and columns at the same time is equivalent to short circuit four different data sets. any element not in the selected row or column. Since each of 4 grounded terminals solution impractical. Also, at large array W 10 μ sizes, the improvement in the noise margin is impractical since the margin almost vanishes. 1

4. Sneak Paths Solutions 0.1 In this section the main solutions proposed in the literature

Power Consumption/ Power for the sneak paths are discussed. 0.01 4 16 64 256 1024 4096 16384 Array Size 4.1. Multistage Reading

Floating (All Ones) Floating (checkered) This method was introduced in [17] by the HP Labs team. Grounded (All Ones) Grounded (checkered) Their technique attempts to overcome the sneak paths problem Ideal Case using a straightforward, but long, algorithm. The reading pro- cedure is given as: 1) perform current measurement for the tar- Figure 6: Power consumption versus array size plotted logarith- get cell, 2) put the target cell in the OFF state, and perform mically for the cases of grounded and floating array terminals. current measurement for the target cell, 3) put the target cell in The dotted line shows the ideal case without the sneak paths the ON state, and perform current measurement for the target ff e ect. cell, 4) compare the measured currents to determine the state of the cell, and 5) return the memory cell to its (assumed) original state. This sensing algorithm requires a large amount of time these unselected elements two terminals will be connected to and also a large sensing circuit (three sample-and-hold circuits, ground. Therefore, the total resistance of the sneak-path will a voltage comparator, voltage divider, and the control circuit). be less than the case of grounding either rows or columns sepa- This technique will also be inefficient for the narrow noise mar- rately. gins at large array sizes, since the effect of sneak paths will The main disadvantage of the grounded technique is the huge dominate and the resistance value of the target cell will be neg- power consumption for the reading operation compared to the ligible. According to the simulations shown in Fig. 5a, ∆′ could floating terminals case. Fig. 6 shows a logarithmic plot of be as low as 0.00145 for an array size of only 4kbit. the average power consumption for the cases of floating and grounded terminals. The figure shows the enormous increase in power consumption for the grounded terminals case com- 4.2. Unfolded Architecture pared to the floating terminals case. Fig. 7 shows that the in- This solution is presented in [20], and is based on having a crease in power consumption is much more than the increase separate column for each memristor, as shown in Fig. 8. While in noise margin. At an array size of 16kbit, an average power this solution eliminates the sneak paths problem, it enormously . µ of 12 77 W is consumed in the grounded terminals case, com- reduces the memory density. The decreased density can be de- . pared to 48 88nW in the case of floating terminals, i.e. power fined as: consumption in the grounded terminals case is higher by a D factor of 261.2. This level of power consumption makes the D = o (4) u f no. of rows

Delta' ratio Energy consumption ratio where Du f is the new density of the unfolded architecture and 300 Do is the original density. An array with only one row will also eliminate the eﬀect of sneak paths while occupying much less grounded value 250 ratio = area than the unfolded architecture. floating value 200

150

100

0 1 4 16 64 256 1024 4096 16384 Array Size

Figure 7: Ratio of power consumptions and noise margins for the grounded array versus the ﬂoating one. Figure 8: Unfolded architecture.

5 4.3. Diode Gating Ro f f ”, as introduced in [47]. Having always a high resistance One of the proposed solutions for the sneak paths is to add cell reduces the sneak-path current significantly. In this method a diode to each memory cell [20], producing a new cell of one ONE is distinguished from the ZERO by the orientation of the { } { } diode and one memristor (1D1M), as shown in Fig. 9. Such desired cell, Ron, Ro f f or Ro f f , Ron . Therefore, a complex a strategy would eliminate sneak paths. According to [44], reading technique is required. Moreover, the system will not / adding diodes to the array will increase the delay of the sys- take full advantage of having high Ro f f Ron device. tem by adding capacitive loads and diode threshold voltages will decrease the output swing. However, the major problem 4.6. Using Memristors Nonlinearity facing such a strategy is that it will block the writing process in The voltage drop on the desired cell is higher than any of the the native array structure, since writing to a memristor requires sneak-path elements, since the shortest sneak-path will contain two different polarities. In [45] a 3D array structure is provided at least three series memristors. In [48], a high nonlinear device to enable the write operation with a diode present. In this tech- is reported, such that I(V/2) ≈ I(V)/100 at V ≈ 1V. This very nique, each cell will contain one programming element, two useful property will significantly reduce the sneak paths current diodes, and four connecting crossbars. While this technique al- relative to the desired cell current, and will consistently reduce lows the write operation, it consumes more area per cell. In the sneak-path effect by a high factor. This solution also will addition, the 3D alignment for four bars may reduce the array not be practical for large memory array. density significantly. Finally, it is not clear that the new structure containing four bars will still eliminate the sneak paths. 4.7. AC Sense Instead of using regular DC signal an AC signal is used for 4.4. Transistor Gating sensing the data stored in the desired cell, as introduced in [49]. This technique uses load capacitance at the input of the sense Using large transistors for gating the memristor will solve amplifier to implement a low pass filter, as shown in Fig. 10. the sneak paths problem. On the other hand this method will The response of the filter is mainly based on the resistive value ruin the high memristor-memory density, since the gating tran- of the desired cell. However,this method adds extra complex- sistor’s size is much larger than that of the memristor.Although ity for the memory system, since AC input and sensing are re- using small devices will reduce the sneak paths it will not elim- quired. Moreover, this method will not be as effective for large inate it. This is due to the fact that the recently introduced small arrays. transistors are consider to act as leaky valves. Moreover, these devices with relatively high OFF current will increase the static power component significantly. Finally, it should be mentioned that one of the major issue of using transistor gating is its limi- tation to the 3D stacking of memristor arrays. In [46] an array of one transistor and one memristor (1T1M) is reported. They report a gating transistor of 10µm channel length and 200µm channel width. Moreover, two wires are required for driving each cell; one for the transistor and one for the memristor.

4.5. Complimentary Memristors In this technique two complimentary memristors are used a Figure 10: Simple memory array showing the added column the memory cell, so that their total resistance are always “R + on capacitors for the AC sense.

5. Array Aspect Ratio R

o ﬀ

w In this section we study the e ect of the aspect ratio on the

S performance of memristor array. Non-unity aspect ratio could e l e

c be thought of as a helping method towards a sneak-paths free t o

r memory. The aspect ratio of an array is defined as its number of columns to the number of rows. Normal square arrays have aspect ratios of unity. The aspect ratio of the memory array is one of the main parameters which could be used to limit the effect of the sneak paths. A memory with one row or one col- Sensing Circuit umn will not suffer from sneak paths at all, since there will be only one path for the current as shown in Fig. 11. As the aspect Figure 9: Simple memory array with 1D1M used for each mem- ratio approaches unity, the possibilities for sneak paths increase ory cell. and ∆′ decreases. An unbalanced aspect ratio structure could 6 Fig. 12 shows the simulation results for the noise margin ∆′ versus the aspect ratio for different array sizes. The simulations are made for array structures with both floating and grounded terminals with the “all ones” data set (the worst case). In gen- eral the simulations show that the minimum values for ∆′ occur 8:2 ff 4:4 at an aspect ratio of one. Conversely, the sneak paths e ect dis- appears completely for the cases of a one-row or one-column array. By comparing Fig. 12a and Fig. 12b we can see that the rate of decay of the noise margin with aspect ratio is much faster 16:1 in the floating case than the grounded one. For the grounded arrays, the noise margin depends mainly on the number of rows Figure 11: Examples of different organizations with different rather than the aspect ratio. This is due to the fact that the cur- aspect ratios for a 16-cell memory array. rent sneaks mainly through the columns near the active cell, regardless of the total number of columns. be fabricated in a square area by folding the array in a zigzag shape. However, the main cost of using an aspect ratio other 6. Gating Using Three-Terminal Memistor Device than one is the increase in the required area for selection and sensing circuitry. This area could be given as: Memristors can be considered better gates compared to tran- [ ] sistors or diodes, since they can be characterized by having very √ θ √ = √ + ρ high OFF resistance with much smaller area. In [17], memristor Sense Circuit Area S A (5) = Ω A devices are reported to have Ro f f 1G . Moreover, memristors are not intruder species to the memory array, compared to θ where S is the array size, A is the aspect ratio, is the column transistors and diodes. However, it is not possible to write on ei- ρ cell area, and is the row cell area. ther the gate memristor or the data memristor separately, given / 4 16 64 256 1024 a device with high ON OFF ratios of more than one hundred. 1 Also, trying to introduce extra rows or columns to enable separate writing will return us to the initial point, where the sneak 0.8 paths are dominant. The three-terminal memistor device captures both of the 0.6 advantages of the memristor and transistor as a gate device.

' Δ This device was introduced prior to the memristor in 1960 by 0.4 Widrow [50]. The memistor is a three-terminal device where

0.2

Aspect Ratio (a) Floating terminals 4 16 64 256 1024 1

0.8

0.6

' Δ 0.4

0.2

0 Desired Cell Data Device Aspect Ratio ON Memistor OFF Memistor (b) Grounded terminals

Figure 12: Noise margin (∆′) versus aspect ratio for diﬀerent Figure 13: Structure of the proposed memristor gated array, array sizes. where an example of selected of selected cell is shown.

7 the resistance between two terminals is controlled using the Floating Terminals (All Ones) Memristor Gating (All Ones) 50 third one, in the same analogy of transistor but with a mem- 45 nW ory effect. In other words, the resistance of the device is con- 40 trolled by time integral of the current on the third terminal and 35 30 not the instantaneous current as the case of transistor, as stated 25 be in [50, 51]. This means that there is no need to keep an ac- 20 tive bias on the third terminal to keep the device ON (or OFF). 15 The memistor will retain is ON or OFF state after removing the 10 5 bias from the third terminal. One of the advantages of this bias- Consumption/ Power 0 less switching is the very low static power consumed. Memis- 4 16 64 256 1024 4096 16384 tors can inherent the high ON/OFF ratio and small footprint of Array Size memristors and the high controllability of transistor by having a third terminal. Fig. 13 shows the structure of the memistor Figure 15: Average power consumption versus the array size for gated array, where each memory cell is gated with a memis- the normal array with floating terminals and the new introduced tor device. Extra columns are required for programming the memistor gated array for “All Ones” data set. memistor gate. It is a assumed that the memistor has the same ON/OFF values of the data cell. At the desired cell the gate de- ff vice is turned ON and all the other gates are turned OFF, which e ect, where the worst case of the memistor gating is almost as is how the desired cell is selected. Therefore, all the sneak paths the best case of the normal array with floating terminals. For will contain at least three series high resistances. This will shift 16Kbit array the memristor gating architecture noise margins is the operation of the memory to work equivalently to the best 619.5x compared to the normal array with floating terminals. In case scenario, where all the sneak paths are made of OFF de- the same direction, the worst case power consumption is signif- vices. icantly decreased as shown in Fig. 15. For the worst case with the memory filled with “all ones”, average power consumption All the unselected cells will have a total resistance higher was reduced more than five time for an array size of 16kbit. than R . The resistance of the selected cell, with open gate, o f f This ratio increases as the array size increases. Finally, in worth will depend mainly on the data device resistance. This resis- mentioning that while miniaturizing the three-terminal memis- tance will be either 2R or R +R , with a very high ON/OFF on o f f on tor as a single device did not pass the same long path as the ratio. Our proposed method has a major advantage over the two-terminal memristor, we believe that its great advantages as complementary memristors technique that the desired cell has a gating device will motivate the fabrication community for cre- much higher ratio between its ON and OFF states. In comple- ating better memistor devices. mentary structures the total resistance is always (Ron + Ro f f ), in all of the cases. Based on that, our proposed solution has higher average signal to noise ratio. Moreover, the Ro f f /Ron ratio of 7. Conclusion the device is directly reflected on desired cell state values. Fig. 14 show the noise margins for the proposed technique We reviewed the main introduced solutions for the memris- and the normal array with floating terminals versus the array tors sneak-paths problem. We proposed a new technique for an- size for the worst case data set “all ones”. It appears clearly that alyzing the sneak paths problem facing memristor-based mem- the memistor gating has a significant impact on the sneak paths ory arrays. The new analysis is accompanied by simulations on Cadence Virtuoso 6 for different memory array sizes, data sets, and architectures. We also studied the memory array as- Memistor Gating Floating Terminals Ratio pect ratio effect on the sneak paths. Finally, we introduced an 1 new solution for the problem based on using the three-terminal 600 memistor device. 0.8 450

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