80387 Coprocessor Instruction Set

80387 coprocessor instruction set Continue 80x87 is capable of multiplying, sharing, adding, subtracting, finding sqrt and calculating transcendental functions and logariths. Data types include 16-, 32- and 64-bit signed integers; 18-digit BCD data; and 32-, 64- and 80-bit (advanced accuracy) floating point numbers. DW, dd and dq directives are used to declare signed storage of integrators, while dd, dq and dt are used for floating point. Conversion from decimal to floating point is made: Conversion of the decimal number into binary. The normalization of the binary number. Calculate a biased figure. Keep the number in floating point format. Bias is 0x7F, 0x3FF and 0x3FFF for 3 types of floating current. Special rules: Number 0 is stored as all 0s (except for the bit mark). In/- Infinity is stored as logic 1s in the exhibitor, with significand all 0s. The bit of the sign is used to represent infinity. NAN (non- number) is an invalid floating point result that has all 1s in the indicator with significand it's not all zeros. Conversion from floating point to decimal is carried out: Separate the sign-bit, biased indicator, and significand. Transform a biased exhibitor into a true exhibitor, subtracting bias. Write the number as a normalized binary number. Transform it into a de-normalized binary number. Conversion of de-normalized binary numbers into decimal numbers. The 80x87 follows 68 different instructions. The basic structure of the co-processor. Registers in the coprocessor stack always contain 80-bit extended accurate data. These memories, of course, can take other views. Thus, transformations occur during translations. FSTSW AX (STore Floating Point Status Word). An instruction that transmits data between the coprocessor and the AX register. The terms of the error can be checked in your program by studying bits of the word status. The TEST instruction can be used to test bits or SAHF instructions to transfer the most left-handed 8 bits to the EFLAGs register. This register selects accuracy, rounding control and control of infinity. For example, 00 for P and C sets a single accuracy mode. R and C controls round, for example, round down, up or truncated to 0. Data Transfer Instructions: FLD (Load Real) Loads Floating Point Data into Stack Top (ST). The stack pointer is then decremented at 1. The data can be extracted from memory or another stack position. Note that ST is registered 0 after initialization. FST (Store Real), FSTP (Store Real and Pop) stores a copy of the top of the stack (and pop for FSTP) in memory or other coprocessor register. Rounding occurs when the storage operation is completed in accordance with the control register. FXCH (Exchange) Exchange Register, given as operand with ST. FCMOV (MOV) Data Transfer Instructions FILD (load loader) FISTP (Store integer) similar to FLD, FST and FSTP, except for their transmission (and (and Integer. Arithmetic instructions: Stack address mode is limited to using ST (top stack) and ST1. The source of operand is ST while the operand's destination is ST1. After surgery, the source pops out, leaving dest. st. Arithmetic instructions (cont): Please note that FSUB subtracts ST from ST1, such as ST and ST1 - ST. Use FSUBR to cancel your order. For example, to calculate mutual (1/X): Register address mode should use ST as one of the operas. Another operend can be any register, including ST0, which is ST. Note that the destination can be either ST or STn. Also, unlike stack addresses, non-popping versions can be used. Memory address mode always uses ST as a destination. Arithmetic instructions (cont): The following letters are used for additional operation qualifications: P: Perform a register pop-up after surgery, FADD, and FADDP. R: Reverse mode for subtraction and division. I: Points to the fact that the memory opera is an integrator. I appear as a second letter in instructions such as FIDD, FISUB, FIMUL, FIDIV. Arithmetic Related Instructions: FS'RT: Finds Square Root Operands on ST. Leave the result there. Check the IE bit for an invalid result, for example, operand was negative using FSTSW AX, and TEST AX, 1. FSCALE: Adds ST1 content (interpreted as an integrator) to the ST exhibitor. FPREM1: Performs modlo division ST ST ST1. As a result, the remainder is on ST. FRNDINT: Rounds ST to integer. Arithmetic relevant instructions (cont): FXTRACT: Decomposes ST into an impartial indicator and significand. Extracted significand is on ST and an impartial exhibitor on ST1. FABS: Changing the ST sign to positive. FCHS: Invert st sign. Instructions by comparison: These instructions examine ST relative to another item and return the result of the comparison to the C3-C0 bit status registry. FCOM: Compares ST to memory or registers operand. FCOM itself compares ST and ST1. FCOMP/FCOMPP: Compare and pop once or twice. FICOM/FICOMP: Compare ST with integer memory and additionally abcet the stack. FTST: Compare ST to 0.0. FXAM: Exam ST and change CC bits to indicate whether the content is positive, negative, normalized, etc. (see text). FCOMI/FUCOMI: combines FCOM, FNSTSW AX and SAHF. Transcendental operations: (see text for semantics). FPTAN FPATAN F2XM1: Calculate 2x-1 FSINCOS FYL2X: Calculate Ylog2XFP1: Calculate Ylog2 (X No. 1) Permanent Return Operations: FLD: Store 0.0 to ST. FLD1: Store 1.0 to ST. FLDPI: Store pi to ST. FLDL2T: Store log210 to ST. FLDL2E: Store log2e to ST. FLDLG2: Store log102 to ST. FLDLN2: Store loge2 to ST. Coprocessor Control Instructions: FINIT/FNINIT: Reset with or without waiting after that. FWAIT: Stops the microprocessor until the coprocessor finishes work. It should be used before the microprocessor has access to memory data that is affected by the coprocessor. Coprocessor. The link is shown in the text along with the examples. Up: Chapter 3 -- Instructions for Applications Set Prev: 3.8 Flag Control Instructions as follows: 3.10 Segment Registration Instructions for Coprocessor Numbers (e.g. 80387 or 80287) provides an extension of the set of basic architecture instructions. The coprocessor expands a set of basic architecture instructions to support high-precision calculations with integrators and floating points. This extended set of instructions includes arithmetic, comparison, transcendental, and data transfer instructions. The coprocessor also contains a set of useful constants to increase the speed of numerical calculations. The program contains instructions for the coprocessor in accordance with the instructions for the processor. The system performs these instructions in the same way as in the instructions stream. The coprocessor works simultaneously with the processor, providing maximum bandwidth for numerical calculation. The 80386 also has features to support the emulation of the numeric coprocessor when there is no coprocessor. The emulation of the coprocessor software is transparent to the application of the software, but requires more time to perform. For more information about emulation of the coprocessor, please refer to Chapter 11. ESC (Escape) is a 5-bit sequence that starts with an opcode that determines the numerical instruction of a floating point. The ESC template tells 80386 to send the opcode and address operand to the coprocessor of the number. The Numeric Coprocessor uses escape instructions to perform high performance, high-precision floating arithmetic point that corresponds to the IEEE floating point of the standard 754. WAIT is an 80386 instruction that suspends the program until the 80386 processor detects that the BUSY pin is inactive. This condition indicates that the coprocessor has completed its processing task and that the processor can get results. Up: Chapter 3 -- Instructions Applications Set prev: 3.8 Flag Control Instructions as follows: 3.10 Segment Registration Instructions x87 is a floating point associated with a subset of x86 architecture set of instructions. It originated as an extension of the 8086 instruction, set in the form of additional floating toxistors that worked in tandem with the corresponding x86 processors. These microchips had names ending at 87. It was also known as NPX (Numeric Processor eXtension). Like other extensions to the basic set of instructions, the x87 instructions are not strictly necessary for building work programs, but provide hardware and microcode implementations of common numerical tasks, allowing you to perform these tasks much faster than the appropriate machine code procedures. The x87 set of instructions includes instructions for basic floating point operations such as adding, subtraction and comparison, as well as for more such as the computational function and its reverse, for example. For example. x86 processors with Intel 80486 had these x87 instructions implemented in the main processor, but the term is sometimes still used to refer to this part of the set of instructions. Before the x87 instructions were standard on PCs, compilers or programmers had to use fairly slow library calls to perform floating-point operations, a method that is still common in (low-cost) built-in systems. Description Registers x87 form an eight-tier deep, not-strict stack structure, ranging from ST(0) to ST (7) with registers that can be directly accessed either operand, using biases relative to the top, as well as pushed and popped up. (This diagram can be compared to how the frame stack can be both pushed/popped and indexed.) There are instructions to click, calculate, and pop values at the top of this stack; then non-arary operations (FSRT, FPTAN, etc.) implicitly turn to the very top ST (0), while binary operations (FADD, FMUL, FCOM, etc.) implicitly address ST (0) and ST(1). The non-strict stack model also allows binary operations to use ST(0) along with a direct memory opend or with a clearly specified stack register, ST (x), in a role similar to a traditional battery (combined destination and left operand).

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