The Heat Is On: Rudolph Technologies and Entrepix, Inc

Volume 11, Number 4

QUARTER FOUR 2007

A Publication of The MicroElectronics Packaging & Test Engineering Council

INDUSTRY NEWS The 4th Annual The Heat is On: Rudolph Technologies and Entrepix, Inc. have announced that Rudolph has granted Entrepix Thermal Solutions for an exclusive license to manufacture, sell, service and support the Rudolph AutoEL® series of thin-film ellipsometers. page 12 Advancing Technology

MIG (MEMS Industry Group), the trade association representing the microelectromechanical One Day Technical Symposium and Exhibits systems (MEMS) and micro-structures industries, and MEPTEC have announced a strategic Coming to San Jose February 28th ... page 5 alliance that will benefit companies designing and packaging MEMS devices. page 12

SEMI, along with Freiburg Wirtschaft Touristik MEMBER COMPANY PROFILE und Messe GmbH & Co (FWTM) and Solar Promotion GmbH, organizers of Intersolar, the he ASE Group was estab- world’s largest trade fair for solar technology, lished in 1984 as a semi- have announced a partnership to host Interso- conductor assembly com- lar North America. page 13 pany headquartered in Tai- Twan. Over the course of 23 years, ASE has gradually evolved into a $3.1 billion company, offering a broad range of services including Asymtek has introduced its next generation conformal coating platform, the Select Coat® IC packaging, test, material, with SL-940E. page 15 complete turnkey capabilities.

SUSS MicroTec has announced that it has received the first order for its new Gamma ASE’s manufacturing was initially carried Semiconductor equipment bookings remain XPress coat/ develop cluster from Rohm and out in Taiwan, and later expanded into seven even with September 2007 level. page 16 Haas Electronics Materials. page 16 countries spread over four continents. From an original employee headcount of just one hundred, ASE now employs over 28,000 Book- people worldwide. Today, ASE has achieved market leadership, and is the world’s largest provider of independent semiconductor to-Bill manufacturing services in assembly and test. With key customers spanning the consumer, Ratio The Pan Pacific Microelectronics Symposium computing, and communication sectors, ASE and Tabletop Exhibition, sponsored by SMTA, serves both the IDM and Fabless communi- FOR will be held January 22nd through the 24th at ties, to meet the electronic industry’s grow- OCTOBER the Sheraton Kauai Resort. .83 page 17 ing needs. page 18 www.meptec.org Q4 2007 / MEPTEC Report 1 the right fit

With the right investments in the right places at the right time, we’re uniquely positioned to help you make the connection from idea to product success.

Honeywell’s ongoing research and development in chemistry, metallurgy, and the processes that bring them together—from our new packaging R&D facility in Spokane, Washington, to our technology center in Shanghai, China—ensure that wherever challenges arise, we’ll continue to create solutions that solve them. And as a partner to most of the top semiconductor houses worldwide, our technology portfolio is consistently at the forefront of invention, empowering the global leaders of innovation. Honeywell Electronic Materials—bridging the path to accelerated success.

Contact Honeywell for solutions to your puzzle… visit www.honeywell.com/sm/em or call 1-408-962-2000.

Right Fit-MR-Q407.indd 1 11/12/07 2:00:45 PM Council Update

Volume 11, Number 4 A Publication of The MicroElectronics Packaging & Test Engineering Council P. O. Box 222 Medicine Park, OK 73557 Tel: (650) 714-1570 Email: [email protected] Published By MEPCOM Editor Bette Cooper Design and Production Gary Brown t’s hard to believe that another year is com- impressive organization. It was established in Sales and Marketing ing to a close. It seems just a short time 1984 as a semiconductor assembly company, and Kim Barber ago we were wrapping up our last issue has since grown and evolved into a $3.1 billion Contributing Editor Jody Mahaffey of 2006, and now it’s upon us again! Here business offering not just assembly but also test –––––––––––––– at MEPTEC we’re looking forward to an services, systems and materials design and service, Iexciting 2008. One of our biggest efforts is a brand among many others. This profile focuses on their MEPTEC Advisory Board new website – we’ll be launching it on January 1. China facilities and markets, and their expansion in Seth Alavi We look forward to continuing to bring you our that area. See their story on page 18. SunSil Jeffrey Braden high quality services which include our popular Our first feature article is from Vertical Cir- LV Sensors, Inc. technical programs, as well as networking and cuits, Inc. (VCI) on “A Low Cost Alternative to Philippe Briot P. Briot & Associates marketing opportunities. We’ve got several new Thru Silicon Via – Can Packaging Technology Joel Camarda programs in the works that you’ll be hearing about Provide the Missing Link?” In this article it is Exar Corporation soon. discussed that current interest has been focused Gary Catlin Plexus See pages 6 and 7 for summaries of our last two on thru-silicon via, which according to VCI is in Tom Clifford technical symposiums. Our 2nd Annual “Medical essence a front-end solution. VCI sees the solution Rob Cole Electronics Symposium – Growth Opportunities remaining in the back-end through the use of vir- John Crane J. H. Crane & Associates for the Microelectronics Industry” is covered tual vias. See page 20 for this informative article. Jeffrey C. Demmin by Jody Mahaffey of JDM Resources/e-Reach Our next feature article is from Jean-Chris- Tessera Bruce Euzent Communications. We’d like to thank Arizona tophe Eloy of Yole Développement. Yole is a Altera Corporation State University again for hosting this event. market research and strategy consulting company, Skip Fehr Julia Goldstein They have invited us back, so we’ll keep you and Eloy has been a speaker at several MEPTEC Advanced Packaging Magazine posted on our third annual event covering this events. He presented at our recent Substrates event, Chip Greely Qualcomm important area of the microelectronics world. and we asked him to follow up with an article on Anna Gualtieri Our most recent event, “Substrates – The the same topic: MEMS Substrates – Going to 6 Inch Elle Technology Foundation of Semiconductor Packaging”, is cov- and 8 Inch. See page 26 for his breakdown of the Lan Hoang Xilinx ered in this issue by Jeffrey Demmin of Tessera, substrates market, and how the 2006 market was Bance Hom and contributing editor for Advanced Packaging $315 million, with a look forward to 2010 at $600 Consultech International, Inc. Ron Jones Magazine. In this event cost and co-design topics million. We’d like to thank Mr. Eloy for traveling N-Able Group International came across as crucial issues of semiconductor Pat Kennedy Gel-Pak packaging. Both event synopses include presenta- Nick Leonardi tion summaries. CDs of both symposiums’ pro- Premier Semiconductor Services Issue Highlights Phil Marcoux ceedings are available – contact the MEPTEC TPL Group office for details. 10 Bhavesh Muni Industry Analysis Henkel Corporation Our Industry Analysis this issue came about as Mary Olsson a result of our Substrate event’s keynote speaker. Gary Smith EDA Industry News 12 Marc Papageorge The article is a joint effort by MEPTEC support- Semiconductor Outsourcing Solutions ers TechSearch International, Inc. and SEMI. Rich Rice Member Company Profile 18 ASE (US) Inc. In “Laminate Substrates Lead the Growth in Jim Walker the Semiconductor Packaging Materials Mar- Gartner Dataquest ket”, Jan Vardaman of TechSearch and Dan Feature Articles Russ Winslow Six Sigma Tracy of SEMI give us a summary of their new A Low Cost Alternative to 20 –––––––––––––– study called the Global Semiconductor Packaging Thru Silicon Via Materials Outlook (see page 10). The market for MEMS Substrates – 26 MEPTEC Report Vol. 11, No. 4. Published quarterly by semiconductor packaging materials is expected MEPCOM, P. O. Box 222, Medicine Park, OK 73557. to reach $15.5 billion in 2007 and grow to $20.2 Going to 6 Inch and 8 Inch Copyright 2007 by MEPTEC/MEPCOM. All rights reserved. Materials may not be reproduced in whole or in billion by 2011. The article covers the importance part without written permission. of laminate substrates, flip chip laminate substrates Events Calendar 37 MEPTEC Report is sent without charge to members of MEPTEC. For non-members, yearly subscriptions are avail- and substrate supply and demand. Thanks to both able for $75 in the United States, $80US in Canada and parties for this important study. Editorial 38 Mexico, and $95US elsewhere. Our Company Profile this issue is from long- For advertising rates and information contact Kim Barber, Sales & Marketing at 408-309-3900, Fax 1-866-424-0130. time Corporate member, the ASE Group, a truly

www.meptec.org Q4 2007 / MEPTEC Report 3 from France on many occasions to speak to our members about all things MEMS. Our Editorial this issue is from MEPTEC Advisory Board member Bhavesh Muni of Henkel Corporation. In “Why Film Will Make the Final Cut for Stacked Die Applica- tions”, Bhavesh makes the case for advanced integrated package technology. He maintains that die attach film materials, specifically Dicing Die Attach Film (DDF) and Flow Over Wire (FOW) will be the driving force for successful integrated package production. Engineered Solders: He describes the benefits of DDF, and ends N Precise chemistries and by saying “As always, consumers will be the physical properties big winners”. See his enlightening piece on N Lab-tested and field-proven page 38. Wire N Reliable performance and excellent technical service This issue is one of our biggest “bonus Washers distribution” issues annually, meaning that Products and Applications: Squares in addition to our regular circulation to our members and at MEPTEC events, this issue N Frames Pure indium for low temperature sealing is also being distributed at several other

N Indium alloys for step soldering and Foil industry Outside •POSITION: right page group events. We’re pleased to thermal interfacing Flux be sponsoring two SMTA programs (their N AuSn alloys for fluxless die-attach and Medical conference and Pan Pacific), as well Arrays hermetic packaging as IMAPS Device Packaging, DesignCon www.esolders.com [email protected] Split Rings 2008, and the Semico Summit. Ribbon We’d like to thank all of our contributors for making this a great issue. If you’re read- ASIA: Singapore: +65 6268 8678 Spheres CHINA: Suzhou, Liuzhou, Shenzhen: +86 (0)512 628 34900 ing our publication for the first time at one EUROPE: Milton Keynes, Torino: +44 (0) 1908 580400 Paste of the many events where we distribute, or if USA: Utica, Chicago: +1 315 853 4900 Custom Shapes you’reINDI-1682-0335 •MEPETEC Report -e solders Ad •Due at 8/25/06 pub: • AD __ • AE __ • PP __ • SzCk __ CD & OUTPUT: color proof SIZE:1/3 sq- 4.5" x 4.875" 5.125" Bleed: x 5.5" a new member, we hope you enjoy it. Thanks for joining us! ◆

INDI-1636 NASA tech.indd 1 8/23/06 4:15:45 PM

SILICON VALLEY

• Free Wireless Internet Access • 176 Spacious Guest Rooms • Full Service Restaurant • In Room Coffee Makers, Refrigerators, Hairdryers, Irons and Ironing Boards, AM/FM Clock Radios and Digital Safes • On Demand Movies • Voice Mail • Heated Outdoor Pool and Jacuzzi • Banquet/Meeting Space for 250 • Japanese Tatami Rooms

• Minutes from Light Rail, Santa Clara Convention Center and Paramount’s Great America • 24 Hour San Jose Airport Transportation • Special Group Rates and Packages

The only full services Ramada in Silicon Valley 408-245-5330 1217 WILDWOOD AVENUE • SUNNYVALE, CA 94089

4 MEPTEC Report / Q4 2007 www.meptec.org MEPTECPresents MicroElectronics Packaging and Test Engineering Council Join Us!

A ONE-DAY TECHNICAL SYMPOSIUM & EXHIBITS

February 28, 2008 • Wyndham San Jose • San Jose, California The 4th Annual The Heat is On: Thermal Solutions for Advancing Technology

PLATINUM SPONSOR Sessions will include: n Thermal Solutions for Tomorrows ICs GOLD SPONSORS n LEDs and Solid State Lighting – Bright Future for Hot Products

n Telecommunications – Power Users are Power Hungry

n Portables – Things Are Getting Faster, Smaller and Hotter

MEDIA SPONSORS MEPTEC Event Follow-up

A SPECIAL ONE-DAY TECHNICAL SYMPOSIUM 2nd Annual 2nd Annual Medical Electronics Symposium – Medical Electronics Symposium

Growth Opportunities for the Growth Opportunities for the Microelec- tronics Industry Microelectronics Industry Presented by ASU CAMPUS • T E M P E • ARIZONA

In association with

MacroTechnology Works Jody Mahaffey at Arizona State University 9.25.07 JDM Resources/e-Reach Communications

he opportunities available for devices, is finding a power source other Session leader Dr. Roger Emigh of microelectronics packaging to fit than batteries, which eventually wear out. STATS ChipPac started his session with into the growing field of medical For example, piezoelectric microstimulators Randal Schulhauser of Medtronic who electronic products was the focus of (powered by motion like watches ) are being showed us the unique packaging challenges MEPTEC’s 2nd Annual Symposium developed at ASU for use in pain manage- that Medtronic faced while developing their Ton Medical Electronics held on September ment and possibly treatment for Parkinson’s family of implantable Reveal® monitor sys- 25th, 2007, at Arizona State University. This disease. Other power options being devel- tems to diagnose cardiac arrhythmias and the year’s Medical Electronics symposium was oped include RF inductive and transcutane- solutions they implemented to bring these once again presented in association with the ous solar. products to market. MacroTechnology Works and co-chaired by Dr. Jerzy Rozenblit and Dr. Allan Ham- Eric Beyne, Program Director of IMEC Nick Leonardi of Premier Semiconductor ilton of the University of Arizona presented next presented information on new products Services and David Ruben of Medtronic a fascinating example of how the medical and being developed to allow embedding ultra- who led an interesting and diverse list of electronics communities can work together in thin die and die stacking as an alternative experts through the presentations of the day. their presentation, Virtually Assisted Surgical for through-silicon vias in 3D stacking. In Celeste Null of Intel began the program Training: Concepts, Foundations and Sen- this process, ultra-thin die are embedded in with a lively keynote presentation showing sor-Based Techniques. The first half of this silicone ribbon and stretchable substrates to many of the breakthrough technologies being presentation was a little depressing, focusing create a flexible electrode array for use in developed between the medical and electron- on the many mistakes made by our medical medical devices such as cochlear implants. ics communities that could virtually revolu- community which are classified as Medically According to Beyne, one of the largest prob- tionize the way our healthcare system works. Adverse Events (MAEs). The numbers were lems associated with developing new tech- According to Null, our healthcare system quite frightening, showing that one out of nology is the narrow scope of approved must evolve quickly to keep pace with global every six patients will suffer from an MAE materials due to the stringent regulations aging, a growing clinician shortage and the and medical errors are the fifth leading cause involved. technology expectations of our next genera- of death in the United States. Knowing the Lisa Murphy of Ansoft Corporation tions. Many people in the healthcare area are full scope of the problem proved the impor- finished off the session with a look at how looking to the electronics industry as the path tance of the research presented in the second advances in three-dimensional (3D) electro- to an integrated implantable for a total end- half of the presentation. Research is currently magnetic simulation software using the full- to-end solution. underway at the University of Arizona to wave finite-element method (FEM) are mov- The first session, a business and technol- develop computerized and sensor technology ing out of the traditional applications areas ogy overview, chaired by Dan Nienhauser to teach surgeons how to perform surgical and emerging into the biomedical engineer- of ASU’s MacroTechnology Works includ- procedures with more accuracy. The system ing field. Case studies were presented included views by several of Arizona’s academic being developed, the microBIRD™ 6, uses ing Duke University’s design of microwave experts, including Dr. Bruce Towe of ASU. virtual tissue and organ models and is capable heating elements for hyperthermia treatment, Dr. Towe’s presentation showed the many of high fidelity motion tracking of surgical the design of a directional microwave heat- opportunities for microelectronic implants instruments to provide tracking of the training element used in photodynamic cancer being developed today. For our military per- ee’s dexterity and skill level while offering therapy, and a joint program between Ansoft sonnel, implantable bio sensors are being computer aided movement guidance. and Philips to analyze and improve MRI developed which may one day be able to Ending session one, Sayfe Kiaei of Con- systems using a human-body model created track a soldier’s health and external environ- nection One NSF Center gave a more in by Ansoft. mental situations, such as biohazards, as an depth look at the development of wireless More enabling technologies were dis- early warning detection system. Injectible bio sensors and MEMS for bio-implants and bio- cussed in the third session led by Bruce sensors could be used for getting immediate telemetry. Some examples discussed were; Bowers of Flip Chip International. Bob health information in emergency situations. MEMS microphones used in hearing aids, Gosliak of HEI started off the session show- For a more everyday purpose, implantable implantable wireless neural-sensors and con- ing how high-density interconnect (HDI) bio sensors can be used to continuously mon- trols used to send information to prosthetics, flexible substrates are used in many medi- itor blood glucose levels rather than invasive and 3-axis MEMS accelerometers used to cal applications such as medical imaging, monitoring, such as blood draws. locate movement and sense health. These cardiac devices and neurostimulators. The Many of the envisioned sensors must be last being used for fireman, elderly and the advantages of HDI flex increase as the size packaged to endure many years of relatively military. of the devices decrease. With advancements hostile conditions inside the human body The second session, Packaging Medical in flex circuits such as Fold-Over Flex and while communicating wirelessly through the Electronics focused on the special challenges Rigid Flex technology, flexible substrates are skin. One of the issues to solve in order to that packaging systems must solve to be used poised for continued growth for use in medi- further facilitate the usage of implantable in medical applications. cal applications to provide a space-efficient 6 MEPTEC Report / Q4 2007 www.meptec.org A SPECIAL ONE-DAY TECHNICAL SYMPOSIUM packaging solution. tripping) and sensors in a patient’s bed that while Endicott Interconnect was cited as the In the next presentation, Gary Dashney periodically takes the person’s vital statistics only remaining major U.S. supplier of flip 2nd Annual of IceMOS Technology showed how Sili- are among those being developed. chip laminate substrates. con-On-Insulator (SOI) substrates are being The audience seemed to be very pleased Vardaman also discussed cost issues, Medical Electronics used to further enable MEMS devices for with the speakers, topics and symposium as a including the impact of gold and copper the medical market. According to Dashney, whole. “This symposium has again highlight- prices, as well as energy costs, which affect Symposium SOI substrates offer greater control of the ed that the medical industry will continue the whole supply chain. The cost of high- mechanical properties of MEMS structures to leverage state-of-the-art electronic tech- density, thin core substrates remains high, but Growth Opportunities for the Microelec- and enable more complex designs due to nologies to advance the capability of implant- the technology has developed and suppliers tronics Industry embedded structures in multi-layers. The able devices, diagnostic equipment and other are waiting for demand to catch up and drive Presented by third session finished with an interesting types of medical systems,” according to Nick the prices down. Overall, prices for flip chip ASU CAMPUS • T E M P E • ARIZONA presentation by Kent E. Dicks of MedApps. Leonardi, Symposium General Co-Chair- laminate substrates have improved as a result In association with MedApps is developing a wireless system man and Business Development Director for of increased capacity in the factories. Her last MacroTechnology Works that will take data from several different Premier Semiconductor Services. bullet – “co-design key to future success” at Arizona State University 9.25.07 bio devices (including implantables), using One of the major unresolved questions – was a preview of a point made by many of Bluetooth technology and make them com- that came out of the symposium was, “Who the speakers to follow about the increasing municate to each other and to external media. will pay for advancements in medical elec- complexity of semiconductor products and This new technology is designed to help tronics?” If there are not monetary incentives their substrates. those patients who suffer from one or more for doctors and hospitals, they will be less Symposium co-chairs Joel Camarda of chronic diseases such as diabetes, conges- likely to spend the extra money needed to Sipex and Rich Rice of ASE structured the tive heart failure (CHF), COPD, asthma or put some of these new systems in place. event along the lines of the supply chain, and other diseases, lead a more active lifestyle by Perhaps this will be a session topic for the first session, chaired by Lan Hoang of allowing their medical records and monitor- MEPTEC’s 2008 medical electronics sympo- Xilinx, covered “Substrate Manufacturing ing data to be disseminated through wireless sium. ◆ and 1st Level Interconnection.” The first talk devices to physicians and physician’s offices of the session, “Buildup Technology Require-

and can help monitor and react to changes in A SPECIAL ONE-DAY TECHNICAL SYMPOSIUM ment Roadmap: An FPGA Sector Perspec- individuals’ medical conditions. tive,” was given by Paul Wu of Xilinx. The final session of the day, led by This was an excellent choice to lead off the John Crane of J. H. Crane and Associ- symposium program – a significant user of a ates brought together some leading medical technology presenting its upcoming needs is products companies to discuss their products Substrates: an ideal conference talk. A key point made and developing technologies. D. Nguyen The Foundation of by Wu was that, although Xilinx does not of Bioptics, started off the session with a Semiconductor Packaging shrink its silicon technology too fast because look at the design of an innovative X-ray of cost and yield issues at the leading edge, active pixel sensor in CMOS technology to the increasing density and performance still help advance Digital Mammography. Among puts a lot of pressure on the package technol- other advancements, the new technology will S A N J O S E • CALIFORNIA ogy. He cited power integrity as a serious allow for immediate testing during surgery challenge, requiring co-design of the power to make sure all cancer cells have been Presented by distribution network linking the silicon, pack- removed. 11.8.07 age, and board. He also gave some numbers We found that packaging issues don’t stop for the upcoming progression of linewidths at the semiconductor IC level when the next and other substrate features and explained that speaker, Joan Vrtis gave a fascinating pre- Jeffrey C. Demmin all of these design features affect the cost. sentation on a “Palm-Size Breath Analyzer Tessera Following Wu’s talk from the user for the Detection and Monitoring of Meta- perspective was a representative from the bolic States” being developed by Kemeta. EPTEC’s final technical sym- supplier’s side, James Lin of Kinsus. His This product is used to directly monitor an posium of 2007, “Substrates: talk, “Example of a Substrate Technology individual’s fat burn rate by analyzing breath The Foundation of Semicon- Roadmap,” provided the Kinsus view of acetone which is a biomarker of fat metabo- ductor Packaging,” identified upcoming requirements and capabilities. The lism. One of Kemeta’s obstacles to overcome cost and co-design as piv- range of products shown – wire bond and in bringing this product to market was user- Motal issues for the most critical component of flip chip versions of CSP, SiP, PBGA, and friendly packaging with easy to understand semiconductor packaging. very-high density PCB – was an indication readings. In order to meet these demands, Jan Vardaman, president of TechSearch, of the challenges that the suppliers face. semiconductor and portable hand-held appli- opened with a keynote titled “Markets and Lin’s roadmap charts were quite detailed and cation knowledge had to be leveraged. Trends in Laminate Substrates.” She high- complex, illustrating the trends in manufac- As a perfect wrap up for the session and lighted the growing importance of laminate turing processes, layer count, surface finish, the day, Ken Bobis, Director of Technology substrates, noting that they represented 37% bump pitch, dielectric material, linewidths, for the Mayo Clinic presented, “Advance- of the $15B packaging materials business in and many other variables. Those charts also ments in Hospital Technology” to show how 2006, easily surpassing leadframes at 20% of showed that new developments are needed the electronics and medical industries are the market. In terms of volume, the shift of every year in virtually every area. The tech- joining together to automate the healthcare DRAM from TSOPs to laminate CSPs was nology is indeed moving very quickly. Lin industry with developments in electron- a big driver of that trend. Another part of wrapped up his talk with some interesting ics medical record systems, expanded use the equation was flip chip substrates, which cross-sections showing their approach for of RFID and systems such as the Healthy didn’t have as much volume but accounted embedded passives. Home. The Healthy Home is a new system for over half of the dollar value of the sub- The last talk of the first session, “Flip being developed that will put sensors into strate market. As she usually does, Vardaman Chip Packaging Applications Using a patient’s home and connect them with an provided a list of significant substrate sup- Advanced Substrates,” was given by Bernd outside monitoring system. Sensors showing pliers with comments on their current status. Appelt of ASE. ASE, as a packaging sub- shuffling feet (indicating an increased risk of Ibiden in Japan was identified as the largest, contractor that also has in-house substrate

www.meptec.org Q4 2007 / MEPTEC Report 7 MEPTEC Event Follow-up

manufacturing capability, should have excel- to be a good approach for reducing power of an integrated design capability. The set lent insight into both the requirements and the noise. of skills required of a SiP designer are also capabilities. Appelt presented quite a bit of Sean Moran of Tessera presented prohibitively diverse, covering layout, RF manufacturing, design, and reliability data on mechanical and reliability issues in substrate analysis, digital design, and manufacturing thin core and coreless substrates for large-die design in his talk “Substrate Topologies and knowledge. Better quick-turn prototyping flip-chip applications. Some key results of Mechanical Reliability Analysis for Minia- capabilities would also help the industry. the analysis showed why electroless nickel turized Mobile Systems.” He summarized the Nachnani suggested that designers should / electroless palladium / immersion gold has drivers for thin components and substrates, use the simplest possible available, high- become a popular choice for surface finish on as well as the various factors affecting the volume technologies whenever possible to advanced substrates (… in spite of the unfor- mechanical, electrical, reliability, and envi- minimize risks and maximize the chance of tunate acronym ENEPIG). A key advantage ronmental properties of the materials. A good design success. His 802.11 case study illus- is that it works well for both wire bonded and example on the reliability side is cyclic trated his approach to SiP design challenges. soldered connections. bending resulting from the rise of texting Bhavesh Muni of Henkel chaired the Bruce Euzent of Altera chaired the with mobile devices. Moran noted that the third sessions, titled “2nd Level Interconnect second session, “Design and Simulation: material requirements are often in conflict and Reliability,” which included the diverse Silicon, Substrate, System,” with speakers with each other, but that low cost is the one perspectives of an EMS provider (Jabil), an from a chip company, a packaging company, constant in the list of desirable attributes. He IC company (LSI), and an OEM (Cisco). and a design specialist. Hong Shi of Altera reviewed some thin substrate approaches, Quyen Chu of Jabil presented “Ultra-fine led off with “Deliver Electrical Performance including Tessera’s copper post technology, Pitch SMT Assembly – Assembly Challenges to FPGA and ASIC Applications by Die- and illustrated some of the best ways to of Product Miniaturization to the EMS.” Package-System Co-Design.” He highlighted compare technologies. One key conclusion is This included extensive design-of-experi- application challenges, including dramatic that material improvements are needed from ments (DOE) work on SMT process and shrinking of timing margins, and analyzed material suppliers to continue meeting the design. It was a good reminder for the chip key issues in the die, package, and board needs. and package designers out there what the that affect the performance. Like the Xilinx Some detailed electrical design and simu- next company in the supply chain has to think speaker in the first session, he cited power lation work was presented by Manoj Nach- about. One interesting outcome was that the distribution as the dominant factor in timing nani of Enabling Solutions. His talk, “Chal- DOE approach can be used to maximize the margin performance. Shi then showed some lenges in Design and Electrical Analysis of stencil thickness while allowing for 0.4 mm elements of co-design strategy, including Low Cost Wi-Fi 802.11 System in Package,” pitch CSPs. optimized package floorplanning, I/O vs. started by highlighted the significant chal- Kishor Desai of LSI Logic followed ground distribution, and decoupling strate- lenges of SiP design. Design tools for pieces Jabil with “IC Package Design, Materials, gies. On-package decoupling was shown of the process exist, but they still fall short and Assembly Ensuring System Level Solu-

8 MEPTEC Report / Q4 2007 www.meptec.org tion.” He started with the concept that you and board level reliability in ever shrinking happens over the next year or two. need to understand the needs of your cus- design cycles.” There is plenty of work for Yole’s founder and general manager tomer’s customer to achieve the best design. everyone in the supply chain. Jean-Christophe Eloy provided a view from LSI has spoken prominently on the topic of Finally, the fourth session covered the MEMS world with “Status of the MEMS co-design, and Desai showed here how the “Emerging Substrate Technologies,” follow- Industry: Substrate and Material Markets.” substrate is that center of co-design. He pre- ing the MEPTEC tradition of looking ahead He described the maturing markets and sented electrical, mechanical, thermal, and in the final session of its technical symposia. rapid growth in areas such as RF MEMS and reliability evaluations of complex designs, Session chair Tom Clifford recruited Joe silicon microphones. The MEMS foundry illustrating the many factors that go into Fjelstad of Verdant Electronics, Jean- business is also healthy – some MEMS identifying the best design for a particular Christophe Eloy of Yole Developpement, foundries are actually profitable – and 8” application. Board level assembly challenges and Tuomas Waris of Imbera to give some wafer processing is on the rise. Silicon is still are also a significant part of the equation. excellent talks on new technical solutions to the dominant MEMS substrates, but SOI, The messaging in this session was con- industry challenges. quartz, glass, and polymer substrates are all sistent, with Mudasir Ahmad of Cisco Verdant is the high-profile start-up that finding more applications too. Systems presenting “Impact of Package serial entrepreneur Joe Fjelstad launched to The last talk of the day was worth Substrate Design and Material Changes on develop and proliferate an intriguing embed- the wait, with Tuomas Waris of Finland’s 2nd Level Interconnect Reliability.” A key ded technology. Nearly any kind of device Imbera Electronics presenting “Further point from Ahmad was the value of doing – packaged or bare – can be embedded in the Miniaturization Utilizing IMB Technology.” a second level qualification earlier in the substrate, with the exterior contacts eliminat- Waris gave some background on Imbera’s design process to identify any issues that ing the need for solder. Fjelstad emphasized integrated module board (IMB) technol- might appear downstream from the pack- the low cost and simplicity of his “Occam ogy for embedding active components in age-level design. This would not need to be Process,” and challenged the industry to substrates. He had some of the same mes- a full daisy-chain qualification, since a fairly think of electronic assembly in some signifi- sages as Verdant’s Fjestad – high design simple second-level qualification can iden- cantly different ways. He showed some of freedom, no custom materials, very high tify the majority of issues. He also reviewed the design and process options for embed- yield, supply chain integration – and he also high-performance requirements, including ding devices in a single molded component, showed approaches for EMI shielding, ther- low-k dielectric effects and warpage with and he drew an analogy to Lego block mal performance, and package-on-package large devices. In his summary, he relayed assembly. Verdant’s technology is arguably stacking with Imbera’s substrates. Imbera’s Cisco’s recommendation that “the substrate the most intriguing development of 2007, technology was introduced five years ago, and packaging industry needs to transition and after Fjestad’s inspiring talk, it is pos- but it seems to be getting more attention to an iterative, concurrent qualification pro- sible to envision the approach gaining some now with others investigating the embedded cess that spans silicon level, substrate level, traction. It should be interesting to see what approach. ◆

www.meptec.org Q4 2007 / MEPTEC Report 9 MEPTEC Industry Analysis

Laminate Substrates Lead the Growth in the Semiconductor Packaging Materials Market

E. Jan Vardaman - TechSearch International, Inc. Dan Tracy - SEMI

riven by performance and nate substrates for its central processing contain 10 or more CSPs. form factor requirements, unit (CPU) microprocessors facilitated Stacked die packages have been semiconductor packaging is this migration to organic substrates by common for many years, with as many now recognized as one of the providing a volume application that as five die found in production today. most important factors in the enabled the technology to mature faster While the two-die stacks are very com- Dgrowth of advanced packages. Materials for flip chip applications. mon, die stacks with many more die are are key to the success of semiconductor Personal computers (desktops, serv- increasingly common (see Figure 1). packaging for today’s devices as well as ers, and laptops) remain the largest- These packages typically use laminate future products. volume application for BGAs – almost substrates. Mobile phones from compa- The market for semiconductor pack- exclusively for plastic BGAs (PBGAs). nies including Apple, Motorola, Nokia, aging materials, including thermal inter- Game machines such as Sony’s PlaySta- and Samsung use package-on-package face materials, is expected to reach tion, Microsoft’s Xbox, and Nintendo’s (PoP). The PoP features two laminate $15.5 billion in 2007 and grow to $20.2 DS and Wii systems use PBGAs for substrates in each package (see Figure billion by 2011, according to a new processors and graphics chips. Comput- 2). study by SEMI and TechSearch Interna- ers, network systems, and telecommu- DRAM has made the transition from tional. Laminate substrates remain the nications equipment remain the major wire bonded leadframe-based packages largest segment of the market, worth an applications for high-pin-count BGAs. (TSOPs) to wire bonded laminate CSPs estimated $6.2 billion globally in 2007, Mobile phones remain the major (FBGA). With increased demand for and on a unit basis are projected to grow driver for growth in CSP unit ship- memory, shipments of laminate sub- at a compound annual growth rate of ments and laminate substrates are com- strates will grow dramatically. over 12 percent over the next five years. monly used. Consumer products such as Table 1 shows the semiconductor pack- watches, digital camcorders and cam- Flip Chip Laminate Substrates aging materials market by segment. eras, PDAs, DVDs, MP3 players such as Within the laminate substrate market, Apple’s iPod, games, and flash memory high-density substrates for flip chip rep- Importance of Laminate Substrates cards also use laminate CSPs. Laminate resent a large share of the dollar value. Laminate substrates represent a large CSPs in mobile phones typically contain The availability of flip chip substrates is dollar value today, more than double the package pin counts range from 32 balls key to the growth of flip chip for many value of the leadframe market. While to 399 balls. Today’s camcorder may applications. the number of units for leadframe packages remains larger that the number of laminate substrates, the complexity and Semiconductor Packaging Estimate of 2007 Global Market type of materials used make the value Materials Segment $M greater in the laminate segment. This has not always been the case. Historically Laminate Substrates $6,196.0 ceramic substrates and leadframe sub- Flex Circuit/Tape Substrates $262.5 strates were major choices for IC packages. The transition to organic laminate Leadframes $3,118.0 substrates has been driven by the shift Bonding Wire $3,178.3 from the era of ceramic packages to the plastic ball grid array (PBGA). Motorola Mold Compounds $1,371.0 and Citizen Watch share the early patent Underfill Materials $138.0 for the over molded pad array package (OMPAC), the first PBGA. Motorola Liquid Encapsulants $117.0 first adopted the package in two-way Die Attach Materials $562.2 radios and pagers. Disk drive applications followed with a major push from Solder Balls $265.0 Compaq (now part of Hewlett-Packard). Wafer Level Package Dielectrics $9.8 As CSP enabled the introduction smaller, lighter mobile phones, the volume of Thermal Interface Materials $303.0 laminate-based CSPs also increased. Intel’s shift from ceramic to lami- Table 1. Semiconductor Packaging Materials Market. Source: SEMI and TechSearch International, Inc.

10 MEPTEC Report / Q4 2007 www.meptec.org The drivers for flip chip continue to be performance, on-chip power distribution, pad limited designs, and form factor requirements. Microprocessor makers and high-performance logic suppliers such as ASIC, field programmable gate array (FPGA), DSPs, chipset, graphics, and microprocessor makers are expanding their use of flip chip in package (FCIP). Driven by form factor, many wireless products are adopting flip chip interconnect. To achieve small package body sizes, an increasing number of companies use flip chip inside the package, especially for the bottom die in a package of a PoP. Flip chip also provides a reduction in pitch for the top package of a PoP, and improved electrical performance for devices such as baseband processors by delivering power directly to the processor core, along with reduced IR drop and reduced EMI. There are examples of both gold stud bump and Figure 1. Stacked Die CSPs. solder bump in production today. While the shift to flip chip and WLP did not materialize in high volume for DDR2 DRAM, performance requirements are expected to generate a shift in interconnect methods from wire bond to bumps for some high-performance DDR3 and DDR4.

Substrate Supply and Demand Laminate substrate suppliers include Access (formerly AMITEC), ASE, CMK, Dai Nippon Printing, Daisho Denshi, Eastern, Endicott Interconnect Technologies, Fujitsu Interconnect, Hitachi Chemical, Ibiden, JCI, Kin- sus, Kyocera, MicroCircuit Technol- ogy, Mitsui Chemicals, Nan Ya PCB, NEC Toppan Circuit Solutions, NTK, Phoenix Precision Technology (PPT), Ryowa, Samsung Electro-Mechanics, Samsung Techwin, Shinko Electric Industries, SMIED Globetronics Tech- nology Industries (SGTI), a subsidiary of Sumitomo Metals Industries Elec- tronic Devices, Sumitomo Metal Min- ing-Shinko, Tripod, and Unimicron. Figure 2. Package-on-Package (PoP). IC package substrate production has transitioned from Japan to Taiwan and will slowly expand into China. Com- Intel’s projected move from wire bond to be a key enabler in advanced semi- panies in Taiwan such as ASE, Kinsus, to flip chip for its ICH (Southbridge) conductor packaging. Communications Phoenix Precision Technology, and Uni- chipset. The transition has been delayed, between suppliers of the raw materials micron, have all expanded production creating an over capacity situation. for the substrate, substrates, semicon- capacity to meet growing demand. While there is no oversupply of more ductor manufacturers and IC packaging The substrate shortage experience in complex substrates, the industry has assembly houses, and the system maker 2005 has been replaced by an oversup- seen delivery times return to normal. or assembly service provider are critical ply of capacity for 2-2-2 layer structures. in maintaining the required infrastruc- This is the result of capacity expansion Conclusions ture and supply chain to meet product by companies in Taiwan in response to Laminate substrates will continue demand. ◆ www.meptec.org Q4 2007 / MEPTEC Report 11 MEPTEC Industry News

to-business Marcom practices refurbish, service and support The orders were placed by three Indium’s worldwide. pre-owned tools on their behalf. global smart card manufactur- Corporate For more information about Under the terms of the ers and are anticipated to be Indium Corporation visit www. Agreement, the transfer of assets delivered in the fourth quarter Communications indium.com or email abrown@ and inventory will be com- of 2007. Director Earns indium.com pleted sometime in the fourth For more information about quarter. Entrepix is licensed to Besi, please visit their website SMTA Award market the AutoEL on a global at www.besi.com. Rudolph basis (excluding Japan) begin- Technologies ning immediately. All inquiries for the AutoEL received by MIG and MEPTEC and Entrepix, Rudolph will now be redirected Announce to Entrepix. Inc. Announce Headquartered in Flanders, Strategic Alliance License New Jersey, Rudolph supports its customers with a worldwide PITTSBURGH, PA and MED- Agreement sales and service organization. ICINE PARK, OK – MEMS Additional information can be Industry Group (MIG), the trade FLANDERS, NJ – Rudolph found on the company’s website association representing the Technologies, Flanders, NJ, and at www.rudolphtech.com. microelectromechanical systems Entrepix, Inc., Tempe, AZ, have (MEMS) and micro-structures announced that Rudolph has BESI Announces industries, and the MicroElec- granted Entrepix an exclusive tronics Packaging and Test Engi- license to manufacture, sell, ser- Packaging and neering Council (MEPTEC) vice and support the Rudolph have announced a strategic alli- Indium Corporation’s Director AutoEL® series of thin-film RFID Die Bonding ance that will benefit companies of Corporate Communications, ellipsometers. The AutoEL® Equipment Orders designing and packaging MEMS Rick Short, was honored with was the first microprocessor- devices. Through a variety of the Excellence in International based automated ellipsometer DUIVEN, THE NETHER- marketing programs, MIG and Leadership Award by the Sur- and is recognized worldwide LANDS – BE Semiconduc- MEPTEC will collaborate to face Mount Technology Associ- as a high-performance, high- tor Industries N.V. (BESI) has eliminate the barriers that pre- ation (SMTA) on October 10th, precision instrument used in the announced the receipt of orders vent the greater commercial use 2007. This award recognizes measurement of film thickness. in October 2007 aggregating of MEMS and MEMS-enabled Rick’s global achievements in Thousands of AutoEL tools approximately $4.3 million technology. the industry and his support of have been placed in universities, for packaging and die bonding “MIG and MEPTEC have the SMTA over his career of semiconductor research labs and equipment. complementary goals,” stated nearly 25 years. semiconductor production lines The Company’s Fico sub- Karen Lightman, Managing Since joining Indium Corpo- since it was commercialized sidiary received an order of Director, MEMS Industry Group. ration in 1984, Rick has played in 1977, with many of those approximately $2.8 million for “MIG is the unifying voice of an active role in the SMTA. He tools in continuous use today. four AMS-I molding systems the commercial MEMS industry, helped launch regional chapters All systems to be sold will be and two Compact Line trim and and MEPTEC is a trade associa- in Australia and Malaysia, and labeled “Rudolph Technologies form systems from a leading tion of semiconductor suppliers has supported the SMTA’s pres- AutoEL® – provided and sup- Chinese semiconductor manu- and manufacturers, committed to ence in China. Rick serves as a ported by Entrepix”. facturer. The customer intends enhancing the competitiveness member of the SMTA Market- “The AutoEL technology to utilize Besi’s equipment for of the back-end portion of the ing Committee and the SMTAI was the foundation of our over- the packaging of SOT/SOD dis- semiconductor business. During Exhibitor committee. whelming success in thin-film crete devices in conventional the coming year, we will work JoAnn Stromberg, of the metrology,” said Paul McLaugh- leadframe process applications together to address the packaging SMTA, commented “Rick has lin, chairman and chief execu- as part of their expansion of issues that can further enhance truly captured the meaning of tive officer of Rudolph. “We are discrete production capacity. the adoption and commercializa- our ‘international excellence in confident that Entrepix will con- Delivery is scheduled for the tion of MEMS.” leadership’ award. His influence tinue to maintain the high level first quarter of 2008. “Packaging of MEMS de- will benefit the SMTA for years of support for this product that Besi’s Datacon subsidiary vices holds special challenges to come.” our customers have expected also received orders recently in the semiconductor business,” Based at Indium’s global over the past thirty years.” aggregating $1.5 million for its said Bette Cooper, President of headquarters in Clinton, NY, Entrepix provides CMP 8800 FC (“Flip Chip”) Smart the MicroElectronics Packaging Rick is an innovator in his field. process outsourcing and equip- Line die bonding system. Data- and Test Engineering Council. He has received the Pro-Comm ment services, including refur- con’s 8800 FC Smart Line sys- “MEMS devices must withstand Award for the world’s first bishment of CMP, post-CMP tem is a fully automated, high- electromechanical, thermome- electronics assembly materi- cleaning and thin-film metrol- performance production line chanical and other stressors and als online video advertisement, ogy equipment. Due to the com- providing customers a complete still remain robust and reliable. titled “INDIUM CORPORA- plementary nature of Entrepix Radio Frequency Identification Bridging the gap between stan- TION: We Know SMT Inside foundry and equipment capa- Device (“RFID”) chip assem- dard semiconductor packaging and Out”. He is the author of bilities, many semiconductor bly solution based on a highly and MEMS packaging is one Rick Short’s B2B Marcom blog industry OEMs have authorized cost-effective method of direct way to address these challenges, on new media and business- the company to exclusively chip attach to RFID antennae. and it is this convergence that

12 MEPTEC Report / Q4 2007 www.meptec.org has been our focus.” United States, and will be held Ms. Cooper added: “MEMS at the Moscone Center in San is the new wave of the future, Francisco on July 15-17, 2008, and our collaboration with in conjunction with SEMICON MEMS Industry Group will West, the world’s first and most help us to further explore this prestigious industry event dedi- promising technology.” cated to microelectronics man- Through their alliance, MIG ufacturing. and MEPTEC will support each Intersolar, held in Munich, other’s upcoming events: Germany, has become the world´s largest trade fair for • MIG was a co-sponsor of solar technology and focuses on MEPTEC Substrates Sympo- the areas of photovoltaic tech- sium - The Foundation of Semi- nologies, solar thermal technol- conductor Packaging, Thursday, ogy and solar architecture. Cur- November 8, 2007, San Jose, rently, SEMI organizes a range CA; of PV-related events including ,OOKINGFOR • MIG will conduct a packag- PVJapan, the PV Fab Managers THEBESTINSURANCE ing survey of its members at Forum and PV-focused techni- its annual members-only technical events at major expositions AGAINSTFLIPCHIPDEFECTS cal event, METRIC (May 7-9, such as SEMICON Taiwan, 2008); SEMICON China, SEMICON Europa, and SEMICON West. • MIG will present find- "OFYBNQMFPGBOBDUVBM This agreement comes as a 4POPTDBO$4".¥BDPVTUJD ings of its packaging survey at response to the rapid expansion TDBOTIPXJOHBnJQDIJQ MEPTEC’s 6th Annual MEMS of solar energy markets world- XJUIEJFDSBDLTBOE Symposium on May 22, 2008; wide and the need for coop- EFMBNJOBUJPOEFGFDUT and eration between all the major • MIG and MEPTEC will industry participants to serve cross-promote each other’s the increasingly global supply events to their respective mem- chain and customer base. berships. Intersolar North America will address the entire supply For more information con- chain in solar energy includ- 3ONOSCAN'EN©# 3!- tact MIG at 412/390-1644, ing solar thermal energy and info@memsindustrygroup. PV. Exhibitors will include PV org or visit www.memsindus- cell, module and inverter manu- trygroup.org. facturers, polysilicon suppliers, ;]eYf\ÛJgfgk[Yf Contact MEPTEC via email equipment and material suppli- #RACKS VOIDSANDDELAMINATIONSCANELUDEELECTRICALTESTS!NDIF at [email protected] or visit ers, components and subsys- www.meptec.org. tems, manufacturers of solar LEFTUNDISCOVERED THEYMAYRESULTINCOSTLYPRODUCTIONSHUTDOWNS thermal applications for heat- QUARANTINEDPRODUCTSANDVERYDISAPPOINTEDCUSTOMERS Intersolar Joins ing, process heat and cooling as well as architectural/construc- 3ONOSCANSYSTEMSAREWIDELY 0ACKAGING!PPLICATIONS SEMICON West tion services. Intersolar North RELIEDUPONFORNONDESTRUCTIVE s0LASTIC%NCAPSULATED)# America will be a co-located to Form North event with SEMICON West, INSPECTION5SINGTHEMOST s$IE!TTACH America’s occupying portions of the West ADVANCEDACOUSTICTECHNOLOGY s&LIP#HIP Hall of Moscone Center. Reg- AVAILABLE 3ONOSCANACCURATELY s3TACKED$IE Largest Solar istered visitors to SEMICON LOCATESANDANALYZESTHESE s3MART#ARD West and Intersolar will be able HIDDENDEFECTSBEFORETHEY s#HIP3CALE0ACKAGE Technology to attend the exhibition part of Exposition both events without additional LEADTOFAILURES sANDMANYOTHERS fees or separate badges. Fol- SAN JOSE, CA – SEMI, along lowing the successful format 4OLEARNMOREABOUT3ONOSCANSYSTEMSAND with Freiburg Wirtschaft Tour- of Intersolar Europe, a 1.5-day !-)TECHNOLOGY VISITWWWSONOSCANCOM istik und Messe GmbH & Co conference on PV technology (FWTM) and Solar Promotion and solar thermal energy will GmbH, organizers of Interso- be held as part of Intersolar lar, the world’s largest trade North America, requiring a fair for solar technology, have separate conference fee. announced a partnership to host For more information about Intersolar North America. The Intersolar visit their website at new exposition will be the larg- www.intersolar.us. est trade event serving the full For more information about solar energy supply chain in the SEMI visit www.semi.org. www.meptec.org Q4 2007 / MEPTEC Report 13 IMAPS Presents the Fourth International DeviceDevice PackagingPackaging ConferenceConference && ExhibitionExhibition (www.imaps.org/devicepackaging) Exhibits: March 18 - 19, 2008 Conference & Events: March 17 - 20, 2008 co-located with Global Business Council Spring 2008 Meeting: March 16 & 17 (www.imaps.org/gbc) Raddisson Fort McDowell Scottsdale, AZ

General Chair: Larry Jacombsen, JH Technologies

Sponsored by: International Microelectronics And Packaging Society (IMAPS) www.imaps.org/devicepackaging

“Everything in electronics between the chip and the system!” MEPTEC Industry News

Asymtek IMEC Extends (metal-insulator-metal capaci- technology generations. This tors) process technology as part newly added focus follows an Introduces Select Its CMOS Device of its (sub-)32nm CMOS device earlier extension of its tradition- scaling program. This research al logic- and SRAM-oriented IMAPS Presents the Fourth International Coat SL-940 Scaling Program will enable IMEC and its part- program with a DRAM periph- Conformal LEUVEN, BELGIUM – IMEC ners to address the material and ery transistor sub-program in launches research on next- integration requirements to scale November 2006. The objective Coating Platform generation DRAM MIMCAP DRAM MIMCAP to future of the latter sub-program is to CARLSBAD, CA – Asymtek DeviceDevice PackagingPackaging has introduced its next genera- y it tion conformal coating plat- il Global Low-Cost ® c form, the Select Coat SL-940E. ew a f n With up to 30 percent faster N a i 7 si n 0 Wafer Bumping Services throughput, a vision system, y e 20 a p r closed-loop process controls, al o e traceability, and advanced inte- to b M to • Europe – USA – Asia • ConferenceConference && ExhibitionExhibition grated software, the Select Coat c O SL-940 provides high quality (www.imaps.org/devicepackaging) and increased productivity in a high-speed, high-accuracy coat- Exhibits: March 18 - 19, 2008 ing system. With the Select Coat SL- Conference & Events: March 17 - 20, 2008 940E, advanced monitoring makes it easier to keep the coating process in control. Fluid co-located with and air pressures are set and Global Business Council Spring 2008 Meeting: March 16 & 17 monitored through software- controlled electronic regulators, (www.imaps.org/gbc) allowing traceability for these critical parameters. Data log- ging and automatic adjustments Raddisson Fort McDowell of other parameters such as fan Scottsdale, AZ widths, fluid temperatures, and � Quick-turn and flow rates, further ensure the mass-production Available Processes quality of the coating process. � The new, faster motion sys- Highly competitive, � Electroless Ni/Au under-bump metallization General Chair: low-cost bumping tem of the SL-940E unleashes � Ni/Au bump for ACF or NCP assembly the performance capability of technology Larry Jacombsen, JH Technologies Asymtek’s SC-104/204 Film � Exceptional quality � Solder paste stencil printing Coater applicator, attaining 750 through high-level � Solder ball drop for wafer-level CSP mm per second speed and 1g expertise peak acceleration. It accommo- � Solder jet for micro-ball placement dates product sizes up to 500 mm for higher speed and faster � BGA and CSP reballing cycle times. � Wafer backside thinning and wafer dicing The SL-940E has a large Pac Tech GmbH dispense area of 500 x 475 mm Tel: +49 (0)3321/4495-100 [email protected] Special Features/Technologies (19.7 x 18.7 in.). The enlarged www.pactech.de work area enables flexibility � Over 10 years experience Pac Tech USA during production to add mul- � tiple board arrays or to coat Tel: 408-588-1925, ext. 202 U.S. Government Certified large substrates. Programming [email protected] � 4- to 12-inch wafer capability is made easier with the optional www.pactech-usa.com camera and pattern recognition Pac Tech Asia Sdn. Bhd. � Wafer pad metallization: Al and Cu system. The controls of popular Tel: +60 (4) 6430 628 � Solder alloys: eutectic SnPb37, lead-free, options like Asymtek’s Laser [email protected] Fan Width Control, Viscosity www.pactech-asia.com low-alpha, and AuSn Sponsored by: Control System, Bar Code Sys- � tem, and Flow Monitoring have Fluxless and contactless bumping for MEMS International Microelectronics And Packaging Society (IMAPS) been fully integrated within the Tel: +81-3-5640-2282 and optoelectronics www.imaps.org/devicepackaging machine for a more seamless [email protected] � Ni/Au interface for wire-bond applications operation. www.nagase.co.jp “Everything in electronics between the chip and the system!” For more information visit Asymtek’s website at www. asymtek.com. The leader in low-cost electroless wafer bumping.

www.meptec.org Q4 2007 / MEPTEC Report 15 MEPTEC Industry News

research high-k and metal gate Building on its expertise in Haas Electronics Materials, a nology like InterVia™ photore- options sustaining a high-k dielectrics and memory world leader in the development sists and photodielectrics to mar- DRAM-oriented process flow. research, IMEC expands its and manufacture of electronic ket requires our development In order to scale DRAM CMOS device scaling program materials for the semiconduc- labs to work with next gen- towards the 50nm node and to address these challenges. tor markets. The system from eration processing equipment”, beyond, MIMCAP dielectrics Further information on SUSS MicroTec will be used says Mike Toben, Global R&D require materials with a higher IMEC can be found at www. by Rohm and Haas Electronic Director for Rohm and Haas dielectric constant compared imec.be. Materials to develop, character- Electronic Materials, Packag- to current industrial materials ize and optimize photodielec- ing and Finishing Technologies such as ZrO2. By mid 2008, Rohm and Haas trics and both thick and thin “Our goal in selecting a new an effective oxide thickness of photoresists. The SUSS Gamma coating cluster was finding a 0.5nm is targeted for the MIM- Purchases CAP dielectric in the sub-50nm XPress was chosen over alter- system with the combination of technology node, going down Coating Cluster native equipment due to its high throughput and state-of- to 0.3nm in 2009 for the sub- from SUSS superior thick resist processing the-art control, and we believe 45nm node. Scaling the dielec- capability and its bridge tool we have found that with the tric equivalent oxide thickness MUNICH – SUSS Micro- design that permits concurrent new Gamma XPress. The SUSS while attaining very low leak- Tec has announced that it has handling of wafers with differ- MicroTec tool will significantly age currents is one of the major received the first order for ent sizes without mechanical enhance our R&D and customer bottlenecks DRAM industry is its new Gamma XPress coat/ changeover. modeling capabilities.” ◆ facing. develop cluster from Rohm and “Bringing leading edge tech- North American Semiconductor Equipment Industry Posts October 2007 Book-To-Bill Ratio of .83

SAN JOSE, CA – North American-based The SEMI book-to-bill is a ratio of Shipments and bookings figures are in manufacturers of semiconductor equip- three-month moving average bookings to millions of U.S. dollars. ◆ ment posted $1.23 billion in orders in three-month moving average shipments. October 2007 (three-month average basis) and a book-to-bill ratio of 0.83 according 12 Months Ending October 2007 to the October 2007 Book-to-Bill Report 2000 published by SEMI. A book-to-bill of 2000 0.83 means that $83 worth of orders were Average Shipments 1900 received for every $100 of product billed in Millions of Dollars 1800 for the month. $1488.1 1700 1600 The three-month average of worldwide 1500 bookings in October 2007 was $1.23 1500 billion. The bookings figure is flat with 1400 the final September 2007 level of $1.24 billion and 16 percent less than the $1.47 Average Bookings $1231.6 billion in orders posted in October 2006. in Millions of Dollars 1000 The three-month average of worldwide billings in October 2007 was $1.49 billion. The billings figure is about four percent less than the final September 2007 level of $1.56 billion and about five per- 500 cent less than the October 2006 billings level of $1.56 billion. “Actual sales of new semiconductor Book-to-BillBook-to-Bill equipment have generally followed the Ratio bookings trends, which have declined Ratio 0 Bar scale starts at 25 sequentially since the cyclic peak in early 5 per increment summer,” said Stanley T. Myers, presi- 1.01 .96 1.00 .98 .99 .98 .98 .91 dent and CEO of SEMI. “However, our .83 .82 .79 .83 expectation remains that 2007 equipment revenues will remain comparable to or slightly above 2006 sales.” Nov Dec Jan Feb Mar Apr May Jun Jul Aug Sep Oct 07

16 MEPTEC Report / Q4 2007 www.meptec.org PAN PACIFIC Microelectronics Symposium and Tabletop Exhibition

22 - 24 JANUARY 2008, SHERATON KAUAI RESORT

The Pan Paciﬁ c Symposium focuses on the critical business markets and technologies of microelectronic packaging, interconnection, microsystems technology and assembly. The Pan Paciﬁ c Tabletop Exhibition puts you in contact with global key decision makers and provides access and international visibility for your company and products.

SPONSORED BY SMTA Surface Mount Technology Association www.smta.org | 952-920-7682 | [email protected] MEPTEC Member Company Profile

ASE Kaohsiung, the flagship company in ASE Group, possesses valuable expertise in product and process technology for the manufacturing of CSP, high frequency packages, MCM, flip chip and wafer bumping manufacturing.

he ASE Group was established in 1984 as a semiconductor assembly company headquartered in Tai- wan. Over the course of 23 years, ASE has gradually evolved into a T$3.1 billion company, offering a broad range of services including IC packaging, test, material, with complete turnkey capabilities. Manufacturing was initially carried out in Taiwan, and later expanded into seven countries spread over four continents. From ASE: THE COMPLETE SOLUTION an original employee headcount of just one hundred, ASE now employs over 28,000 people worldwide. Today, ASE has achieved market leadership, and is the world’s largest provider of independent semiconductor manufacturing services in assembly and test. With key customers spanning the consumer, computing, and communication sectors, ASE serves both the IDM and Fabless communities, to meet the electronic industry’s growing need for faster, smaller, and higher performance semiconductor chips. The development of high- performance electronic products has spurred the innovation of semiconductor packages that have higher interconnect density and better electrical performance. As part of this technology migration, semiconductor packages have evolved from leadframe-based packages to substrate-based packages. The key differences of these package types are the size of the package; the density of the electri- with gold wire. ASE is the industry leader benefits include smaller package size, higher cal connections the packages can support; in fine-pitch wire bonding with the world’s pin-count, greater reliability, superior electri- and, the thermal and electrical characteristics largest capability. The company also holds cal signal transmission, and, better heat dis- of the package. patents for tri-tier fine-pitch technology, and sipation. BGA packages available from ASE ASE’s vast package portfolio meets exist- is ramping up quad-tier capabilities. In addi- include flip chip BGA, flip chip CSP, and ing and emerging market needs for both tion, ASE currently has more than 5,000 wire wire bond BGA family groups covering die leadframe and substrate-based packages. bonders in service, of which over 3,400 have combination and package combination. Die To address increased pin counts, ASE has fine-pitch bonding capabilities. combination packages include MCM BGA developed innovative packaging solutions ASE’s substrate-based package family and Stacked Die Package (SCSP), while with reduced footprint and higher electrical generally employs the BGA design which package combinations include Multi Package performance. Their leadframe-based pack- utilizes a substrate rather than a leadframe. BGA (MPBGA) and Stacked Package BGA age family includes offerings such as QFP BGA package types place the electrical con- (SPBGA), such as Package-in-Package (PiP), and QFN that are packaged by connecting nection at the bottom of the package surface System-in-Package (SiP), Package-on-Pack- the die, using wire bonders, to the leadframe in the form of small bumps or balls, and age (PoP), and so on.

ISE Labs Fremont California ASE Singapore ASE Shanghai, China (A&T) ASE Shanghai, China (Substrate) 18 and Austin, Texas ASE’S ROLE IN THE MANUFACTURING VALUE CHAIN To build a stronger foundation in its China operations, ASE carefully considered the needs of its employees who are relocated from other areas in China. ASE constructed dormitories on a 100,000 square meter land, within proximity of its production facilities to house 6,000 employees. By 2008, ASE will complete another housing project on a land space of 100,000 square meters, and a future expansion of another 200,000 square meters, offering accommodation for 30,000 employees. The Mainland Chinese government’s strong support for business investments and people development, complements ASE’s vision to serve customers with quality products and services. With the China economy registering near double-digit growth, Shanghai is thriving and has established itself as the Chinese capital of commerce, industry, finance, and technology. Their new manufacturing facilities are located close to Shanghai Pudong airport and ASE is the only assembly and test service ing its commitment in a number of areas, Shanghai’s metro system, which is one of provider with a sizable substrate operation. particularly the China market. Strategically the world’s newest, most rapidly expanding And with substrates becoming an increas- positioned within China’s electronics cluster, subway systems. ingly important factor in the IC packaging ASE’s newest facilities are located in the The China-based facilities are comple- process, customers are able to significantly Greater Shanghai area - Zhangjiang and Kun- mentary to ASE’s existing manufacturing reduce their costs and their cycle times by shan – and are aimed at providing cost-effec- facilities. In fact, ASE China serves as an taking advan tage of ASE’s state-of-art in- tive IC manufacturing services to customers operational unit of ASE factories in Korea, house substrate capabilities. ASE has the requiring supply chain support within the Japan, and Kaohsiung, Taiwan, providing capacity to supply laminate substrate for wire region. Operations commenced in 2005, as additional capacity and services to meet bonding innovations, as well as the build-up the first substrate manufacturing company growing customer needs. substrate for flip chip technology. in China. Today, ASE is the largest PBGA The scale of ASE in China has enabled ASE is the clear leader in test service mar- substrate supplier and continues to expand its the company to embark on an expansion of ket share, front-end engineering test, multi- business and product offerings. China, with its service offerings by including low pin platform testing and test program conversion. its abundant resources and booming infra- count and discrete IC packaging and test into They maintain more than 1,200 test systems, structure, will be the next engine of growth its portfolio. Leveraging on its manufactur- including the Agilent 93000, Teradyne Tiger, for ASE. In 5 years’ time, ASE estimates that ing expertise, land and business operations, etc, and are also the largest probing service its China operations will account for 50% of ASE will offer customers large scale and low provider with a capacity approaching 80,000 its total revenues. The company expects this cost manufacturing capacity. With an opera- wafers per month. ASE Group member ISE steady growth to propel it to achieve total tional unit comprising skilled engineering Labs has the largest engineering test cus- Group revenue of $24B by 2013. and logistical teams, ASE China is well-pre- tomer base in Silicon Valley. ASE has its customers’ interests in mind pared to assist and service customers, making Rounding out ASE’s complete service as it responds to the continuing evolution their manufacturing experience in China as solution set are turnkey Design Manufac- and domination of the consumer market. smooth as possible. Key to ASE’s ongoing turing Services (DMS) – the final step that Investing in strategic areas, such as China, success is a steadfast commitment to support brings customers sub-assemblies to the mar- and in particular the China infrastructure is capacity ramp-up, while constantly improv- ketplace. Again, ASE facilitates lower costs a priority. The ASE facility in Zhangjiang, ing cost structure and productivity. and shorter cycle times by deploying their occupies 190,000 square meters of produc- The electronics industry landscape is module capabilities in Shanghai and Shen- tion facilities and has an employee popula- undergoing major changes, in terms of con- zhen, China, close to major manufacturing tion of 7,000. ASE plans to acquire another solidation, innovation, and China market centers. 200,000 square meters of land which is scal- growth, and ASE is transforming itself to ASE’s turnkey services provide custom- able to employing 54,000 people. Leveraging better serve customers and positively impact ers a one-stop manufacturing solution, ulti- on China’s vast consumer market and human the future of the electronics industry. mately lowering overall costs and speeding capital, ASE devised a massive infrastructure The ASE Group welcomes all to learn time-to-market. development program offering customers more about their China initiative, visit their low cost manufacturing, and a skilled, disci- facilities, and engage their local engineering Focus on China plined workforce including highly educated teams. Go to www.aseglobal.com for more As ASE enters its next evolution of engineers and technicians from universities information about the ASE Group. ◆ growth, the company is focused on expand across the country.

ASE ChungLi, Taiwan ASE Takahata, Japan ASE Paju, Korea ASE Penang, Malaysia 19 MEPTEC SiP Technology

A Low Cost Alternative to Thru Silicon Via Can Packaging Technology Provide the Missing Link?

Marc Robinson Vertical Circuits, Inc.

ecently there has been much interest focused on TSV (thru-silicon via) technology as a solution to a number of problems facing the electron- Rics industry as we endeavor to continue increasing product complexity while simultaneously reducing cost. Essentially a front-end solution, TSV requires expensive equipment, and much process development, before it can be considered ready for reliable, low cost manufacture. Vertical Circuits (VCI), however, sees the solution remaining in the back end, through the use of virtual vias at the peripheral edges of the die stack, which offer a low cost, production ready solution today.

Why 3D? Relentless increases in electronic product complexity has been fueled over Figure 1. Market Drivers for 3 D Integration. the last half century by the semiconductor ind eature size shrinks, which occur approximately every 18 months, dutifully obeying Moore’s law. Accompanied by significant reductions in cost, the increase in useable transistors per square mil- limeter, has brought many new products within financial reach of the average consumer, including cell phones, digital music players, digital cameras, and personal digital assistants, just to name a few. However, there are clouds on the horizon, as the cost of continuing along this 2-dimensional shrink path become too burdensome for all but the largest global corporations to bear. There has always been strong interest in 3D solutions for increasing density, and improving performance. Small printed circuit boards have been stacked above other circuitry as daughter cards, and packaged devices have been stacked as well, especially for memory applications. Of late, there has been strong interest in Figure 2. The Overall 3D Market. moving the stacking focus from packaging and assembly based solutions into the wafer fabrication area to allow an “orders with relentless feature size reduction. As entails the use of complex wafer proof magnitude” increase in the number of a wafer fab focused technique, “through cessing steps, and hence the use of very vertical interconnections, and hence cre- silicon via”, or TSV as it is known, is the expensive wafer processing equipment, to ating significantly higher functional chip key technology at the core of most wafer create vias from the front side to the back densities without the need to continue fabrication focused 3D solutions. TSV side of the die. Due to the expense and 20 MEPTEC Report / Q4 2007 www.meptec.org complexity, TSV application is likely to be limited to the highest volume applications, and practiced by companies with the deepest pockets. It is clear from market forecasts, that there is a voracious appetite for high density 3D integration driven by the need to put more functionality in a single package. (Figure 1) Applica- tions abound in cell phones, portable music players, digital cameras, PDAs, and other consumer applications. Today, many such applications are addressed by stacked die packages utilizing wirebonds for interconnection of multiple die to a single substrate and by Package on Package solutions (PoP) solutions. Figure 3. The Laws of 3D-SiP. With all the hype surrounding TSV, one might conclude that stacking is about to move from the assembly house to the foundry, and will soon become a wafer processing “game”. However, with forecasts showing that 75% of the stacked die products are likely to be memory-only stacks, (Figure 2) one must question if there is a missing link in the industry’s 3D integration roadmap for the vast majority of the expected applications which will need more than today’s packaging solutions can provide, but do not need the high number of vertical interconnections which are provided by TSV. We must ask ourselves if the semiconductor industry has all the necessary tools in the toolbox to address the growing 3D demand, and if some of those capabilities can be cost effectively provided by a packaging based solution. Figure 4. Does TSV Obey the Laws of 3D-SiP?. The Laws of 3D SiP Performance, form-factor, cost, and adoptability have always been the key attributes a technology must satisfy to be viable in the marketplace. Simply stated, any new technology must be a better mouse trap, or there will be no customer interest. (Figure 3) Beyond the basic performance questions embodied by the question “Does it work?” the vertical interconnects must exceed the applications’ electrical and routability requirements, the process must be robust as demonstrated by CpK data, and products must pass appropri- ate reliability and quality tests for the intended application. From a form-factor perspective, the technology must enable significant increases in circuit densities, and be able to scale to support ever greater interconnect and die counts. For example, while 2 high stacks for DRAM memory cards Figure 5. The Vertical Interconnect Process (ViP). www.meptec.org Q4 2007 / MEPTEC Report 21 MEPTEC SiP Technology

represented one of the largest application areas just few years ago, today, in the flash memory area, there is currently a strong interest to stack between 8 and 16 die for memory card and solid state drive (SSD) applications, and there is great demand for mixed die stacking of multiple types of memory, graphics processors, and baseband processors for cell phone applications. Cost will always be king; not only the manufacturing cost, but also the cost of adoption. Low capital equipment expen- ditures in comparison to TSV, in the 1-3M$ range for an assembly based solution, can make a 3D technology much more available to the broad mainstream of users who are accustomed to having their needs served by traditional assembly and packaging subcontractors. Assem- bly techniques that allow massive pro- Figure 6. VCI Side Interconnect Technology. cess parallelism in assembly can serve to greatly reduce unit costs. Any technique for vertical stacking must also address the “known good die” (KGD) issue. Inclusion of bad die in a stack can cause loss of otherwise good die, effectively increasing the cost of a 3D solution. PoP has addressed this well, in that memory components can be thor- oughly tested before they are added to the PoP stack. With PoP, die ownership and yield ownership can be clearly defined. For most memory die, the inclusion of redundancy in the die design, and for flash, the ability to map out and avoid use of bad bits, somewhat mitigates the KGD problem, and has likely been one of the key reasons we have seen the largest adoption of 3D in memory applications. In contrast with the complicated IC level TSV processes in development at large corporations and university labs, VCI believes that a simple solution that utilizes existing assembly infrastructure can be used for many products today. Figure 7. Packaged Performance of ViP vs. Wirebond. An assembly based technique that mini- mizes disruptive processes, equipment and materials sets is ideal for high volume Does TSV Obey These Laws Yet? curve” that significantly reduces cost. As manufacture (HVM). Many aspects of TSV technology are a wafer fabrication based technology, it Adoptability, as well as the whole eco- clearly better and smaller than assem- is not likely to be simpler. Basic, main- nomic equation, can be further compli- bly and packaging based alternatives. stream, packaging and assembly tech- cated if the different die in the stack must The vias are clearly smaller in diam- niques, however, are ready today to meet be sourced from multiple suppliers. Will eter, and therefore can be more numer- a sizeable percentage of the expected 3D a memory supplier be willing to make ous. Most of the techniques currently demand. his die bigger to accommodate vias for a in development do an excellent job of TSV solution without increasing the price addressing thin die issues, as well as A Near-TSV Alternative of the die? And will suppliers cooperate alignment and die bonding issues. Unfor- Recognizing the need for a low cost on their process roadmaps so that a mixed tunately, while it may be better and small- mainstream approach applicable to the source solution continues to be viable er, TSV is neither cheaper nor simpler majority of expected 3D applications, through a 10 year horizon? Business than an assembly/packaging approach. VCI has developed a side interconnect die issues, as well as technical issues, must be (Figure 4) It is likely to be many years stacking technology that integrates eas- resolved for any 3D solution to be viable before TSV volumes grow sufficiently ily into a mainstream assemble factory, in mainstream, high volume applications. to drive the technology down a “learning thus making it available to a broad range

22 MEPTEC Report / Q4 2007 www.meptec.org of customers. (Figure 5) Vertical connections in contact with the edge of the die result in small component footprints barely larger than the die. The vertical interconnect is as close as you can get to TSV, without the need to make any vias in the die. (Figure 6) A non-disruptive approach, side interconnect stacking technology can make used of today’s extensive back-end infrastructure for low cost, high volume manufacture. A wafer array process is used to insu- late the die edges so that polymer conductors can later be applied to the sides of the die stacks without electrically shorting to the die. As the polymer insulation process coats all surfaces of the die, laser abla- tion is used to remove the polymer from the connection pads on the die. As the Figure 8. Reliability Summary. die remain in their original wafer array, the pre stacking die preparation steps benefit from the same economies of scale normally enjoyed by wafer foundry processes without the necessity to spend on extremely expensive capital equipment. In some cases, if the die have not been designed for edge connection stacking, or if the die pads are not in the proper location, an optional RDL layer can be applied to reposition the pads prior to the die insulation step. The wafers are thinned and singu- lated using standard, backend thinning techniques, in preparation for stacking and lamination. As standard backend thinning and singulation techniques are employed, any die thickness routinely achievable by the assembly factory can be utilized. For high die count memory card products, die thicknesses can be 50um or less. Following thinning and singulation, the die are stacked and laminated to each other using a thin, die attach preform, and vertical conductors are applied as a liquid to the side Figure 9. Scalability: Form-Factor and Die-Count. of the stack using standard deposition techniques and equipment, and cured at than wirebond or package on package in the polymer, either within the conduc- relatively low temperatures (~160C). The approaches. DC resistance of the vertical tors, or between conductors. completed stack with vertical intercon- conductor for typical side interconnect As noted earlier, chip scale packaging nections, known as a micropede® can be stacks is less than 20 milliohms, and AC footprints can be achieved, resulting in electrically and physically attached to performance excels. Figure 7 illustrates very high levels of packaging efficiency, any substrate, leadframe, or mother board a comparison between a wirebonded die and allowing dramatic volumetric reduc- using the same low temperature material stack, and a micropede® stack at DDR3 tions in the size of products such as SSDs. used to form the vertical interconnects. data rates. Both stacks utilize an identical (Figures 9 & 10). RDL to reroute the DRAMs’ center pads Low costs can be achieved as the The micropede® Meets the Laws of to the die periphery. The reduced parasit- key process of die stacking and vertical 3D SiP - Benefits ics and shorter length of the micropede® interconnection can be done as batch pro- As a side interconnect solution, results in larger valid data windows. cesses. Compared to the serial nature of the micropede® offers performance, Reliability testing shows that this side conventional stacked die wirebond meth- density(size) and cost advantages for the interconnect approach meets industry ods, the micropede® process is parallel majority of 3D Flash and DRAM applica- standards for server and handheld appli- in nature, as all the die can be stacked tions. A very short conduction path pro- cations. (Figure 8). Further tests of the and laminated in one step, and all of the vides lower inductance, and hence, better metal filled polymer conductors show that vertical interconnects can be applied in electrical characteristics and performance there is no migration of the metal particles one step. (Figure 11) While the general www.meptec.org Q4 2007 / MEPTEC Report 23 MEPTEC SiP Technology

KGD issue still must be addressed, the micropede® can be tested and/or burned in prior to final attachment to a substrate, and larger stacks can be assembled from a number of smaller stacks, allowing the test and verification of smaller subunits prior to assembly of larger stacks. This side interconnection method is much simpler than a wafer fabrication based TSV approach. As can be seen in Figure 12, with the exception of 2 unique steps, all the manufacturing capabilities for this approach are present in today’s assembly and packaging infrastructures, both within captive assembly facilities, and at assembly subcontractors. Further- more, the equipment required for these unique steps is significantly lower in capital cost, and cost of operation, than the etchers and other high cost fabrication equipment required for TSV.

The Conclusion Figure 10. 32GB SSD – Package Efficiency Comparison. A good carpenter owns more than one saw and a good mechanic owns more than one wrench. No one would expect them to approach all tasks with the same tool. Similarly, the 3D industry needs new tools in the 3D Toolbox to excel. These tools need to obey the “Laws of 3D-SIP” if they are to be adopted (Better, Smaller, Cheaper, Simpler). Stacked wire-bond CSP is a very strong incumbent, but it does not meet all of the industry’s 3D roadmap scaling needs. It will always coexist with other 3D solutions. PoP solves the die ownership and the KGD issue through the clear separation of the ASIC and memory into separate packages which are later stacked, and will continue to experience strong growth until 3D TSV wafer level solutions are low-cost. Single chip SoC embedded solutions force a process compromise for many functions on the chip, resulting in low yielding complicated fabri- Figure 11. Cycle Time: Advantage of Parallelism. cation processes that are neither cost effect, nor silicon efficient. TSV is a very attractive solution in terms of “Better & Smaller”, but needs years of technology and business development before it is “Cheaper & Simpler”. Side interconnection approaches, such as VCI’s micropede® offer a simple, cheap, and ready stacked CSP technology today that can handle the majority of 3D applications with minimal form factors and proven reliability. While side interconnection approaches will not replace stacked wire-bond, PoP, or TSV approaches, the micropede® approach represents a new “Tool in the 3D Tool Box” that is appro- priate for many high volume applications. ◆ Figure 12. VCI’s ViP Manufacturing Process.

24 MEPTEC Report / Q4 2007 www.meptec.org

MEPTEC MEMS Technology

MEMS Substrates: Going to 6 Inch and 8 Inch

Jean-Christophe Eloy Yole Développement

ole Développement has just released its new analysis of the MEMS markets (“Sta- tus of the MEMS industry 2007” report, now avail- Yable), see Figures 1 and 2 for a detailed analysis. The MEMS markets in 2006 reached US $5.8 B. Concerning the future, we can estimate that the 2011 MEMS markets will reach more than US $10.7 B, with very diverse growth rate depending on the devices and the applications: silicon microphone and RF MEMS are the fastest growing applications (see Figure 2). These devices will more and more impact the consumer applications (mobile phone, DSC…) but are also finding industrial, medical and security applications. Ink jet head and pressure sensors have limited growth (around 4%) due to the maturity of the market. The Figure 1. Evolution of the MEMS markets (Source Yole Développement). price pressure is very high and is lim- iting the growth of these applications. Inertial sensors (accelerometers and IR image sensors are very promising growing application and the fuel for gyroscopes) are finding their growth devices with incredible growth at the new innovation in the MEMS indus- both in the automotive and consumer moment. try. A lot of new devices are under markets. Here also, price pressure is The new emerging applications development and will impact the mar- very high and the growth in number (like microfuel cell, silicon oscillator, ket within 3 years. of units is much stronger. energy harvesting devices… which All in all, we can say that the Optical MEMS are finding a lot represent a zero value at the moment) MEMS markets are growing and are of new applications and we are also will reach within 5 years 7% of the impacting more and more applica- expecting strong growth rate. MEMS business. This is the fastest tions, from high end security sys-

Figure 2. MEMS markets figures (Source Yole Développement).

26 MEPTEC Report / Q4 2007 www.meptec.org tems to consumer last gadget. But the strong increase of the consumer applications are pushing the changes of the manufacturing infrastructure.

MEMS Substrate Markets MEMS substrate materials include silicon, quartz, glass, SOI, polymers and other materials. The figures 3 and 4 are describing the use of these different substrates in production and the forecast up to 2010. Silicon is the dominant material for the manufacturing of MEMS devices. The 2006 market for silicon substrate for MEMS manufacturing was close to $315 M and will reach approximately $600 M by 2012. The market has seen a very strong evolution size 2002. At that time, the 4’’ wafers were the dominant wafer diameter. This has totally changed. Now 6’’ wafer are dominating the Figure 3. Global substrate market for MEMS manufacturing. market with more than 14% of annual growth rate (compared to a decrease of 15% per year for the 4’’ silicon wafer market). The Figure 4 is giv- ing all the details of such evolution. The fastest growing market are linked to 8’’ wafers, with a 53% compound aanual growth rate. These changes can be explained on a simple way: most of the companies have both seen an increase of the sales volume in number of units and a strong pressure on price coming from customers. So at one point, the solution is to change the wafer size in order to get benefit of the impact on manufacturing cost of such changes. So most of the Top 30 MEMS manufacturers are now manufacturing on 6’’ wafer and an important number of companies outside this Top 30 ranking have also make the choice to manufacturer on 6’’. What about 8’’ and 300 mm? 300 mm is actually not the choice of the Figure 4. Evolution of the silicon MEMS substrate use in production. MEMS manufacturers. But several companies are already using 8’’ manufacturing. In this category we can see provided to MemsIC and several other Several of the new fabless compa- 2 types of companies: MEMS device companies), TMT (for the manufac- nies including SiTime, MemsIC … manufacturers (with large design or turing of micromirrors), Dai Nip- have chosen to subcontract the manu- looking at consumer applications) and pon Printing (for foundry services in facturing of the MEMS devices to fabless companies targeting the con- accelerometer), Canon (ink jet head), semiconductor companies or MEMS sumer markets. STMicroelectronics, SVTC, Omron, manufacturers working on 8’’. SiTime Several device manufacturers are Silex, Freescale … are among the few is working with SVTC, MemsIC with already producing on 8’’ lines: Texas companies with 8’’ capacities. LETI TSMC. They have done this choice Instruments (for digital light projec- in France has also now a dedicated in order to get the cost benefit of an tors), TMSC (for the foundry services MEMS R&D facility on 8’’. 8’’ line and also because the compat- www.meptec.org Q4 2007 / MEPTEC Report 27 MEPTEC MEMS Technology

foundries. • One foundry (TSMC) has 50% market share, reducing the size of the other players (UMC, SMIC, etc.) If we apply this ratio to the MEMS industry in 2016, the results are surprising: • 10% of the MEMS business will be in the hands of MEMS foundries, meaning a US $2 billion industry (compared to a US $400 million market today). • One player will have 50% of the market, resulting in one US $1 billion MEMS foundry. The question remains, who will be able to build a US $1 billion MEMS foundry company in the next 10 years? And in order to do this, will MEMS manufacturing processes have to be standardized? This dream Figure 5. Evolution of the thick SOI MEMS substrate use in production. may not seem possible today but the semiconductor industry achieved this goal 15 years ago while many people ibility on the long run with pure semi- or beneath MEMS devices). These were sceptical about the viability of conductor manufacturing will be key, technologies seems to be so promising the semiconductor foundry business in order to prepare future integration that SOITEC (France) has acquired model. with IC devices. Tracit Technologies few months ago, Following the semiconductor ex- Another key trend is the use of in order to get full access to these ample, we hope that the dream of SOI wafer. It is the material of choice technologies and embedded it in its building a US $1B MEMS foundry to manufacture accelerometers, gyro- offers. The key objective is to target will turn into a reality! scopes and optical mirrors (see figure wafer level packaging/advanced pack- MEMS business is growing and 5). aging business and the integration of changing. Yole Développement is day All these trends lead to a very heterogeneous materials and layers for after day looking at the evolution strong increase of the silicon wafer semiconductor applications, including of the MEMS markets and industry market for MEMS manufacturing. MEMS. and reporting these evolutions in our The wafer market for MEMS manu- The MEMS technologies are more publications Micronews, the online facturing is rather limited compare to and more re-used for other applica- news provider iMicronews and in our the semiconductor one and the techni- tions, linked to the mainstream semi- reports. With its strong involvement cal requirements are different. Many conductor business. MEMS is clearly in MEMS industrial business (we are MEMS manufacturers need double more and more a key enabling tech- making more than 1500 industrial con- side polished wafers, specific technology for the whole industry. tacts every year linked to MEMS busi- nical specifications, even very thin ness), Yole Développement is leading wafers! Looking to the Future, Let’s Imagine the MEMS Foundry the way in the analysis of MEMS Several companies have been spe- markets worldwide. ◆ cialised in this area like Okmetic (Fin- Business in 2016… land), Virginia Semiconductor (USA) In 2016, we expect the MEMS … and several key silicon manufac- market to generate approximately US Yole Développement is a market turers are also involved like SHE, $20 billion in revenue based on a research and strategy consulting com- Siltronics … 2006-2016 13% compound annual pany, world leader in the analysis and We can see also new trends which growth rate (see Figure 1). evaluation of the Mems markets and could be important on the long run. We also predict that the “MEMS also involved in the compound semi- Several companies (like Ziptronics law: one product one process” will be conductor industry (SiC, GaN and USA, and Tracit Technologies France), solved, resulting in the evolution to a SOI) and power devices markets. Yole are developing innovative solutions in more mature industry. Développement is editing reports, order to transfer active layers from If we can extrapolate what has hap- describing the different Mems markets one wafer to other wafers. This could pened in the semiconductor industry: and industry trends (www.yole.fr) be applied to the transfer of MEMS • Approximately 10% of overall semi- You can reach J.C. Eloy at the fol- devices above IC (or IC devices above conductor business is in the hands of lowing email : [email protected] ◆

28 MEPTEC Report / Q4 2007 www.meptec.org ad 08_wbleeds 11/21/07 9:52 AM Page 1

SMTA Medical Electronics Symposium

Anaheim Convention Center | Anaheim, CA JANUARY 29-31, 2008 MEDICAL ELECTRONICS SYMPOSIUM

The 2008 SMTA Medical Electronics Symposium will include the market’s current and future outlooks, regulatory requirements, legal perspectives, components, reliability, trends, initiative projects and advanced applications.

This year’s symposium will feature:

* Two half-day tutorials led by an expert in the industry. * Two full days of technical presentations from Henkel, HEI, Inc., Trace Laboratories, the FDA, and many more...

* More than 1,200 exhibiting companies at MD&M West. * An exciting Keynote Presentation from Celeste Null, Director of Biomedical Engineering, Intel Corporation.

Celeste Null, Director of Biomedical Engineering, Intel Corporation

WWW.SMTA.ORG MEPTEC Solder Joint Reliability

Pb-free Solder Sphere Alloys – Future of High Reliability

Ranjit Pandher and Robert Healey Cookson Electronics Semiconductor Products

he drop shock reliability of sol- alloys can be minimized through the Electronics’ proprietary alloy contain-ing der joints has become a major selection of low-Ag alloys. At lower Ag 0.3% Ag.) issue for the electronics indus- there is less Ag3Sn IMC in the bulk alloy First, the “DS” micro-additive combi- try partly because of the ever with concomitant reduction in mechani- nation increases solder wetting character- increasing popularity of por- cal strength. Clearly, lower Ag alloys istics, modifies the bulk grain structure, Ttable electronics and partly due to the have an advantage in potentially absorb- alters the nature of bulk IMCs, and transition to Pb-free solders. Most of the ing the effect of high strain rate deforma- controls the thickness of the interfacial commonly recommended Pb-free solders tion. The other factor examined is the IMC. This results in maximized drop- are high-Sn alloys which have relatively nature and amount of the IMC formed in shock resistance when compared to cur- higher strength and modulus. This plays soldering. rent leading alloys such as SAC105 and a critical role in the reliability of Pb-free The work described in this article SAC125+Ni, as shown in Figure 1. solder joints. It is the Sn in solder alloys focuses on alternative alloys for BGA Second, the “DS” micro-additive that principally participates in solder and CSP applications which drastically combination significantly lowers surface joint formation. Despite this, intermetal- improve drop-shock performance over oxidation resulting in much better tarnish lic compound (IMC) layers formed with high-silver alloys such as SAC305 and resistance. See Figure 2. SnPb and Pb-free alloys are different. SAC405, while maintaining acceptable The markedly different process condi- thermal cycling properties. In developing tions for SnPb and Pb-free alloys also improved performance solders, Cook- affect solder joint quality. son Electronics has addressed ductility Brittle failure of solder joints in drop through the development of low-Ag SAC shock occurs at or in the interfacial IMC alloys with improved wetting and spread layer(s). This is due to the inherent brittle properties, and modification and control nature of the IMC, defects within or at of IMC through manipulation and com- IMC interfaces or transfer of stress to the bina-tions of micro-alloying additives. interfaces as a result of the low ductility Various micro-additives have been Figure 2. Sphere discoloration test after 200°C of the bulk solder. investigated including Bi, Ni, In, Cr, and for 24 hours. In developing improved perfor- Ge. Each additive and different combina- mance alloys, Cookson Electronics has tions of additives in low-Ag alloys have The SACX-DS alloy has displayed addressed both issues – improved duc- been investigated. the best drop-shock performance and tility, and modification and control of exhibited the best tarnish resistance com- the intermetallic layer. A broad range pared to all other alloys tested. In addi- of base alloy compositions, combined tion to superb drop-shock performance, with selected micro-alloying additions the SACX® family has exhibited excep- to SnAgCu alloys, have been evaluated. tional temperature cycling performance The objective is to control bulk alloy over traditional low-Ag alloys due to the mechanical properties and alter the diffu- modified bulk grain structure. SACX® is sion processes operating in the formation currently under temperature cycling reli- and growth of the intermetallic interfacial ability testing (-55°C – 125°C) and has layer(s). survived >5000 cycles with no failures With the electronics industry move to to date, while low silver alloys such as Pb-free soldering, SAC305 and SAC405 SAC105 have failed around 4000 cycles. have become the alloys of choice based In addition to solder spheres, Cookson ® on lowest available melting temperature, Figure 1. Drop Shock test results using 0.30mm Electronics offers other SACX family near eutectic composition and acceptable (12mil) spheres attached to CABGA84 substrate solder products, such as solder paste and to good cyclic thermal fatigue proper- with NiAu pad finish. bar solder. To learn more, please contact ties. your local Cookson Electronics Semi- A large number of alloys have been It has been discovered that a particular conductor Products representative or visit evaluated and discussed as alternatives combination of micro-additives, referred www.cooksonsemi.com. ◆ to high-Ag SAC alloys for BGA and to as “DS” has a unique positive syner- CSP dependent devices. The first factor gistic effect on solder joint characteristics addressed is bulk alloy properties. The when incorporated into both SAC105 and effect of the higher strength of high-Sn SACX® base alloys. (SACX® is Cookson

30 MEPTEC Report / Q4 2007 www.meptec.org cookson_cesp_ad.qxp 10/30/07 7:32 AM Page 1

WhatWhat demanding demanding solder solder relatedrelated packaging packaging challengeschallenges do do you you faceface every every day? day?

Do you experience high missing-ball rates during the ball

® attach process? Are you constantly making trade-off decisions between high drop-shock alloy reliability and temperature cycling performance. Is flip-chip die misalignment or underfill delamination reducing your package yield? Cookson Electronics Semiconductor Products line of solder products will deliver consistently reliable package results while helping you control process costs and increase yield. Our commitment to high level R&D drives our world class formulation capabilities. We offer: • ALPHA® Flux for BGA/CSP/wafer level ball attach, flip chip attach and wafer bumping • ALPHA® Solder Spheres for area array packages, wafer-level packages, flip chip wafer bumping and substrate bumping • ALPHA® Solder Paste for component attachment and wafer bumping

alpha For more information about Cookson Electronics semiconductor solder products, and our epoxy mold compounds and electronic polymer lines, go to www.cooksonsemi.com. or contact your Cookson Electronics Semiconductor Products representative.

Worldwide Headquarters • 3950 Johns Creek Court, Suite 300 • Suwanee, GA, USA • +1-888-263-0443 Asia-Pacific Headquarters • 12 Joo Koon Road • Singapore-628975 • +65-6861-0244 © 2007 Cookson Electronics December 2007

The Total Package: Next-Generation Tacky Flux and Solder Spheres

Mark Currie and Henry Wang The Electronics Group of Henkel

rray package production, in partic- miss the largest of the smallest diameter of the der spheres is becoming crucial. By partnering ular BGA and CSP package manu- sphere. Roundness is also a measurement that with the right supplier, you can maintain cur- facture, has increased by nearly should be taken into account and is employed rent component manufacturing yields achieved 25% CAGR over the past decade by very few sphere suppliers. The sphere, for with large spheres. Choose the wrong supplier, and is forecast to maintain that maximum performance, should be nearly per- however, and issues such as co-planarity may Acontinued growth rate. Simultaneously, devic- fectly round. Sphere geometry is important for plague your process. es are packing in more functionality, yielding many reasons. First, today’s sphere deposition Once the spheres have been produced, it higher I/O counts and finer pitches. But for equipment is very precise and any odd-shaped is critical to have a robust tacky flux system these new packages to deliver the performance spheres may cause the equipment to jam, thus for ball attach. When one is attaching solder and reliability required for today’s advanced affecting throughput significantly. Secondly, if spheres to the die for BGA and CSP produc- electronics products, technically robust sol- spheres used on the same BGA have different tion, there are two flux systems: no clean and der spheres and tacky fluxes are essential. In diameters and the differential is quite large, water water-wash fluxes. As with all Henkel relation to the spheres specifically, it is quite coplanarity issues can be the result. materials, the new line of tacky fluxes has surprising that there currently exists no world- A novel sphere production method, how- been designed in-process and in-package to wide standard to define the quality of solder ever, is delivering spheres with a level of qual- ensure excellent results in the filed. All of spheres, leaving packaging firms to rely on the ity, repeatability and control not achievable the formulations are lead-free capable and sphere manufacturer’s production and quality through traditional manufacturing methods – a exhibit outstanding performance in today’s methods as well as their own analysis. And, process that eliminates virtually all of the pre- demanding manufacturing environments and, with sphere diameters continuing to shrink to viously mentioned issues, yielding very round because each of these materials has also been address device miniaturization, this becomes a spheres with consistent, repeatable diameters developed to the highest reliability standards, more difficult proposition. and extremely low oxidation levels. The pro- users are assured that there will be absolutely Conventional sphere production methods cess, patented by Henkel, utilizes a proprietary no potential for corrosion post-component incorporate a mechanical process whereby mechanical jetting procedure and innovative build. Building on the success of Henkel’s small metal particles are cut or punched out sorting method that results in superior quality approach to low-voiding solder pastes, similar from fine wire or metal sheets. The particles control, very low contamination (oxidation) technologies have been used in the develop- are dropped into a hot oil bath where they are and outstanding coplanarity. To address the ment of these next generation flux systems. melted to form small round drops. As the oil common issue of oxidation, Accurus’ process As compared to competitive materials, Hen- cools, the droplets solidify into spheres. This was developed to reduce the amount of surface kel’s tacky fluxes deliver much faster wetting, procedure has intrinsic limitations that result oxygen and, therefore, minimize the “blacken- which is critical for void reduction. When the in coarse dimensional tolerances because each ing effect” and increase the sphere shelf life. device goes through reflow, slow wetting can mechanical operation adds a certain amount Diameter and roundness are also addressed enable flux entrapment and surface oxides of deviation to the size and uniformity of the with some unique perspectives. The technolo- may become trapped, causing void creation particles which, together, produce an unaccept- gists at Henkel firmly believe that two mea- and a less than sufficient interconnect. With able cumulative effect. surements to determine sphere diameter are Henkel’s faster wetting formulations, the flux The other factor which affects sphere per- simply not enough. For Multicore® Accurus™ works faster during the reflow process, yield- formance is what is commonly referred to as spheres, 100 measurements per sphere – some- ing quicker intermetallic growth and much the “blackening effect”, in short: oxidation. It times more – are taken and the diameter of stronger interconnects. In addition, Henkel’s is well known that spheres will turn dark after the sphere is the average value of the multiple new flux technologies do not slump – the they collide against each other and against measurements. Per every 1 million spheres, fluxes wet and clean, which is also critical the container wall during handling, storage over 1,000 spheres are sampled and each is in minimizing void levels in the sphere to and shipment. The oxidation, if severe and subjected to a minimum of 100 measurements, component connections. These latest no-clean not amended during reflow due to insufficient ensuring that deviation within each batch is tacky flux systems – Multicore® TFN600, and flux or too thick an oxide layer, can be quite minimal, and the Cpk of each batch remains an Multicore TFN610 - have been optimized for a detrimental. This condition can cause an inad- industry high. In addition, a roundness value variety of different surfaces including Cu-OSP, equate solder bond between the sphere and its (R) is determined by dividing the difference Ni-Au and ImmAg as well as various types of corresponding substrate solder pad. Minimal between the largest diameter measurement flux application, including screen printing, pin oxidation is obviously the most ideal condi- and the smallest diameter measurement by the transfer and dispensing and, going forward, for tion. sphere diameter. As a rule, a sphere’s round- jetting or spraying. Last, but certainly not least is sphere ness factor will be considered good when its R Do you have the total package? For more geometry – diameter and roundness. Most value (based on the above formula) is less than information on Henkel’s advanced solder sphere suppliers determine the diameter of 0.033. Considering the movement in the indus- sphere and tacky flux technologies, call 949- their spheres by measuring in two directions, try demanding smaller and smaller diameter 789-2500 or log onto www.henkel.com/elec- x and y. This is not optimal, as it is easy to spheres and tighter pitches, the quality of sol- tronics. ◆

32 MEPTEC Report / Q4 2007 www.meptec.org AIE Eye Ad-MEPTEC 5/30/07 12:51 PM Page 1

More than meets the eye Compatibility-proven Material Sets from Henkel.

Trust Henkel’s Material Sets that truly work together. Trying to force non-optimized materials to work together in advanced packages and assemblies? At Henkel, our materials are specifically designed to work together, delivering tested, reliable and guaranteed compatible material sets for all of your semiconductor packaging and circuit board assembly requirements.

Contact our application experts today for material set solutions that work: Henkel Americas: +1 949 789 2500 Henkel Europe: +44 1442 278 000 Henkel Asia: +852 2233 0000

Across the Board. Across the Globe. www.henkelna.com/electronics

Advanced Component Labs, Inc. COMPLEX FLIP-CHIP ASSEMBLY WITH SAME DAY TURN

• Over 3200 bump/ball IO’s • Flexible Process Flows • Wide Material Selection • Gold Stud Bumping SRO – Solder • Prototypes: as quick as Reflow Ovens 8 hours! • Production: 1000’s of “Time Critical” � Perfect reflow soldering units per week Semiconductor Substrates � Rapid thermal annealing under controlled atmosphere, vacuum and pressure CORWIL has developed into the premier U.S.- BGA, CSP, Flip Chip, High Frequency, � Perfect solder joints, no voids based packaging subcontractor with world-class High Speed and Thermally Enhanced wafer thinning, dicing, pick-and-place and visual Rigid and Flex Packages Also available inspection, plus state-of-the-art IC assembly in PEO – Semiconductor BGA, ceramic, plastic, QFN, COB and MCM ACL is the only Process Furnaces packages. In addition to flip-chip capability, CORWIL North American company has outstanding wirebonding expertise for ultra- focusing exclusively on the fine pitch applications in gold and aluminum wire. fabrication of “Quick Turn” Since 1990 CORWIL has built its reputation providing U.S. and Canada customers with: semiconductor packages. Representative: 328 Martin Avenue • Santa Clara, CA 95050 Excellent Quality and Superior Service Phone: 408.327.0200 Email: [email protected] Tel: 408-588-1925 • Fax: 408-588-1927 Phone 408-321-6404 • Fax 408-321-6407 Email: [email protected] www.aclusa.com www.pactech.de www.corwil.com Chip HANA Microelectronics Hestia SYSTEM IN PACKAGE & Packaging 2.0 MULTI CHIP PACKAGES

In the current “Chip Packaging 1.0” world, chips are thrown “over the

wall” to PCB designers, often years Servicing the Semiconductor Industry for over 25 years with manufacturing locations in Thailand after the chips were designed. There and China. is no channel for chipmakers to talk • Specializing in Low Pin count Plastic Packages with PCB designers. In the proposed • Ceramic and Laminate LGA’s • Standard and Custom QFN’s “Chip Packaging 2.0” world, PCB • Custom Package Development for Sensor designers use EDA software to re- Applications. ENGINEERING - PROTOTYPE - PRODUCTION map the package pinout of legacy • Full service Semiconductor processing including; Hestia Technologies, Inc.: Provides packaging die without altering the performance Back Grinding, Wafer Saw, Packaging, Test and solutions for multi-chip applications. If your require- Drop Shipment coordination of the silicon to arrive at the optimal ment is for a lead frame or substrate based package, • Lead Free, Green and RoHS compliant Packages point for PCB board design. wire bond or flip chip Hestia has a packaging solution. available We have provided packages and sub-assemblies for • QS9000, TS16949, and ISO14001 Certified multi-chip, hybrids and MCM’S for over 12 years. For more information visit our website or call Bruce If your packaging requirements call for SIP, MCM, Stromstad at 408-467-0911. single or multiple die, with or without passive components or any custom application contact Hestia for its innovative and refreshing approach to packaging. Hestia continues providing packaging solutions from inception through design, material selection along with engineering, prototype and production volume quanti- [email protected] ties since 1983. For more information on our capabilities and ser- (949) 250-4001 vices contact Hal Shoemaker at 408-844-8675. www.Hanagroup.com www.hestiatechnologies.com www.MirrorSemi.com

34 MEPTEC Report / Q4 2007 www.meptec.org MEPTEC Network

cost effective Solution to SOLDER SPHERES ceramic packaging 1`iÀwÊÊvÀÊ9ÕÀÊ ÕÀÀiÌÊ >`ÊÕÌÕÀiÊ,iµÕÀiiÌÃ ÊÊ

SEMPAC, Inc. designs and manufactures Pre-Molded, Open Cavity Plastic Packages. -ISALEADINGSOURCEFORHIGH Our Open-Pak™ is becoming the technol- TECHNOLOGY UNDERlLLS ENCAPSULANTS ogy of choice for many who must meet the COATINGSANDSPECIALTYADHESIVESUSED demands of today’s small outline integrated circuit package applications. SEMPAC’s BYPRODUCERSOFSEMICONDUCTORDEVIC LEAD FREE SPHERES products provide an ideal choice for IC Die ES (EADQUARTERED IN .IIGATA *APAN EUTECTIC SPHERES qualification, Prototype & Test applications, WITHSUBSIDIARIESINTHE53! %UROPE ISO 9001 & 14000 & QS 9000 CERTIFIED and device packaging for MEMS, Optoelec- 3INGAPOREAND#HINA .!-)#3SERVES LOCAL STOCK tronic, RF, Sensor and Telecommunication devices. ITSWORLDWIDECUSTOMERSWITHENABLING ™ Profound Materials Technology Co. Ltd. Open-Pak is available in standard JEDEC PRODUCTS FOR LEADING EDGE APPLICA products supported and distributed by outlines including QFN, QFP, SOIC and TIONS SSOP architectures. Cumulative Technologies Corp. Phone: 408-400-9002 990 Richard Ave. #109 &ORMOREINFORMATIONVISITOURWEBSITE Santa Clara, CA 95050 Fax: 408-400-9006 ORCALL 408-969-9918 e-mail [email protected] Email: [email protected] ÜÜÜ°>VÃ°V°« www.profound-material.com www.sempac.com

Don’t Miss Your Chance to Advertise SGP Ventures, Inc. is the exclusive sales in the Next Issue agent in North America for San-Ei Kagaku Providing semiconductor packaging trends and Co., Ltd., a Japanese manufacturer of via- market forecasts for the past 20 years. of the plugging materials used in the processing of Analysis on: advanced Printed Wiring Boards. The PHP- • Embedded Components/Integrated Passives MEPTEC Report 900 Series • 3D Interconnect, including Through of non-conductive, solvent-free, Silicon Vias epoxy resin-based materials is used worldwide • Flip Chip/ Wafer Level Packaging by the leading PWB manufacturers to plug • BGAs, CSPs, System-in-Packages plated through holes for a wide range of appli- • Electronics Manufacturing in India/China For Advertising Rates Contact cations, including automotive, aerospace, and • Product Teardown Reports other high reliability environments. A variety • Semiconductor Packaging Materials Kim Barber • Workshops on Emerging Packaging Trends of formulations of PHP-900 are available, • Technology Licensing Director including IR-6, IR-6P, and IR-10F, in order Sales & Marketing to meet specific cost/performance requirements. Also, a new SSR-6300S Series liq- [email protected] uid photo-imageable solder resist is available to meet the needs of the rapidly growing LED (408) 309-3900 market. SSR-6300S is white in color, with high reflectivity and resistance to discoloration attributable to thermal exposure.

For more information about San-ei’s products For more information contact call 408.879.6224 or Jan Vardaman or Becky Travelstead at Join Us! e-mail [email protected]. 512-372-8887 or [email protected] www.sgpv.com www.techsearchinc.com www.meptec.org www.meptec.org Q4 2007 / MEPTEC Report 35 “WE SAvED WEEkS OF TIME AND FOuND THE ‘PERFECT FIT’ AT APEX!”

“In what could have taken weeks to do, I was able to see firsthand what technology was available, view up close how the equipment was designed, understand how much thought went into putting it together, and determine how serviceable and ergonomically valuable it was. This new equipment is compact, improves our cost/sq. ft. ratio, and provides added flexibility and functionality. Overall, it improves our bottom line so we can be more competitive.” Richard Moraca, Engineer St. Jude Medical — CRMD

IPC Printed Circuits Expo®, APEX® and the Designers Summit The ONLY international show featuring a premier exhibition, influential standards development meetings, an exclusive technical conference and first-rate professional development courses.

It’s MY Show!

DESIGN PRINTED BOARDS ELECTRONICS ASSEMBLY TEST

CONFERENCE & EXHIBITION: April 1–3, 2008 MEETINGS: March 29–April 3, 2008 Mandalay Bay Resort & Convention Center, Las Vegas +1 847-597-2860 | 877-472-4724 (U.S./Canada) | [email protected] | www.GoIPCShows.org SUNDAY MONDAY TUESDAY WEDNESDAY THURSDAY FRIDAY SATURDAY 1 1 2 3 4 5

NEW YEAR’S DAY

6 7 8 9 10 11 12

13 14 15 16 17 18 19 SUNNYVALE MEPTEC LUNCHEON Ramada Silicon Valley Sunnyvale, CA 20 21 22 23 24 25 26 SOUTHWEST MARTIN LUTHER KING MEPTEC LUNCHEON JR. DAY Dobson Ranch Inn Mesa, AZ JANUARY 2008 27 28 29 30 31 1 2

SMTA MEDICAL ELECTRONICS SYMPOSIUM January 29 - 31 Anaheim Convention Center, Anaheim, California 3 4 5 6 7 8 9

DESIGNCON 2008 February 4 - 7 Santa Clara Convention Center, Santa Clara, California 10 11 12 13 14 15 16

LINCOLN’S BIRTHDAY VALENTINE’S DAY

17 18 19 20 21 22 23

PRESIDENT’S DAY WASHINGTON’S BIRTHDAY

24 25 26 27 28 29 1 MEPTEC THERMAL

FEBRUARY 2008 MANAGEMENT SYMPOSIUM San Jose, California 2 3 4 5 6 7 8

9 10 11 12 13 14 15

SUNNYVALE SOUTHWEST DAYLIGHT SAVING MEPTEC LUNCHEON MEPTEC LUNCHEON TIME BEGINS Ramada Silicon Valley Dobson Ranch Inn Sunnyvale, CA Mesa, AZ 16 17 18 19 20 21 22

SEMICO SUMMIT IMAPS 4TH INTERNATIONAL DEVICE PKG CONFERENCE March 16 - 18, Camelback Inn, Scottsdale, AZ March 17 - 20, Raddison Fort McDowell, Scottsdale, Arizona

ST. PATRICK’S DAY SPRING BEGINS 23 30 24 31 25 26 27 28 29 M A R C H 2 0 0 8

EASTER (23RD) www.meptec.org Q4 2007 / MEPTEC Report 37 MEPTEC Editorial

Why Film Will Make the Final Cut for Stacked Die Applications

Bhavesh Muni The Electronics Group of Henkel

hough we may not have pre- manufacturing approach for multiple die- When using DDF materials, packaging dicted how quickly the minia- stack, integrated devices. Paste-based die specialists must carefully evaluate DDF turization craze would progress, stacking processes are much more time characteristics that may have an impact we all certainly recognized that intensive and require a more significant on package performance and processing new materials technology was equipment investment than that of die requirements. Thermal-mechanical prop- Tgoing to be required if thinner wafers attach films. Die attach paste is dispensed erties affect the stress placed on the thin, and die were going to be the norm. Only onto the mother die, the second level die is stacked die and must be optimized to a few short years ago, wafers were being placed and then the stack is transferred into reduce the possibility of die cracking and thinned to 150 microns to enable 4-die the curing oven. This process must then be delamination. Next, the visco-elastic prop- stacks – a watershed moment for the repeated for every level of the die stack. erties of the DDF affects the processing of packaging industry, to be sure. But, as Once the stack is complete, the package the film so these films must also embody they say, records were made to be broken can move to wire bonding. Films, on the excellent visco-elastic properties to allow and we are now finding wafers thinned to other hand, deliver significant advantages. easy die pick-up from the dicing film and 75-microns to be commonplace, and are DDF materials, specifically, are dual func- fast die bonding placement times. Dicing beginning to see 50 micron and 25 micron tion products that combine the dicing tape film release is also an important factor. thick wafers in production. These ultra DDF films are designed so that the die thin wafers and die are enabling the new- attach material releases from the dicing est generation of stacked die CSP (SCSP) tape adhesive when picked up along with and stacked package (POP) technologies. Die attach film the die. Some DDF materials require an In fact, these thin die are vital if minia- materials will be extra UV cure step to promote film sepa- turized and highly functional devices are ration. Not only do UV processes require going to progress even further. the way forward additional time and equipment, but they There are clear advantages to inte- may also be problematic. If the UV proce- grated packages. In addition to the obvious for successful dure is not perfectly executed, film release footprint reduction, these products often integrated package may not occur, resulting in the potential deliver lower overall packaging costs, too. scrapping of the entire wafer. And, finally Take SCSPs, for example: only one HDI production. the curing abilities of the DDF must be substrate is being used, only one mold- considered. Ideally, these materials should ing process is necessary and the device not require cure prior to wirebonding and provides for significantly lower packaging and die attach material into one prod- should be robust enough to withstand costs when compared to other 3-D pack- uct. The use of DDF materials delivers the repeated heat cycles of the die attach ages or individually packaged die. For the mechanical rigidity of the wafer – allow- and wirebond processing of multiple die true value of these advanced packages to ing it to be processed without cracking within the stack. be realized, however, thinner and thinner or curling. The film is laminated to the Certain DDF formulations provide wafers must be used and production effi- backside of the wafer, the wafer is diced, other benefits as well: they leave no burrs ciency is imperative. Complex handling the die is picked up, the pressure sensitive after dicing, deliver superior bondline issues and the multiple cure steps currently dicing tape released and the die is moved thickness control and eliminate common associated with traditional die stacking to die placement. Each die level can be bleed issues often associated with die processes and materials (die attach pastes) stacked without incorporating a curing attach pastes. And, while die attach pastes limit throughput and can introduce poten- step. Once all the levels of the die stack used to have a UPH (units per hour) advan- tial wafer or die cracking problems. have been placed, the package moves to tage over film, that’s no longer the case. For these reasons, I maintain that die wire bonding and then molding. Unlike Generally speaking, a good paste process attach film materials – namely Dicing die attach pastes that must be cured after would average die placement dwell times Die Attach film (DDF) and Flow Over each die level placement, DDF materials of approximately 0.3 seconds. Next-gen- Wire (FOW) film technology – will be cure during the standard molding process, eration DDF technology is challenging the way forward for successful integrated thus streamlining manufacturing and dra- that, delivering die placement dwell times package production. These newer gen- matically improving throughput. Another as low as 0.1 seconds. eration materials offer the production, key benefit of die attach film materials is So, I rest my case. Advanced inte- handling and cost efficiencies necessary the mechanical rigidity and handling sta- grated package technology will require to enable advanced packages to move bility they provide. Ultra thin wafers can the robustness and process advantages of into the mainstream realm. When com- crack and curl under even the slightest bit next-generation dicing die attach films. pared to die attach pastes – which still of stress, but film materials improve the And, as always, consumers will be the big have advantages for certain package types mechanical integrity required for handling winners. ◆ – die attach films offer a more streamlined and processing.

38 MEPTEC Report / Q4 2007 www.meptec.org DC08 MEPTEC ad2 12/3/07 9:43 AM Page 1

Connecting the World of Electronic Design

Conference Exhibition February 4–7, 2008 February 5–6, 2008 Santa Clara Convention Center | Santa Clara, California

DesignCon is the premier educational forum and technology exhibition for engineers and allied professionals from all levels and disciplines. If you desire to stay abreast of the most current information regarding design engineering theories, techniques, and practical strategies, this event is for you.

• 130 exhibiting companies • 10 half-day tutorials • Keynotes and plenary panel • Nearly 100 technical papers • 8 technical panels • Business Forum

CHAIRPERSON Terry Morris Fellow, High Performance Systems Division Hewlett-Packard

OFFICIAL HOST SPONSOR

International Engineering Consortium www.iec.org

Complimentary Exhibits PLUS Pass! Gain unlimited access to the DesignCon technology exhibition and other complimentary educational programming when registering at designcon.com/2008/register/vip_exhibits_reg.html Magazines and Carriers for Process Handling Solutions

Film Frames Film Frame Film Frame Shippers Grip Rings Magazines

Grip Ring Magazines Grip Ring Shippers Lead Frame Stack Magazines - E.O.L. Magazines - F.O.L./E.O.L.

Process Carriers Boat Magazines I. C. Trays - I. C. Tubes and Rails (Boats) Multi-Channel

Miscellaneous Substrate Carrier TO Tapes & Wafer Carriers Magazines Magazines Magazines

Accept Nothing Less.

Perfection Products Inc. 1320 S. Indianapolis Ave. • Lebanon, IN 46052 Phone: (765) 482-7786 • Fax: (765) 482-7792 Check out our Website: www.perfection-products.com Email: