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Memory Management Arkaprava Basu Indian Institute of Science (IISc), Bangalore, India Memory Management Arkaprava Basu Dept. of Computer Science and Automation Indian Institute of Science www.csa.iisc.ac.in/~arkapravab/ www.csa.iisc.ac.in Indian Institute of Science (IISc), Bangalore, India Memory is virtual ! ▪ Application software sees virtual address ‣ int * p = malloc(64); Virtual address ‣ Load, store instructions carries virtual addresses 2/19/2019 2 Indian Institute of Science (IISc), Bangalore, India Memory is virtual ! ▪ Application software sees virtual address ‣ int * p = malloc(64); Virtual address ‣ Load, store instructions carries virtual addresses ▪ Hardware uses (real) physical address ‣ e.g., to find data, lookup caches etc. ▪ When an application executes (a.k.a process) virtual addresses are translated to physical addresses, at runtime 2/19/2019 2 Indian Institute of Science (IISc), Bangalore, India Bird’s view of virtual memory Physical Memory (e.g., DRAM) 2/19/2019 Picture credit: Nima Honarmand, Stony Brook university 3 Indian Institute of Science (IISc), Bangalore, India Bird’s view of virtual memory Process 1 Physical Memory (e.g., DRAM) 2/19/2019 Picture credit: Nima Honarmand, Stony Brook university 3 Indian Institute of Science (IISc), Bangalore, India Bird’s view of virtual memory Process 1 // Program expects (*x) // to always be at // address 0x1000 int *x = 0x1000; Physical Memory (e.g., DRAM) 2/19/2019 Picture credit: Nima Honarmand, Stony Brook university 3 Indian Institute of Science (IISc), Bangalore, India Bird’s view of virtual memory Process 1 Process 2 // Program expects (*x) // to always be at // address 0x1000 int *x = 0x1000; Physical Memory (e.g., DRAM) 2/19/2019 Picture credit: Nima Honarmand, Stony Brook university 3 Indian Institute of Science (IISc), Bangalore, India Bird’s view of virtual memory Process 1 Process 2 // Program expects (*x) // to always be at Only one physical // address 0x1000 address 0x1000!! int *x = 0x1000; 0x1000 Physical Memory (e.g., DRAM) 2/19/2019 Picture credit: Nima Honarmand, Stony Brook university 3 Indian Institute of Science (IISc), Bangalore, India Bird’s view of virtual memory Process 1 Process 2 App’s view of memory App’s view of memory 0x1000 0x1000 0x1000 Physical Memory (e.g., DRAM) 2/19/2019 4 Indian Institute of Science (IISc), Bangalore, India Bird’s view of virtual memory Process 1 Process 2 App’s view of memory App’s view of memory 0x1000 0x1000 Virtual address Virtual 0x1000 Physical Memory (e.g., DRAM) 2/19/2019 4 Indian Institute of Science (IISc), Bangalore, India Bird’s view of virtual memory Process 1 Process 2 App’s view of memory App’s view of memory 0x1000 0x1000 Virtual address Virtual 0x1000 Physical Memory (e.g., DRAM) 2/19/2019 4 Indian Institute of Science (IISc), Bangalore, India Bird’s view of virtual memory Process 1 Process 2 App’s view of memory App’s view of memory 0x1000 0x1000 Virtual address Virtual Virtual memory is a layer of indirection between s/w’s view of memory and h/w’s view 0x1000 Physical Memory (e.g., DRAM) 2/19/2019 4 Indian Institute of Science (IISc), Bangalore, India Roles of software and hardware Process 1 1. Operating systemProcess creates 2 and manages Virtual to physical address mappings. App’s view of memory App’s view of memory 2. (Typically) Hardware performs the VA to 0x1000 PA translation at runtime.0x1000 Virtual address Virtual Virtual memory is a layer of indirection between s/w’s view of memory and h/w’s view 0x1000 Physical Memory (e.g., DRAM) 2/19/2019 5 Indian Institute of Science (IISc), Bangalore, India Virtual memory terminology Process 1 Process 2 Virtual address space Virtual address space 0x1000 0x1000 Virtual address Virtual 2/19/2019 6 Indian Institute of Science (IISc), Bangalore, India Virtual memory terminology Process 1 Process 2 Virtual address space Virtual address space 0x1000 0x1000 Virtual address Virtual 2/19/2019 Physical address space 6 Indian Institute of Science (IISc), Bangalore, India Virtual memory terminology Process 1 Process 2 Virtual address space Virtual address space 0x1000 0x1000 Virtual address Virtual Memory Management Unit (MMU) 2/19/2019 Physical address space 6 Indian Institute of Science (IISc), Bangalore, India Why virtual memory? 2/19/2019 7 Indian Institute of Science (IISc), Bangalore, India Why virtual memory? ▪ Relocation: Ease of programming by providing application contiguous view of memory ‣ But actual physical memory can be scattered 2/19/2019 7 Indian Institute of Science (IISc), Bangalore, India Why virtual memory? ▪ Relocation: Ease of programming by providing application contiguous view of memory ‣ But actual physical memory can be scattered ▪ Resource management: Application writer can assume there is enough memory ‣ But, system can manage physical memory across concurrent processes ▪ Isolation: Bug in one process should not corrupt memory of another under multi-programming ‣ Provide each process with separate virtual address space ▪ Protection: Enforce rules on what memory a process can or cannot access 2/19/2019 7 Indian Institute of Science (IISc), Bangalore, India Why virtual memory? ▪ Sharing/communication: Inter-process communication and sharing 2/19/2019 8 Indian Institute of Science (IISc), Bangalore, India Why virtual memory? ▪ Sharing/communication: Inter-process communication and sharing ‣ Same physical address can be mapped onto two process’s virtual address space with different virtual address • Could be used for inter-process-communication 2/19/2019 8 Indian Institute of Science (IISc), Bangalore, India Why virtual memory? ▪ Sharing/communication: Inter-process communication and sharing ‣ Same physical address can be mapped onto two process’s virtual address space with different virtual address • Could be used for inter-process-communication • Very useful for code/library sharing 2/19/2019 8 Indian Institute of Science (IISc), Bangalore, India Aside: How hardware knows which software is OS? ▪ x86 (Intel/AMD) protection rings: ‣ ring 0 to ring 3 ▪ User application runs in ring 3 (least privileged/user mode) ▪ OS runs in ring 0 (supervisor/privileged) 2/19/2019 9 Indian Institute of Science (IISc), Bangalore, India Aside: How hardware knows which software is OS? ▪ x86 (Intel/AMD) protection rings: ‣ ring 0 to ring 3 ▪ User application runs in ring 3 (least privileged/user mode) ▪ OS runs in ring 0 (supervisor/privileged) ▪ What about other rings? ‣ Typically not used ‣ SMM uses ring 2 for running firmware 2/19/2019 9 Indian Institute of Science (IISc), Bangalore, India Aside: What privileges the OS gets by running in ring 0? ▪ A subset of instructions only executable in ring 0 ‣ Typically ones that changes system state, e.g., invlpg ▪ System state accessible/modifiable only in ring 0 ‣ e.g., interrupt flag IF 2/19/2019 10 Indian Institute of Science (IISc), Bangalore, India Aside: What privileges the OS gets by running in ring 0? ▪ A subset of instructions only executable in ring 0 ‣ Typically ones that changes system state, e.g., invlpg ▪ System state accessible/modifiable only in ring 0 ‣ e.g., interrupt flag IF ▪ Parts of physical memory that is accessible only in ring0 (virtual memory help enforce this) ▪ Physical addresses are visible to software only in ring 0(ring 3 can never see physical address) 2/19/2019 10 Indian Institute of Science (IISc), Bangalore, India Plan for the lectures What is virtual memory? Hardware implementations of virtual memory Software management of memory (Linux) Advanced topics in memory management 2/19/2019 11 Indian Institute of Science (IISc), Bangalore, India Plan for the lectures What is virtual memory? Hardware implementations of virtual memory Software management of memory (Linux) Advanced topics in memory management 2/19/2019 11 Indian Institute of Science (IISc), Bangalore, India Implementing virtual memory ▪ Many ways to implement virtual memory ‣ Base and bound register Useful/versatile ‣ Segmentation ‣ Paging Complexity Complexity 2/19/2019 12 Indian Institute of Science (IISc), Bangalore, India Base and bound registers Process 1 Process 2 Virtual address space Virtual address space 2/19/2019 13 Indian Institute of Science (IISc), Bangalore, India Base and bound registers Process 1 Process 2 Virtual address space Virtual address space 2/19/2019 13 Indian Institute of Science (IISc), Bangalore, India Base and bound registers Process 1 Process 2 Virtual address space Virtual address space Base Bound 2/19/2019 13 Indian Institute of Science (IISc), Bangalore, India Base and bound registers Process 1 Process 2 Virtual address space Virtual address space Base Bound Base Bound 2/19/2019 13 Indian Institute of Science (IISc), Bangalore, India Base and bound registers ▪ How it works? ‣ Each CPU core has base and bound registers ‣ Each process has own values for base and bound ‣ Base and bound values are assigned by OS ‣ On a context switch, a process’s base and bound registers are saved/restored by the OS 2/19/2019 14 Indian Institute of Science (IISc), Bangalore, India Base and bound registers ▪ How it works? ‣ Each CPU core has base and bound registers ‣ Each process has own values for base and bound ‣ Base and bound values are assigned by OS ‣ On a context switch, a process’s base and bound registers are saved/restored by the OS ▪ Example: Cray-1 (very old system) ▪ Advantage ‣ Simple 2/19/2019 14 Indian Institute of Science (IISc), Bangalore, India Base and bound registers ▪ How it works? ‣ Each CPU core has base and bound registers ‣ Each process has own values for base and bound ‣ Base and bound values are
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