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TUSB9261 USB 3.0 to SATA Bridge Datasheet (Rev. I)

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TUSB9261 USB 3.0 to SATA Bridge Datasheet (Rev. I) Product Sample & Technical Tools & Support & Reference Folder Buy Documents Software Community Design TUSB9261 SLLSE67I –MARCH 2011–REVISED MARCH 2016 TUSB9261 USB 3.0 to SATA Bridge 1 Features 2 Applications 1• Universal Serial Bus (USB) • External HDD/SSD – SuperSpeed USB 3.0 Compliant – TID • External DVD 340730020 • External CD – Integrated Transceiver Supports SS/HS/FS • HDD-Based Portable Media Player Signaling – Best-in-Class Adaptive Equalizer 3 Description ® ® – Allows for Greater Jitter Tolerance in the The TUSB9261 is an ARM Cortex M3 Receiver microcontroller based USB 3.0 to serial ATA bridge. It provides the necessary hardware and firmware to – USB Class Support implement a USB attached SCSI protocol (UASP)- – USB Attached SCSI Protocol (UASP) compliant mass storage device suitable for bridging – USB Mass Storage Class Bulk-Only hard disk drives (HDD), solid state disk drives (SSD), Transport (BOT) optical drives, and other compatible SATA 1.5-Gbps or SATA 3.0-Gbps devices to a USB 3.0 bus. In – Support for Error Conditions Per the 13 addition to UASP support, the firmware implements Cases (Defined in the BOT Specification) the mass storage class BOT and USB HID interfaces. – USB Bootability Support (1) – USB Human Interface Device (HID) Device Information – Supports Firmware Update Via USB, Using a PART NUMBER PACKAGE BODY SIZE (NOM) TI Provided Application TUSB9261 HTQFP (64) 7.00 × 7.00 mm • SATA Interface (1) For all available packages, see the orderable addendum at the end of the data sheet. – Serial ATA Specification Revision 2.6 – Gen1i, Gen1m, Gen2i, and Gen2m Simplified Schematic – Support for Mass-Storage Devices Compatible ROM GRSTz Power With the ATA/ATAPI-8 Specification ARM TCK and TMS Cortex M3 VDD3.3 JTAG TDO RAM Reset TDI TRST • Integrated ARM Cortex M3 Core 64 kB VDD1.1 Distribution – Customizable Application Code Loaded from Data Path EEPROM by SPI Interface USB 3.0 RAM XI Device Clock 80 kB – Two Additional SPI Port Chip Selects for Generation X0 Controller Peripheral Connection SATA – Up to 12 GPIOs for End-User Configuration AHCI Watchdog Timer – Two GPIOs have PWM Functionality for Timer LED Blink Speed Control SATA II USB SS USB HS/FS SCI GPIO PHY PHY PHY SPI – Serial Communications Interface for Debug (UART) PWM ] T - + ] U X :0] X VBUS K O :0 R R L _ [11:0 A [2 rtTX A C A T artRX (UART) S T T S SSTX- A SSRX- WM[1 Ua SSTX+ A DP/DM U SSRX+ C A USB_R1 DATA_IN SATATX- S P SATATX+ S GPIO D • General Features USB_R1RTN – Integrated Spread Spectrum Clock Generation Enables Operation from a Single Low-Cost Crystal or Clock Oscillator – Supports 40 MHz – A JTAG Interface is Used for IEEE1149.1 and IEEE1149.6 Boundary Scan – Available in a Fully RoHS-Compliant Package 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TUSB9261 SLLSE67I –MARCH 2011–REVISED MARCH 2016 www.ti.com Table of Contents 1 Features .................................................................. 1 7.3 Feature Description................................................. 10 2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 13 3 Description ............................................................. 1 8 Application and Implementation ........................ 15 4 Revision History..................................................... 2 8.1 Application Information............................................ 15 5 Pin Configuration and Functions ......................... 3 8.2 Typical Application .................................................. 15 6 Specifications......................................................... 7 9 Power Supply Recommendations...................... 19 6.1 Absolute Maximum Ratings ...................................... 7 9.1 Digital Supplies 1.1-V and 3.3-V............................. 19 6.2 ESD Ratings.............................................................. 7 9.2 Analog Supplies 1.1-V and 3.3-V ........................... 19 6.3 Recommended Operating Conditions....................... 7 10 Layout................................................................... 19 6.4 Thermal Information.................................................. 7 10.1 Layout Guidelines ................................................. 19 6.5 DC Electrical Characteristics for 3.3-V Digital I/O..... 8 10.2 Layout Examples................................................... 20 6.6 SuperSpeed USB Power Consumption .................... 8 11 Device and Documentation Support ................. 22 6.7 High-Speed USB Power Consumption ..................... 8 11.1 Community Resources.......................................... 22 6.8 Oscillator Specification.............................................. 9 11.2 Trademarks ........................................................... 22 6.9 Crystal Specification.................................................. 9 11.3 Electrostatic Discharge Caution............................ 22 7 Detailed Description ............................................ 10 11.4 Glossary ................................................................ 22 7.1 Overview ................................................................. 10 12 Mechanical, Packaging, and Orderable 7.2 Functional Block Diagram ....................................... 10 Information ........................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (July 2015) to Revision I Page • Changed the CDM value in the ESD Ratings table From: 5000 To: ±1500 .......................................................................... 7 Changes from Revision G (October 2014) to Revision H Page • Moved Tstg from Handling Ratings table to Absolute Maximum Ratings and renamed Handling Ratings to ESD Ratings ... 7 • Updated the frequency for the USB2 and USB3 to 5 Hz and 10 Hz, respectively ............................................................. 16 Changes from Revision F (March 2014) to Revision G Page • Updated supported frequency to 40 MHz .............................................................................................................................. 1 • Updated supported frequency in Clock and Reset Signals table .......................................................................................... 4 • Updated the frequency for the clock to 40 MHz .................................................................................................................... 9 • Updated the frequency for the crystal to 40 MHz .................................................................................................................. 9 • Updated oscillation frequency and ESR equivalent series resistance .................................................................................. 9 • Updated Table 1 ................................................................................................................................................................... 12 2 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: TUSB9261 TUSB9261 www.ti.com SLLSE67I –MARCH 2011–REVISED MARCH 2016 5 Pin Configuration and Functions PVP Package 48-Pin HTQFP Top View US._SSwXa US._SSTXa US._w1wTb US._SSwXt US._SSTXt US._5a V55A33 V55A33 V55A33 US._5t US._w1 V55 V55 V55 VSS bC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 V55 49 32 V55 US._V.US 50 31 CwEvSEL1 V5533 51 30 CwEvSEL0 XI 52 29 WTAD_TwSTz VSShSC 53 28 WTAD_TaS Xh 54 27 WTAD_T5h V55 55 26 WTAD_T5I SATA_TXa 56 65 25 WTAD_TCY SATA_TXt 57 VSS 24 V5533 VSS 58 23 StI_CS2 / DtLh11 SATA_wXa 59 22 StI_CS1 / DtLh10 SATA_wXt 60 21 StI_CS0 V55 61 20 StI_5ATA_IN V55A33 62 19 V55 V55 63 18 StI_5ATA_hUT bC 64 17 StI_SCLY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 tWa0 tWa1 DwSTz DtIh8 / UAwT_wX / DtIh9 UAwT_TX DtIh0 DtIh1 DtIh2 DtIh3 DtIh4 DtIh5 DtIh6 DtIh7 V55 V5533 V55 Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TUSB9261 TUSB9261 SLLSE67I –MARCH 2011–REVISED MARCH 2016 www.ti.com Signal Descriptions – I/O Definitions I/O TYPE DESCRIPTION I Input O Output I/O Input/output PU Internal pullup resistor PD Internal pulldown resistor PWR Power signal Clock and Reset Signals PIN I/O DESCRIPTION NAME NO. I Global power reset. This reset brings all of the TUSB9261 internal registers to their default GRSTz 4 PU states. When GRSTz is asserted, the device is completely nonfunctional. Crystal input. This terminal is the crystal input for the internal oscillator. The input may alternately XI 52 I be driven by the output of an external oscillator. When using a crystal, a 1-MΩ feedback resistor is required between X1 and XO. Crystal output. This terminal is the crystal output for the internal oscillator. If XI is driven by an XO 54 O external oscillator, this pin may be left unconnected. When using a crystal, a 1-MΩ feedback resistor is required between X1 and XO. Frequency select. These terminals indicate the oscillator input frequency and are used to configure the correct PLL multiplier. The field encoding is as follows: I FREQSEL[1:0] 31, 30 PU FREQSEL[1] FREQSEL[0] INPUT CLOCK FREQUENCY 1 1 40 MHz SATA Interface Signals(1) PIN I/O DESCRIPTION NAME NO. SATA_TXP 57 O Serial ATA transmitter differential pair
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