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Dreamcast/Dev.Box System Architecture Last Update : 99/09/03

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Dreamcast/Dev.Box System Architecture Last Update : 99/09/03 Dreamcast/ Dev.Box System Architecture Last Update: 99/09/02 18:41 (Preliminary) Dreamcast/Dev.Box System Architecture Last Update : 99/09/03 REVISION HISTORY [1999] 9/2 ・ Modified terms: KATANA -> Dreamcast, SET5 -> Dev.Box (Revisions in green: Up to next release) ・ Distinction between HOLLY1 and HOLLY2 were unnecessary, and so combined as just HOLLY. (Revisions in green: Up to next release) 8/23 ・ Corrected description of FNS and OCT settings in section 8.1.1.4. ・ Corrected description of FNS[9:0] in the register descriptions (channel data) in section 8.4.5. 3/10 ・ Added descriptions of register modification procedures in section 2.7.2. 2/4 ・ Corrected register addresses in section 8.4.1.1: 6930 -> 6920, 6950 -> 6930, etc. (Revisions in green: Up to next release) 1/27 [1998] 11/25 ・ Corrected descriptions of revisions added to section 1.4 and 9. ・ Corrected description of parameters in the common data for the AICA register in section 8.4.5. 11/20 ・ Made additions to and corrected descriptions related to revisions in sections 1.4 and 9. ・ Added description for the STARTRENDER register (0x005F8014) in section 8.4.2. ・ Corrected a portion of the description of G2-related registers in section 8.4.1.4. ・ Made additions to and corrected supplementary descriptions for the mapping table in section 2.1. 11/10 ・ Corrected description and headings concerning section 4.2, "G2 Interface." (Revisions in green: Up to next release) ・ Corrected description of G2-related registers in section 8.4.1.4. (Revisions in green: Up to next release) 11/4 ・ Corrected description of Maple-related registers in section 8.4.1.2. (Revisions in green: Up to next release) 10/30 ・ Corrected description concerning PVR-DMA registers in section 8.4.1.5. (Revisions in green: Up to next release) ・ Corrected description in section 5, "User Interface" -- Described hard triggers again. (Revisions in green: Up to next release) 10/15 10/13 ・ Corrected description in section 3.6.2.3, "VQ Textures," and Figs. 3-1 and 3-2. 9/30 ・ Corrected description in Section 1.4, "Dev.Box Board." ・ Changed description in section 9, "Bug List." ・ Added description to section 8.4.2 for the STARTRENDER Register (0x005F8014). 9/25 9/16 ・ Corrected description in section 1.1.5, "Expansion Devices." 8/31 ・ Corrected description in section 3.7.4.4.3, "Obj Control." bit 16-8 -> bit 8/28 ・ Added description in section 4.2.3, "RTC." ・ Corrected description in section 8.4.5, "AICA Registers," concerning channel data:PCMS, and cutoff frequency (FLV) and common data: DLG. ・ Corrected description of external memory specifications in section 4.2.2.4, "Wave Memory (AICA)." ・ Corrected portion of description in section 8.1.1, "Audio-related..." ・ Corrected description in section 3.4.5.3, "Modifier Volume Processing of Various Polygons." ・ Corrected table in section 3.5.1, "Sync Pulse Generator." 8/21 ・ Added and corrected a portion of text and figure in section 3.6.2.4, "MIPMAP Texture." ・ Added to and corrected ISP_FEED_CFG Register in section 8.4.2(0x005F8098). ・ Changed a portion of 3.4.3.1, "ISP Cache Size." ・ Changed a portion of 3.4.5.2, "Volume Mode." ・ Changed a portion of 3.4.11.2, "Y Scaler." ・ Changed Type A diagram in section 3.4.12, "Flicker-free Interlacing" - 2 - Dreamcast/Dev.Box System Architecture Last Update : 99/09/03 8/18 ・ Changed "ARC" to "SRC" in section 3.4.7.2.3, "Trilinear Filtering." 8/7 8/4 ・ Corrected a portion of ISP_FEED_CFG Register in section 8.4.2(0x005F8098). ・ Corrected a portion of display lists in sections 3.7.8 and 3.7.9.2. ・ Corrected a portion of section 3.4.3, Punch Through Polygons." 7/31 7/28 ・ Changed a portion of section 3.3, "Register Map (Graphics System)." 7/27 ・ Corrected a portion of Figs. 3-77 and 3-78 in section 3.7, "Display List Details." ・ Corrected a portion of FPU_PARAM_CFG Register (0x005F807C) in section 8.4.2. 7/14 ・ Corrected a portion of section 3.1.1.1. ・ Corrected a portion of the HOLY version table in section 1.4, "Dev.Box." 7/9 ・ Corrected all pages. ・ Changed "Opaqu" to "Opaque" in section 3.1.1.9, "Polygon List." 7/7 ・ Made "Expansion Devices" the term used consistently for external expansion devices that are connected to the G2 Bus. ・ Added description to section 3.4.3, "Punch Through Polygons." ・ Corrected references in section 3.7.7, "Region Array Data Configuration." ・ Corrected explanation in section 4.2.5, "Expansion Devices." ・ Corrected SDRAM_CFG Register (0x005F80A8) in section 8.4.2. 7/1 ・ Deleted the hidden character portion of section 4.1.4, "System Codes." ・ Changed the underlining of the additional HOLLY2 specifications in section 3, "Graphics System," from a broken line to a wavy line. ・ Returned the setting for the portion of section 5.1.6 that was composed of hidden characters back to normal characters. 6/30 ・ Submitted to Software Technology Development Group. 6/10 ・ Submitted to Software Technology Development Group. 5/26 ・ Submitted to Software Technology Development Group. 5/1 ・ Submitted to Software Technology Development Group. 4/21 ・ Submitted to Software Technology Development Group. 3/27 ・ Submitted to Software Technology Development Group. 2/24 ・ Submitted to Software Technology Development Group. 2/4 ・ Submitted to Software Technology Development Group. 1/30 ・ Submitted to Software Technology Development Group. 1/23 ・ Submitted to Software Technology Development Group. 12/16 ・ Submitted to Software Technology Development Group. 11/25 ・ Submitted to Software Technology Development Group. - 3 - Dreamcast/Dev.Box System Architecture Last Update : 99/09/03 Table of Contents Dreamcast/Dev.Box System Architecture..........................................................................................................................1 REVISION HISTORY......................................................................................................................................................2 §1 THE SYSTEM.............................................................................................................................................................9 §1.1 Overview..........................................................................................................................................10 §1.2 System Architecture.........................................................................................................................10 §1.3 Block Diagram.................................................................................................................................12 §1.4 Dev.Box Board.................................................................................................................................15 §2 CPU AND PERIPHERAL MEMORY......................................................................................................................16 §2.1 System Mapping..............................................................................................................................17 §2.1.1 Cache Access...........................................................................................................................19 §2.2 SH4..................................................................................................................................................20 §2.2.1 Overview of the SH4.................................................................................................................20 §2.2.2 CPU Bus Interface....................................................................................................................21 §2.2.3 Initial Settings for the SH4.........................................................................................................22 §2.3 System Memory...............................................................................................................................34 §2.3.1 System Memory Configuration and Control...............................................................................34 §2.3.2 System Memory Initial Settings.................................................................................................34 §2.3.3 Access Procedure.....................................................................................................................36 §2.4 Register Map...................................................................................................................................37 §2.5 Single Access to Each Block............................................................................................................41 §2.6 DMA Transfers.................................................................................................................................42 §2.6.1 Overview of DMA Transfers.......................................................................................................42 §2.6.2 Types of DMA............................................................................................................................43 §2.6.3 GD-ROM Data Transfers...........................................................................................................44 §2.6.4 Texture Data Transfers..............................................................................................................47 §2.6.4.1 Direct Texture Transfers.....................................................................................................................47 §2.6.4.2 YUV Texture Transfer.........................................................................................................................55 §2.6.5
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