Review der Kernel Sourcen von 4.9 auf 4.10

Reviewed by: Tested by: stecan stecan

Period of Review: Period of Test: From: Thursday, 11 January 2018 07:26:18 o'clock +01: From: Thursday, 11 January 2018 07:26:18 o'clock +01:

To: Thursday, 11 January 2018 07:44:27 o'clock +01: To: Thursday, 11 January 2018 07:44:27 o'clock +01:

Report automatically generated with: LxrDifferenceTable, V0.9.2.548

Provided by: Certified by: Approved by: Account: stecan Name / Department:

Date: Friday, 4 May 2018 13:43:07 o'clock CEST

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Review_4.10_0_to_1000.pdf 1 of 793 May 04, 2018

Review der Sourcen von 4.9 auf 4.10

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1 .mailmap#0140 Repo: 9ebf73b275f0 Stephen Tue Jan 10 16:57:57 2017 -0800 Description: mailmap: add codeaurora.org names for nameless email commits ------Some codeaurora.org emails have crept in but the names don't exist for them. Add the names for the emails so git can match everyone up.

Link: http://lkml.kernel.org/r/[email protected]

2 .mailmap#0154 3 .mailmap#0160 4 CREDITS#2481 Repo: 0c59d28121b9 Arnaldo Mon Feb 13 14:15:44 2017 -0300 Description: MAINTAINERS: Remove old e-mail address ------The ghostprotocols.net domain is not working, remove it from CREDITS and MAINTAINERS, and change the status to "Odd fixes", and since I haven't been maintaining those, remove my address from there.

CREDITS: Remove outdated address information ------This address hasn't been accurate for several years now.

Simply remove it.

Merge branch 'x86-microcode-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip ------Pull x86 microcode update from Ingo Molnar: "The biggest change (by Borislav Petkov) is a thorough rewrite of the Intel microcode loader and its interactions with the core code.

The biggest conceptual change is the decoupling of the microcode loading on boot and application processors (which load the microcode in different scenarios), so that both parse the input patches with as few assumptions as possible - this also fixes various kernel address space randomization bugs. (The AP side then goes on and caches the result to improve boot performance.)

Since the AMD side already did this, this change also opened up the path towards more unification/simplification of the core microcode loading infrastructure:

10 files changed, 647 insertions(+), 940 deletions(-)

Review_4.10_0_to_1000.pdf Page 2 of 793 May 04, 2018

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which speaks for itself"

* 'x86-microcode-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/microcode: Bump driver version, update copyrights x86/microcode: Rework microcode loading x86/microcode/intel: Remove intel_lib. x86/microcode/amd: Move private inlines to .c and mark local functions static x86/microcode: Collect CPU info on resume x86/microcode: Issue the debug printk on resume only on success x86/microcode/amd: Hand down the CPU family x86/microcode: Export the microcode linked list x86/microcode: Remove one #ifdef clause x86/microcode/intel: Simplify generic_load_microcode() x86/microcode: Move driver authors to CREDITS x86/microcode: Run the AP-loading routine only on the application processors

5 CREDITS#2484 6 CREDITS#2486 7 CREDITS#2778 8 CREDITS#3951 9 MAINTAINERS#0038 Repo: 0c59d28121b9 Arnaldo Mon Feb 13 14:15:44 2017 -0300 Description: MAINTAINERS: Remove old e-mail address ------The ghostprotocols.net domain is not working, remove it from CREDITS and MAINTAINERS, and change the status to "Odd fixes", and since I haven't been maintaining those, remove my address from there.

Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM SoC fixes from Arnd Bergmann:

- A relatively large patch restores on i.MX platforms that failed to boot after a cleanup was merged for v4.10.

- A quirk for USB needs to be enabled on the STi platform

- On the Meson platform, we saw memory corruption with part of the memory used by the secure monitor, so we have to stay out of that area.

- The same platform also has a problem with ethernet under load, which is fixed by disabling EEE negotiation.

Review_4.10_0_to_1000.pdf Page 3 of 793 May 04, 2018

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- imx6dl has an incorrect pin configuration, which prevents SPI from working.

- Two maintainers have lost their access to their email addresses, so we should update the MAINTAINERS file before the release

- Renaming one of the orion5x linkstation models to help simplify the debian install.

- A couple of fixes for build warnings that were introduced during v4.10-rc.

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: defconfigs: make NF_CT_PROTO_SCTP and NF_CT_PROTO_UDPLITE built-in MAINTAINERS: socfpga: update email for Dinh Nguyen ARM: orion5x: fix Makefile for linkstation-lschl.dtb ARM: dts: orion5x-lschl: More consistent naming on linkstation series ARM: dts: orion5x-lschl: Fix model name MAINTAINERS: change email address from atmel to microchip MAINTAINERS: at91: change email address ARM64: dts: meson-gx: Add firmware reserved memory zones ARM64: dts: meson-gxbb-odroidc2: fix GbE tx link breakage ARM: dts: STiH407-family: set snps,dis_u3_susphy_quirk ARM: dts: imx: Pass 'chosen' and 'memory' nodes ARM: dts: imx6dl: fix GPIO4 range ARM: imx: hide unused variable in #ifdef

MAINTAINERS: socfpga: update email for Dinh Nguyen ------My opensource.altera.com email will be going away soon.

Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost ------Pull virtio/vhost fixes from Michael S. Tsirkin: "Last minute fixes:

- ARM DMA fix revert

- vhost endian-ness fix

- MAINTAINERS: email address change for Amit"

* tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost: MAINTAINERS: update email address for Amit Shah vhost: fix initialization for vq->is_le Revert "vring: Force use of DMA API for ARM-based systems with legacy devices"

Review_4.10_0_to_1000.pdf Page 4 of 793 May 04, 2018

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MAINTAINERS: update email address for Amit Shah ------I'm leaving my job at , this email address will stop working next week. Update it to one that I will have access to later.

Merge tag 'at91-ab-4.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux into fixes ------AT91 SoC fixes for 4.10:

- change email addresses for Nicolas and Ludovic following the Microchip-Atmel merger

* tag 'at91-ab-4.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: MAINTAINERS: change email address from atmel to microchip MAINTAINERS: at91: change email address

MAINTAINERS: change email address from atmel to microchip ------Use microchip email address instead of old atmel one.

MAINTAINERS: at91: change email address ------Following the Microchip / Atmel merger and the unification of internal IT, it's more convenient for me to swith to the microchip.com address. Change all my entries to reflect this.

Merge tag 'wireless-drivers-for-davem-2017-01-29' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers ------Kalle Valo says:

======wireless-drivers fixes for 4.10

Most important here are fixes to two iwlwifi crashes, but there's also a firmware naming fix for iwlwifi and a revert of an older bcma patch. ======

MAINTAINERS: ath9k-devel is closed ------ath9k-devel list is now closed, only linux-wireless should be used.

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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net ------Pull networking fixes from David Miller:

1) GTP fixes from Andreas Schultz (missing genl module alias, clear IP DF on transmit).

2) needs to reflect the fwmark when sending resets, from Pau Espin Pedrol.

3) nftable dump OOPS fix from Liping Zhang.

4) Fix erroneous setting of VIRTIO_NET_HDR_F_DATA_VALID on transmit, from Rolf Neugebauer.

5) Fix build error of ipt_CLUSTERIP when is disabled, from Arnd Bergmann.

6) Fix regression in handling of NETIF_F_SG in harmonize_features(), from Eric Dumazet.

7) Fix RTNL deadlock wrt. lwtunnel module loading, from David Ahern.

8) tcp_fastopen_create_child() needs to setup tp->max_window, from Alexey Kodanev.

9) Missing kmemdup() failure check in ipv6 segment routing code, from Eric Dumazet.

10) Don't execute unix_bind() under the bindlock, otherwise we deadlock with splice. From WANG Cong.

11) ip6_tnl_parse_tlv_enc_lim() potentially reallocates the skb buffer, therefore callers must reload cached header pointers into that skb. Fix from Eric Dumazet.

12) Fix various bugs in legacy IRQ fallback handling in alx driver, from Tobias Regnery.

13) Do not allow lwtunnel drivers to be unloaded while they are referenced by active instances, from Robert Shearman.

14) Fix truncated PHY LED trigger names, from Geert Uytterhoeven.

15) Fix a few regressions from virtio_net XDP support, from John Fastabend and Jakub Kicinski.

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (102 commits) ISDN: eicon: silence misleading array-bounds warning net: phy: micrel: add support for KSZ8795

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gtp: fix cross netns recv on gtp socket gtp: clear DF bit on GTP packet tx gtp: add genl family modules alias tcp: don't annotate mark on control socket from tcp_v6_send_response() ravb: unmap descriptors when freeing rings virtio_net: reject XDP programs using header adjustment virtio_net: use dev_kfree_skb for small buffer XDP receive r8152: check rx after napi is enabled r8152: re-schedule napi for tx r8152: avoid start_xmit to schedule napi when napi is disabled r8152: avoid start_xmit to call napi_schedule during autosuspend net: dsa: Bring back device detaching in dsa_slave_suspend() net: phy: leds: Fix truncated LED trigger names net: phy: leds: Break dependency of phy.h on phy_led_triggers.h net: phy: leds: Clear phy_num_led_triggers on failure to avoid crash net-next: ethernet: mediatek: change the compatible string Documentation: devicetree: change the mediatek ethernet compatible string bnxt_en: Fix RTNL lock usage on bnxt_get_port_module_status(). ...

Merge tag 'drm-intel-fixes-2017-01-26' of git://anongit.freedesktop.org/git/drm-intel into drm-fixes ------More fixes than I'd like at this stage, but I think the holidays and conferences have delayed finding and fixing the stuff a bit. Almost all of them have Fixes: tags, so it's not just random fixes, we can point fingers at the commits that broke stuff.

There's an ABI fix to GVT from Alex, before we go on an release a kernel with the wrong attribute name.

* tag 'drm-intel-fixes-2017-01-26' of git://anongit.freedesktop.org/git/drm-intel: drm/i915: reinstate call to trace_i915_vma_bind drm/i915: Move atomic state free from out of fence release drm/i915: Check for NULL atomic state in intel_crtc_disable_noatomic() drm/i915: Fix calculation of rotated x and y offsets for planar formats drm/i915: Don't init hpd polling for vlv and chv from runtime_suspend() drm/i915: Don't leak edid in intel_crt_detect_ddc() drm/i915: Release temporary load-detect state upon switching drm/i915: prevent crash with .disable_display parameter drm/i915: Avoid drm_atomic_state_put(NULL) in intel_display_resume MAINTAINERS: update new mail list for intel gvt driver drm/i915/gvt: Fix kmem_cache_create() name drm/i915/gvt/kvmgt: mdev ABI is available_instances, not available_instance drm/i915/gvt: Fix relocation of shadow bb drm/i915/gvt: Enable the shadow batch buffer

MAINTAINERS: update new mail list for intel gvt driver

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------We've moved to lists.freedesktop.org from lists.01.org. Update info in MAINTAINERS.

Merge branch 'akpm' (patches from Andrew) ------Merge fixes from Andrew Morton: "26 fixes"

* emailed patches from Andrew Morton : (26 commits) MAINTAINERS: add Dan Streetman to zbud maintainers MAINTAINERS: add Dan Streetman to maintainers mm: do not export ioremap_page_range symbol for external module mn10300: fix build error of missing fpu_save() romfs: use different way to generate fsid for BLOCK or MTD frv: add missing atomic64 operations mm, page_alloc: fix premature OOM when racing with cpuset mems update mm, page_alloc: move cpuset seqcount checking to slowpath mm, page_alloc: fix fast-path race with cpuset update or removal mm, page_alloc: fix check for NULL preferred_zone kernel/panic.c: add missing \n fbdev: color map copying bounds checking frv: add atomic64_add_unless() mm/mempolicy.c: do not put mempolicy before using its nodemask radix-tree: fix private list warnings Documentation/filesystems/proc.txt: add VmPin mm, memcg: do not retry precharge charges proc: add a schedule point in proc_pid_readdir() mm: alloc_contig: re-allow CMA to compact FS pages mm/.c: trace free objects at KERN_INFO ...

MAINTAINERS: add Dan Streetman to zbud maintainers ------Add myself as zbud maintainer.

Link: http://lkml.kernel.org/r/[email protected]

MAINTAINERS: add Dan Streetman to zswap maintainers ------Add myself as zswap maintainer.

Link: http://lkml.kernel.org/r/[email protected]

Merge tag 'platform-drivers-x86-v4.10-4' of git://git.infradead.org/linux-platform-drivers- x86 ------Pull x86 platform-driver fixes from Andy Shevchenko:

Review_4.10_0_to_1000.pdf Page 8 of 793 May 04, 2018

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"This is my first pull request since I become a co-maintainer of Platform Drivers x86 subsystem. It's a bit bigger than usual due to material collected for almost two weeks in a row.

MAINTAINERS: - Add myself to X86 PLATFORM DRIVERS as a co-maintainer

ideapad-laptop: - handle ACPI event 1

intel_mid_powerbtn: - Set IRQ_ONESHOT

surface3-wmi: - fix uninitialized symbol - Shut up unused-function warning

mlx-platform: - free first dev on error"

* tag 'platform-drivers-x86-v4.10-4' of git://git.infradead.org/linux-platform-drivers-x86: MAINTAINERS: Add myself to X86 PLATFORM DRIVERS as a co-maintainer platform/x86: ideapad-laptop: handle ACPI event 1 platform/x86: intel_mid_powerbtn: Set IRQ_ONESHOT platform/x86: surface3-wmi: fix uninitialized symbol platform/x86: surface3-wmi: Shut up unused-function warning platform/x86: mlx-platform: free first dev on error

MAINTAINERS: Add myself to X86 PLATFORM DRIVERS as a co-maintainer ------For last few months Darren and I are co-maintaining PDx86 subsystem. Make this fact official by updating MAINTAINERS database.

Merge tag 'drm-fixes-for-v4.10-rc6' of git://people.freedesktop.org/~airlied/linux ------Pull drm fixes from Dave Airlie: "drm fixes across the board.

Okay holidays and LCA kinda caught up with me, I thought I'd get some of this dequeued last week, but Hobart was sunny and warm and not all gloomy and rainy as usual.

This is a bit large, but not too much considering it's two weeks stuff from AMD and Intel.

core: - one locking fix that helps with dynamic suspend/resume races

Review_4.10_0_to_1000.pdf Page 9 of 793 May 04, 2018

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i915: - mostly GVT updates, GVT was a recent introduction so fixes for it shouldn't cause any notable side effects.

amdgpu: - a bunch of fixes for GPUs with a different memory controller design that need different firmware.

exynos: - decon regression fixes

msm: - two regression fixes

etnaviv: - a workaround for an mmu bug that needs a lot more work.

virtio: - sparse fix, and a maintainers update"

* tag 'drm-fixes-for-v4.10-rc6' of git://people.freedesktop.org/~airlied/linux: (56 commits) drm/exynos/decon5433: set STANDALONE_UPDATE_F on output enablement drm/exynos/decon5433: fix CMU programming drm/exynos/decon5433: do not disable video after reset drm/i915: Ignore bogus plane coordinates on SKL when the plane is not visible drm/i915: Remove WaDisableLSQCROPERFforOCL KBL workaround. drm/amdgpu: add support for new hainan variants drm/radeon: add support for new hainan variants drm/amdgpu: change clock gating mode for uvd_v4. drm/amdgpu: fix program vce instance logic error. drm/amdgpu: fix bug set incorrect value to vce register Revert "drm/amdgpu: Only update the CUR_SIZE register when necessary" drm/msm: fix potential null ptr issue in non-iommu case drm/msm/mdp5: rip out plane->pending tracking drm/exynos/decon5433: set STANDALONE_UPDATE_F also if planes are disabled drm/exynos/decon5433: update shadow registers iff there are active windows drm/i915/gvt: rewrite gt reset handler using new function intel_gvt_reset_vgpu_locked drm/i915/gvt: fix vGPU instance reuse issues by vGPU reset function drm/i915/gvt: introduce intel_vgpu_reset_mmio() to reset mmio space drm/i915/gvt: move mmio init/clean function to mmio.c drm/i915/gvt: introduce intel_vgpu_reset_cfg_space to reset configuration space ...

Merge tag 'drm-qemu-20170110' of git://git.kraxel.org/linux into drm-fixes ------drm-qemu: virtio sparse fix, MAINTAINERS updates.

* tag 'drm-qemu-20170110' of git://git.kraxel.org/linux: drm: flip cirrus driver status to "obsolete".

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drm: update MAINTAINERS for qemu drivers (bochs, cirrus, qxl, virtio-gpu) drm/virtio: fix framebuffer sparse warning

Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM SoC fixes from Olof Johansson: "We've been sitting on fixes for a while, and they keep trickling in at a low rate. Nothing in here comes across as particularly scary or noteworthy, for the most part it's a large collection of small DT tweaks"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (24 commits) ARM: dts: da850-evm: fix access to SPI flash ARM: dts: omap3: Fix Card Detect and Write Protect on Logic PD SOM-LV ARM64: dts: meson-gxbb-odroidc2: Disable SCPI DVFS ARM: dts: OMAP5 / DRA7: indicate that SATA port 0 is available. ARM: dts: NSP: Fix DT ranges error ARM: multi_v7_defconfig: set bcm47xx watchdog ARM: multi_v7_defconfig: fix config typo ARM: dts: dra72-evm-revc: fix typo in ethernet-phy node soc: ti: wkup_m3_ipc: Fix error return code in wkup_m3_ipc_probe() ARM: ux500: fix prcmu_is_cpu_in_wfi() calculation ARM: dts: sunxi: Change node name for pwrseq pin on Olinuxino-lime2-emmc ARM: dts: sun8i: Support DTB build for NanoPi M1 ARM: dts: sun6i: hummingbird: Enable display engine again ARM: dts: sun6i: Disable display pipeline by default ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus" part 3 ARM: dts: imx6qdl-nitrogen6_som2: fix sgtl5000 pinctrl init ARM: dts: imx6qdl-nitrogen6_max: fix sgtl5000 pinctrl init ARM: OMAP1: DMA: Correct the number of logical channels ARM: dts: am335x-icev2: Remove the duplicated pinmux setting ARM: OMAP2+: Fix WL1283 Bluetooth Baud Rate ...

MAINTAINERS: update cxgb4 maintainer ------Ganesg will be taking over as maintainer from now

Merge branch 'fixes' of git://git.armlinux.org.uk/~rmk/linux-arm ------Pull ARM fixes from Russell King: "A few ARM fixes:

- fix a crash while performing TLB maintanence on early ARM SMP cores

- blacklist Scorpion CPUs for hardware breakpoints

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- ARMs asm/types.h has been included as part of the UAPI due to the way the makefiles work, move it to uapi/asm/types.h to make it official

- fix up syscall name matching"

* 'fixes' of git://git.armlinux.org.uk/~rmk/linux-arm: ARM: 8613/1: Fix the uaccess crash on PB11MPCore MAINTAINERS: update rmk's entries ARM: put types.h in uapi ARM: 8634/1: hw_breakpoint: blacklist Scorpion CPUs ARM: 8632/1: ftrace: fix syscall name matching

Merge tag 'samsung-fixes-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into fixes ------Samsung fixes for v4.10: 1. Update maintainers entry with Patchwork address. 2. Fix invalid values for NF_CT_PROTO_* in s3c2410 defconfig (these options cannot be modules anymore).

* tag 'samsung-fixes-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: s3c2410_defconfig: Fix invalid values for NF_CT_PROTO_* MAINTAINERS: Add Patchwork URL to Samsung Exynos entry

MAINTAINERS: update rmk's entries ------Update my entries in the MAINTAINERS file with the same email address for kernel work, and, now that the git tree is hosted on more suitable hardware, add git tree references where appropriate.

Merge tag 'dmaengine-fix-4.10-rc4' of git://git.infradead.org/users/vkoul/slave-dma ------Pull dmaengine fixes from Vinod Koul: "The fixes this time around are spread over drivers, pretty normal update:

- PCI ID for SKL ioatdma, workaround for SKX and ioat_alloc_chan_resources sleepy allocation fix

- dw kconfig typo fix

- null pointer deref for stm32

- MAINTAINERS Update for at_hdmac

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- pl330 runtime pm fixes

- omap-dma port window fix

- rcar-dmac unmap slave resource fix"

* tag 'dmaengine-fix-4.10-rc4' of git://git.infradead.org/users/vkoul/slave-dma: dmaengine: rcar-dmac: unmap slave resource when channel is freed dmaengine: omap-dma: Fix the port_window support dmaengine: iota: ioat_alloc_chan_resources should not perform sleeping allocations. dmaengine: pl330: Fix runtime PM support for terminated transfers MAINTAINERS: dmaengine: Update + Hand over the at_hdmac driver to Ludovic dmaengine: omap-dma: Fix dynamic lch_map allocation dmaengine: ti-dma-crossbar: Add some 'of_node_put()' in error path. dmaengine: stm32-dma: Fix null pointer dereference in stm32_dma_tx_status dmaengine: stm32-dma: Set correct args number for DMA request from DT dmaengine: dw: fix typo in Kconfig dmaengine: ioatdma: workaround SKX ioatdma version dmaengine: ioatdma: Add Skylake PCI Dev ID

MAINTAINERS: remove duplicate bug filling description ------I have noticed that two different descriptions for B: entries in MAINTAINERS were merged: commit 686564434e88 ("MAINTAINERS: Add bug tracking system location entry type") and 2de2bd95f456 ("MAINTAINERS: add "B:" for URI where to file bugs").

This patch keeps the description from 2de2bd95f456. There has been a discussion [1] about whether this more detailed description is useful and what it exactly implies. I find it more useful and general, and the author of 686564434e88 agreed in the end that either is fine.

[1] https://lkml.org/lkml/2016/12/8/71

Link: http://lkml.kernel.org/r/[email protected]

drm: flip cirrus driver status to "obsolete". ------Also update Kconfig help text, explaining things:

Cirrus is obsolete, the hardware was designed in the 90ies and can't keep up with todays needs. More background: https://www.kraxel.org/blog/2014/10/qemu-using-cirrus-considered-harmful/

Better alternatives are: - stdvga (DRM_BOCHS, qemu -vga std, default in qemu 2.2+) - qxl (DRM_QXL, qemu -vga qxl, works best with spice) - virtio (VIRTIO_GPU), qemu -vga virtio)

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drm: update MAINTAINERS for qemu drivers (bochs, cirrus, qxl, virtio-gpu) ------Changes: * add myself as maintainer, so patches land in my inbox. * add @lists.linux-foundation.org mailing list. * add drm-qemu git repo. * flip bochs and qxl status to "Maintained".

Merge branch 'drm-fixes-4.10' of git://people.freedesktop.org/~agd5f/linux into drm-fixes ------Fixes for 4.10: - Polaris 12 support - Add new amd-gfx mailing list to MAINTAINERS file - UVD clockgating fix - SI dpm fixes

* 'drm-fixes-4.10' of git://people.freedesktop.org/~agd5f/linux: drm/amdgpu: drop verde dpm quirks drm/radeon: drop verde dpm quirks drm/radeon: update smc firmware selection for SI drm/amdgpu: update si kicker smc firmware drm/amd/powerplay: extend smu's response timeout time. drm/amdgpu: remove static integer for uvd pp state drm/amd/amdgpu: add Polaris12 PCI ID drm/amdgpu/powerplay: add Polaris12 support drm/amd/amdgpu: add Polaris12 support (v3) MAINTAINERS: Update mailing list for radeon and amdgpu

Merge tag 'char-misc-4.10-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char- misc ------Pull char/misc fixes from Greg KH: "Here are a few small char/misc driver fixes for 4.10-rc3.

Two MEI driver fixes, and three NVMEM patches for reported issues, and a new Hyper-V driver MAINTAINER update. Nothing major at all, all have been in linux-next with no reported issues"

* tag 'char-misc-4.10-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: hyper-v: Add myself as additional MAINTAINER nvmem: fix nvmem_cell_read() return type doc nvmem: imx-ocotp: Fix wrong register size nvmem: qfprom: Allow single byte accesses for read/write mei: move write cb to completion on credentials failures mei: bus: fix mei_cldev_enable KDoc

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Merge tag 'staging-4.10-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging ------Pull staging/IIO fixes from Greg KH: "Here are some staging and IIO driver fixes for 4.10-rc3.

Most of these are minor IIO fixes of reported issues, along with one network driver fix to resolve an issue. And a MAINTAINERS update with a new mailing list. All of these, except the MAINTAINERS file update, have been in linux-next with no reported issues (the MAINTAINERS patch happened on Friday...)"

* tag 'staging-4.10-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: MAINTAINERS: add greybus subsystem mailing list staging: octeon: Call SET_NETDEV_DEV() iio: accel: st_accel: fix LIS3LV02 reading and scaling iio: common: st_sensors: fix channel data parsing iio: max44000: correct value in illuminance_integration_time_available iio: adc: TI_AM335X_ADC should depend on HAS_DMA iio: bmi160: Fix time needed to sleep after command execution iio: 104-quad-8: Fix active level mismatch for the preset enable option iio: 104-quad-8: Fix off-by-one errors when addressing IOR iio: 104-quad-8: Fix index control configuration

MAINTAINERS: add greybus subsystem mailing list ------The Greybus driver subsystem has a mailing list, so list it in the MAINTAINERS file so that people know to send patches there as well.

MAINTAINERS: Update mailing list for radeon and amdgpu ------amdgpu and radeon development has moved to this list.

Merge tag 'pm-4.10-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm ------Pull power management fixes from Rafael Wysocki: "These fix a few issues in the intel_pstate driver, a documetation issue, a false-positive warning in the generic power domains framework and two problems in the devfreq subsystem. They also update the MAINTAINERS entry for devfreq and add a new "compatible" string to the generic cpufreq-dt driver.

Specifics:

- Fix a few intel_pstate driver issues: add missing locking it two places, avoid exposing a useless interface and keep the attribute values in in (Rafael Wysocki).

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- Drop confusing kernel-doc references related to power management and ACPI from the driver API manual (Rafael Wysocki).

- Make a false-positive compiler warning in the generic power domains framework go away (Augusto Mecking Caringi).

- Fix two initialization issues in the devfreq subsystem and update the MAINTAINERS entry for it (Chanwoo Choi).

- Add a new "compatible" string for APM X-Gene 2 to the generic DT cpufreq driver (Hoan Tran)"

* tag 'pm-4.10-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: cpufreq: dt: Add support for APM X-Gene 2 PM / devfreq: exynos-bus: Fix the wrong return value PM / devfreq: Fix the bug of devfreq_add_device when governor is NULL MAINTAINERS: Add myself as reviewer for DEVFREQ subsystem support PM / docs: Drop confusing kernel-doc references from infrastructure.rst PM / domains: Fix 'may be used uninitialized' build warning cpufreq: intel_pstate: Always keep all limits settings in sync cpufreq: intel_pstate: Use locking in intel_cpufreq_verify_policy() cpufreq: intel_pstate: Use locking in intel_pstate_resume() cpufreq: intel_pstate: Do not expose PID parameters in passive mode

Merge branches 'pm-domains', 'pm-docs' and 'pm-devfreq' ------* pm-domains: PM / domains: Fix 'may be used uninitialized' build warning

* pm-docs: PM / docs: Drop confusing kernel-doc references from infrastructure.rst

* pm-devfreq: PM / devfreq: exynos-bus: Fix the wrong return value PM / devfreq: Fix the bug of devfreq_add_device when governor is NULL MAINTAINERS: Add myself as reviewer for DEVFREQ subsystem support

Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM SoC fixes from Arnd Bergmann: "This is a rather large set of bugfixes, as we just returned from the Christmas break. Most of these are relatively unimportant fixes for regressions introduced during the merge window, and about half of the changes are for mach-omap2.

A couple of patches are just cleanups and dead code removal that I would not normally have considered for merging after -rc2, but I decided to take them along with the fixes this time.

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Notable fixes include:

- removing the skeleton.dtsi include broke a number of machines, and we have to put empty /chosen nodes back to be able to pass kernel command lines as before

- enabling Samsung platforms no longer hardwires CONFIG_HZ to 200, as it had been for no good reason for a long time"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (46 commits) MAINTAINERS: extend PSCI entry to cover the newly add PSCI checker code drivers: psci: annotate timer on stack to silence odebug messages ARM64: defconfig: enable DRM_MESON as module ARM64: dts: meson-gx: Add Graphic Controller nodes ARM64: dts: meson-gxl: fix GPIO include ARM: dts: imx6: Disable "weim" node in the dtsi files ARM: dts: qcom: apq8064: Add missing scm clock ARM: davinci: da8xx: Fix sleeping function called from invalid context ARM: davinci: Make __clk_{enable,disable} functions public ARM: davinci: da850: don't add emac clock to lookup table twice ARM: davinci: da850: fix infinite loop in clk_set_rate() ARM: i.MX: remove map_io callback ARM: dts: vf610-zii-dev-rev-b: Add missing newline ARM: dts: imx6qdl-nitrogen6x: remove duplicate iomux entry ARM: dts: imx31: fix AVIC base address ARM: dts: am572x-idk: Add gpios property to control PCIE_RESETn arm64: dts: vexpress: Support GICC_DIR operations ARM: dts: vexpress: Support GICC_DIR operations firmware: arm_scpi: fix reading sensor values on pre-1.0 SCPI firmwares arm64: dts: msm8996: Add required memory carveouts ...

hyper-v: Add myself as additional MAINTAINER ------Update the Hyper-V MAINTAINERS to include myself.

Merge tag '-for-linus-4.10-rc3' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linux ------Pull xfs fixes from Darrick Wong:

- fixes for crashes and double-cleanup errors

- XFS maintainership handover

- fix to prevent absurdly large block reservations

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- fix broken sysfs getter/setters

* tag 'xfs-for-linus-4.10-rc3' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linux: xfs: fix max_retries _show and _store functions xfs: update MAINTAINERS xfs: fix crash and data corruption due to removal of busy COW extents xfs: use the actual AG length when reserving blocks xfs: fix double-cleanup when CUI recovery fails

Merge branch 'for-linus' of git://git.kernel.dk/linux-block ------Pull block layer fixes from : "A set of fixes for the current series, one fixing a regression with block size < page cache size in the alias series from Jan. Outside of that, two small cleanups for wbt from Bart, a nvme pull request from Christoph, and a few small fixes of documentation updates"

* 'for-linus' of git://git.kernel.dk/linux-block: block: fix up io_poll documentation block: Avoid that sparse complains about context imbalance in __wbt_wait() block: Make wbt_wait() definition consistent with declaration clean_bdev_aliases: Prevent cleaning blocks that are not in block range genhd: remove dead and duplicated scsi code block: add back plugging in __blkdev_direct_IO nvmet/fcloop: remove some logically dead code performing redundant ret checks nvmet: fix KATO offset in Set Features nvme/fc: simplify error handling of nvme_fc_create_hw_io_queues nvme/fc: correct some printk information nvme/scsi: Remove START STOP emulation nvme/pci: Delete misleading queue-wrap comment nvme/pci: Fix whitespace problem nvme: simplify stripe quirk nvme: update maintainers information

MAINTAINERS: add myself as maintainer of fbdev ------I would like to help with fbdev maintenance. I can dedicate some time for reviewing and handling patches but won't have time for much more.

The subsystem will remain in maintenance mode (no new drivers will be added to it).

xfs: update MAINTAINERS ------I am taking over as XFS maintainer from Dave Chinner[1], so update contact information and git tree pointers.

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[1] http://lkml.iu.edu/hypermail/linux/kernel/1612.1/04390.html

MAINTAINERS: extend PSCI entry to cover the newly add PSCI checker code ------This patch extends the file entry for PSCI so that the newly added PSCI checker module code is also covered.

MAINTAINERS: dmaengine: Update + Hand over the at_hdmac driver to Ludovic ------Hand over the Microchip / Atmel DMA driver handled by at_hdmac driver to Ludovic who is responsible for the newer at_xdmac driver as well. Also update the entry name and position to follow company changes.

MAINTAINERS: Add myself as reviewer for DEVFREQ subsystem support ------Add myself to the DEVFREQ entry as reviewer, I've been helping reviewing and tesing the devfreq support patches for the couple of years. Also, I'm going to contribute the improvement for devfreq subsystem. It would be easier for me for review if I'm cc'ed for patches.

MAINTAINERS: Add Patchwork URL to Samsung Exynos entry ------I use Patchwork for handling incoming patches. Put its address here so submitters could know what is in the queue.

Merge tag 'watchdog-for-linus-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging ------Pull watchdog updates from Wim Van Sebroeck and Guenter Roeck:

- new driver for Add Loongson1 SoC

- minor cleanup and fixes in various drivers

* tag 'watchdog-for-linus-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux- staging: watchdog: it87_wdt: add IT8620E ID watchdog: mpc8xxx: Remove unneeded linux/miscdevice.h include watchdog: octeon: Remove unneeded linux/miscdevice.h include watchdog: bcm2835_wdt: set WDOG_HW_RUNNING bit when appropriate watchdog: loongson1: Add Loongson1 SoC watchdog driver watchdog: cpwd: remove memory allocate failure message watchdog: da9062/61: watchdog driver intel-mid_wdt: Error code is just an integer intel-mid_wdt: make sure watchdog is not running at startup

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watchdog: mei_wdt: request stop on reboot to prevent false positive event watchdog: hpwdt: changed maintainer information watchdog: jz4740: Fix modular build watchdog: qcom: fix kernel panic due to external abort on non-linefetch watchdog: davinci: add support for deferred probing watchdog: meson: Remove unneeded platform MODULE_ALIAS watchdog: Standardize leading tabs and spaces in Kconfig file watchdog: max77620_wdt: fix module autoload watchdog: bcm7038_wdt: fix module autoload

Merge tag 'ntb-4.10' of git://github.com/jonmason/ntb ------Pull NTB update from Jon Mason:

- NTB bug fixes for removing an unnecessary call to ntb_peer_spad_read, and correcting a free_irq inconsistency

- add Intel SKX support

- change the AMD NTB maintainer, and fix some bugs present there

* tag 'ntb-4.10' of git://github.com/jonmason/ntb: ntb_transport: Remove unnecessary call to ntb_peer_spad_read NTB: Fix 'request_irq()' and 'free_irq()' inconsistancy ntb: fix SKX NTB config space size register offsets NTB: correct ntb_peer_spad_read for case when callback is not supplied. MAINTAINERS: Change in maintainer for AMD NTB ntb_transport: Limit memory windows based on available, scratchpads NTB: Register and offset values fix for memory window NTB: add support for hotplug feature ntb: Adding Skylake Xeon NTB support

MAINTAINERS: Change in maintainer for AMD NTB ------I would like to take maintainership for AMD NTB

Merge tag 'scsi-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi ------Pull late SCSI updates from James Bottomley: "This is mostly stuff which missed the initial pull.

There's a new driver: qedi, and some ufs, ibmvscsis and ncr5380 updates plus some assorted driver fixes and also a fix for the bug where if a device goes into a blocked state between configuration and sysfs device add (which can be a long time under async probing) it would become permanently blocked"

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* tag 'scsi-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: (30 commits) scsi: avoid a permanent stop of the scsi device's request queue scsi: mpt3sas: Recognize and act on iopriority info scsi: qla2xxx: Fix Target mode handling with Multiqueue changes. scsi: qla2xxx: Add Block Multi Queue functionality. scsi: qla2xxx: Add multiple queue pair functionality. scsi: qla2xxx: Utilize pci_alloc_irq_vectors/pci_free_irq_vectors calls. scsi: qla2xxx: Only allow operational MBX to proceed during RESET. scsi: hpsa: remove memory allocate failure message scsi: Update 3ware driver email addresses scsi: zfcp: fix rport unblock race with LUN recovery scsi: zfcp: do not trace pure benign residual HBA responses at default level scsi: zfcp: fix use-after-"free" in FC ingress path after TMF scsi: libcxgbi: return error if interface is not up scsi: cxgb4i: libcxgbi: add missing module_put() scsi: cxgb4i: libcxgbi: cxgb4: add T6 iSCSI completion feature scsi: cxgb4i: libcxgbi: add active cmd for T6 adapters scsi: cxgb4i: use cxgb4_tp_smt_idx() to get smt_idx scsi: qedi: Add QLogic FastLinQ offload iSCSI driver framework. scsi: aacraid: remove wildcard for series 9 controllers scsi: ibmvscsi: add write to CRQ processing ...

Merge branch 'nvme-4.10' of git://git.infradead.org/nvme into for-linus ------Christoph writes:

The most significant one is that we've agreed on shared maintaince and a common repository for the PCIe NVMe driver and NVMe over Fabrics. The target code still only has a subset of the maintainers but goes through the same tree as well. Keith, Sagi and me will take turns at collecting patches and sending you pull requests.

Merge tag 'leds_for_4.10_email_update' of git://git.kernel.org/pub/scm/linux/kernel/git/j.anaszewski/linux-leds ------Pull LED maintainer email update from Jacek Anaszewski: "Update Jacek Anaszewski's email address"

* tag 'leds_for_4.10_email_update' of git://git.kernel.org/pub/scm/linux/kernel/git/j.anaszewski/linux-leds: MAINTAINERS: Update Jacek Anaszewski's email address

Merge branch 'x86-cache-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip ------Pull x86 cache allocation interface from Thomas Gleixner: "This provides support for Intel's Cache Allocation Technology, a cache

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partitioning mechanism.

The interface is odd, but the hardware interface of that CAT stuff is odd as well.

We tried hard to come up with an abstraction, but that only allows rather simple partitioning, but no way of sharing and dealing with the per package nature of this mechanism.

In the end we decided to expose the allocation bitmaps directly so all combinations of the hardware can be utilized.

There are two ways of associating a cache partition:

- Task

A task can be added to a resource group. It uses the cache partition associated to the group.

- CPU

All tasks which are not member of a resource group use the group to which the CPU they are running on is associated with.

That allows for simple CPU based partitioning schemes.

The main expected user sare:

- Virtualization so a VM can only trash only the associated part of the cash w/o disturbing others

- Real-Time systems to seperate RT and general workloads.

- sensitive enterprise workloads

- In theory this also can be used to protect against cache side channel attacks"

[ Intel RDT is "Resource Director Technology". The interface really is rather odd and very specific, which delayed this pull request while I was thinking about it. The pull request itself came in early during the merge window, I just delayed it until things had calmed down and I had more time.

But people tell me they'll use this, and the good news is that it is _so_ specific that it's rather independent of anything else, and no user is going to depend on the interface since it's pretty rare. So if push comes to shove, we can just remove the interface and nothing will break ]

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* 'x86-cache-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (31 commits) x86/intel_rdt: Implement show_options() for resctrlfs x86/intel_rdt: Call intel_rdt_sched_in() with disabled x86/intel_rdt: Update task closid immediately on CPU in rmdir and unmount x86/intel_rdt: Fix setting of closid when adding CPUs to a group x86/intel_rdt: Update percpu closid immeditately on CPUs affected by changee x86/intel_rdt: Reset per cpu closids on unmount x86/intel_rdt: Select when enabling INTEL_RDT_A x86/intel_rdt: Prevent deadlock against hotplug lock x86/intel_rdt: Protect info directory from removal x86/intel_rdt: Add info files to Documentation x86/intel_rdt: Export the minimum number of set mask bits in sysfs x86/intel_rdt: Propagate error in rdt_mount() properly x86/intel_rdt: Add a missing #include MAINTAINERS: Add maintainer for Intel RDT resource allocation x86/intel_rdt: Add scheduler hook x86/intel_rdt: Add schemata file x86/intel_rdt: Add tasks files x86/intel_rdt: Add cpus file x86/intel_rdt: Add mkdir to resctrl x86/intel_rdt: Add "info" files to resctrl file system ...

MAINTAINERS: Update Jacek Anaszewski's email address ------My previous email address is no longer valid. From now on, [email protected] should be used instead.

nvme: update maintainers information ------Switch the new, shared nvme git repository, which is co-maintained by everyone involved with NVMe.

Also add the nvme_ioctl.h UAPI header to the files list.

Merge tag 'platform-drivers-x86-v4.10-2' of git://git.infradead.org/users/dvhart/linux- platform-drivers-x86 ------Pull more x86 platform driver updates from Darren Hart: "Move and add registration for the mlx-platform driver. Introduce button and lid drivers for the surface3 (different from the surface3-pro). Add BXT PMIC TMU support. Add Y700 to existing ideapad-laptop quirk.

Summary:

ideapad-laptop:

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- Add Y700 15-ACZ to no_hw_rfkill DMI list

surface3_button: - Introduce button support for the Surface 3

surface3-wmi: - Add custom surface3 platform device for controlling LID - Balance locking on error path

mlx-platform: - Add mlxcpld-hotplug driver registration - Fix semicolon.cocci warnings - Move module from arch/x86

platform/x86: - Add Whiskey Cove PMIC TMU support"

* tag 'platform-drivers-x86-v4.10-2' of git://git.infradead.org/users/dvhart/linux-platform- drivers-x86: platform/x86: surface3-wmi: Balance locking on error path platform/x86: Add Whiskey Cove PMIC TMU support platform/x86: ideapad-laptop: Add Y700 15-ACZ to no_hw_rfkill DMI list platform/x86: Introduce button support for the Surface 3 platform/x86: Add custom surface3 platform device for controlling LID platform/x86: mlx-platform: Add mlxcpld-hotplug driver registration platform/x86: mlx-platform: Fix semicolon.cocci warnings platform/x86: mlx-platform: Move module from arch/x86

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net ------Pull networking fixes and cleanups from David Miller:

1) Revert bogus nla_ok() change, from Alexey Dobriyan.

2) Various bpf validator fixes from Daniel Borkmann.

3) Add some necessary SET_NETDEV_DEV() calls to hsis_femac and hip04 drivers, from Dongpo Li.

4) Several ethtool ksettings conversions from Philippe Reynes.

5) Fix bugs in inet port management wrt. soreuseport, from Tom Herbert.

6) XDP support for virtio_net, from John Fastabend.

7) Fix NAT handling within a vrf, from David Ahern.

8) Endianness fixes in dpaa_eth driver, from Claudiu Manoil

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* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (63 commits) net: mv643xx_eth: fix build failure isdn: Constify some function parameters mlxsw: spectrum: Mark split ports as such cgroup: Fix CGROUP_BPF config qed: fix old-style function definition net: ipv6: check route protocol when deleting routes r6040: move in r6040_close as SOFTIRQ-unsafe lock order detected irda: w83977af_ir: cleanup an indent issue net: sfc: use new ethtool_{get|set}_link_ksettings net: davicom: dm9000: use ethtool_{get|set}_link_ksettings net: cirrus: ep93xx: use new api ethtool_{get|set}_link_ksettings net: chelsio: cxgb3: use new api ethtool_{get|set}_link_ksettings net: chelsio: cxgb2: use new api ethtool_{get|set}_link_ksettings bpf: fix mark_reg_unknown_value for spilled regs on map value marking bpf: fix overflow in prog accounting bpf: dynamically allocate digest scratch buffer gtp: Fix initialization of Flags octet in GTPv1 header gtp: gtp_check_src_ms_ipv4() always return success net/x25: use designated initializers isdn: use designated initializers ...

MAINTAINERS: net: add entry for Freescale QorIQ DPAA Ethernet driver ------Add record for Freescale QORIQ DPAA Ethernet driver adding myself as maintainer.

platform/x86: mlx-platform: Move module from arch/x86 ------Since mlx-platform is not an architectural driver, it is moved out of arch/x86/platform to drivers/platform/x86. Relevant Makefile and Kconfig are updated.

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs ------Pull vfs updates from Al Viro:

- more ->d_init() stuff (work.dcache)

- pathname resolution cleanups (work.namei)

- a few missing iov_iter primitives - copy_from_iter_full() and friends. Either copy the full requested amount, advance the iterator and return true, or fail, return false and do _not_ advance the iterator. Quite a few open-coded callers converted (and became more readable and harder to fuck up that way) (work.iov_iter)

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- several assorted patches, the big one being removal

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs: logfs: remove from tree vfs: fix put_compat_statfs64() does not handle errors namei: fold should_follow_link() with the step into not-followed link namei: pass both WALK_GET and WALK_MORE to should_follow_link() namei: invert WALK_PUT logics namei: shift interpretation of LOOKUP_FOLLOW inside should_follow_link() namei: saner calling conventions for mountpoint_last() namei.c: get rid of user_path_parent() switch getfrag callbacks to ..._full() primitives make skb_add_data,{_nocache}() and skb_copy_to_page_nocache() advance only on success [iov_iter] new primitives - copy_from_iter_full() and friends don't open-code file_inode() : switch to use of ->d_init() ceph: unify dentry_operations instances : switch to use of ->d_init()

Merge tag 'media/v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux- media ------Pull media updates from Mauro Carvalho Chehab:

- new Mediatek drivers: mtk-mdp and mtk-vcodec

- some additions at the media documentation

- the CEC core and drivers were promoted from staging to mainstream

- some cleanups at the DVB core

- the LIRC serial driver got promoted from staging to mainstream

- added a driver for Renesas R-Car FDP1 driver

- add DVBv5 statistics support to mn88473 driver

- several fixes related to printk continuation lines

- add support for HSV encoding formats

- lots of other cleanups, fixups and driver improvements.

* tag 'media/v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (496 commits) [media] v4l: tvp5150: Add missing break in set control handler

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[media] v4l: tvp5150: Don't inline the tvp5150_selmux() function [media] v4l: tvp5150: Compile tvp5150_link_setup out if !CONFIG_MEDIA_CONTROLLER [media] em28xx: don't store usb_device at struct em28xx [media] em28xx: use usb_interface for dev_foo() calls [media] em28xx: don't change the device's name [media] mn88472: fix chip id check on probe [media] mn88473: fix chip id check on probe [media] lirc: fix error paths in lirc_cdev_add() [media] s5p-mfc: Add support for MFC v8 available in Exynos 5433 SoCs [media] s5p-mfc: Rework clock handling [media] s5p-mfc: Don't keep clock prepared all the time [media] s5p-mfc: Kill all IS_ERR_OR_NULL in clocks management code [media] s5p-mfc: Remove dead conditional code [media] s5p-mfc: Ensure that clock is disabled before turning power off [media] s5p-mfc: Remove special clock rate management [media] s5p-mfc: Use printk_ratelimited for reporting errors [media] s5p-mfc: Set DMA_ATTR_ALLOC_SINGLE_PAGES [media] vivid: Set color_enc on HSV formats [media] v4l2-tpg: Init hv_enc field with a valid value ...

Merge tag 'edac/v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux- edac ------Pull edac updates from Mauro Carvalho Chehab: "This contains the conversion of the EDAC uAPI documentation to ReST and the addition of the EDAC kAPI documentation to the driver-api docs.

It also splits the EDAC headers by their functions"

* tag 'edac/v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac: EDAC: Document HW_EVENT_ERR_DEFERRED type edac.rst: move concepts dictionary from edac.h edac: fix kenel-doc markups at edac.h edac: fix kernel-doc tags at the drivers/edac_*.h edac: adjust docs location at MAINTAINERS and 00-INDEX driver-api: create an edac.rst file with EDAC documentation edac: move documentation from edac_mc.c to edac_core.h edac: move documentation from edac_pci*.c to edac_pci.h edac: move documentation from edac_device to edac_core.h edac: rename edac_core.h to edac_mc.h edac: move EDAC device definitions to drivers/edac/edac_device.h edac: move EDAC PCI definitions to drivers/edac/edac_pci.h docs-rst: admin-guide: add documentation for EDAC edac.txt: Improve documentation, adding RAS introduction edac.txt: update information about newer Intel CPUs edac.txt: remove info that the Nehalem EDAC is experimental

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edac.txt: convert EDAC documentation to ReST edac.txt: add a section explaining the dimmX and rankX directories edac: edac_core.h: remove prototype for edac_pci_reset_delay_period() edac: edac_core.h: get rid of unused kobj_complete

watchdog: hpwdt: changed maintainer information ------

Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost ------Pull virtio updates from Michael Tsirkin: "virtio, vhost: new device, fixes, speedups

This includes the new virtio crypto device, and fixes all over the place. In particular enabling endian-ness checks for sparse builds found some bugs which this fixes. And it appears that everyone is in agreement that disabling endian-ness sparse checks shouldn't be necessary any longer.

So this enables them for everyone, and drops the __CHECK_ENDIAN__ and __bitwise__ .

IRQ handling in virtio has been refactored somewhat, the larger switch to IRQ_SHARED will have to wait as it proved too aggressive"

* tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost: (34 commits) Makefile: drop -D__CHECK_ENDIAN__ from cflags fs/logfs: drop __CHECK_ENDIAN__ Documentation/sparse: drop __CHECK_ENDIAN__ linux: drop __bitwise__ everywhere checkpatch: replace __bitwise__ with __bitwise Documentation/sparse: drop __bitwise__ tools: enable endian checks for all sparse builds linux/types.h: enable endian checks for all sparse builds virtio_mmio: Set dev.release() to avoid warning vhost: remove unused feature bit virtio_ring: fix description of virtqueue_get_buf vhost/scsi: Remove unused but set variable tools/virtio: use {READ,WRITE}_ONCE() in uaccess.h vringh: kill off ACCESS_ONCE() tools/virtio: fix READ_ONCE() crypto: add virtio-crypto driver vhost: cache used event for better performance vsock: lookup and setup guest_cid inside vhost_vsock_lock virtio_pci: split vp_try_to_find_vqs into INTx and MSI-X variants virtio_pci: merge vp_free_vectors into vp_del_vqs ...

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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM SoC driver updates from Arnd Bergmann: "Driver updates for ARM SoCs, including a couple of newly added drivers:

- A new driver for the power management controller on TI Keystone

- Support for the prerelease "SCPI" firmware protocol that ended up being shipped by Amlogic in their GXBB SoC.

- A soc_device can now be matched using a glob from inside the kernel, when another driver wants to know the specific chip it is running on and cannot find out from DT, firmware or hardware.

- Renesas SoCs now support identification through the soc_device interface, both in and kernel.

- Renesas r8a7743 and r8a7745 gain support for their system controller

- A new checking module for the ARM "PSCI" (not to be confused with "SCPI" mentioned above) firmware interface.

- A new driver for the Tegra GMI memory interface

- Support for the Tegra firmware interfaces with their power management controllers

As usual, the updates for the reset controller framework are merged here, as they tend to touch multiple SoCs as well, including a new driver for the Oxford (now Broadcom) OX820 chip and the Tegra bpmp interface.

The existing drivers for Atmel, Qualcomm, NVIDIA, TI Davinci, and Rockchips SoCs see some further updates"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (76 commits) misc: sram: remove useless #ifdef drivers: psci: Allow PSCI node to be disabled drivers: psci: PSCI checker module soc: renesas: Identify SoC and register with the SoC bus firmware: qcom: scm: Return PTR_ERR when devm_clk_get fails firmware: qcom: scm: Remove core, iface and bus clocks dependency dt-bindings: firmware: scm: Add MSM8996 DT bindings memory: da8xx-ddrctl: drop the call to of_flat_dt_get_machine_name() bus: da8xx-mstpri: drop the call to of_flat_dt_get_machine_name() ARM: shmobile: Document DT bindings for Product Register

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soc: renesas: rcar-sysc: add R8A7745 support reset: Add Tegra BPMP reset driver dt-bindings: firmware: Allow child nodes inside the Tegra BPMP dt-bindings: Add power domains to Tegra BPMP firmware firmware: tegra: Add BPMP support firmware: tegra: Add IVC library dt-bindings: firmware: Add bindings for Tegra BPMP mailbox: tegra-hsp: Use after free in tegra_hsp_remove_doorbells() mailbox: Add Tegra HSP driver firmware: arm_scpi: add support for pre-v1.0 SCPI compatible ...

Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources:

- Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line - Rockchip PX5 automotive platform, a relative of their popular rk3368 Android tablet chips

Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time:

- Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board

For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE"

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* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits) arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066

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- Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC

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ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

Merge tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM SoC 64-bit updates from Arnd Bergmann: "Changes to platform code for 64-bit ARM platforms. We are not adding any new platforms that require code or Kconfig changes this time, so it's basically just defconfig changes to enable support for more drivers used on the existing platforms.

This is mainly interesting for the 3, which should now work much better with the default build"

* tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: arm64: defconfig: drop GPIO_SYSFS on multiplatforms arm64: defconfig: Do not lower CONFIG_LOG_BUF_SHIFT arm64: defconfig: allow rk3399-based boards to boot from mmc and usb arm64: defconfig: enable RK808 components arm64: defconfig: enable I2C and DW MMC controller on rockchip platform arm64: defconfig: Enable Tegra186 SoC ARM64: configs: Activate Internal PHY for Meson GXL arm64: qcom: enable GPIOLIB in Kconfig arm64: configs: enable configs for msm899(2/4) basic support ARM64: bcm2835: add thermal driver to default config ARM64: configs: Add Platform MHU in defconfig MAINTAINERS: Update Broadcom Vulcan maintainer email arm64: defconfig: enable EEPROM_AT25 config option arm64: Enable HIBERNATION in defconfig arm64: defconfig: Enable DRM DU and V4L2 FCP + VSP modules ARM64: defconfig: Enable MMC related configs arm64: Add BCM2835 (Raspberry Pi 3) support to the defconfig

Merge tag 'arc-4.10-rc1-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc ------Pull ARC updates from Vineet Gupta: "These are mostly timer/clocksource driver updates which were

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Reviewed/Acked by Daniel but had to be merged via ARC tree due to dependencies.

I will follow up with another pull request with actual ARC changes early next week !

Summary:

- Moving ARC timer driver into drivers/clocksource

- EZChip timer driver updates [Noam]

- ARC AXS103 and HAPS platform updates [Alexey]"

* tag 'arc-4.10-rc1-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: axs10x: really enable ARC PGU ARC: rename Zebu platform support to HAPS clocksource: nps: avoid maybe-uninitialized warning clocksource: Add clockevent support to NPS400 driver clocksource: update "fn" at CLOCKSOURCE_OF_DECLARE() of nps400 timer soc: Support for NPS HW clocksource: import ARC timer driver ARC: breakout timer include code into separate header ... ARC: move mcip.h into include/soc and adjust the includes ARC: breakout aux handling into a separate header ARC: time: move time_init() out of the driver ARC: timer: gfrc, rtc: build under same option (64-bit timers) ARC: timer: gfrc, rtc: Read BCR to detect whether hardware exists ... ARC: timer: gfrc, rtc: deuglify big endian code

crypto: add virtio-crypto driver ------This patch introduces virtio-crypto driver for Linux Kernel.

The virtio crypto device is a virtual cryptography device as well as a kind of virtual hardware accelerator for virtual machines. The encryption anddecryption requests are placed in the data queue and are ultimately handled by thebackend crypto accelerators. The second queue is the control queue used to create or destroy sessions for symmetric algorithms and will control some advanced features in the future. The virtio crypto device provides the following cryptoservices: CIPHER, MAC, HASH, and AEAD.

For more information about virtio-crypto device, please see: http://qemu-project.org/Features/VirtioCrypto

CC: Michael S. Tsirkin CC: Cornelia Huck

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CC: Stefan Hajnoczi CC: Herbert Xu CC: Halil Pasic CC: David S. Miller CC: Zeng Xin

Merge tag 'platform-drivers-x86-v4.10-1' of git://git.infradead.org/users/dvhart/linux- platform-drivers-x86 ------Pull x86 platform driver updates from Darrent Hart: "Introduce one new driver for Mellanox platforms. Add support for various new models to existing drivers via quirks, hotkeys, etc. Significant updates to intel_pmc_core in support of Kabylake and Sunrise Point PCH power management debug. Some cleanup and refactoring across various drivers.

Detailed summary:

dell-laptop: - Use brightness_set_blocking for kbd_led_level_set

thinkpad_acpi: - Initialize local in_tablet_mode and type - Fix old style declaration GCC warning - Adding new hotkey ID for Lenovo thinkpad - Add support for X1 Yoga (2016) Tablet Mode - Move tablet detection into separate function

asus-nb-wmi: - Add X45U quirk - Make use of dmi->ident

asus-wmi: - Set specified XUSB2PR value for X550LB

intel_mid_thermal: - Fix suspend handlers unused warning

intel-vbtn: - Switch to use devm_input_allocate_device

dell-wmi: - Add events created by Dell Rugged 2-in-1s - Adjust wifi catcher to emit KEY_WLAN

intel_pmc_core: - Add KBL CPUID support - Add LTR IGNORE debug feature - Add MPHY PLL clock gating status - ModPhy core lanes pg status

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- Add PCH IP Power Gating Status - Fix PWRMBASE mask and mmio reg len

acer-wmi: - Only supports AMW0_GUID1 on acer family

mlx-platform: - Introduce support for Mellanox hotplug driver

platform/x86: - Use ACPI_FAILURE at appropriate places"

* tag 'platform-drivers-x86-v4.10-1' of git://git.infradead.org/users/dvhart/linux-platform- drivers-x86: (22 commits) platform/x86: thinkpad_acpi: Initialize local in_tablet_mode and type platform/x86: dell-laptop: Use brightness_set_blocking for kbd_led_level_set platform/x86: thinkpad_acpi: Fix old style declaration GCC warning platform/x86: thinkpad_acpi: Adding new hotkey ID for Lenovo thinkpad platform/x86: thinkpad_acpi: Add support for X1 Yoga (2016) Tablet Mode platform/x86: thinkpad_acpi: Move tablet detection into separate function platform/x86: asus-nb-wmi.c: Add X45U quirk platform/x86: asus-nb-wmi: Make use of dmi->ident platform/x86: asus-wmi: Set specified XUSB2PR value for X550LB platform/x86: intel_mid_thermal: Fix suspend handlers unused warning platform/x86: intel-vbtn: Switch to use devm_input_allocate_device platform/x86: Use ACPI_FAILURE at appropriate places platform/x86: dell-wmi: Add events created by Dell Rugged 2-in-1s platform/x86: dell-wmi: Adjust wifi catcher to emit KEY_WLAN platform/x86: intel_pmc_core: Add KBL CPUID support platform/x86: intel_pmc_core: Add LTR IGNORE debug feature platform/x86: intel_pmc_core: Add MPHY PLL clock gating status platform/x86: intel_pmc_core: ModPhy core lanes pg status platform/x86: intel_pmc_core: Add PCH IP Power Gating Status platform/x86: intel_pmc_core: Fix PWRMBASE mask and mmio reg len ...

Merge branch 'i2c/for-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux ------Pull i2c updates from Wolfram Sang:

- the first series of making i2c_device_id optional instead of mandatory (in favor of alternatives like of_device_id).

This involves adding a new probe callback (probe_new) which removes some peculiarities I2C had for a long time now. The new probe is matching the other subsystems now and the old one will be removed once all users are converted. It is expected to take a while but there is ongoing interest in that.

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- SMBus Host Notify introduced 4.9 got refactored. They are now using instead of the alert callback which solves multiple issues.

- new drivers for iMX LowPower I2C, Mellanox CPLD and its I2C mux

- significant refactoring for bcm2835 driver

- the usual set of driver updates and improvements

* 'i2c/for-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (46 commits) i2c: fsl-lpi2c: read lpi2c fifo size in probe() i2c: octeon: thunderx: Remove double-check after i2c: octeon: thunderx: TWSI software reset in recovery i2c: cadence: Allow Cadence I2C to be selected for Cadence Xtensa CPUs i2c: sh_mobile: Add per-Generation fallback bindings i2c: rcar: Add per-Generation fallback bindings i2c: imx-lpi2c: add low power i2c bus driver dt-bindings: i2c: imx-lpi2c: add devicetree bindings i2c: designware-pcidrv: Add 10bit address feature to medfield/merrifield i2c: pxa: Add support for the I2C units found in Armada 3700 i2c: pxa: Add definition of fast and high speed modes via the regs layout dt-bindings: i2c: pxa: Update the documentation for the Armada 3700 i2c: qup: support SMBus block read i2c: qup: add ACPI support i2c: designware: Consolidate default functionality bits i2c: i2c-mux-gpio: update mux with gpiod_set_array_value_cansleep i2c: mux: pca954x: Add ACPI support for pca954x i2c: use an IRQ to report Host Notify events, not alert i2c: i801: remove SMBNTFDDAT reads as they always seem to return 0 i2c: i801: use the BIT() macro for FEATURES_* also ...

Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma ------Pull rdma updates from Doug Ledford: "This is the complete update for the rdma stack for this release cycle.

Most of it is typical driver and core updates, but there is the entirely new VMWare pvrdma driver. You may have noticed that there were changes in DaveM's pull request to the bnxt Ethernet driver to support a RoCE RDMA driver. The bnxt_re driver was tentatively set to be pulled in this release cycle, but it simply wasn't ready in time and was dropped (a few review comments still to address, and some multi-arch build issues like prefetch() not working across all arches).

Summary:

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- shared mlx5 updates with net stack (will drop out on merge if Dave's tree has already been merged)

- driver updates: cxgb4, hfi1, hns-roce, i40iw, mlx4, mlx5, qedr, rxe

- debug cleanups

- new connection rejection helpers

- SRP updates

- various misc fixes

- new paravirt driver from vmware"

* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma: (210 commits) IB: Add vmw_pvrdma driver IB/mlx4: fix improper return value IB/ocrdma: fix bad initialization infiniband: nes: return value of skb_linearize should be handled MAINTAINERS: Update Intel RDMA RNIC driver maintainers MAINTAINERS: Remove Mitesh Ahuja from emulex maintainers IB/core: fix unmap_sg argument qede: fix may occur on probe IB/mthca: Replace pci_pool_alloc by pci_pool_zalloc mlx5, calc_sq_size(): Make a debug message more informative mlx5: Remove a set-but-not-used variable mlx5: Use { } instead of { 0 } to init struct IB/srp: Make writing the add_target sysfs attr interruptible IB/srp: Make mapping failures easier to debug IB/srp: Make login failures easier to debug IB/srp: Introduce a local variable in srp_add_one() IB/srp: Fix CONFIG_DYNAMIC_DEBUG=n build IB/multicast: Check ib_find_pkey() return value IPoIB: Avoid reading an uninitialized member variable IB/mad: Fix an array index check ...

afs, rxrpc: Update the MAINTAINERS file ------Update the MAINTAINERS file for AFS and AF_RXRPC to include a website pointer.

edac: adjust docs location at MAINTAINERS and 00-INDEX ------Update MAINTAINERS to reflect the location of edac.rst and ras.rst.

In the case of 00-INDEX, there's already an entry to the admin-guide,

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so all we need to do is to remove the entry there.

Merge branch 'patchwork' into v4l_for_linus ------* patchwork: (496 commits) [media] v4l: tvp5150: Add missing break in set control handler [media] v4l: tvp5150: Don't inline the tvp5150_selmux() function [media] v4l: tvp5150: Compile tvp5150_link_setup out if !CONFIG_MEDIA_CONTROLLER [media] em28xx: don't store usb_device at struct em28xx [media] em28xx: use usb_interface for dev_foo() calls [media] em28xx: don't change the device's name [media] mn88472: fix chip id check on probe [media] mn88473: fix chip id check on probe [media] lirc: fix error paths in lirc_cdev_add() [media] s5p-mfc: Add support for MFC v8 available in Exynos 5433 SoCs [media] s5p-mfc: Rework clock handling [media] s5p-mfc: Don't keep clock prepared all the time [media] s5p-mfc: Kill all IS_ERR_OR_NULL in clocks management code [media] s5p-mfc: Remove dead conditional code [media] s5p-mfc: Ensure that clock is disabled before turning power off [media] s5p-mfc: Remove special clock rate management [media] s5p-mfc: Use printk_ratelimited for reporting ioctl errors [media] s5p-mfc: Set DMA_ATTR_ALLOC_SINGLE_PAGES [media] vivid: Set color_enc on HSV formats [media] v4l2-tpg: Init hv_enc field with a valid value ...

logfs: remove from tree ------Logfs was introduced to the kernel in 2009, and hasn't seen any non drive-by changes since 2012, while having lots of unsolved issues including the complete lack of error handling, with more and more issues popping up without any fixes.

The logfs.org domain has been bouncing from a mail, and the maintainer on the non-logfs.org domain hasn't repsonded to past queries either.

Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 ------Pull crypto updates from Herbert Xu: "Here is the crypto update for 4.10:

API: - add skcipher walk interface - add asynchronous compression (acomp) interface - fix algif_aed AIO handling of zero buffer

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Algorithms: - fix unaligned access in poly1305 - fix DRBG output to large buffers

Drivers: - add support for iMX6UL to caam - fix givenc descriptors (used by IPsec) in caam - accelerated SHA256/SHA512 for ARM64 from OpenSSL - add SSE CRCT10DIF and CRC32 to ARM/ARM64 - add AEAD support to Chelsio chcr - add Armada 8K support to omap-rng"

* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (148 commits) crypto: testmgr - fix overlap in chunked tests again crypto: arm/crc32 - accelerated support based on x86 SSE implementation crypto: arm64/crc32 - accelerated support based on x86 SSE implementation crypto: arm/crct10dif - port x86 SSE implementation to ARM crypto: arm64/crct10dif - port x86 SSE implementation to arm64 crypto: testmgr - add/enhance test cases for CRC-T10DIF crypto: testmgr - avoid overlap in chunked tests crypto: chcr - checking for IS_ERR() instead of NULL crypto: caam - check caam_emi_slow instead of re-lookup platform crypto: algif_aead - fix AIO handling of zero buffer crypto: aes-ce - Make aes_simd_algs static crypto: algif_skcipher - set error code when kcalloc fails crypto: caam - make aamalg_desc a proper module crypto: caam - pass key buffers with typesafe pointers crypto: arm64/aes-ce-ccm - Fix AEAD decryption length MAINTAINERS: add crypto headers to crypto entry crypt: doc - remove misleading mention of async API crypto: doc - fix header file name crypto: api - fix comment typo crypto: skcipher - Add separate walker for AEAD decryption ..

scsi: Update 3ware driver email addresses ------This change updates the 3ware drivers (3w-xxxx, 3w-9xxx, 3w-sas) email addresses from [email protected] to [email protected], since the old email address doesn't exist.

This patch was updated to remove www.lsi.com text.

[mkp: applied by hand]

scsi: qedi: Add QLogic FastLinQ offload iSCSI driver framework. ------

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The QLogic FastLinQ Driver for iSCSI (qedi) is the iSCSI specific module for 41000 Series Converged Network Adapters by QLogic.

This patch consists of following changes:

- MAINTAINERS Makefile and Kconfig changes for qedi, - PCI driver registration, - iSCSI host level initialization, - Debugfs and log level infrastructure.

The following indiviual changes are merged into this commit:

qedi: Add LL2 iSCSI interface for offload iSCSI. qedi: Add support for iSCSI session management. qedi: Add support for data path.

Merge branch 'vmw_pvrdma' into merge-test ------

IB: Add vmw_pvrdma driver ------This patch series adds a driver for a paravirtual RDMA device. The device is developed for VMware's Virtual Machines and allows existing RDMA applications to continue to use existing Verbs API when deployed in VMs on ESXi. We recently did a presentation in the OFA Workshop [1] regarding this device.

Description and RDMA Support ======The virtual device is exposed as a dual function PCIe device. One part is a virtual network device (VMXNet3) which provides networking properties like MAC, IP addresses to the RDMA part of the device. The networking properties are used to register GIDs required by RDMA applications to communicate.

These patches add support and the all required infrastructure for letting applications use such a device. We support the mandatory Verbs API as well as the base extensions (Local Inv, Send with Inv and Fast Register Work Requests). We currently support both Reliable Connected and Unreliable Datagram QPs but do not support Shared Receive Queues (SRQs).

Also, we support the following types of Work Requests: o Send/Receive (with or without Immediate Data) o RDMA Write (with or without Immediate Data) o RDMA Read o Local Invalidate o Send with Invalidate

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o Fast Register Work Requests

This version only adds support for version 1 of RoCE. We will add RoCEv2 support in a future patch. We do support registration of both MAC-based and IP-based GIDs. I have also created a git tree for our user-level driver [2].

Testing ======We have tested this internally for various types of Guest OS - Red Hat, Centos, Ubuntu 12.04/14.04/16.04, Oracle Enterprise Linux, SLES 12 using backported versions of this driver. The tests included several runs of the performance tests (included with OFED), Intel MPI PingPong benchmark on OpenMPI, krping for FRWRs. Mellanox has been kind enough to test the backported version of the driver internally on their hardware using a VMware provided ESX build. I have also applied and tested this with Doug's k.o/for-4.9 branch (commit 5603910b). Note, that this patch series should be applied all together. I split out the commits so that it may be easier to review.

PVRDMA Resources ======[1] OFA Workshop Presentation - https://openfabrics.org/images/eventpresos/2016presentations/102parardma.pdf

[2] Libpvrdma User-level library - http://git.openfabrics.org/?p=~aditr/libpvrdma.git;a=summary

MAINTAINERS: Update Intel RDMA RNIC driver maintainers ------

MAINTAINERS: Remove Mitesh Ahuja from emulex maintainers ------Remove Mitesh Ahuja from maintainers file. This email address seems not active and causes to mail bounces during submissions.

Merge tag 'sound-4.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound ------Pull sound updates from Takashi Iwai: "No dramatic changes are found in this development cycle, but as usual, many commits are applied in a wide range of drivers.

Most of big changes are in ASoC, where a few bits of framework work and quite a lot of cleanups and improvements to existing code have been done. The rest are usual stuff, a few HD-audio and USB-audio quirks and fixes, as well as the drop of kthread usages in the whole

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subsystem.

Below are some highlights:

ASoC: - support for stereo DAPM controls - some initial work on the of-graph sound card - regmap conversions of the remaining AC'97 drivers - a new version of the topology ABI; this should be backward compatible - updates / cleanups of rsnd, sunxi, sti, nau8825, samsung, arizona, Intel skylake, atom-sst - new drivers for Cirrus Logic CS42L42, Qualcomm MSM8916-WCD, and Realtek RT5665

USB-audio: - yet another race fix at disconnection - tolerated packet size calculation for some Android devices - quirks for Axe-Fx II, QuickCam, TEAC 501/503

HD-audio: - improvement of Dell pin fixup mapping - quirks for HP Z1 Gen3, Alienware 15 R2 2016 and ALC622 headset mic

Misc: - replace all kthread usages with simple works"

* tag 'sound-4.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (296 commits) ALSA: hiface: Fix M2Tech hiFace driver sampling rate change ALSA: usb-audio: Eliminate noise at the start of DSD playback. ALSA: usb-audio: Add native DSD support for TEAC 501/503 DAC ASoC: wm_adsp: wm_adsp_buf_alloc should use kfree in error path ASoC: topology: avoid uninitialized kcontrol_type ALSA: usb-audio: Add QuickCam Communicate Deluxe/S7500 to volume_control_quirks ALSA: usb-audio: add implicit fb quirk for Axe-Fx II ASoC: zte: spdif: correct ZX_SPDIF_CLK_RAT define ASoC: zte: spdif and i2s drivers are not zx296702 specific ASoC: rsnd: setup BRGCKR/BRRA/BRRB when starting ASoC: rsnd: enable/disable ADG when suspend/resume timing ASoC: rsnd: tidyup ssi->usrcnt counter check in hw_params ALSA: cs46xx: add a new line ASoC: Intel: update bxt_da7219_max98357a to support quad ch dmic capture ASoC: nau8825: disable sinc filter for high THD of ADC ALSA: usb-audio: more tolerant packetsize ALSA: usb-audio: avoid setting of sample rate multiple times on bus ASoC: cs35l34: Simplify the logic to set CS35L34_MCLK_CTL setting ALSA: hda - Gate the mic jack on HP Z1 Gen3 AiO ALSA: hda: when comparing pin configurations, ignore assoc in addition to seq

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...

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid ------Pull HID updates from Jiri Kosina:

- support for new Wacom "MobileStudio Pro" class of tablets from Jason Gerecke

- Microsoft Surface 3 support from Benjamin Tissoires and Microsoft Surface 4 support from Daniel Keller

- uDraw PS3 tablet support from Bastien Nocera

- timeout scheduling fixes for intel-ish-hid from Even Xu

- HID_QUIRK_MULTI_INPUT in order to simplify LED handling from Benjamin Tissoires

- support for Sony DS4 dongle and various other fixes to Sony driver from Roderick Colenbrander

- other assorted smaller fixes and device ID additions

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid: (63 commits) HID: fix missing irq field HID: i2c-hid: fix build HID: i2c-hid: Disable IRQ before freeing buffers HID: usbhid: fix improper return value HID: wacom: generic: Don't sync input on empty input packets HID: wacom: generic: Pad supports more than buttons HID: wacom: generic: Send data only when the interface is defined HID: wacom: generic: Don't return a value for wacom_wac_event HID: intel_ish-hid: use %pUL for uuid formatting HID: cp2112: explicitly require irqchip support in gpiolib HID: asus: Add i2c touchpad support HID: intel-ish-hid: Fix potential race condition HID: sony: Support DS4 dongle HID: sony: Comply to Linux gamepad spec for DS4 HID: sony: Make the DS4 touchpad a separate device HID: sony: Fix memory issue when connecting device using both Bluetooth and USB HID: cp2112: add IRQ chip handling HID: i2c-hid: force the IRQ level trigger only when not set HID: multitouch: do not retrieve all reports for all devices HID: multitouch: enable the Surface 3 Type Cover to report multitouch data ...

Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi

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------Pull SCSI updates from James Bottomley: "This update includes the usual round of major driver updates (ncr5380, lpfc, hisi_sas, megaraid_sas, ufs, ibmvscsis, mpt3sas).

There's also an assortment of minor fixes, mostly in error legs or other not very user visible stuff. The major change is the pci_alloc_irq_vectors replacement for the old pci_msix_.. calls; this effectively makes IRQ mapping generic for the drivers and allows blk_mq to use the information"

* tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: (256 commits) scsi: qla4xxx: switch to pci_alloc_irq_vectors scsi: hisi_sas: support deferred probe for v2 hw scsi: megaraid_sas: switch to pci_alloc_irq_vectors scsi: scsi_devinfo: remove synchronous ALUA for NETAPP devices scsi: be2iscsi: set errno on error path scsi: be2iscsi: set errno on error path scsi: hpsa: fallback to use legacy REPORT PHYS command scsi: scsi_dh_alua: Fix RCU annotations scsi: hpsa: use %phN for short hex dumps scsi: hisi_sas: fix free'ing in probe and remove scsi: isci: switch to pci_alloc_irq_vectors scsi: ipr: Fix runaway IRQs when falling back from MSI to LSI scsi: dpt_i2o: double free on error path scsi: cxlflash: Migrate scsi command pointer to AFU command scsi: cxlflash: Migrate IOARRIN specific routines to function pointers scsi: cxlflash: Cleanup queuecommand() scsi: cxlflash: Cleanup send_tmf() scsi: cxlflash: Remove AFU command lock scsi: cxlflash: Wait for active AFU commands to timeout upon tear down scsi: cxlflash: Remove private command pool ...

Merge tag 'ext4_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4 ------Pull updates from Ted Ts'o: "This merge request includes the dax-4.0-iomap-pmd branch which is needed for both ext4 and xfs dax changes to use iomap for DAX. It also includes the fscrypt branch which is needed for encryption work as well as ext4 encryption and fscrypt cleanups.

Lots of cleanups and bug fixes, especially making sure ext4 is robust against maliciously corrupted file systems --- especially maliciously corrupted xattr blocks and a maliciously corrupted superblock. Also fix ext4 support for 64k block sizes so it works well on ppcle. Fixed mbcache so we don't miss some common xattr blocks that can be merged"

* tag 'ext4_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4: (86

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commits) dax: Fix sleep in atomic contex in grab_mapping_entry() fscrypt: Rename FS_WRITE_PATH_FL to FS_CTX_HAS_BOUNCE_BUFFER_FL fscrypt: Delay bounce page pool allocation until needed fscrypt: Cleanup page locking requirements for fscrypt_{decrypt,encrypt}_page() fscrypt: Cleanup fscrypt_{decrypt,encrypt}_page() fscrypt: Never allocate fscrypt_ctx on in-place encryption fscrypt: Use correct index in decrypt path. fscrypt: move the policy flags and encryption mode definitions to uapi header fscrypt: move non-public structures and constants to fscrypt_private.h fscrypt: unexport fscrypt_initialize() fscrypt: rename get_crypt_info() to fscrypt_get_crypt_info() fscrypto: move ioctl processing more fully into common code fscrypto: remove unneeded Kconfig dependencies MAINTAINERS: fscrypto: recommend linux-fsdevel for fscrypto patches ext4: do not perform data journaling when data is encrypted ext4: return -ENOMEM instead of success ext4: reject with negative size ext4: remove another test in ext4_alloc_file_blocks() Documentation: fix description of ext4's block_validity mount option ext4: fix checks for data=ordered and journal_async_commit options ...

Merge branches 'for-4.10/asus', 'for-4.10/cp2112', 'for-4.10/i2c-hid-nopower', 'for- 4.10/intel-ish', 'for-4.10/mayflash', 'for-4.10/microsoft-surface-3', 'for-4.10/multitouch', 'for- 4.10/sony', 'for-4.10/udraw-ps3', 'for-4.10/upstream' and 'for-4.10/wacom/generic' into for-linus ------

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux ------Pull s390 updates from Martin Schwidefsky: "The main bulk of the s390 patches for the 4.10 merge window:

- Add support for the contiguous memory allocator.

- The recovery for I/O errors in the dasd is improved, the driver will now remove channel paths that are not working properly.

- Additional fields are added to /proc/sysinfo, the extended partition name and the partition UUID.

- New naming for PCI devices with system defined UIDs.

- The last few remaining alloc_bootmem calls are converted to memblock.

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- The thread_info structure is stripped down and moved to the task_struct. The only field left in thread_info is the flags field.

- Rework of the arch topology code to fix a fake numa issue.

- Refactoring of the atomic primitives and add a new preempt_count implementation.

- Clocksource steering for the STP sync check offsets.

- The s390 specific headers are changed to make them usable with CLANG.

- Bug fixes and cleanup"

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux: (70 commits) s390/cpumf: Use configuration level indication for sampling data s390: provide memmove implementation s390: cleanup arch/s390/kernel Makefile s390: fix initrd corruptions with gcov/kcov instrumented kernels s390: exclude early C code from gcov profiling s390/dasd: channel path aware error recovery s390/dasd: extend dasd path handling s390: remove unused labels from entry.S s390/vmlogrdr: fix IUCV buffer allocation s390/crypto: unlock on error in prng_tdes_read() s390/sysinfo: show partition extended name and UUID if available s390/numa: pin all possible cpus to nodes early s390/numa: establish cpu to node mapping early s390/topology: use cpu_topology array instead of per cpu variable s390/smp: initialize cpu_present_mask in setup_arch s390/topology: always use s390 specific sched_domain_topology_level s390/smp: use smp_get_base_cpu() helper function s390/numa: always use logical cpu and core ids s390: Remove VLAIS in ptff() and clear_table() s390: fix machine check panic stack switch ...

Merge tag 'for-linus-4.10-rc0-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip ------Pull updates from Juergen Gross: "Xen features and fixes for 4.10

These are some fixes, a move of some arm related headers to share them between arm and arm64 and a series introducing a helper to make code more readable.

The most notable change is David stepping down as maintainer of the Xen interface. This results in me sending you the pull

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requests for Xen related code from now on"

* tag 'for-linus-4.10-rc0-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip: (29 commits) xen/balloon: Only mark a page as managed when it is released xenbus: fix deadlock on writes to /proc/xen/xenbus xen/scsifront: don't request a slot on the ring until request is ready xen/x86: Increase xen_e820_map to E820_X_MAX possible entries x86: Make E820_X_MAX unconditionally larger than E820MAX xen/pci: Bubble up error and fix description. xen: xenbus: set error code on failure xen: set error code on failures arm/xen: Use alloc_percpu rather than __alloc_percpu arm/arm64: xen: Move shared architecture headers to include/xen/arm xen/events: use xen_vcpu_id mapping for EVTCHNOP_status xen/gntdev: Use VM_MIXEDMAP instead of VM_IO to avoid NUMA balancing xen-scsifront: Add a missing call to kfree MAINTAINERS: update XEN HYPERVISOR INTERFACE xenfs: Use proc_create_mount_point() to create /proc/xen xen-platform: use builtin_pci_driver xen-netback: fix error handling output xen: make use of xenbus_read_unsigned() in xenbus xen: make use of xenbus_read_unsigned() in xen-pciback xen: make use of xenbus_read_unsigned() in xen-fbfront ...

Merge tag 'char-misc-4.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char- misc ------Pull char/misc driver updates from Greg KH: "Here's the big char/misc driver patches for 4.10-rc1. Lots of tiny changes over lots of "minor" driver subsystems, the largest being some new FPGA drivers. Other than that, a few other new drivers, but no new driver subsystems added for this kernel cycle, a nice change.

All of these have been in linux-next with no reported issues"

* tag 'char-misc-4.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (107 commits) uio-hv-generic: store physical addresses instead of virtual Tools: hv: kvp: configurable external scripts path uio-hv-generic: new userspace i/o driver for VMBus vmbus: add support for dynamic device id's hv: change clockevents unbind tactics hv: acquire vmbus_connection.channel_mutex in vmbus_free_channels() hyperv: Fix spelling of HV_UNKOWN mei: bus: enable non-blocking RX mei: fix the back to back interrupt handling mei: synchronize irq before initiating a reset.

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VME: Remove shutdown entry from vme_driver auxdisplay: ht16k33: select framebuffer helper modules MAINTAINERS: add git url for fpga fpga: Clarify how write_init works streaming modes fpga zynq: Fix incorrect ISR state on bootup fpga zynq: Remove priv->dev fpga zynq: Add missing \n to messages fpga: Add COMPILE_TEST to all drivers uio: pruss: add clk_disable() char/pcmcia: add some error checking in scr24x_read() ...

Merge tag 'staging-4.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging ------Pull staging/IIO updates from Greg KH: "Here's the "big" staging/iio pull request for 4.10-rc1.

Not as big as 4.9 was, but still just over a thousand changes. We almost broke even of lines added vs. removed, as the slicoss driver was removed (got a "clean" driver for the same hardware through the netdev tree), and some iio drivers were also dropped, but I think we ended up adding a few thousand lines to the source tree in the end. Other than that it's a lot of minor fixes all over the place, nothing major stands out at all.

All of these have been in linux-next for a while. There will be a merge conflict with Al's vfs tree in the lustre code, but the resolution for that should be pretty simple, that too has been in linux-next"

* tag 'staging-4.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (1002 commits) staging: comedi: comedidev.h: Document usage of 'detach' handler staging: fsl-mc: remove unnecessary info prints from bus driver staging: fsl-mc: add sysfs ABI doc staging/lustre/o2iblnd: Fix misspelled attemps->attempts staging/lustre/o2iblnd: Fix misspelling intialized->intialized staging/lustre: Convert all bare unsigned to unsigned int staging/lustre/socklnd: Fix whitespace problem staging/lustre/o2iblnd: Add missing space staging/lustre/lnetselftest: Fix potential integer overflow staging: greybus: audio_module: remove redundant OOM message staging: dgnc: Fix lines longer than 80 characters staging: dgnc: fix blank line after '{' warnings. staging/android: remove Sync Framework tasks from TODO staging/lustre/osc: Revert erroneous list_for_each_entry_safe use staging: slicoss: remove the staging driver staging: lustre: libcfs: remove lnet upcall code staging: lustre: remove set but unused variables

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staging: lustre: osc: set lock data for lock staging: lustre: import: don't reconnect during connect interpret staging: lustre: clio: remove mtime check in vvp_io_fault_start() ...

Merge tag 'pm-4.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm ------Pull power management updates from Rafael Wysocki: "Again, cpufreq gets more changes than the other parts this time (one new driver, one old driver less, a bunch of enhancements of the existing code, new CPU IDs, fixes, cleanups)

There also are some changes in cpuidle (idle injection rework, a couple of new CPU IDs, online/offline rework in intel_idle, fixes and cleanups), in the generic power domains framework (mostly related to supporting power domains containing CPUs), and in the Operating Performance Points (OPP) library (mostly related to supporting devices with multiple voltage regulators)

In addition to that, the system sleep state selection interface is modified to make it easier for distributions with unchanged user space to support suspend-to-idle as the default system suspend method, some issues are fixed in the PM core, the latency tolerance PM QoS framework is improved a bit, the Intel RAPL power capping driver is cleaned up and there are some fixes and cleanups in the devfreq subsystem

Specifics:

- New cpufreq driver for Broadcom STB SoCs and a Device Tree binding for it (Markus Mayer)

- Support for ARM Integrator/AP and Integrator/CP in the generic DT cpufreq driver and elimination of the old Integrator cpufreq driver (Linus Walleij)

- Support for the zx296718, r8a7743 and r8a7745, Socionext UniPhier, and PXA SoCs in the the generic DT cpufreq driver (Baoyou Xie, Geert Uytterhoeven, Masahiro Yamada, Robert Jarzmik)

- cpufreq core fix to eliminate races that may lead to using inactive policy objects and related cleanups (Rafael Wysocki)

- cpufreq schedutil governor update to make it use SCHED_FIFO kernel threads (instead of regular workqueues) for doing delayed work (to reduce the response latency in some cases) and related cleanups (Viresh Kumar)

- New cpufreq sysfs attribute for resetting statistics (Markus Mayer)

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- cpufreq governors fixes and cleanups (Chen Yu, Stratos Karafotis, Viresh Kumar)

- Support for using generic cpufreq governors in the intel_pstate driver (Rafael Wysocki)

- Support for per-logical-CPU P-state limits and the EPP/EPB (Energy Performance Preference/Energy Performance Bias) knobs in the intel_pstate driver (Srinivas Pandruvada)

- New CPU ID for Knights Mill in intel_pstate (Piotr Luc)

- intel_pstate driver modification to use the P-state selection algorithm based on CPU load on platforms with the system profile in the ACPI tables set to "mobile" (Srinivas Pandruvada)

- intel_pstate driver cleanups (Arnd Bergmann, Rafael Wysocki, Srinivas Pandruvada)

- cpufreq powernv driver updates including fast switching support (for the schedutil governor), fixes and cleanus (Akshay Adiga, Andrew Donnellan, Denis Kirjanov)

- acpi-cpufreq driver rework to switch it over to the new CPU offline/online state machine (Sebastian Andrzej Siewior)

- Assorted cleanups in cpufreq drivers (Wei Yongjun, Prashanth Prakash)

- Idle injection rework (to make it use the regular idle path instead of a home-grown custom one) and related powerclamp thermal driver updates (Peter Zijlstra, Jacob Pan, Petr Mladek, Sebastian Andrzej Siewior)

- New CPU IDs for Atom Z34xx and Knights Mill in intel_idle (Andy Shevchenko, Piotr Luc)

- intel_idle driver cleanups and switch over to using the new CPU offline/online state machine (Anna-Maria Gleixner, Sebastian Andrzej Siewior)

- cpuidle DT driver update to support suspend-to-idle properly (Sudeep Holla)

- cpuidle core cleanups and misc updates (Daniel Lezcano, Pan Bian, Rafael Wysocki)

- Preliminary support for power domains including CPUs in the generic power domains (genpd) framework and related DT bindings (Lina Iyer)

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- Assorted fixes and cleanups in the generic power domains (genpd) framework (Colin Ian King, Dan Carpenter, Geert Uytterhoeven)

- Preliminary support for devices with multiple voltage regulators and related fixes and cleanups in the Operating Performance Points (OPP) library (Viresh Kumar, Masahiro Yamada, Stephen Boyd)

- System sleep state selection interface rework to make it easier to support suspend-to-idle as the default system suspend method (Rafael Wysocki)

- PM core fixes and cleanups, mostly related to the interactions between the system suspend and runtime PM frameworks (Ulf Hansson, Sahitya Tummala, Tony Lindgren)

- Latency tolerance PM QoS framework imorovements (Andrew Lutomirski)

- New Knights Mill CPU ID for the Intel RAPL power capping driver (Piotr Luc)

- Intel RAPL power capping driver fixes, cleanups and switch over to using the new CPU offline/online state machine (Jacob Pan, Thomas Gleixner, Sebastian Andrzej Siewior)

- Fixes and cleanups in the exynos-ppmu, exynos-nocp, rk3399_dmc, rockchip-dfi devfreq drivers and the devfreq core (Axel Lin, Chanwoo Choi, Javier Martinez Canillas, MyungJoo Ham, Viresh Kumar)

- Fix for false-positive KASAN warnings during resume from ACPI S3 (suspend-to-RAM) on x86 (Josh Poimboeuf)

- Memory map verification during resume from hibernation on x86 to ensure a consistent address space layout (Chen Yu)

- Wakeup sources debugging enhancement (Xing Wei)

- rockchip-io AVS driver cleanup (Shawn Lin)"

* tag 'pm-4.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (127 commits) devfreq: rk3399_dmc: Don't use OPP structures outside of RCU locks devfreq: rk3399_dmc: Remove dangling rcu_read_unlock() devfreq: exynos: Don't use OPP structures outside of RCU locks Documentation: intel_pstate: Document HWP energy/performance hints cpufreq: intel_pstate: Support for energy performance hints with HWP cpufreq: intel_pstate: Add locking around HWP requests PM / sleep: Print active wakeup sources when blocking on wakeup_count reads PM / core: Fix bug in the error handling of async suspend PM / wakeirq: Fix dedicated wakeirq for drivers not using autosuspend

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PM / Domains: Fix compatible for domain idle state PM / OPP: Don't WARN on multiple calls to dev_pm_opp_set_regulators() PM / OPP: Allow platform specific custom set_opp() callbacks PM / OPP: Separate out _generic_set_opp() PM / OPP: Add infrastructure to manage multiple regulators PM / OPP: Pass struct dev_pm_opp_supply to _set_opp_voltage() PM / OPP: Manage supply's voltage/current in a separate structure PM / OPP: Don't use OPP structure outside of rcu protected section PM / OPP: Reword binding supporting multiple regulators per device PM / OPP: Fix incorrect cpu-supply property in binding cpuidle: Add a kerneldoc comment to cpuidle_use_deepest_state() ..

Merge branch 'for-4.10/block' of git://git.kernel.dk/linux-block ------Pull block layer updates from Jens Axboe: "This is the main block pull request this series. Contrary to previous release, I've kept the core and driver changes in the same branch. We always ended up having dependencies between the two for obvious reasons, so makes more sense to keep them together. That said, I'll probably try and keep more topical branches going forward, especially for cycles that end up being as busy as this one.

The major parts of this pull request is:

- Improved support for O_DIRECT on block devices, with a small private implementation instead of using the pig that is fs/direct-io.c. From Christoph.

- Request completion tracking in a scalable fashion. This is utilized by two components in this pull, the new hybrid polling and the writeback queue throttling code.

- Improved support for polling with O_DIRECT, adding a hybrid mode that combines pure polling with an initial sleep. From me.

- Support for automatic throttling of writeback queues on the block side. This uses feedback from the device completion latencies to scale the queue on the block side up or down. From me.

- Support from SMR drives in the block layer and for SD. From Hannes and Shaun.

- Multi-connection support for nbd. From Josef.

- Cleanup of request and bio flags, so we have a clear split between which are bio (or rq) private, and which ones are shared. From Christoph.

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- A set of patches from Bart, that improve how we handle queue stopping and starting in blk-mq.

- Support for WRITE_ZEROES from Chaitanya.

- Lightnvm updates from Javier/Matias.

- Supoort for FC for the nvme-over-fabrics code. From James Smart.

- A bunch of fixes from a whole slew of people, too many to name here"

* 'for-4.10/block' of git://git.kernel.dk/linux-block: (182 commits) blk-stat: fix a few cases of missing batch flushing blk-flush: run the queue when inserting blk-mq flush elevator: make the rqhash helpers exported blk-mq: abstract out blk_mq_dispatch_rq_list() helper blk-mq: add blk_mq_start_stopped_hw_queue() block: improve handling of the magic discard payload blk-wbt: don't throttle discard or write zeroes nbd: use dev_err_ratelimited in io path nbd: reset the setup task for NBD_CLEAR_SOCK nvme-fabrics: Add FC LLDD loopback driver to test FC-NVME nvme-fabrics: Add target support for FC transport nvme-fabrics: Add host support for FC transport nvme-fabrics: Add FC transport LLDD api definitions nvme-fabrics: Add FC transport FC-NVME definitions nvme-fabrics: Add FC transport error codes to nvme.h Add type 0x28 NVME type code to scsi fc headers nvme-fabrics: patch target code in prep for FC transport support nvme-fabrics: set sqe.command_id in core not transports parser: add u64 number parser nvme-rdma: align to generic ib_event logging helper ...

Merge tag 'drm-for-v4.10' of git://people.freedesktop.org/~airlied/linux ------Pull drm updates from Dave Airlie: "This is the main pull request for drm for 4.10 kernel.

New drivers: - ZTE VOU display driver (zxdrm) - Amlogic Meson Graphic Controller GXBB/GXL/GXM SoCs (meson) - MXSFB support (mxsfb)

Core: - Format handling has been reworked - Better atomic state debugging - drm_mm leak debugging

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- Atomic explicit fencing support - fbdev helper ops - Documentation updates - MST fbcon fixes

Bridge: - Silicon Image SiI8620 driver

Panel: - Add support for new simple panels

i915: - GVT Device model - Better HDMI2.0 support on skylake - More watermark fixes - GPU idling rework for suspend/resume - DP Audio workarounds - Scheduler prep-work - Opregion CADL handling - GPU scheduler and priority boosting

amdgfx/radeon: - Support for virtual devices - New VM manager for non-contig VRAM buffers - UVD powergating - SI register header cleanup - Cursor fixes - Powermanagement fixes

nouveau: - Powermangement reworks for better voltage/clock changes - Atomic modesetting support - Displayport Multistream (MST) support. - GP102/104 hang and cursor fixes - GP106 support

hisilicon: - hibmc support (BMC chip for aarch64 servers)

armada: - add support for overlay change - refactor plane support - de-midlayer the driver

omapdrm: - Timing code cleanups

rcar-du: - R8A7792/R8A7796 support - Misc fixes.

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sunxi: - A31 SoC display engine support

imx-drm: - YUV format support - Cleanup plane atomic update

mali-dp: - Misc fixes

dw-hdmi: - Add support for HDMI i2c master controller

tegra: - IOMMU support fixes - Error handling fixes

tda998x: - Fix connector registration - Improved robustness - Fix infoframe/audio compliance

virtio: - fix busid issues - allocate more vbufs

qxl: - misc fixes and cleanups.

vc4: - Fragment shader threading - ETC1 support - VEC (tv-out) support

msm: - A5XX GPU support - Lots of atomic changes

tilcdc: - Misc fixes and cleanups.

etnaviv: - Fix dma-buf export path - DRAW_INSTANCED support - fix driver on i.MX6SX

exynos: - HDMI refactoring

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fsl-dcu: - fbdev changes"

* tag 'drm-for-v4.10' of git://people.freedesktop.org/~airlied/linux: (1343 commits) drm/nouveau/kms/nv50: fix atomic regression on original G80 drm/nouveau/bl: Do not register interface if Apple GMUX detected drm/nouveau/bl: Assign different names to interfaces drm/nouveau/bios/dp: fix handling of LevelEntryTableIndex on DP table 4.2 drm/nouveau/ltc: protect clearing of comptags with mutex drm/nouveau/gr/gf100-: handle GPC/TPC/MPC trap drm/nouveau/core: recognise GP106 chipset drm/nouveau/ttm: wait for bo fence to signal before unmapping vmas drm/nouveau/gr/gf100-: FECS intr handling is not relevant on proprietary ucode drm/nouveau/gr/gf100-: properly ack all FECS error interrupts drm/nouveau/fifo/gf100-: recover from host mmu faults drm: Add fake controlD* symlinks for backwards compat drm/vc4: Don't use drm_put_dev drm/vc4: Document VEC DT binding drm/vc4: Add support for the VEC (Video Encoder) IP drm: Add TV connector states to drm_connector_state drm: Turn DRM_MODE_SUBCONNECTOR_xx definitions into an enum drm/vc4: Fix ->clock_select setting for the VEC encoder drm/amdgpu/dce6: Set MASTER_UPDATE_MODE to 0 in resume_mc_access as well drm/amdgpu: use pin rather than pin_restricted in a few cases ...

Merge tag 'fbdev-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux ------Pull fbdev update from Tomi Valkeinen: "No one has stepped up to take the job, so I've marked fbdev as orphan"

* tag 'fbdev-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux: fbdev: remove current maintainer

Merge tag 'vfio-v4.10-rc1' of git://github.com/awilliam/linux-vfio ------Pull VFIO updates from Alex Williamson:

- VFIO updates for v4.10 primarily include a new Mediated Device interface, which essentially allows software defined devices to be exposed to users through VFIO. The host vendor driver providing this virtual device polices, or mediates user access to the device.

These devices often incorporate portions of real devices, for instance the primary initial users of this interface expose vGPUs which allow the user to map mediated devices, or mdevs, to a portion of a physical GPU. QEMU composes these mdevs into PCI representations using the existing VFIO user API. This enables both Intel KVM-GT

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support, which is also expected to arrive into Linux mainline during the v4.10 merge window, as well as NVIDIA vGPU, and also Channel I/O devices (aka CCW devices) for s390 virtualization support. (Kirti Wankhede, Neo Jia)

- Drop unnecessary uses of pcibios_err_to_errno() (Cao Jin)

- Fixes to VFIO capability chain handling (Eric Auger)

- Error handling fixes for fallout from mdev (Christophe JAILLET)

- Notifiers to expose struct kvm to mdev vendor drivers (Jike Song)

- type1 IOMMU model search fixes (Kirti Wankhede, Neo Jia)

* tag 'vfio-v4.10-rc1' of git://github.com/awilliam/linux-vfio: (30 commits) vfio iommu type1: Fix size argument to vfio_find_dma() in pin_pages/unpin_pages vfio iommu type1: Fix size argument to vfio_find_dma() during DMA UNMAP. vfio iommu type1: WARN_ON if notifier block is not unregistered kvm: set/clear kvm to/from vfio_group when group add/delete vfio: support notifier chain in vfio_group vfio: vfio_register_notifier: classify iommu notifier vfio: Fix handling of error returned by 'vfio_group_get_from_dev()' vfio: fix vfio_info_cap_add/shift vfio/pci: Drop unnecessary pcibios_err_to_errno() MAINTAINERS: Add entry VFIO based Mediated device drivers docs: Sample driver to demonstrate how to use Mediated device framework. docs: Sysfs ABI for mediated device framework docs: Add Documentation for Mediated devices vfio: Define device_api strings vfio_platform: Updated to use vfio_set_irqs_validate_and_prepare() vfio_pci: Updated to use vfio_set_irqs_validate_and_prepare() vfio: Introduce vfio_set_irqs_validate_and_prepare() vfio_pci: Update vfio_pci to use vfio_info_add_capability() vfio: Introduce common function to add capabilities vfio iommu: Add blocking notifier to notify DMA_UNMAP ...

Merge tag 'gcc-plugins-v4.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux ------Pull gcc plugins updates from Kees Cook: "Minor changes to the gcc plugins:

- add the gcc plugins Makefile to MAINTAINERS to route things correctly

- hide cyc_complexity behind !CONFIG_TEST for the future unhiding of plugins generally"

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* tag 'gcc-plugins-v4.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux: gcc-plugins: Adjust Kconfig to avoid cyc_complexity MAINTAINERS: add GCC plugins Makefile

Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux ------Pull thermal management updates from Zhang Rui:

- Thermal core code reorganization and cleanup. Two new files are created for thermal sysfs I/F code and thermal helper functions (Eduardo Valentin).

- Sanitize hotplug and locking for x86_pkg_temp driver (Thomas Gleixner)

- Update MAINTAINER file for pwm-fan driver and Samsung thermal driver (Lukasz Majewski)

- Fix module auto-load for max77620, tango and db8500 thermal driver (Javier Martinez Canillas)

- Fix a bug that thermal hwmon sysfs I/F returns wrong critical trip point temperature value (Krzysztof Kozlowski)

- Add Skylake PCH 100 series support for intel_pch_thermal driver (OGAWA Hirofumi)

- Small fixes and cleanups for platform thermal drivers (Julia Lawall, Luis Henriques, Leo Yan, Stephen Boyd, Shawn Lin, Javi Merino and Lukasz Luba)

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux: (76 commits) MAINTAINERS: Samsung: Update maintainer for PWM FAN and SAMSUNG THERMAL thermal/x86 pkg temp: Convert to hotplug state machine thermal/x86_pkg_temp: Sanitize package management thermal/x86_pkg_temp: Move work into package struct thermal/x86_pkg_temp: Move work scheduled flag into package struct thermal/x86_pkg_temp: Sanitize locking thermal/x86_pkg_temp: Cleanup code some more thermal/x86_pkg_temp: Cleanup namespace thermal/x86_pkg_temp: Get rid of ref counting thermal/x86_pkg_temp: Sanitize callback (de)initialization thermal/x86_pkg_temp: Replace open coded cpu search thermal/x86_pkg_temp: Remove redundant package search thermal/x86_pkg_temp: Cleanup thermal interrupt handling thermal: hwmon: Properly report critical temperature in sysfs devfreq_cooling: pass a pointer to devfreq in the power model callbacks devfreq_cooling: make the structs devfreq_cooling_xxx visible for all

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dt-bindings: rockchip-thermal: fix the misleading description thermal: rockchip: improve the warning log thermal: db8500: Fix module autoload thermal: tango: Fix module autoload ...

Merge tag 'rproc-v4.10' of git://github.com/andersson/remoteproc ------Pull remoteproc updates from Bjorn Andersson:

- introduce remoteproc "subdevice" support, which allows remoteproc driver to associate devices to the "running" state of the remoteproc, allowing devices to be probed and removed as the remote processor is booted, shut down or recovering from a crash.

- handling of virtio device resources was improved, vring memory is now allocated as part of other memory allocation. This ensures that all vrings for all virtio devices are allocated before we boot the remote processor.

- the debugfs mechanism for starting and stopping remoteproc instances was replaced with a sysfs interface, also providing a mechanism for specifying firmware to use by the instance. This allows user space to load and boot use case specific firmware on remote processors.

- new drivers for the ST Slimcore and Qualcomm Hexagon DSP as well as removal of the unused StE modem loader.

- finally support for crash recovery in the Qualcomm Wirelss subsystem (used for WiFi/BT/FM on a number of platforms) and a number of bug fixes and cleanups

* tag 'rproc-v4.10' of git://github.com/andersson/remoteproc: (49 commits) remoteproc: qcom_adsp_pil: select qcom_scm remoteproc: Drop wait in __rproc_boot() remoteproc/ste: Delete unused driver remoteproc: Remove "experimental" warning remoteproc: qcom_adsp_pil: select qcom_scm dt-binding: soc: qcom: smd: Add label property remoteproc: qcom: mdt_loader: add include for sizes remoteproc: Update last rproc_put users to rproc_free remoteproc: qcom: adsp: Add missing MODULE_DEVICE_TABLE remoteproc: wcnss-pil: add QCOM_SMD dependency dmaengine: st_fdma: Revert: "Revert: Update st_fdma to 'depends on REMOTEPROC'" remoteproc: Add support for xo clock remoteproc: adsp-pil: fix recursive dependency remoteproc: Introduce Qualcomm ADSP PIL dt-binding: remoteproc: Introduce ADSP loader binding remoteproc: qcom_wcnss: Fix circular module dependency

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remoteproc: Merge table_ptr and cached_table pointers remoteproc: Remove custom vdev handler list remoteproc: Update max_notifyid as we allocate vrings remoteproc: Decouple vdev resources and devices ...

Merge tag 'mmc-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc ------Pull MMC updates from Ulf Hansson: "It's been an busy period for mmc. Quite some changes in the mmc core, two new mmc host drivers, some existing drivers being extended to support new IP versions and lots of other updates.

MMC core: - Delete eMMC packed command support - Introduce mmc_abort_tuning() to enable eMMC tuning to fail gracefully - Introduce mmc_can_retune() to see if a host can be retuned - Re-work and improve the sequence when sending a CMD6 for mmc - Enable CDM13 polling when switching to HS and HS DDR mode for mmc - Relax checking for CMD6 errors after switch to HS200 - Re-factoring the code dealing with the mmc block queue - Recognize whether the eMMC card supports CMDQ - Fix 4K native sector check - Don't power off the card when starting the host - Increase MMC_IOC_MAX_BYTES to support bigger firmware binaries - Improve error handling and drop meaningless BUG_ONs() - Lots of clean-ups and changes to improve the quality of the code

MMC host: - sdhci: Fix tuning sequence and clean-up the related code - sdhci: Add support to via DT override broken SDHCI cap register bits - sdhci-cadence: Add new driver for Cadence SD4HC SDHCI variant - sdhci-msm: Update clock management - sdhci-msm: Add support for eMMC HS400 mode - sdhci-msm: Deploy runtime/system PM support - sdhci-iproc: Extend driver support to newer IP versions - sdhci-pci: Add support for Intel GLK - sdhci-pci: Add support for Intel NI byt sdio - sdhci-acpi: Add support for 80860F14 UID 2 SDIO bus - sdhci: Lots of various small improvements and clean-ups - tmio: Add support for tuning - sh_mobile_sdhi: Add support for tuning - sh_mobile_sdhi: Extend driver to support SDHI IP on R7S72100 SoC - sh_mobile_sdhi: remove support for sh7372 - davinci: Use mmc_of_parse() to enable generic mmc DT bindings - meson: Add new driver to support GX platforms - dw_mmc: Deploy generic runtime/system PM support

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- dw_mmc: Lots of various small improvements

As a part of the mmc changes this time, I have also pulled in an immutable branch/tag (soc-device-match-tag1) hosted by Geert Uytterhoeven, to share the implementation of the new soc_device_match() interface. This is needed by these mmc related changes:

- mmc: sdhci-of-esdhc: Get correct IP version for T4240-R1.0-R2.0 - soc: fsl: add GUTS driver for QorIQ platforms"

* tag 'mmc-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (136 commits) mmc: sdhci-cadence: add Cadence SD4HC support mmc: sdhci: export sdhci_execute_tuning() mmc: sdhci: Tidy tuning loop mmc: sdhci: Simplify tuning block size logic mmc: sdhci: Factor out tuning helper functions mmc: sdhci: Use mmc_abort_tuning() mmc: mmc: Introduce mmc_abort_tuning() mmc: sdhci: Always allow tuning to fall back to fixed sampling mmc: sdhci: Fix tuning reset after exhausting the maximum number of loops mmc: sdhci: Fix recovery from tuning timeout Revert "mmc: sdhci: Reset cmd and data circuits after tuning failure" mmc: mmc: Relax checking for switch errors after HS200 switch mmc: sdhci-acpi: support 80860F14 UID 2 SDIO bus mmc: sdhci-of-at91: remove bogus MMC_SDHCI_IO_ACCESSORS select mmc: sdhci-pci: Use ACPI to get max frequency for Intel NI byt sdio mmc: sdhci-pci: Add PCI ID for Intel NI byt sdio mmc: sdhci-s3c: add spin_unlock_irq() before calling clk_round_rate mmc: dw_mmc: display the clock message only one time when card is polling mmc: dw_mmc: add the debug message for polling and non-removable mmc: dw_mmc: check the "present" variable before checking flags ...

Merge tag 'regulator-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator ------Pull regulator updates from Mark Brown: "A quiet release for the regulator API, conference season must've been slowing everyone down:

- a new interface allowing drivers to provide an interface for reading a more detailed description of error conditions which allows devices using these regulators to build

- ACPI support for the fixed voltage regulator.

- cleanups for the TI TWL drivers to reduce code duplication"

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* tag 'regulator-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator: (24 commits) regulator: tps65086: Fix 25mV ranges for BUCK regulators 1, 2, and 6 regulator: Fix regulator_get_error_flags() signature mismatch regulator: core: add newline in debug message regulator: tps65086: Fix 25mV ranges for BUCK regulators regulator: core: Correct type of mode in regulator_mode_constrain regulator: max77620: add documentation for MPOK property regulator: max77620: add support to configure MPOK regulator: twl6030: Remove unused fields from struct twlreg_info regulator: twl: Remove unused fields from struct twlreg_info regulator: twl: split twl6030 logic into its own file regulator: twl: kill unused functions regulator: twl: make driver DT only regulator: twl-regulator: rework fixed regulator definition regulator: max77620: remove unused variable regulator: pwm: Add missing quotes to DT example regulator: stw481x-vmmc: fix ages old enable error regulator: gpio: properly check return value of of_get_named_gpio regulator: lp873x: Add support for populating input supply regulator: axp20x: Fix axp809 ldo_io registration error on cold boot regulators: helpers: Fix handling of bypass_val_on in get_bypass_regmap ...

Merge tag 'docs-4.10' of git://git.lwn.net/linux ------Pull documentation update from Jonathan Corbet: "These are the documentation changes for 4.10.

It's another busy cycle for the docs tree, as the sphinx conversion continues. Highlights include:

- Further work on PDF output, which remains a bit of a pain but should be more solid now.

- Five more DocBook template files converted to Sphinx. Only 27 to go... Lots of plain-text files have also been converted and integrated.

- Images in binary formats have been replaced with more source-friendly versions.

- Various bits of organizational work, including the renaming of various files discussed at the kernel summit.

- New documentation for the device_link mechanism.

... and, of course, lots of typo fixes and small updates"

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* tag 'docs-4.10' of git://git.lwn.net/linux: (193 commits) dma-buf: Extract dma-buf.rst Update Documentation/00-INDEX docs: 00-INDEX: document directories/files with no docs docs: 00-INDEX: remove non-existing entries docs: 00-INDEX: add missing entries for documentation files/dirs docs: 00-INDEX: consolidate / and admin-guide/ description scripts: add a script to check if Documentation/00-INDEX is sane Docs: change sh -> awk in REPORTING-BUGS Documentation/core-api/device_link: Add initial documentation core-api: remove an unexpected unident ppc/idle: Add documentation for powersave=off Doc: Correct typo, "Introdution" => "Introduction" Documentation/atomic_ops.txt: convert to ReST markup Documentation/local_ops.txt: convert to ReST markup Documentation/assoc_array.txt: convert to ReST markup docs-rst: parse-headers.pl: cleanup the documentation docs-rst: fix media cleandocs target docs-rst: media/Makefile: reorganize the rules docs-rst: media: build SVG from graphviz files docs-rst: replace bayer.png by a SVG image ...

Merge branch 'akpm' (patches from Andrew) ------Merge updates from Andrew Morton:

- various misc bits

- most of MM (quite a lot of MM material is awaiting the merge of linux-next dependencies)

- kasan

- printk updates

- procfs updates

- MAINTAINERS

- /lib updates

- checkpatch updates

* emailed patches from Andrew Morton : (123 commits) init: reduce rootwait polling interval time to 5ms binfmt_elf: use vmalloc() for allocation of vma_filesz checkpatch: don't emit unified-diff error for rename-only patches checkpatch: don't check c99 types like uint8_t under tools

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checkpatch: avoid multiple line dereferences checkpatch: don't check .pl files, improve absolute path commit log test scripts/checkpatch.pl: fix spelling checkpatch: don't try to get maintained status when --no-tree is given lib/ida: document locking requirements a bit better lib/rbtree.c: fix typo in comment of ____rb_erase_color lib/Kconfig.debug: make CONFIG_STRICT_DEVMEM depend on CONFIG_DEVMEM MAINTAINERS: add drm and drm/i915 irc channels MAINTAINERS: add "C:" for URI for chat where developers hang out MAINTAINERS: add drm and drm/i915 bug filing info MAINTAINERS: add "B:" for URI where to file bugs get_maintainer: look for arbitrary letter prefixes in sections printk: add Kconfig option to set default console loglevel printk/sound: handle more message headers printk/: handle more message headers printk/kdb: handle more message headers ...

MAINTAINERS: Samsung: Update maintainer for PWM FAN and SAMSUNG THERMAL ------Since I leave Samsung, I would like to step down from maintenance duties. Bartek Zolnierkiewicz will replace.

MAINTAINERS: add drm and drm/i915 irc channels ------Link: http://lkml.kernel.org/r/[email protected]

MAINTAINERS: add "C:" for URI for chat where developers hang out ------Make it easier to find the developer chat for the subsystem or driver.

Link: http://lkml.kernel.org/r/[email protected]

MAINTAINERS: add drm and drm/i915 bug filing info ------Link: http://lkml.kernel.org/r/[email protected]

MAINTAINERS: add "B:" for URI where to file bugs ------Different subsystems and drivers have different preferences for where to file bugs and what information to include. Add "B:" entry for specifying the URI for the bug tracker directly, a web page for detailed info on filing bugs, or a mailto: URI.

Link: http://lkml.kernel.org/r/[email protected]

Merge branch 'x86-idle-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip ------

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Pull x86 idle updates from Ingo Molnar: "There were two bigger changes in this development cycle:

- remove idle notifiers:

32 files changed, 74 insertions(+), 803 deletions(-)

These notifiers were of questionable value and the main usecase, the i7300 driver, was essentially unmaintained and can be removed, plus modern power management concepts don't need the callback - so use this golden opportunity and get rid of this opaque and fragile callback from a latency sensitive code path.

(Len Brown, Thomas Gleixner)

- improve the AMD Erratum 400 workaround that used high overhead MSR polling in the idle loop (Borisla Petkov, Thomas Gleixner)"

* 'x86-idle-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86: Remove empty idle.h header x86/amd: Simplify AMD E400 aware idle routine x86/amd: Check for the C1E bug post ACPI subsystem init x86/bugs: Separate AMD E400 erratum and C1E bug x86/cpufeature: Provide helper to set bugs bits x86/idle: Remove enter_idle(), exit_idle() x86: Remove x86_test_and_clear_bit_percpu() x86/idle: Remove is_idle flag x86/idle: Remove idle_notifier i7300_idle: Remove this driver

Merge branch 'pm-cpuidle' ------* pm-cpuidle: cpuidle: Add a kerneldoc comment to cpuidle_use_deepest_state() cpuidle: fix improper return value on error intel_idle: Convert to hotplug state machine intel_idle: Remove superfluous SMP fuction call MAINTAINERS: Add Jacob Pan as a new intel_idle maintainer MAINTAINERS: Add bug tracking system location entries for cpuidle x86/intel_idle: Add Knights Mill CPUID x86/intel_idle: Add CPU model 0x4a (Atom Z34xx series) thermal/intel_powerclamp: stop sched tick in forced idle thermal/intel_powerclamp: Convert to CPU hotplug state thermal/intel_powerclamp: Convert the kthread to kthread worker API thermal/intel_powerclamp: Remove duplicated code that starts the kthread sched/idle: Add support for tasks that inject idle cpuidle: Allow enforcing deepest idle state selection cpuidle/powernv: staticise powernv_idle_driver cpuidle: dt: assign ->enter_freeze to same as ->enter callback function

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cpuidle: governors: Remove remaining old module code

Merge branch 'pm-cpufreq' ------* pm-cpufreq: (51 commits) Documentation: intel_pstate: Document HWP energy/performance hints cpufreq: intel_pstate: Support for energy performance hints with HWP cpufreq: intel_pstate: Add locking around HWP requests cpufreq: ondemand: Set MIN_FREQUENCY_UP_THRESHOLD to 1 cpufreq: intel_pstate: Add Knights Mill CPUID MAINTAINERS: Add bug tracking system location entry for cpufreq cpufreq: dt: Add support for zx296718 cpufreq: acpi-cpufreq: drop rdmsr_on_cpus() usage cpufreq: acpi-cpufreq: Convert to hotplug state machine cpufreq: intel_pstate: fix intel_pstate_exit_perf_limits() prototype cpufreq: intel_pstate: Set EPP/EPB to 0 in performance mode cpufreq: schedutil: Rectify comment in sugov_irq_work() function cpufreq: intel_pstate: increase precision of performance limits cpufreq: intel_pstate: round up min_perf limits cpufreq: Make cpufreq_update_policy() void ACPI / processor: Make acpi_processor_ppc_has_changed() void cpufreq: Avoid using inactive policies cpufreq: intel_pstate: Generic governors support cpufreq: intel_pstate: Request P-states control from SMM if needed cpufreq: dt: Add support for r8a7743 and r8a7745 ...

Merge schedutil governor updates for v4.10. ------

Merge branch 'efi-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip ------Pull EFI updates from Ingo Molnar: "The main changes in this development cycle were:

- Implement EFI dev path parser and other changes to fully support thunderbolt devices on Apple Macbooks (Lukas Wunner)

- Add RNG seeding via the EFI stub, on ARM/arm64 (Ard Biesheuvel)

- Expose EFI framebuffer configuration to user-space, to improve tooling (Peter Jones)

- Misc fixes and cleanups (Ivan Hu, Wei Yongjun, Yisheng Xie, Dan Carpenter, Roy Franz)"

* 'efi-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:

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efi/libstub: Make efi_random_alloc() allocate below 4 GB on 32-bit thunderbolt: Compile on x86 only thunderbolt, efi: Fix Kconfig dependencies harder thunderbolt, efi: Fix Kconfig dependencies thunderbolt: Use Device ROM retrieved from EFI x86/efi: Retrieve and assign Apple device properties efi: Allow bitness-agnostic protocol calls efi: Add device path parser efi/arm*/libstub: Invoke EFI_RNG_PROTOCOL to seed the UEFI RNG table efi/libstub: Add random.c to ARM build efi: Add support for seeding the RNG from a UEFI config table MAINTAINERS: Add ARM and arm64 EFI specific files to EFI subsystem efi/libstub: Fix allocation size calculations efi/efivar_ssdt_load: Don't return success on allocation failure efifb: Show framebuffer layout as device attributes efi/efi_test: Use memdup_user() as a cleanup efi/efi_test: Fix uninitialized variable 'rv' efi/efi_test: Fix uninitialized variable 'datasize' efi/arm*: Fix efi_init() error handling efi: Remove unused include of

Merge tag 'openrisc-for-linus' of git://github.com/openrisc/linux ------Pull Openrisc updates from Stafford Horne:

- changes to MAINTAINER for openrisc

- probably biggest actual change is the move to memblock from bootmem

- ... plus several bug and build fixes

* tag 'openrisc-for-linus' of git://github.com/openrisc/linux: openrisc: prevent VGA console, fix builds openrisc: include l.swa in check for write data pagefault openrisc: Updates after openrisc.net has been lost openrisc: Consolidate setup to use memblock instead of bootmem openrisc: remove the redundant of_platform_populate openrisc: add NR_CPUS Kconfig default value openrisc: Support both old (or32) and new (or1k) toolchain openrisc: Add -local storage (TLS) support openrisc: restore all regs on rt_sigreturn openrisc: fix PTRS_PER_PGD define

Merge remote-tracking branches 'asoc/topic/ab8500', 'asoc/topic/arizona', 'asoc/topic/atmel', 'asoc/topic/bcm' and 'asoc/topic/bitfield' into asoc-next ------

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openrisc: Updates after openrisc.net has been lost ------The openrisc.net domain expired and was taken over by squatters. These updates point documentation to the new domain, mailing lists and git repos.

Also, Jonas is not the main maintainer anylonger, he reviews changes but does not maintain a repo or sent pull requests. Updating this to add Stafford and Stefan who are the active maintainers.

Merge remote-tracking branches 'regulator/topic/tps65086' and 'regulator/topic/twl' into regulator-next ------

MAINTAINERS: fscrypto: recommend linux-fsdevel for fscrypto patches ------The filesystem level encryption support, currently used by ext4 and and proposed for ubifs, does not yet have a dedicated mailing list. Since no mailing lists were specified in MAINTAINERS, get_maintainer.pl only recommended to send patches directly to the maintainers and to linux-kernel. This patch adds linux-fsdevel as the preferred mailing list for fscrypto patches for the time being.

fbdev: remove current maintainer ------Remove Tomi Valkeinen from fbdev maintainer and mark fbdev as orphan.

Merge tag 'meson-drm-for-4.10' of github.com:superna9999/linux into drm-next ------Add support for the Amlogic Meson Video Processing Unit - Only CVBS/Composite output for Amlogic Meson GXBB/GXL/GXM SoCs - Add MAINTAINERS entry - Add DT bindings documentation

* tag 'meson-drm-for-4.10' of github.com:superna9999/linux: MAINTAINERS: add entry for Amlogic DRM drivers dt-bindings: display: add Amlogic Meson DRM Bindings drm: Add support for Amlogic Meson Graphic Controller

staging: slicoss: remove the staging driver ------A "real" driver for this hardware has now landed in the networking tree, so remove this old staging driver so that we don't have multiple drivers for the same hardware, and so people don't waste their time trying to clean up this old code.

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MAINTAINERS: add entry for slicoss ethernet driver ------Add myself as maintainer for the slicoss ethernet driver.

nvme-fabrics: Add FC LLDD loopback driver to test FC-NVME ------Add FC LLDD loopback driver to test FC host and target transport within nvme-fabrics

To aid in the development and testing of the lower-level api of the FC transport, this loopback driver has been created to act as if it were a FC hba driver supporting both the host interfaces as well as the target interfaces with the nvme FC transport.

uio-hv-generic: new userspace i/o driver for VMBus ------This is a new driver to enable userspace networking on VMBus. It is based largely on the similar driver that already exists for PCI, and earlier work done by Brocade to support DPDK.

MAINTAINERS: add entry for Amlogic DRM drivers ------Add myself as maintainer for Amlogic DRM drivers.

nvme-fabrics: Add target support for FC transport ------Implements the FC-NVME T11 definition of how nvme fabric capsules are performed on an FC fabric. Utilizes a lower-layer API to FC host adapters to send/receive FC-4 LS operations and perform the FCP transactions necessary to perform and FCP IO request for NVME.

The T11 definitions for FC-4 Link Services are implemented which create NVMeOF connections. Implements the hooks with nvmet layer to pass NVME commands to it for processing and posting of data/response base to the host via the different connections.

nvme-fabrics: Add host support for FC transport ------Implements the FC-NVME T11 definition of how nvme fabric capsules are performed on an FC fabric. Utilizes a lower-layer API to FC host adapters to send/receive FC-4 LS operations and FCP operations that comprise NVME over FC operation.

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The T11 definitions for FC-4 Link Services are implemented which create NVMeOF connections. Implements the hooks with blk-mq to then submit admin and io requests to the different connections.

nvme-fabrics: Add FC transport LLDD api definitions ------Host: - LLDD registration with the host transport - registering host ports (local ports) and target ports seen on fabric (remote ports) - Data structures and call points for FC-4 LS's and FCP IO requests

Target: - LLDD registration with the target transport - registering nvme subsystem ports (target ports) - Data structures and call points for reception of FC-4 LS's and FCP IO requests, and callbacks to perform data and rsp transfers for the io.

Add to MAINTAINERS file

nvme-fabrics: Add FC transport FC-NVME definitions ------Formats for Cmd, Data, Rsp IUs - Formats FC-4 LS definitions - Add to MAINTAINERS file

drm: Add new driver for MXSFB controller ------Add new driver for the MXSFB controller found in i.MX23/28/6SX . The MXSFB controller is a simple framebuffer controller with one parallel LCD output. Unlike the MXSFB fbdev driver that is used on these systems now, this driver uses the DRM/KMS framework.

Merge branch 'drm-etnaviv-next' of git://git.pengutronix.de/lst/linux into drm-next ------fix dma-buf export path to return correct SG table - trivially implement direct dma-buf mapping - allow DRAW_INSTANCED commands in validator - make the driver work on i.MX6SX, yielding a working 2D/3D stack together with Mareks MXS DRM driver

* 'drm-etnaviv-next' of git://git.pengutronix.de/lst/linux: MAINTAINERS: add etnaviv mailinglist drm/etnaviv: move linear window on MC1.0 parts if necessary drm/etnaviv: don't invoke OOM killer from dump code

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drm/etnaviv: fix gem_prime_get_sg_table to return new SG table drm/etnaviv: Allow DRAW_INSTANCED commands drm/etnaviv: implement dma-buf mmap

Merge branch 'for-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next ------Johan Hedberg says:

======pull request: bluetooth-next 2016-12-03

Here's a set of Bluetooth & 802.15.4 patches for net-next (i.e. 4.10 kernel):

- Fix for a potential NULL deref in the ieee802154 code - Fix for the ED values of the at86rf2xx driver - Documentation updates to ieee802154 - Cleanups to u8 vs __u8 usage - Timer API usage cleanups in HCI drivers

Please let me know if there are any issues pulling. Thanks. ======

Backmerge tag 'v4.9-rc8' into drm-next ------Linux 4.9-rc8

Daniel requested this so we could apply some follow on fixes cleanly to -next.

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net ------Couple conflicts resolved here:

1) In the MACB driver, a bug fix to properly initialize the RX tail pointer properly overlapped with some changes to support variable sized rings.

2) In XGBE we had a "CONFIG_PM" --> "CONFIG_PM_SLEEP" fix overlapping with a reorganization of the driver to support ACPI, OF, as well as PCI variants of the chip.

3) In 'net' we had several probe error path bug fixes to the stmmac driver, meanwhile a lot of this code was cleaned up and reorganized in 'net-next'.

4) The cls_flower classifier obtained a helper function in

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'net-next' called __fl_delete() and this overlapped with Daniel Borkamann's bug fix to use RCU for object destruction in 'net'. It also overlapped with Jiri's change to guard the rhashtable_remove_fast() call with a check against tc_skip_sw().

5) In mlx4, a revert bug fix in 'net' overlapped with some unrelated changes in 'net-next'.

6) In geneve, a stale header pointer after pskb_expand_head() bug fix in 'net' overlapped with a large reorganization of the same code in 'net-next'. Since the 'net-next' code no longer had the bug in question, there was nothing to do other than to simply take the 'net-next' hunks.

MAINTAINERS: add etnaviv mailinglist ------The etnaviv project now has its own mailinglist, add it to the MAINTAINERS file, so kernel patches get CC'ed to it.

10 MAINTAINERS#0044 11 MAINTAINERS#0057 12 Makefile#0002 Repo: c470abd4fde4 Linus Sun Feb 19 14:34:00 2017 -0800 Description: Linux 4.10 ------

Linux 4.10-rc8 ------

Linux 4.10-rc7 ------Some versions of ARM GCC compiler such as Android toolchain throws in a '-fpic' flag by default. This causes the gcc-goto check script to fail although some config would have '-fno-pic' flag in the KBUILD_CFLAGS.

This patch passes the KBUILD_CFLAGS to the check script so that the script does not rely on the default config from different .

Link: http://lkml.kernel.org/r/[email protected]

jump label: pass kbuild_cflags when checking for asm goto support ------

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Linux 4.10-rc6 ------

Linux 4.10-rc5 ------

Linux 4.10-rc4 ------

Linux 4.10-rc3 ------

Linux 4.10-rc2 ------

Linux 4.10-rc1 ------

13 Makefile#0005 14 Makefile#0800 15 README#0001 Repo: 6bef44b9b969 Mauro Tue Oct 18 10:46:38 2016 -0200 Description: README: add a new README file, pointing to the Documentation/ ------As we moved the real README file to Documentation/admin-guide/README.rst, let's add a replacement, pointing to it, and giving the main directions about documentation.

In the future, perhaps it would be worth to move the contents of Documentation/00-Index into this README.

docs-rst: create an user's manual book ------Place README, REPORTING-BUGS, SecurityBugs and kernel-parameters on an user's manual book.

As we'll be numbering the user's manual, remove the manual numbering from SecurityBugs.

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README: convert it to ReST markup ------Adjust the readme file for it to use the ReST markup:

- add chapter/section markups; - use ``foo`` for commands; - use :: for verbatim and script blocks; - replace unsupported markup _foo_ by **foo**; - add cross-references to other ReST files; - use lower case on the section titles, to match other ReST files.

16 README#0004 17 README#0007 18 README#0009 19 README#0013 20 README#0018 21 REPORTING-BUGS#fileDeleted Repo: 9d85025b0418 Mauro Wed Sep 21 09:51:11 2016 -0300 Description: docs-rst: create an user's manual book ------Place README, REPORTING-BUGS, SecurityBugs and kernel-parameters on an user's manual book.

As we'll be numbering the user's manual, remove the manual numbering from SecurityBugs.

REPORTING-BUGS: convert to ReST markup ------add a title to the document; - use :: before verbatim blocks; - add blank lines where required; - use protocol for URL references; - use a verbatim block for the bugs template; - add cross references to SecurityBugs.

arch\ 22 arch\Kconfig#0008 Repo: 467d27824920 Thiago Jung Mon Dec 19 16:22:32 2016 -0800 Description: powerpc: ima: get the buffer passed by the previous kernel ------

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Patch series "ima: carry the measurement list across kexec", v8.

The TPM PCRs are only reset on a hard reboot. In order to validate a TPM's quote after a soft reboot (eg. kexec -e), the IMA measurement list of the running kernel must be saved and then restored on the subsequent boot, possibly of a different architecture.

The existing securityfs binary_runtime_measurements file conveniently provides a serialized format of the IMA measurement list. This patch set serializes the measurement list in this format and restores it.

Up to now, the binary_runtime_measurements was defined as architecture native format. The assumption being that userspace could and would handle any architecture conversions. With the ability of carrying the measurement list across kexec, possibly from one architecture to a different one, the per boot architecture information is lost and with it the ability of recalculating the template digest hash. To resolve this problem, without breaking the existing ABI, this patch set introduces the boot command line option "ima_canonical_fmt", which is arbitrarily defined as little endian.

The need for this boot command line option will be limited to the existing version 1 format of the binary_runtime_measurements. Subsequent formats will be defined as canonical format (eg. TPM 2.0 support for larger digests).

A simplified method of Thiago Bauermann's "kexec buffer handover" patch series for carrying the IMA measurement list across kexec is included in this patch set. The simplified method requires all file measurements be taken prior to executing the kexec load, as subsequent measurements will not be carried across the kexec and restored.

This patch (of 10):

The IMA kexec buffer allows the currently running kernel to pass the measurement list via a kexec segment to the kernel that will be kexec'd. The second kernel can check whether the previous kernel sent the buffer and retrieve it.

This is the architecture-specific part which enables IMA to receive the measurement list passed by the previous kernel. It will be used in the next patch.

The change in machine_kexec_64.c is to factor out the logic of removing an FDT memory reservation so that it can be used by remove_ima_buffer.

Link: http://lkml.kernel.org/r/1480554346-29071-2-git-send-email- [email protected]

Merge tag 'gcc-plugins-v4.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux

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------Pull gcc plugins updates from Kees Cook: "Minor changes to the gcc plugins:

- add the gcc plugins Makefile to MAINTAINERS to route things correctly

- hide cyc_complexity behind !CONFIG_TEST for the future unhiding of plugins generally"

* tag 'gcc-plugins-v4.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux: gcc-plugins: Adjust Kconfig to avoid cyc_complexity MAINTAINERS: add GCC plugins Makefile

Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip ------Pull scheduler updates from Ingo Molnar: "The main scheduler changes in this cycle were:

- support Intel Turbo Boost Max Technology 3.0 (TBM3) by introducig a notion of 'better cores', which the scheduler will prefer to schedule single threaded workloads on. (Tim Chen, Srinivas Pandruvada)

- enhance the handling of asymmetric capacity CPUs further (Morten Rasmussen)

- improve/fix load handling when moving tasks between task groups (Vincent Guittot)

- simplify and clean up the cputime code (Stanislaw Gruszka)

- improve mass ()ed task spread a.k.a. hackbench speedup (Vincent Guittot)

- make struct kthread kmalloc()ed and related fixes (Oleg Nesterov)

- add uaccess atomicity debugging (when using access_ok() in the wrong context), under CONFIG_DEBUG_ATOMIC_SLEEP=y (Peter Zijlstra)

- implement various fixes, cleanups and other enhancements (Daniel Bristot de Oliveira, Martin Schwidefsky, Rafael J. Wysocki)"

* 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (41 commits) sched/core: Use load_avg for selecting idlest group sched/core: Fix find_idlest_group() for fork kthread: Don't abuse kthread_create_on_cpu() in __kthread_create_worker() kthread: Don't use to_live_kthread() in kthread_[un]park() kthread: Don't use to_live_kthread() in kthread_stop()

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Revert "kthread: Pin the stack via try_get_task_stack()/put_task_stack() in to_live_kthread() function" kthread: Make struct kthread kmalloc'ed x86/uaccess, sched/preempt: Verify access_ok() context sched/x86: Make CONFIG_SCHED_MC_PRIO=y easier to enable sched/x86: Change CONFIG_SCHED_ITMT to CONFIG_SCHED_MC_PRIO x86/sched: Use #include instead of #include cpufreq/intel_pstate: Use CPPC to get max performance acpi/bus: Set _OSC for diverse core support acpi/bus: Enable HWP CPPC objects x86/sched: Add SD_ASYM_PACKING flags to x86 ITMT CPU x86/sysctl: Add sysctl for ITMT scheduling feature x86: Enable Intel Turbo Boost Max Technology 3.0 x86/topology: Define x86's arch_update_cpu_topology sched: Extend scheduler's asym packing sched/fair: Clean up the tunable parameter definitions ...

sparc64:Support User Probes for sparc ------

sched/cputime, powerpc, s390: Make scaled cputime arch specific ------Only s390 and powerpc have hardware facilities allowing to measure cputimes scaled by frequency. On all other architectures utimescaled/stimescaled are equal to utime/stime (however they are accounted separately).

Remove {u,s}timescaled accounting on all architectures except powerpc and s390, where those values are explicitly accounted in the proper places.

gcc-plugins: Adjust Kconfig to avoid cyc_complexity ------In preparation for removing "depends on !COMPILE_TEST" from GCC_PLUGINS, the GCC_PLUGIN_CYC_COMPLEXITY plugin needs to gain the restriction, since it is mainly an example, and produces (intended) voluminous stderr reporting, which is generally undesirable for allyesconfig-style build tests. This additionally puts the plugin behind EXPERT and improves the help text.

23 arch\Kconfig#0102

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24 arch\Kconfig#0370 25 arch\Kconfig#0372 26 arch\Kconfig#0382 27 arch\Kconfig#0524 arch\alpha\boot\ 28 arch\alpha\boot\misc.c#0024 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro arch\alpha\include\asm\ 29 arch\alpha\include\asm\mutex.h#fileDeleted Repo: 890658b7ab48 Peter Zijlstra Tue Aug 23 13:36:04 2016 +0200 Description: locking/mutex: Kill arch specific code ------Its all generic atomic_long_t stuff now.

30 arch\alpha\include\asm\processor.h#0061 Repo: 6d0d287891a0 Christian Wed Nov 16 13:23:05 2016 +0100 Description: locking/core: Provide common cpu_relax_yield() definition ------No need to duplicate the same define everywhere. Since the only user is stop-machine and the only provider is s390, we can use a default implementation of cpu_relax_yield() in sched.h.

locking/core, arch: Remove cpu_relax_lowlatency() ------As there are no users left, we can remove cpu_relax_lowlatency() implementations from every architecture.

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locking/core: Introduce cpu_relax_yield() ------For spinning loops people do often use barrier() or cpu_relax(). For most architectures cpu_relax and barrier are the same, but on some architectures cpu_relax can add some latency. For example on power,sparc64 and arc, cpu_relax can shift the CPU towards other hardware threads in an SMT environment. On s390 cpu_relax does even more, it uses an hypercall to the hypervisor to give up the timeslice. In contrast to the SMT yielding this can result in larger latencies. In some places this latency is unwanted, so another variant "cpu_relax_lowlatency" was introduced. Before this is used in more and more places, lets revert the logic and provide a cpu_relax_yield that can be called in places where yielding is more important than latency. By default this is the same as cpu_relax on all architectures.

arch\alpha\include\uapi\asm\ 31 arch\alpha\include\uapi\asm\socket.h#0100 Repo: 1c885808e456 Francis Yan Sun Nov 27 23:07:18 2016 -0800 Description: tcp: SOF_TIMESTAMPING_OPT_STATS option for SO_TIMESTAMPING ------This patch exports the sender chronograph stats via the socket SO_TIMESTAMPING channel. Currently we can instrument how long a particular application unit of data was queued in TCP by tracking SOF_TIMESTAMPING_TX_SOFTWARE and SOF_TIMESTAMPING_TX_SCHED. Having these sender chronograph stats exported simultaneously along with these timestamps allow further breaking down the various sender limitation. For example, a video server can tell if a particular chunk of video on a connection takes a long time to deliver because TCP was experiencing small receive window. It is not possible to tell before this patch without packet traces.

To prepare these stats, the user needs to set SOF_TIMESTAMPING_OPT_STATS and SOF_TIMESTAMPING_OPT_TSONLY flags while requesting other SOF_TIMESTAMPING TX timestamps. When the timestamps are available in the error queue, the stats are returned in a separate control message of type SCM_TIMESTAMPING_OPT_STATS, in a list of TLVs (struct nlattr) of types: TCP_NLA_BUSY_TIME, TCP_NLA_RWND_LIMITED, TCP_NLA_SNDBUF_LIMITED. Unit is microsecond.

arch\alpha\kernel\ 32 arch\alpha\kernel\irq.c#0029 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800

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Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

33 arch\alpha\kernel\osf_sys.c#0042 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

-timers: Make them configurable ------Some embedded systems have no use for them. This removes about 25KB from the kernel binary size when configured out.

Corresponding syscalls are routed to a stub logging the attempt to use those syscalls which should be enough of a clue if they were disabled without proper consideration. They are: timer_create, timer_gettime: timer_getoverrun, timer_settime, timer_delete, clock_adjtime, setitimer, getitimer, alarm.

The clock_settime, clock_gettime, clock_getres and clock_nanosleep syscalls are replaced by simple wrappers compatible with CLOCK_REALTIME, CLOCK_MONOTONIC and CLOCK_BOOTTIME only which should cover the vast majority of use cases with very little code.

34 arch\alpha\kernel\osf_sys.c#1032

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35 arch\alpha\kernel\osf_sys.c#1039 36 arch\alpha\kernel\osf_sys.c#1055 37 arch\alpha\kernel\process.c#0034 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

38 arch\alpha\kernel\ptrace.c#0019 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

ptrace: Don't allow accessing an undumpable mm ------It is the reasonable expectation that if an executable file is not readable there will be no way for a user without special privileges to read the file. This is enforced in ptrace_attach but if ptrace is already attached before exec there is no enforcement for read-only executables.

As the only way to read such an mm is through access_process_vm spin a variant called ptrace_access_vm that will fail if the target process is not being ptraced by the current process, or the current process did not have sufficient privileges when ptracing began to read the target processes mm.

In the ptrace implementations replace access_process_vm by ptrace_access_vm. There remain several ptrace sites that still use

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access_process_vm as they are reading the target executables instructions (for kernel consumption) or register stacks. As such it does not appear necessary to add a permission check to those calls.

This bug has always existed in Linux.

Fixes: v1.0

39 arch\alpha\kernel\ptrace.c#0286 40 arch\alpha\kernel\setup.c#0056 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

41 arch\alpha\kernel\signal.c#0025 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

42 arch\alpha\kernel\srm_env.c#0038 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

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to do the replacement at the end of the merge window.

Requested-by: Al Viro

srm_env: don't bother with pointer to srm_env_t ------Since the only thing in it the methods actually care about is variable id, just store that directly.

srm_env: use proc_remove_subtree() ------

43 arch\alpha\kernel\srmcons.c#0021 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

44 arch\alpha\kernel\time.c#0037 Repo: a5a1d1c2914b Thomas Wed Dec 21 20:32:01 2016 +0100 Description: clocksource: Use a plain u64 instead of cycle_t ------There is no point in having an extra type for extra confusion. u64 is unambiguous.

Conversion was done with the following coccinelle script:

@rem@ @@ -typedef u64 cycle_t;

@fix@ typedef cycle_t; @@ -cycle_t +u64

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Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

45 arch\alpha\kernel\time.c#0136 46 arch\alpha\kernel\time.c#0263 47 arch\alpha\kernel\traps.c#0021 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro arch\alpha\math-emu\ 48 arch\alpha\math-emu\math.c#0006 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

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Line Link NR. Descriptions arch\alpha\mm\ 49 arch\alpha\mm\init.c#0025 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

mm/alpha: unify mem_init() for both UMA and NUMA architectures ------Now mem_init() for both Alpha UMA and Alpha NUMA are the same, so unify it to reduce duplicated code.

mm/alpha: prepare for removing num_physpages and simplify mem_init() ------Prepare for removing num_physpages and simplify mem_init().

mm: concentrate modification of totalram_pages into the mm core ------Concentrate code to modify totalram_pages into the mm core, so the arch memory initialized code doesn't need to take care of it. With these changes applied, only following functions from mm core modify global variable totalram_pages: free_bootmem_late(), free_all_bootmem(), free_all_bootmem_node(), adjust_managed_page_count().

With this patch applied, it will be much more easier for us to keep totalram_pages and zone->managed_pages in consistence.

mm: enhance free_reserved_area() to support poisoning memory with zero ------Address more review comments from last round of code review. 1) Enhance free_reserved_area() to support poisoning freed memory with pattern '0'. This could be used to get rid of poison_init_mem() on ARM64. 2) A previous patch has disabled memory poison for initmem on s390 by mistake, so restore to the original behavior. 3) Remove redundant PAGE_ALIGN() when calling free_reserved_area().

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Line Link NR. Descriptions arch\arc\ 50 arch\arc\Kconfig#0011 Repo: eb1357d942e5 Vineet Gupta Mon Jan 16 10:48:09 2017 -0800 Description: ARC: module: Fix !CONFIG_ARC_DW2_UNWIND builds ------commit d65283f7b695b5 added mod->arch.secstr under CONFIG_ARC_DW2_UNWIND, but used it unconditionally which broke builds when the option was disabled. Fix that by adjusting the #ifdef guard.

And while at it add a missing guard (for unwinder) in module.c as well

ARC: enable SG chaining ------

clocksource: import ARC timer driver ------This adds support for

- CONFIG_ARC_TIMERS : legacy 32-bit TIMER0 and TIMER1 which count UP from @CNT to @LIMIT, before optionally triggering an interrupt. These are programmed using ARC auxiliary register interface. These are present in all ARC cores (ARC700 and ARC HS38) TIMER0 serves as clockevent for all ARC linux builds. TIMER1 is used for clocksource in arc700 builds.

- CONFIG_ARC_TIMERS_64BIT: 64-bit counters, RTC and GFRC found in ARC HS38 cores. These are independnet IP blocks with different programming model respectively.

Link: http://lkml.kernel.org/r/20161111231132.GA4186@mai

ARC: timer: gfrc, rtc: build under same option (64-bit timers) ------The original distinction was done as they were developed at different times and primarily because they are specific to UP (RTC) and SMP (GFRC).

But given that driver handles that at runtime, (i.e. not allowing RTC as clocksource in SMP), we can simplify things a bit.

51 arch\arc\Kconfig#0015 52 arch\arc\Kconfig#0032

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53 arch\arc\Kconfig#0119 54 arch\arc\Kconfig#0415 arch\arc\boot\dts\ 55 arch\arc\boot\dts\abilis_tb10x.dtsi#0132 Repo: bd2c6636cc59 Eugeniy Fri Nov 25 17:59:07 2016 +0300 Description: dmaengine: DW DMAC: add multi-block property to device tree ------Several versions of DW DMAC have multi block transfers hardware support. Hardware support of multi block transfers is disabled by default if we use DT to configure DMAC and software emulation of multi block transfers used instead. Add multi-block property, so it is possible to enable hardware multi block transfers (if present) via DT.

Switch from per device is_nollp variable to multi_block array to be able enable/disable multi block transfers separately per channel.

56 arch\arc\boot\dts\axs101.dts#0020 Repo: 7badf6fefca8 Alexey Tue Nov 22 14:16:36 2016 +0300 Description: ARC: axs10x: really enable ARC PGU ------Up until now we had ARC PGU not enabled in axs10x defconfigs trying to not bloat kernel image again with yet another drivers and subsystems.

This change configures ARC PGU (as well as DRM bits it depends on) to be built as a module and so those who need LCD screen to work on axs10x may bundle built .ko files in their target's file-system with help of the following command on host: ------>8------make INSTALL_MOD_PATH=_path_to_target_fs_ modules_install ------>8------

and later on target with commands as simple as: ------>8------modprobe adv7511.ko modprobe arcpgu.ko ------>8------get LCD working.

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57 arch\arc\boot\dts\axs103_idu.dts#0023 Repo: 7badf6fefca8 Alexey Tue Nov 22 14:16:36 2016 +0300 Description: ARC: axs10x: really enable ARC PGU ------Up until now we had ARC PGU not enabled in axs10x defconfigs trying to not bloat kernel image again with yet another drivers and subsystems.

This change configures ARC PGU (as well as DRM bits it depends on) to be built as a module and so those who need LCD screen to work on axs10x may bundle built .ko files in their target's file-system with help of the following command on host: ------>8------make INSTALL_MOD_PATH=_path_to_target_fs_ modules_install ------>8------

and later on target with commands as simple as: ------>8------modprobe adv7511.ko modprobe arcpgu.ko ------>8------get LCD working.

58 arch\arc\boot\dts\zebu_hs.dts#fileDeleted Repo: 4988cc5635ed Vineet Gupta Fri Nov 18 14:19:27 2016 -0800 Description: ARC: rename Zebu platform support to HAPS ------There are more ARC Linux HAPS users than Zebu ones.

Same kernel would work fine on both, even with embedded DT, assuming the FPGA bitfile configuration is same

59 arch\arc\boot\dts\zebu_hs_idu.dts#fileDeleted Repo: 4988cc5635ed Vineet Gupta Fri Nov 18 14:19:27 2016 -0800 Description: ARC: rename Zebu platform support to HAPS ------There are more ARC Linux HAPS users than Zebu ones.

Same kernel would work fine on both, even with embedded DT, assuming the FPGA bitfile configuration is same

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60 arch\arc\boot\dts\haps_hs.dts#newFile Repo: 4988cc5635ed Vineet Gupta Fri Nov 18 14:19:27 2016 -0800 Description: ARC: rename Zebu platform support to HAPS ------There are more ARC Linux HAPS users than Zebu ones.

Same kernel would work fine on both, even with embedded DT, assuming the FPGA bitfile configuration is same

61 arch\arc\boot\dts\haps_hs_idu.dts#newFile Repo: 4988cc5635ed Vineet Gupta Fri Nov 18 14:19:27 2016 -0800 Description: ARC: rename Zebu platform support to HAPS ------There are more ARC Linux HAPS users than Zebu ones.

Same kernel would work fine on both, even with embedded DT, assuming the FPGA bitfile configuration is same

arch\arc\configs\ 62 arch\arc\configs\axs101_defconfig#0078 Repo: 7badf6fefca8 Alexey Tue Nov 22 14:16:36 2016 +0300 Description: ARC: axs10x: really enable ARC PGU ------Up until now we had ARC PGU not enabled in axs10x defconfigs trying to not bloat kernel image again with yet another drivers and subsystems.

This change configures ARC PGU (as well as DRM bits it depends on) to be built as a module and so those who need LCD screen to work on axs10x may bundle built .ko files in their target's file-system with help of the following command on host: ------>8------make INSTALL_MOD_PATH=_path_to_target_fs_ modules_install ------>8------

and later on target with commands as simple as: ------>8------modprobe adv7511.ko modprobe arcpgu.ko ------>8------get LCD working.

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63 arch\arc\configs\axs101_defconfig#0083 64 arch\arc\configs\axs103_smp_defconfig#0080 Repo: 7badf6fefca8 Alexey Tue Nov 22 14:16:36 2016 +0300 Description: ARC: axs10x: really enable ARC PGU ------Up until now we had ARC PGU not enabled in axs10x defconfigs trying to not bloat kernel image again with yet another drivers and subsystems.

This change configures ARC PGU (as well as DRM bits it depends on) to be built as a module and so those who need LCD screen to work on axs10x may bundle built .ko files in their target's file-system with help of the following command on host: ------>8------make INSTALL_MOD_PATH=_path_to_target_fs_ modules_install ------>8------

and later on target with commands as simple as: ------>8------modprobe adv7511.ko modprobe arcpgu.ko ------>8------get LCD working.

65 arch\arc\configs\axs103_smp_defconfig#0085 66 arch\arc\configs\nsimosci_hs_smp_defconfig#0024 Repo: 044214200b0b Vineet Gupta Mon Oct 31 14:26:41 2016 -0700 Description: ARC: timer: gfrc, rtc: build under same option (64-bit timers) ------The original distinction was done as they were developed at different times and primarily because they are specific to UP (RTC) and SMP (GFRC).

But given that driver handles that at runtime, (i.e. not allowing RTC as clocksource in SMP), we can simplify things a bit.

67 arch\arc\configs\vdk_hs38_smp_defconfig#0018 Repo: 044214200b0b Vineet Gupta Mon Oct 31 14:26:41 2016 -0700 Description: ARC: timer: gfrc, rtc: build under same option (64-bit timers) ------The original distinction was done as they were developed at different times and primarily because they are specific to UP (RTC) and SMP (GFRC).

But given that driver handles that at runtime, (i.e. not allowing RTC as clocksource in SMP), we can simplify things a bit.

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68 arch\arc\configs\zebu_hs_defconfig#fileDeleted Repo: 4988cc5635ed Vineet Gupta Fri Nov 18 14:19:27 2016 -0800 Description: ARC: rename Zebu platform support to HAPS ------There are more ARC Linux HAPS users than Zebu ones.

Same kernel would work fine on both, even with embedded DT, assuming the FPGA bitfile configuration is same

69 arch\arc\configs\zebu_hs_smp_defconfig#fileDeleted Repo: 4988cc5635ed Vineet Gupta Fri Nov 18 14:19:27 2016 -0800 Description: ARC: rename Zebu platform support to HAPS ------There are more ARC Linux HAPS users than Zebu ones.

Same kernel would work fine on both, even with embedded DT, assuming the FPGA bitfile configuration is same

70 arch\arc\configs\haps_hs_defconfig#newFile Repo: 4988cc5635ed Vineet Gupta Fri Nov 18 14:19:27 2016 -0800 Description: ARC: rename Zebu platform support to HAPS ------There are more ARC Linux HAPS users than Zebu ones.

Same kernel would work fine on both, even with embedded DT, assuming the FPGA bitfile configuration is same

71 arch\arc\configs\haps_hs_smp_defconfig#newFile Repo: 4988cc5635ed Vineet Gupta Fri Nov 18 14:19:27 2016 -0800 Description: ARC: rename Zebu platform support to HAPS ------There are more ARC Linux HAPS users than Zebu ones.

Same kernel would work fine on both, even with embedded DT, assuming the FPGA bitfile configuration is same

arch\arc\include\asm\ 72 arch\arc\include\asm\arcregs.h#0023 Repo: f64915be2d8c Vineet Gupta Mon Dec 19 11:24:08 2016 -0800

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Description: ARC: mm: No need to save cache version in @cpuinfo ------Historical MMU revisions have been paired with Cache revision updates which are captured in MMU and Cache Build Configuration Registers respectively.

This was used in boot code to check for configurations mismatches, speically in simulations (such as running with non existent caches, non pairing MMU and Cache version etc). This can instead be inferred from other cache params such as line size. So remove @ver from post processed @cpuinfo which could be used later to save soem other interesting info.

ARC: breakout timer include code into separate header ... ------... which allows for use in drivers/clocksource later

ARC: breakout aux handling into a separate header ------ARC timers use aux registers for programming and this paves way for moving ARC timer drivers into drivers/clocksource

73 arch\arc\include\asm\arcregs.h#0115 74 arch\arc\include\asm\arcregs.h#0121 75 arch\arc\include\asm\arcregs.h#0294 76 arch\arc\include\asm\arcregs.h#0337 77 arch\arc\include\asm\cache.h#0070 Repo: 8c47f83ba459 Vineet Gupta Wed Jun 22 16:01:19 2016 +0530 Description: ARCv2: IOC: Adhere to progamming model guidelines to avoid DMA corruption ------On AXS103 release bitfiles, DMA data corruptions were seen because IOC setup was not following the recommended way in documentation.

Flipping IOC on when caches are enabled or coherency transactions are in flight, might cause some of the memory operations to not observe coherency as expected.

So strictly follow the programming model recommendations as documented in comment header above arc_ioc_setup()

ARCv2: IOC: refactor the IOC and SLC operations into own functions ------Move IOC setup into arc_ioc_setup()

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- Move SLC disabling into arc_slc_disable()

78 arch\arc\include\asm\cache.h#0083 79 arch\arc\include\asm\cache.h#0096 80 arch\arc\include\asm\cache.h#0098 81 arch\arc\include\asm\cacheflush.h#0088 Repo: 08fe007968b2 Vineet Gupta Mon Dec 19 11:38:38 2016 -0800 Description: ARC: mm: arc700: Don't assume 2 colours for aliasing VIPT dcache ------An ARC700 customer reported linux boot crashes when upgrading to bigger L1 dcache (64K from 32K). Turns out they had an aliasing VIPT config and current code only assumed 2 colours, while theirs had 4. So default to 4 colours and complain if there are fewer. Ideally this needs to be a Kconfig option, but heck that's too much of hassle for a single user.

82 arch\arc\include\asm\cacheflush.h#0101 83 arch\arc\include\asm\delay.h#0029 Repo: 36425cd67052 Vineet Gupta Tue Jan 24 10:23:42 2017 -0800 Description: ARC: udelay: fix inline assembler by adding LP_COUNT to clobber list ------commit 3c7c7a2fc8811bc ("ARC: Don't use "+l" inline asm constraint") modified the inline assembly to setup LP_COUNT register manually and NOT rely on gcc to do it (with the +l inline assembler contraint hint, now being retired in the compiler)

However the fix was flawed as we didn't add LP_COUNT to asm clobber list, meaning gcc doesn't know that LP_COUNT or zero-delay-loops are in action in the inline asm.

This resulted in some fun - as nested ZOL loops were being generared

| mov lp_count,250000 ;16 # tmp235, | lp .L__GCC__LP14 # <======OUTER LOOP (gcc generated) | .L14: | ld r2, [r5] # MEM[(volatile u32 *)prephitmp_43], w | dmb 1 | breq r2, -1, @.L21 #, w,, | bbit0 r2,1,@.L13 # w,, | ld r4,[r7] ;25 # loops_per_jiffy, loops_per_jiffy | mpymu r3,r4,r6 #, loops_per_jiffy, tmp234 | | mov lp_count, r3 # <======INNER LOOP (from inline asm) | lp 1f

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| nop | 1: | nop_s | .L__GCC__LP14: ; loop end, start is @.L14 #,

This caused issues with drivers relying on sane behaviour of udelay friends.

With LP_COUNT added to clobber list, gcc doesn't generate the outer loop in say above case.

Addresses STAR 9001146134

84 arch\arc\include\asm\entry-arcv2.h#0019 Repo: ecd43afdbe72 Vineet Gupta Sun Jan 8 19:45:48 2017 -0800 Description: ARCv2: save r30 on kernel entry as gcc uses it for code-gen ------This is not exposed to userspace debugers yet, which can be done independently as a seperate patch !

85 arch\arc\include\asm\entry-arcv2.h#0076 86 arch\arc\include\asm\irqflags-arcv2.h#0041 Repo: 107177b14d81 Vineet Gupta Fri Sep 30 16:13:28 2016 -0700 Description: ARCv2: intc: default all interrupts to priority 1 ------ARC HS Cores support configurable multiple interrupt priorities of upto 16 levels. In commit dec2b2849cfcc ("ARCv2: intc: Allow interruption by lowest priority interrupt") we switched to 15 which seems a bit excessive given that there would be rare hardware implementing so many preemption levels AND running Linux. It would seem that 2 levels will be more common so switch to 1 as the default priority level. This will be the "lower" priority level saving 0 for implementing NMI style support.

This scheme also works in systems with more than 2 prioity levels as well.

Review: COMMENT stecan Thu, 11 Jan 2018 07:26:18 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:18 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:26:18 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:18 +0100

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Automatic commented! 87 arch\arc\include\asm\irqflags-arcv2.h#0044 88 arch\arc\include\asm\mcip.h#fileDeleted Repo: 2d7f5c48c03e Vineet Gupta Mon Oct 31 11:27:08 2016 -0700 Description: ARC: move mcip.h into include/soc and adjust the includes ------Also remove the dependency on ARCv2, to increase compile coverage for !ARCV2 builds

ARC: breakout aux handling into a separate header ------ARC timers use aux registers for programming and this paves way for moving ARC timer drivers into drivers/clocksource

89 arch\arc\include\asm\module.h#0017 Repo: eb1357d942e5 Vineet Gupta Mon Jan 16 10:48:09 2017 -0800 Description: ARC: module: Fix !CONFIG_ARC_DW2_UNWIND builds ------commit d65283f7b695b5 added mod->arch.secstr under CONFIG_ARC_DW2_UNWIND, but used it unconditionally which broke builds when the option was disabled. Fix that by adjusting the #ifdef guard.

And while at it add a missing guard (for unwinder) in module.c as well

90 arch\arc\include\asm\module.h#0019 91 arch\arc\include\asm\module.h#0021 92 arch\arc\include\asm\module.h#0024 93 arch\arc\include\asm\mutex.h#fileDeleted Repo: 890658b7ab48 Peter Zijlstra Tue Aug 23 13:36:04 2016 +0200 Description: locking/mutex: Kill arch specific code ------Its all generic atomic_long_t stuff now.

ARC: SMP support ------ARC common code to enable a SMP system + ISS provided SMP extensions.

ARC700 natively lacks SMP support, hence some of the core features are are only enabled if SoCs have the necessary h/w pixie-dust. This

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includes: -Inter Processor Interrupts (IPI) -Cache coherency -load-locked/store-conditional ...

The low level exception handling would be completely broken in SMP because we don't have hardware assisted stack switching. Thus a fair bit of this code is repurposing the MMU_SCRATCH reg for event handler prologues to keep them re-entrant.

Many thanks to Rajeshwar Ranga for his initial "major" contributions to SMP Port (back in 2008), and to Noam Camus and Gilad Ben-Yossef for help with resurrecting that in 3.2 kernel (2012).

Note that this platform code is again singleton design pattern - so multiple SMP platforms won't build at the moment - this deficiency is addressed in subsequent patches within this series.

94 arch\arc\include\asm\processor.h#0063 Repo: 6d0d287891a0 Christian Wed Nov 16 13:23:05 2016 +0100 Description: locking/core: Provide common cpu_relax_yield() definition ------No need to duplicate the same define everywhere. Since the only user is stop-machine and the only provider is s390, we can use a default implementation of cpu_relax_yield() in sched.h.

locking/core, arch: Remove cpu_relax_lowlatency() ------As there are no users left, we can remove cpu_relax_lowlatency() implementations from every architecture.

locking/core: Introduce cpu_relax_yield() ------For spinning loops people do often use barrier() or cpu_relax(). For most architectures cpu_relax and barrier are the same, but on some architectures cpu_relax can add some latency. For example on power,sparc64 and arc, cpu_relax can shift the CPU towards other hardware threads in an SMT environment. On s390 cpu_relax does even more, it uses an hypercall to the hypervisor to give up the timeslice. In contrast to the SMT yielding this can result in larger latencies. In some places this latency is unwanted, so another variant "cpu_relax_lowlatency" was introduced. Before this is used in more and more places, lets revert the logic and provide a cpu_relax_yield

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that can be called in places where yielding is more important than latency. By default this is the same as cpu_relax on all architectures.

95 arch\arc\include\asm\processor.h#0070 96 arch\arc\include\asm\ptrace.h#0087 Repo: ecd43afdbe72 Vineet Gupta Sun Jan 8 19:45:48 2017 -0800 Description: ARCv2: save r30 on kernel entry as gcc uses it for code-gen ------This is not exposed to userspace debugers yet, which can be done independently as a seperate patch !

97 arch\arc\include\asm\setup.h#0034 Repo: e497c8e52a83 Vineet Gupta Wed Jan 18 12:59:21 2017 -0800 Description: ARCv2: IOC: Use actual memory size to setup aperture size ------vs. fixed 512M before.

But this still assumes that all of memory is under IOC which may not be true for the SoC. Improve that later when this becomes a real issue, by specifying this from DT.

ARC: boot log: refactor cpu name/release printing ------The motivation is to identify ARC750 vs. ARC770 (we currently print generic "ARC700").

A given ARC700 release could be 750 or 770, with same ARCNUM (or family identifier which is unfortunate). The existing arc_cpu_tbl[] kept a single concatenated string for core name and release which thus doesn't work for 750 vs. 770 identification.

So split this into 2 tables, one with core names and other with release. And while we are at it, get rid of the range checking for family numbers. We just document the known to exist cores running Linux and ditch others.

With this in place, we add detection of ARC750 which is - cores 0x33 and before - cores 0x34 and later with MMUv2

arch\arc\kernel\ 98 arch\arc\kernel\entry-arcv2.S#0070

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Repo: 78833e79d516 Vineet Gupta Fri Sep 23 14:09:30 2016 -0700 Description: ARCv2: entry: document intr disable in hard isr ------And while at it - use the proper assembler macro which includes the optional irq tracing already - de-uglify'ing the code a bit

99 arch\arc\kernel\entry-arcv2.S#0083 100 arch\arc\kernel\entry-arcv2.S#0085 101 arch\arc\kernel\entry-arcv2.S#0185 102 arch\arc\kernel\entry-compact.S#0262 Repo: f5f3bde4f676 Vineet Gupta Thu Sep 29 15:19:46 2016 -0700 Description: ARC: ARCompact entry: elide re-reading ECR in ProtV handler ------

103 arch\arc\kernel\head.S#0074 Repo: bf02454a741b Vineet Gupta Thu Jan 12 14:30:29 2017 -0800 Description: ARC: smp-boot: Decouple Non masters waiting API from jump to ------For run-on-reset SMP configs, non master cores call a routine which waits until Master gives it a "go" signal (currently using a shared mem flag). The same routine then jumps off the well known entry point of all non Master cores i.e. @first_lines_of_secondary

This patch moves out the last part into one single place in early boot code.

This is better in terms of absraction (the wait API only waits) and returns, leaving out the "jump off to" part.

In actual implementation this requires some restructuring of the early boot code as well as Master now jumps to BSS setup explicitly, vs. falling thru into it before.

Technically this patch doesn't cause any functional change, it just moves the ugly #ifdef'ry from assembly code to "C"

ARC: boot: Non Master cpus only need to call EARLY_CPU_SETUP once ------With prev fixes, all cores now start via common entry point @stext which already calls EARLY_CPU_SETUP for all cores - so no need to invoke it again

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104 arch\arc\kernel\head.S#0079 105 arch\arc\kernel\head.S#0083 106 arch\arc\kernel\intc-arcv2.c#0017 Repo: 2163266c2704 Yuriy KolerovWed Dec 28 11:46:24 2016 +0300 Description: ARC: IRQ: Use hwirq instead of virq in mask/unmask ------It is necessary to use hwirq instead of virq when you communicate with an interrupt controller since there is no guaranty that virq numbers match hwirq numbers.

ARCv2: intc: default all interrupts to priority 1 ------ARC HS Cores support configurable multiple interrupt priorities of upto 16 levels. In commit dec2b2849cfcc ("ARCv2: intc: Allow interruption by lowest priority interrupt") we switched to 15 which seems a bit excessive given that there would be rare hardware implementing so many preemption levels AND running Linux. It would seem that 2 levels will be more common so switch to 1 as the default priority level. This will be the "lower" priority level saving 0 for implementing NMI style support.

This scheme also works in systems with more than 2 prioity levels as well.

107 arch\arc\kernel\intc-arcv2.c#0027 108 arch\arc\kernel\intc-arcv2.c#0070 109 arch\arc\kernel\intc-arcv2.c#0075 110 arch\arc\kernel\intc-arcv2.c#0082 111 arch\arc\kernel\intc-arcv2.c#0088 112 arch\arc\kernel\intc-arcv2.c#0095 113 arch\arc\kernel\intc-compact.c#0060 Repo: 2163266c2704 Yuriy KolerovWed Dec 28 11:46:24 2016 +0300 Description: ARC: IRQ: Use hwirq instead of virq in mask/unmask ------It is necessary to use hwirq instead of virq when you communicate with an interrupt controller since there is no guaranty that virq numbers match hwirq numbers.

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114 arch\arc\kernel\intc-compact.c#0069 115 arch\arc\kernel\Makefile#0011 Repo: c4c9a040ecb7 Vineet Gupta Mon Oct 31 13:46:38 2016 -0700 Description: clocksource: import ARC timer driver ------This adds support for

- CONFIG_ARC_TIMERS : legacy 32-bit TIMER0 and TIMER1 which count UP from @CNT to @LIMIT, before optionally triggering an interrupt. These are programmed using ARC auxiliary register interface. These are present in all ARC cores (ARC700 and ARC HS38) TIMER0 serves as clockevent for all ARC linux builds. TIMER1 is used for clocksource in arc700 builds.

- CONFIG_ARC_TIMERS_64BIT: 64-bit counters, RTC and GFRC found in ARC HS38 cores. These are independnet IP blocks with different programming model respectively.

Link: http://lkml.kernel.org/r/20161111231132.GA4186@mai

ARC: RIP arc_{get|set}_core_freq() clk API ------There are no more users of this - so RIP!

116 arch\arc\kernel\mcip.c#0013 Repo: 517e7610d2ce Vineet Gupta Thu Jan 19 17:05:00 2017 -0800 Description: ARCv2: MCIP: update the BCR per current changes ------

ARCv2: MCIP: Deprecate setting of affinity in Device Tree ------

ARCv2: IRQ: Call entry/exit functions for chained handlers in MCIP ------

ARC: move mcip.h into include/soc and adjust the includes ------

ARCv2: MCIP: Use IDU_M_DISTRI_DEST mode if there is only 1 destination core ------

117 arch\arc\kernel\mcip.c#0015

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118 arch\arc\kernel\mcip.c#0017 119 arch\arc\kernel\mcip.c#0096 120 arch\arc\kernel\mcip.c#0100 121 arch\arc\kernel\mcip.c#0177 122 arch\arc\kernel\mcip.c#0207 123 arch\arc\kernel\mcip.c#0209 124 arch\arc\kernel\mcip.c#0226 125 arch\arc\kernel\mcip.c#0238 126 arch\arc\kernel\mcip.c#0242 127 arch\arc\kernel\mcip.c#0244 128 arch\arc\kernel\mcip.c#0259 129 arch\arc\kernel\mcip.c#0267 130 arch\arc\kernel\module.c#0035 Repo: eb1357d942e5 Vineet Gupta Mon Jan 16 10:48:09 2017 -0800 Description: ARC: module: Fix !CONFIG_ARC_DW2_UNWIND builds ------commit d65283f7b695b5 added mod->arch.secstr under CONFIG_ARC_DW2_UNWIND, but used it unconditionally which broke builds when the option was disabled. Fix that by adjusting the #ifdef guard.

And while at it add a missing guard (for unwinder) in module.c as well

ARC: module: print pretty section names ------Now that we have referece to section name string table in apply_relocate_add(), use it to

- print the name of section being relocated - print symbol with NULL name (since it refers to a section)

before

| Section to fixup 7000a060 | ======| rela->r_off | rela->addend | sym->st_value | ADDR | VALUE | ======| 1c 0 7000e000 7000a07c 7000e000 [] | 40 0 7000a000 7000a0a0 7000a000 []

after

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| Section to fixup .eh_frame @7000a060 | ======| r_off r_add st_value ADDRESS VALUE | ======| 1c 0 7000e000 7000a07c 7000e000 [.init.text] | 40 0 7000a000 7000a0a0 7000a000 [.exit.text]

131 arch\arc\kernel\module.c#0037 132 arch\arc\kernel\module.c#0116 133 arch\arc\kernel\module.c#0119 134 arch\arc\kernel\setup.c#0013 Repo: 92b03314033c Vineet Gupta Mon Oct 31 13:26:25 2016 -0700 Description: ARC: time: move time_init() out of the driver ------to allow future git mv of the driver into drivers/clocksource

ARC: timer: gfrc, rtc: build under same option (64-bit timers) ------The original distinction was done as they were developed at different times and primarily because they are specific to UP (RTC) and SMP (GFRC).

But given that driver handles that at runtime, (i.e. not allowing RTC as clocksource in SMP), we can simplify things a bit.

ARC: boot log: refactor cpu name/release printing ------The motivation is to identify ARC750 vs. ARC770 (we currently print generic "ARC700").

A given ARC700 release could be 750 or 770, with same ARCNUM (or family identifier which is unfortunate). The existing arc_cpu_tbl[] kept a single concatenated string for core name and release which thus doesn't work for 750 vs. 770 identification.

So split this into 2 tables, one with core names and other with release. And while we are at it, get rid of the range checking for family numbers. We just document the known to exist cores running Linux and ditch others.

With this in place, we add detection of ARC750 which is - cores 0x33 and before - cores 0x34 and later with MMUv2

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ARC: boot log: don't assume SWAPE instruction support ------This came to light when helping a customer with oldish ARC750 core who were getting instruction errors because of lack of SWAPE but boot log was incorrectly printing it as being present

ARC: boot log: refactor printing abt features not captured in BCRs ------On older arc700 cores, some of the features configured were not present in Build config registers. To print about them at boot, we just use the Kconfig option i.e. whether linux is built to use them or not. So yes this seems bogus, but what else can be done. Moreover if linux is booting with these enabled, then the Kconfig info is a good indicator anyways.

Over time these "hacks" accumulated in read_arc_build_cfg_regs() as well as arc_cpu_mumbojumbo(). so refactor and move all of those in a single place: read_arc_build_cfg_regs(). This causes some code redcution too:

| bloat-o-meter2 arch/arc/kernel/setup.o.0 arch/arc/kernel/setup.o.1 | add/remove: 0/0 grow/shrink: 2/1 up/down: 64/-132 (-68) | function old new delta | setup_processor 610 670 +60 | cpuinfo_arc700 76 80 +4 | arc_cpu_mumbojumbo 752 620 -132

135 arch\arc\kernel\setup.c#0239 136 arch\arc\kernel\setup.c#0242 137 arch\arc\kernel\setup.c#0454 138 arch\arc\kernel\smp.c#0093 Repo: 78f824d4312a Vineet Gupta Tue Jun 21 14:24:33 2016 +0530 Description: ARCv2: smp-boot: wake_flag polling by non-Masters needs to be uncached ------This is needed on HS38 cores, for setting up IO-Coherency aperture properly

The polling could perturb the caches and coherecy fabric which could be wrong in the small window when Master is setting up IOC aperture etc in arc_cache_init()

We do it only for ARCv2 based builds to not affect EZChip ARCompact based platform.

ARC: smp-boot: Decouple Non masters waiting API from jump to entry point

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------For run-on-reset SMP configs, non master cores call a routine which waits until Master gives it a "go" signal (currently using a shared mem flag). The same routine then jumps off the well known entry point of all non Master cores i.e. @first_lines_of_secondary

This patch moves out the last part into one single place in early boot code.

This is better in terms of absraction (the wait API only waits) and returns, leaving out the "jump off to" part.

In actual implementation this requires some restructuring of the early boot code as well as Master now jumps to BSS setup explicitly, vs. falling thru into it before.

Technically this patch doesn't cause any functional change, it just moves the ugly #ifdef'ry from assembly code to "C"

139 arch\arc\kernel\smp.c#0108 140 arch\arc\kernel\smp.c#0114 141 arch\arc\kernel\smp.c#0121 142 arch\arc\kernel\smp.c#0124 143 arch\arc\kernel\time.c#fileDeleted Repo: c4c9a040ecb7 Vineet Gupta Mon Oct 31 13:46:38 2016 -0700 Description: clocksource: import ARC timer driver ------This adds support for

- CONFIG_ARC_TIMERS : legacy 32-bit TIMER0 and TIMER1 which count UP from @CNT to @LIMIT, before optionally triggering an interrupt. These are programmed using ARC auxiliary register interface. These are present in all ARC cores (ARC700 and ARC HS38) TIMER0 serves as clockevent for all ARC linux builds. TIMER1 is used for clocksource in arc700 builds.

- CONFIG_ARC_TIMERS_64BIT: 64-bit counters, RTC and GFRC found in ARC HS38 cores. These are independnet IP blocks with different programming model respectively.

Link: http://lkml.kernel.org/r/20161111231132.GA4186@mai

ARC: breakout timer include code into separate header ... ------... which allows for use in drivers/clocksource later

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ARC: move mcip.h into include/soc and adjust the includes ------Also remove the dependency on ARCv2, to increase compile coverage for !ARCV2 builds

ARC: time: move time_init() out of the driver ------to allow future git mv of the driver into drivers/clocksource

ARC: timer: gfrc, rtc: build under same option (64-bit timers) ------The original distinction was done as they were developed at different times and primarily because they are specific to UP (RTC) and SMP (GFRC).

But given that driver handles that at runtime, (i.e. not allowing RTC as clocksource in SMP), we can simplify things a bit.

ARC: timer: gfrc, rtc: Read BCR to detect whether hardware exists ... ------... don't rely on cpuinfo populated in arc boot code. This paves way for moving this code in drivers/clocksource/

And while at it, convert the WARN() to pr_warn() as sugested by Daniel

ARC: timer: gfrc, rtc: deuglify big endian code ------A standard "C" shift will be handled appropriately by the compiler depending on the endian for the build. So we don't need the explicit distinction in code

144 arch\arc\kernel\unaligned.c#0244 Repo: a524c218bc94 Vineet Gupta Tue Feb 7 09:44:58 2017 -0800 Description: ARC: [arcompact] brown paper bag bug in unaligned access delay slot fixup ------

ARC: [arcompact] handle unaligned access delay slot corner case ------

Review: COMMENT stecan Thu, 11 Jan 2018 07:26:18 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:18 +0100

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Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:26:18 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:18 +0100 Automatic commented! 145 arch\arc\kernel\unaligned.c#0246 arch\arc\mm\ 146 arch\arc\mm\cache.c#0026 Repo: d0e73e2ac6a6 Vineet Gupta Tue Jan 17 11:09:18 2017 -0800 Description: ARC: Revert "ARC: mm: IOC: Don't enable IOC by default" ------The programming model has been fixed with prev patches so re-enable it by default

This reverts commit 23cb1f644019bac49d87b4dd7c1eac0569cc4f53.

ARC: mm: split arc_cache_init to allow __init reaping of bulk ------arc_cache_init() is called for each core so can't be tagged __init. However bulk of it is only executed by master core and thus is candidate for __init reaping.

So split it up to allow that.

ARCv2: IOC: Use actual memory size to setup aperture size ------vs. fixed 512M before.

But this still assumes that all of memory is under IOC which may not be true for the SoC. Improve that later when this becomes a real issue, by specifying this from DT.

ARCv2: IOC: Adhere to progamming model guidelines to avoid DMA corruption ------On AXS103 release bitfiles, DMA data corruptions were seen because IOC setup was not following the recommended way in documentation.

Flipping IOC on when caches are enabled or coherency transactions are in flight, might cause some of the memory operations to not observe coherency as expected.

So strictly follow the programming model recommendations as documented in comment header above arc_ioc_setup()

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ARCv2: IOC: refactor the IOC and SLC operations into own functions ------Move IOC setup into arc_ioc_setup() - Move SLC disabling into arc_slc_disable()

ARC: mmu: clarify the MMUv3 programming model ------

ARC: mm: arc700: Don't assume 2 colours for aliasing VIPT dcache ------An ARC700 customer reported linux boot crashes when upgrading to bigger L1 dcache (64K from 32K). Turns out they had an aliasing VIPT config and current code only assumed 2 colours, while theirs had 4. So default to 4 colours and complain if there are fewer. Ideally this needs to be a Kconfig option, but heck that's too much of hassle for a single user.

ARC: mm: No need to save cache version in @cpuinfo ------Historical MMU revisions have been paired with Cache revision updates which are captured in MMU and Cache Build Configuration Registers respectively.

This was used in boot code to check for configurations mismatches, speically in simulations (such as running with non existent caches, non pairing MMU and Cache version etc). This can instead be inferred from other cache params such as line size. So remove @ver from post processed @cpuinfo which could be used later to save soem other interesting info.

147 arch\arc\mm\cache.c#0043 148 arch\arc\mm\cache.c#0057 149 arch\arc\mm\cache.c#0107 150 arch\arc\mm\cache.c#0155 151 arch\arc\mm\cache.c#0179 152 arch\arc\mm\cache.c#0277 Review: COMMENT stecan Thu, 11 Jan 2018 07:26:18 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:18 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:26:18 +0100

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Short Description: stecan Thu, 11 Jan 2018 07:26:18 +0100 Automatic commented! 153 arch\arc\mm\cache.c#0465 154 arch\arc\mm\cache.c#0505 155 arch\arc\mm\cache.c#0621 156 arch\arc\mm\cache.c#0981 157 arch\arc\mm\cache.c#0998 158 arch\arc\mm\cache.c#1000 159 arch\arc\mm\cache.c#1003 160 arch\arc\mm\cache.c#1011 Review: COMMENT stecan Thu, 11 Jan 2018 07:26:18 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:18 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:26:18 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:18 +0100 Automatic commented! 161 arch\arc\mm\cache.c#1016 162 arch\arc\mm\cache.c#1019 163 arch\arc\mm\cache.c#1033 164 arch\arc\mm\cache.c#1040 165 arch\arc\mm\cache.c#1053 166 arch\arc\mm\cache.c#1063 167 arch\arc\mm\cache.c#1065 168 arch\arc\mm\cache.c#1072 169 arch\arc\mm\cache.c#1076 170 arch\arc\mm\cache.c#1080 171 arch\arc\mm\cache.c#1083 172 arch\arc\mm\cache.c#1084 173 arch\arc\mm\cache.c#1097

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174 arch\arc\mm\dma.c#0161 Repo: 8a3385d2d47c Alexander Wed Dec 14 15:04:29 2016 -0800 Description: arch/arc: add option to skip sync on DMA mapping ------Patch series "Add support for DMA writable pages being writable by the network stack", v3.

The first 19 patches in the set add support for the DMA attribute DMA_ATTR_SKIP_CPU_SYNC on multiple platforms/architectures. This is needed so that we can flag the calls to dma_map/unmap_page so that we do not invalidate cache lines that do not currently belong to the device. Instead we have to take care of this in the driver via a call to sync_single_range_for_cpu prior to freeing the Rx page.

Patch 20 adds support for dma_map_page_attrs and dma_unmap_page_attrs so that we can unmap and map a page using the DMA_ATTR_SKIP_CPU_SYNC attribute.

Patch 21 adds support for freeing a page that has multiple references being held by a single caller. This way we can free page fragments that were allocated by a given driver.

The last 2 patches use these updates in the igb driver, and lay the groundwork to allow for us to reimplement the use of build_skb.

This patch (of 23):

This change allows us to pass DMA_ATTR_SKIP_CPU_SYNC which allows us to avoid invoking cache line invalidation if the driver will just handle it later via a sync_for_cpu or sync_for_device call.

Link: http://lkml.kernel.org/r/20161110113419.76501.38491.stgit@ahduyck-blue- test.jf.intel.com

175 arch\arc\mm\init.c#0043 Repo: e497c8e52a83 Vineet Gupta Wed Jan 18 12:59:21 2017 -0800 Description: ARCv2: IOC: Use actual memory size to setup aperture size ------vs. fixed 512M before.

But this still assumes that all of memory is under IOC which may not be true for the SoC. Improve that later when this becomes a real issue, by specifying this from DT.

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arch\arc\plat-eznps\include\plat\ 177 arch\arc\plat-eznps\include\plat\ctop.h#0049 Repo: 09dcd1958be4 Noam Wed Nov 16 08:31:11 2016 +0200 Description: soc: Support for NPS HW scheduling ------This new header file is for NPS400 SoC (part of ARC architecture). The header file includes macros for save/restore of HW scheduling. The control of HW scheduling is achieved by writing core registers. This code was moved from arc/plat-eznps so it can be used from drivers/clocksource/, available only for CONFIG_EZNPS_MTM_EXT.

ARC: [plat-eznps] Use dedicated identity auxiliary register. ------With generic "identity" num of CPUs is limited to 256 (8 bit). We use our alternative AUX register GLOBAL_ID (12 bit). Now we can support up to 4096 CPUs.

178 arch\arc\plat-eznps\include\plat\ctop.h#0051 arch\arm\ 179 arch\arm\Kconfig#0706 Repo: d4032ccc406f Arnd Wed Jan 4 16:12:17 2017 +0100 Description: Merge tag 'samsung-soc-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into fixes ------Samsung mach/soc update for v4.10:

1. Minor cleanup in smp_operations. 2. Another step in switching s3c24xx to new DMA API. 3. Drop fixed requirement for HZ=200 on Samsung platforms.

* tag 'samsung-soc-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: Drop fixed 200 Hz timer requirement from Samsung platforms ARM: S3C24XX: Add DMA slave maps for remaining s3c24xx SoCs

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ARM: EXYNOS: Remove smp_init_cpus hook from platsmp.c

Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM SoC platform updates from Arnd Bergmann: "These are updates for platform specific code on 32-bit ARM machines, essentially anything that can not (yet) be expressed using DT files.

Noteworthy changes include:

- Added support for the TI DRA71x family of SoCs in mach-omap2, this is an new variant of the the DRA72x/DRA74x automotive infotainment chips we already supported for a while.

- Added support for the ST STM32F746 SoC, the first Cortex-M7 based microcontroller we support, related to the smaller STM32F4 family.

- Renesas adds support for r8a7743 and r8a7745 in mach-shmobile, see http://elinux.org/RZ-G

- SMP is now supported on the OX820 platform

- A lot of code in mach-omap2 gets removed as a follow-up to removing support for board files in the previous release

- Davinci has some new work to improve USB support

- For i.MX, the performance monitor now supports profiling the memory controller using ''"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (95 commits) ARM: davinci: da830-evm: use gpio descriptor for mmc pins ARM: davinci: da850-evm: use gpio descriptor for mmc pins ARM: davinci: hawk: use gpio descriptor for mmc pins ARM: ARTPEC-6: add select MFD_SYSCON to MACH_ARTPEC6 ARM: davinci: da8xx: Fix ohci device name ARM: oxnas: Add OX820 config and makefile entry ARM: oxnas: Add OX820 SMP support ARM: davinci: PM: fix build when da850 not compiled in ARM: orion5x: remove legacy support of ls-chl ARM: integrator: drop EBI access use syscon ARM: BCM5301X: Add back handler ignoring external imprecise aborts ARM: davinci: PM: support da8xx DT platforms ARM: davinci: PM: cleanup: remove references to pdata ARM: davinci: PM: rework init, remove platform device ARM: Kconfig: Introduce MACH_STM32F746 flag ARM: mach-stm32: Add a new SOC - STM32F746 ARM: shmobile: document SK-RZG1E board

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ARM: shmobile: r8a7745: basic SoC support ARM: imx: mach-imx6ul: add imx6ull support ARM: zynq: Reserve correct amount of non-DMA RAM ...

ARM: Drop fixed 200 Hz timer requirement from Samsung platforms ------All Samsung platforms, including the Exynos, are selecting HZ_FIXED with 200 Hz. Unfortunately in case of multiplatform image this affects also other platforms when Exynos is enabled.

This looks like an very old legacy code, dating back to initial upstreaming of S3C24xx. Probably it was required for s3c24xx timer driver, which was removed in commit ad38bdd15d5b ("ARM: SAMSUNG: Remove unused plat-samsung/time.c").

Since then, this fixed 200 Hz spread everywhere, including out-of-tree Samsung kernels (SoC vendor's and Tizen's). I believe this choice was rather an effect of coincidence instead of conscious choice.

On S3C24xx, the PWM counter is only 16 bit wide, and with the typical 12MHz input clock that overflows every 5.5ms. This works with HZ=200 or higher but not with HZ=100 which needs a 10ms interval between ticks. On Later chips (S3C64xx, S5P and EXYNOS), the counter is 32 bits and does not have this problem.

The new samsung_pwm_timer driver solves the problem by scaling the input clock by a factor of 50 on S3C24xx, which makes it less accurate but allows HZ=100 as well as CONFIG_NO_HZ with fewer wakeups.

Few perf mem and sched tests on Odroid XU3 board (Exynos5422, 4x Cortex A7, 4x Cortex A15) show no regressions when switching from 200 Hz to other values.

ARM: virt: Select ARM_GIC_V3_ITS ------This patch allows ARM guests to use GICv3 ITS on an arm64 host

ARM: Kconfig: Introduce MACH_STM32F746 flag ------This patch introduces the MACH_STM32F746 to make possible to only select STM32F746 pinctrl driver

By default, all the MACH_STM32Fxxx flags will be set with STM32 defconfig.

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180 arch\arm\Kconfig#0891 181 arch\arm\Kconfig#1505 182 arch\arm\Makefile#0194 Repo: 66d466722c39 Linus Thu Dec 15 16:06:15 2016 -0800 Description: Merge branch 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm ------Pull ARM updates from Russell King:

- an update for clkdev registration error detection to simplify users

- add cpu capacity parsing from DT

- support for larger cachelines found on UniPhier caches

- documentation for udelay constants

- properly tag assembly function declarations

- remove unnecessary indirection of asm/mach-types.h

- switch to syscall table based generation to simplify future additions of system calls, along with correpsonding commit for pkey syscalls

- remove redundant sa1101 header file

- RONX protect modules when they're in the vmalloc region

* 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: ARM: mm: allow set_memory_*() to be used on the vmalloc region ARM: mm: fix set_memory_*() bounds checks ARM: 8631/1: clkdev: Detect errors in clk_hw_register_clkdev() for mass registration ARM: 8629/1: vfp: properly tag assembly function declarations in C code ARM: 8622/3: add sysfs cpu_capacity attribute ARM: 8621/3: parse cpu capacity-dmips-mhz from DT ARM: 8623/1: mm: add ARM_L1_CACHE_SHIFT_7 for UniPhier outer cache ARM: Update mach-types ARM: sa1100: remove SA-1101 header file ARM: 8619/1: udelay: document the various constants ARM: wire up new pkey syscalls ARM: convert to generated tables ARM: remove indirection of asm/mach-types.h

ARM: oxnas: Add OX820 config and makefile entry ------Refactor the oxnas Kconfig entries among the OX810SE and OX820 configs, and add the files to support the OX820 SMP feature.

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ARM: convert to generated system call tables ------Convert ARM to use a similar mechanism to x86 to generate the unistd.h system call numbers and the various kernel system call tables. This means that rather than having to edit three places (asm/unistd.h for the total number of system calls, uapi/asm/unistd.h for the system call numbers, and arch/arm/kernel/calls.S for the call table) we have only one place to edit, making the process much more simple.

The scripts have knowledge of the table padding requirements, so there's no need to worry about __NR_syscalls not fitting within the immediate constant field of ALU instructions anymore.

ARM: remove indirection of asm/mach-types.h ------Arrange for mach-types.h to be directly generated in the relevant path, so we don't need a one-liner file in arch/arm/include/asm/.

183 arch\arm\Makefile#0315 184 arch\arm\Makefile#0319 arch\arm\boot\dts\ 185 arch\arm\boot\dts\am335x-baltos-ir2110.dts#0057 Repo: f5c59d165af1 Yegor Wed Nov 23 16:49:26 2016 +0100 Description: ARM: dts: am335x-baltos: use phy-phandle declarations ------phy-phandle is now a preferred method to reference a PHY device. Especially in regards to cpsw it enables PHY specific settings like max-speed etc. being specified in DTS.

186 arch\arm\boot\dts\am335x-baltos-ir2110.dts#0064 187 arch\arm\boot\dts\am335x-baltos-ir2110.dts#0066 188 arch\arm\boot\dts\am335x-baltos-ir2110.dts#0070 189 arch\arm\boot\dts\am335x-baltos-ir2110.dts#0072 190 arch\arm\boot\dts\am335x-baltos-ir3220.dts#0112 Repo: f5c59d165af1 Yegor Wed Nov 23 16:49:26 2016 +0100 Description: ARM: dts: am335x-baltos: use phy-phandle declarations ------phy-phandle is now a preferred method to reference a PHY device.

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Especially in regards to cpsw it enables PHY specific settings like max-speed etc. being specified in DTS.

191 arch\arm\boot\dts\am335x-baltos-ir3220.dts#0115 192 arch\arm\boot\dts\am335x-baltos-ir5221.dts#0117 Repo: f5c59d165af1 Yegor Wed Nov 23 16:49:26 2016 +0100 Description: ARM: dts: am335x-baltos: use phy-phandle declarations ------phy-phandle is now a preferred method to reference a PHY device. Especially in regards to cpsw it enables PHY specific settings like max-speed etc. being specified in DTS.

ARM: dts: am335x-baltos-ir5221: use both musb channels in host mode ------

193 arch\arm\boot\dts\am335x-baltos-ir5221.dts#0130 194 arch\arm\boot\dts\am335x-baltos-ir5221.dts#0133 195 arch\arm\boot\dts\am335x-baltos.dtsi#0367 Repo: f5c59d165af1 Yegor Wed Nov 23 16:49:26 2016 +0100 Description: ARM: dts: am335x-baltos: use phy-phandle declarations ------phy-phandle is now a preferred method to reference a PHY device. Especially in regards to cpsw it enables PHY specific settings like max-speed etc. being specified in DTS.

ARM: dts: am335x-baltos: don't reset gpio3 block ------This change is needed in order to enable some hardware components from bootloader.

196 arch\arm\boot\dts\am335x-baltos.dtsi#0372 197 arch\arm\boot\dts\am335x-baltos.dtsi#0412 198 arch\arm\boot\dts\am335x-bone-common.dtsi#0313 Repo: be53e38f0df2 Milo Kim Fri Dec 9 15:28:31 2016 +0900 Description: dt-bindings: mfd: Remove TPS65217 interrupts ------Interrupt numbers are from the datasheet, so no need to keep them in the ABI. Use the number in the DT file.

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ARM: dts: am335x: Fix the interrupt name of TPS65217 ------Use 'interrupt-names' for getting the charger interrupt number.

Fixes: 1934e89a769b ("ARM: dts: am335x: Add the charger interrupt")

ARM: dts: AM335X-bone-common: Add the internal and external clock nodes for rtc ------rtc can either be supplied from internal 32k clock or external crystal generated 32k clock. Internal clock is SoC specific and the external clock is board dependent. Assigning the corresponding clocks.

ARM: dts: am335x: Add the power button interrupt ------This enables the power button driver gets corresponding IRQ number by using platform_get_irq().

ARM: dts: am335x: Add the charger interrupt ------This enables the charger driver gets corresponding IRQ number by using platform_get_irq_byname() helper.

ARM: dts: am335x: Support the PMIC interrupt ------AM335x bone based boards have the PMIC interrupt named NMI which is connected to TPS65217 device. AM335x main interrupt controller provides it and the number is 7.

199 arch\arm\boot\dts\am335x-bone-common.dtsi#0319 200 arch\arm\boot\dts\am335x-bone-common.dtsi#0411 201 arch\arm\boot\dts\am335x-boneblack.dts#0082 Repo: a291b6b3d287 Jyri Sarha Thu Nov 17 22:13:42 2016 +0200 Description: ARM: dts: am335x-boneblack: Add blue-and-red-wiring -property to LCDC node ------Add blue-and-red-wiring -property to LCDC node. Also adds comments on how to get support 24 bit RGB mode. After this patch am335x-boneblack support RGB565, BGR888, and XBGR8888 color formats. See details in Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt.

The BBB has straight color wiring from am335x to tda19988, however the tda19988 can be configured to cross the blue and red wires. The

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comments show how to do that with video-ports property of tda19988 node and how to tell LCDC that blue and red wires are crossed, with blue-and-red-wiring LCDC node property. This changes supported color formats from 16 bit RGB and 24 bit BGR to 16 bit BGR and 24 bit RGB.

202 arch\arm\boot\dts\am335x-boneblack.dts#0106 203 arch\arm\boot\dts\am335x-evm.dts#0786 Repo: 542a7707ce8c Keerthy Thu Oct 27 11:18:07 2016 +0530 Description: ARM: dts: AM335X-evm: Add the internal and external clock nodes for rtc ------rtc can either be supplied from internal 32k clock or external crystal generated 32k clock. Internal clock is SoC specific and the external clock is board dependent. Assigning the corresponding clocks.

204 arch\arm\boot\dts\am335x-evmsk.dts#0718 Repo: 3fb5c894f6db Keerthy Thu Oct 27 11:18:08 2016 +0530 Description: ARM: dts: AM335X-evmsk: Add the internal and external clock nodes for rtc ------rtc can either be supplied from internal 32k clock or external crystal generated 32k clock. Internal clock is SoC specific and the external clock is board dependent. Assigning the corresponding clocks.

ARM: dts: am335x-evmsk: Add blue-and-red-wiring -property to lcdc node ------Add blue-and-red-wiring -property to lcdc node. The am335x-evmsk has blue and red wires crossed to get 24-bit RGB (and 16-bit BGR) support. After this patch am335x-evmsk supports BGR565, RGB888, and XRGB8888 color formats. See details in Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt.

205 arch\arm\boot\dts\am335x-icev2.dts#0046 Repo: 6ca36a455e27 Lokesh Vutla Wed Jan 4 10:39:40 2017 +0530 Description: ARM: dts: am335x-icev2: Remove the duplicated pinmux setting ------There is no mmc sd card detect on am335x-ice board. But the spi0_cs1 pin being configured as mmcsd_cd. Removing it fixes the below warning during boot:

pinctrl-single 44e10800.pinmux: pin 44e10960.0 already requested by 48030000.spi; cannot claim for 48060000.mmc

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ARM: dts: am335x-icev2: Add ADC support ------7 of the 8 ADC inputs on the am335x are connected to the Industrial I/O header, add this here.

ARM: dts: am335x-icev2: Disable Industrial I/O LEDs and fix naming ------The LEDs tied to the Industrial I/O output pins are meant for providing status feed-back and are not the primary use for the pins. Disable this use by default. Also unify the LED naming across IDK platforms.

ARM: dts: am335x-icev2: Add Industrial input support ------The SN65HVS882 is available on the AM335x-ICEv2 and is attached to SPI0. Input is attached to the I/O header.

206 arch\arm\boot\dts\am335x-icev2.dts#0049 207 arch\arm\boot\dts\am335x-icev2.dts#0055 208 arch\arm\boot\dts\am335x-icev2.dts#0061 209 arch\arm\boot\dts\am335x-icev2.dts#0067 210 arch\arm\boot\dts\am335x-icev2.dts#0073 211 arch\arm\boot\dts\am335x-icev2.dts#0079 212 arch\arm\boot\dts\am335x-icev2.dts#0085 213 arch\arm\boot\dts\am335x-icev2.dts#0091 214 arch\arm\boot\dts\am335x-icev2.dts#0173 215 arch\arm\boot\dts\am335x-icev2.dts#0190 216 arch\arm\boot\dts\am335x-icev2.dts#0228 217 arch\arm\boot\dts\am33xx.dtsi#0019 Repo: 1d8d6d3f2f7d Javier Mon Dec 19 11:44:37 2016 -0300 Description: ARM: dts: am33xx: Add an empty chosen node to top level DTSI ------Commit f8bf01611c99 ("ARM: dts: am33xx: Remove skeleton.dtsi usage") removed the skeleton.dtsi usage since we want to get rid of it.

But this can cause issues when booting a kernel with a boot-loader that doesn't create a chosen node if this isn't present in the DTB since the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info.

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Fixes: f8bf01611c99 ("ARM: dts: am33xx: Remove skeleton.dtsi usage")

Merge tag 'omap-for-v4.10/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt ------Device tree changes for omaps for v4.10 merge window:

- A series of patches to configure tps65217 PMIC interrupts for power button, charger and usb and use them on am335x

- Configure EEPROM, LEDs and USR1 button for omap5 boards

- Add tscadc DMA properites for am33xx and am4372

- Configure baltos-ir5221 both musb channels to host mode

- Configure internal and external RTC clocks for am335x boards

- Don't reset gpio3 block on baltos

- Remove pinmux for dra72-evm for erratum i869, fix the regulators and seprate out tps65917 support

- Add dra718-evm support

- Add minimal droid 4 xt894 support

* tag 'omap-for-v4.10/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux- omap: (22 commits) ARM: dts: Add minimal support for motorola droid 4 xt894 ARM: dts: Add support for dra718-evm ARM: dts: dra72: Add separate dtsi for tps65917 ARM: dts: dra72-evm: Fix modelling of regulators ARM: dts: dra72-evm: Remove pinmux configurations for erratum i869 ARM: dts: am335x-baltos: don't reset gpio3 block ARM: dts: AM335X-evmsk: Add the internal and external clock nodes for rtc ARM: dts: AM335X-evm: Add the internal and external clock nodes for rtc ARM: dts: AM335X-bone-common: Add the internal and external clock nodes for rtc ARM: dts: am335x-baltos-ir5221: use both musb channels in host mode ARM: dts: am4372: add DMA properties for tscadc ARM: dts: am33xx: add DMA properties for tscadc ARM: dts: omap5 uevm: add USR1 button ARM: dts: omap5 uevm: add LEDs ARM: dts: omap5 uevm: add EEPROM ARM: dts: am335x: Add the power button interrupt ARM: dts: am335x: Add the charger interrupt dt-bindings: mfd: Provide human readable defines for TPS65217 interrupts ARM: dts: am335x: Support the PMIC interrupt ARM: dts: tps65217: Add the power button device ...

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ARM: dts: AM335X-bone-common: Add the internal and external clock nodes for rtc ------rtc can either be supplied from internal 32k clock or external crystal generated 32k clock. Internal clock is SoC specific and the external clock is board dependent. Assigning the corresponding clocks.

ARM: dts: am33xx: add DMA properties for tscadc ------Add DMA properties for tscadc

ARM: dts: Add #pinctrl-cells for pinctrl-single instances ------Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the driver changes as the driver supports also the legacy binding without #pinctrl-cells.

218 arch\arm\boot\dts\am33xx.dtsi#0134 219 arch\arm\boot\dts\am33xx.dtsi#0142 220 arch\arm\boot\dts\am33xx.dtsi#0511 221 arch\arm\boot\dts\am33xx.dtsi#0863 222 arch\arm\boot\dts\am3517.dtsi#0069 Repo: be76fd3197df Tony Mon Nov 7 08:27:49 2016 -0700 Description: ARM: dts: Add #pinctrl-cells for pinctrl-single instances ------Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the driver changes as the driver supports also the legacy binding without #pinctrl-cells.

223 arch\arm\boot\dts\am4372.dtsi#0019 Repo: ce95077d0cdf Javier Mon Dec 19 11:44:38 2016 -0300 Description: ARM: dts: am4372: Add an empty chosen node to top level DTSI ------Commit 75813028bbd7 ("ARM: dts: am4372: Remove skeleton.dtsi usage")

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removed the skeleton.dtsi usage since we want to get rid of it.

But this can cause issues when booting a kernel with a boot-loader that doesn't create a chosen node if this isn't present in the DTB since the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info.

Fixes: 75813028bbd7 ("ARM: dts: am4372: Remove skeleton.dtsi usage")

Merge tag 'omap-for-v4.10/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt ------Device tree changes for omaps for v4.10 merge window:

- A series of patches to configure tps65217 PMIC interrupts for power button, charger and usb and use them on am335x

- Configure EEPROM, LEDs and USR1 button for omap5 boards

- Add tscadc DMA properites for am33xx and am4372

- Configure baltos-ir5221 both musb channels to host mode

- Configure internal and external RTC clocks for am335x boards

- Don't reset gpio3 block on baltos

- Remove pinmux for dra72-evm for erratum i869, fix the regulators and seprate out tps65917 support

- Add dra718-evm support

- Add minimal droid 4 xt894 support

* tag 'omap-for-v4.10/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux- omap: (22 commits) ARM: dts: Add minimal support for motorola droid 4 xt894 ARM: dts: Add support for dra718-evm ARM: dts: dra72: Add separate dtsi for tps65917 ARM: dts: dra72-evm: Fix modelling of regulators ARM: dts: dra72-evm: Remove pinmux configurations for erratum i869 ARM: dts: am335x-baltos: don't reset gpio3 block ARM: dts: AM335X-evmsk: Add the internal and external clock nodes for rtc ARM: dts: AM335X-evm: Add the internal and external clock nodes for rtc ARM: dts: AM335X-bone-common: Add the internal and external clock nodes for rtc ARM: dts: am335x-baltos-ir5221: use both musb channels in host mode ARM: dts: am4372: add DMA properties for tscadc ARM: dts: am33xx: add DMA properties for tscadc ARM: dts: omap5 uevm: add USR1 button ARM: dts: omap5 uevm: add LEDs

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ARM: dts: omap5 uevm: add EEPROM ARM: dts: am335x: Add the power button interrupt ARM: dts: am335x: Add the charger interrupt dt-bindings: mfd: Provide human readable defines for TPS65217 interrupts ARM: dts: am335x: Support the PMIC interrupt ARM: dts: tps65217: Add the power button device ...

ARM: dts: am4372: add DMA properties for tscadc ------Add DMA properties for tscadc

ARM: dts: Add #pinctrl-cells for pinctrl-single instances ------Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the driver changes as the driver supports also the legacy binding without #pinctrl-cells.

ARM: dts: am4372: Add missing unit name to memory nodes ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

224 arch\arm\boot\dts\am4372.dtsi#0193 225 arch\arm\boot\dts\am4372.dtsi#0876 226 arch\arm\boot\dts\am437x-idk-evm.dts#0120 Repo: c0a0ee469351 Andrew F. Fri Oct 7 09:44:26 2016 -0500 Description: ARM: dts: am437x-idk: Add Industrial output support ------The TPIC2810 is available on the AM437x IDK and is attached to I2C1. Output is attached to the I/O header and 10 LEDs.

ARM: dts: am437x-idk: Add Industrial input support ------The SN65HVS882 is available on the AM437x IDK and is attached to SPI1. Input is attached to the I/O header.

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227 arch\arm\boot\dts\am437x-idk-evm.dts#0233 228 arch\arm\boot\dts\am437x-idk-evm.dts#0363 229 arch\arm\boot\dts\am437x-idk-evm.dts#0372 230 arch\arm\boot\dts\am437x-idk-evm.dts#0410 231 arch\arm\boot\dts\am572x-idk.dts#0026 Repo: 1a38de880992 Kishon Vijay Fri Dec 30 13:37:20 2016 +0530 Description: ARM: dts: am572x-idk: Add gpios property to control PCIE_RESETn ------Add 'gpios' property to pcie1 dt node and populate it with GPIO3_23 in order to drive PCIE_RESETn high.

This gets PCIe cards to be detected in AM572X IDK board.

ARM: dts: am57xx-idk: Support VBUS detection on USB2 port ------VBUS detection is available on the board via the palmas PMIC. Use extcon-palmas driver instead of extcon-gpio-usb driver.

ARM: dts: am57xx-idk: Add Industrial input support ------The SN65HVS882 is available on both the AM572x and AM571x IDKs and is attached to SPI1. Input is attached to the I/O header. The load trigger is attached to GPIO3_19 on the AM572x IDK.

232 arch\arm\boot\dts\am572x-idk.dts#0079 233 arch\arm\boot\dts\am572x-idk.dts#0086 234 arch\arm\boot\dts\am57xx-beagle-x15-common.dtsi#0207 Repo: 1f166499ce00 Keerthy Thu Nov 10 10:39:19 2016 +0530 Description: ARM: dts: am57xx-beagle-x15-common: Add overide powerhold property ------The PMICs have POWERHOLD set by default which prevents PMIC shutdown even on DEV_CTRL On bit set to 0 as the Powerhold has higher priority. So to enable pmic power off this property lets one over ride the default value and enable pmic power off.

235 arch\arm\boot\dts\am57xx-idk-common.dtsi#0046 Repo: 5acd016c8893 Roger Mon Dec 12 11:58:05 2016 +0200 Description: ARM: dts: am57xx-idk: Put USB2 port in peripheral mode ------

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USB2 port can be operated in dual-role mode but till we have dual-role support in dwc3 driver let's limit this port to peripheral mode.

If we don't do so it defaults to host mode. USB1 port is meant for host only operation and we don't want both ports in host only mode.

ARM: dts: am57xx-idk: Support VBUS detection on USB2 port ------VBUS detection is available on the board via the palmas PMIC. Use extcon-palmas driver instead of extcon-gpio-usb driver.

ARM: dts: am57xx-idk-common: Add overide powerhold property ------The PMICs have POWERHOLD set by default which prevents PMIC shutdown even on DEV_CTRL On bit set to 0 as the Powerhold has higher priority. So to enable pmic power off this property lets one over ride the default value and enable pmic power off.

ARM: dts: am57xx-idk: Add Industrial output support ------The TPIC2810 is available on both the AM571x and the AM572x IDKs and is attached to I2C1. Output is attached to the I/O header and 10 LEDs.

ARM: dts: am57xx-idk: Add Industrial input support ------The SN65HVS882 is available on both the AM572x and AM571x IDKs and is attached to SPI1. Input is attached to the I/O header. The load trigger is attached to GPIO3_19 on the AM572x IDK.

236 arch\arm\boot\dts\am57xx-idk-common.dtsi#0112 237 arch\arm\boot\dts\am57xx-idk-common.dtsi#0306 238 arch\arm\boot\dts\am57xx-idk-common.dtsi#0316 239 arch\arm\boot\dts\am57xx-idk-common.dtsi#0379 240 arch\arm\boot\dts\armada-370-db.dts#0070 Repo: 6f477f43f9de Gregory Sun Nov 6 09:29:35 2016 +0100 Description: ARM: dts: armada-370-xp: Fixup memory DT warning ------memory has a reg property so the unit name should contain an address.

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ARM: dts: armada-370: Fixup pcie DT warnings ------PCIe has a ranges property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-370-xp: Fixup mdio DT warning ------MDIO has a reg property so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

241 arch\arm\boot\dts\armada-370-db.dts#0089 242 arch\arm\boot\dts\armada-370-db.dts#0185 243 arch\arm\boot\dts\armada-370-db.dts#0264 244 arch\arm\boot\dts\armada-370-dlink-dns327l.dts#0065 Repo: 6f477f43f9de Gregory Sun Nov 6 09:29:35 2016 +0100 Description: ARM: dts: armada-370-xp: Fixup memory DT warning ------memory has a reg property so the unit name should contain an address.

ARM: dts: armada-370: Fixup pcie DT warnings ------PCIe has a ranges property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

245 arch\arm\boot\dts\armada-370-dlink-dns327l.dts#0075 246 arch\arm\boot\dts\armada-370-dlink-dns327l.dts#0265 247 arch\arm\boot\dts\armada-370-mirabox.dts#0057 Repo: 6f477f43f9de Gregory Sun Nov 6 09:29:35 2016 +0100 Description: ARM: dts: armada-370-xp: Fixup memory DT warning ------memory has a reg property so the unit name should contain an address.

ARM: dts: armada-370: Fixup pcie DT warnings ------PCIe has a ranges property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-370-xp: Fixup mdio DT warning

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------MDIO has a reg property so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

248 arch\arm\boot\dts\armada-370-mirabox.dts#0067 249 arch\arm\boot\dts\armada-370-mirabox.dts#0116 250 arch\arm\boot\dts\armada-370-mirabox.dts#0200 251 arch\arm\boot\dts\armada-370-netgear-rn102.dts#0059 Repo: 6f477f43f9de Gregory Sun Nov 6 09:29:35 2016 +0100 Description: ARM: dts: armada-370-xp: Fixup memory DT warning ------memory has a reg property so the unit name should contain an address.

ARM: dts: armada-370: Fixup pcie DT warnings ------PCIe has a ranges property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-370-xp: Fixup mdio DT warning ------MDIO has a reg property so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-370-rn102: add pinmuxing for i2c0 ------Up to now a working i2c bus depended on the bootloader to configure the pinmuxing. Make it explicit.

As a side effect this change makes i2c work in barebox.

ARM: dts: armada-370-rn102: drop specification of compatible for i2c0 ------The compatible string is already provided by armada-370.dtsi.

252 arch\arm\boot\dts\armada-370-netgear-rn102.dts#0069 253 arch\arm\boot\dts\armada-370-netgear-rn102.dts#0102

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254 arch\arm\boot\dts\armada-370-netgear-rn102.dts#0123 255 arch\arm\boot\dts\armada-370-netgear-rn102.dts#0125 256 arch\arm\boot\dts\armada-370-netgear-rn102.dts#0260 257 arch\arm\boot\dts\armada-370-netgear-rn104.dts#0059 Repo: 6f477f43f9de Gregory Sun Nov 6 09:29:35 2016 +0100 Description: ARM: dts: armada-370-xp: Fixup memory DT warning ------memory has a reg property so the unit name should contain an address.

ARM: dts: armada-370: Fixup pcie DT warnings ------PCIe has a ranges property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-370-xp: Fixup mdio DT warning ------MDIO has a reg property so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-370-rn104: drop specification of compatible for i2c0 ------The compatible string is already provided by armada-370.dtsi.

ARM: dts: armada-370-rn104: add pinmuxing for i2c0 ------Up to now a working i2c bus depended on the bootloader to configure the pinmuxing. Make it explicit.

As a side effect this change makes i2c work in barebox.

258 arch\arm\boot\dts\armada-370-netgear-rn104.dts#0069 259 arch\arm\boot\dts\armada-370-netgear-rn104.dts#0096 260 arch\arm\boot\dts\armada-370-netgear-rn104.dts#0129 261 arch\arm\boot\dts\armada-370-netgear-rn104.dts#0131 262 arch\arm\boot\dts\armada-370-netgear-rn104.dts#0282

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263 arch\arm\boot\dts\armada-370-rd.dts#0070 Repo: 9e622af05c2e Gregory Sun Nov 6 10:59:19 2016 +0100 Description: ARM: dts: armada-370-xp: Remove button address and fixup names ------The gpio-key nodes do not have a reg property, so remove the address from the unit name.

ARM: dts: armada-370-xp: Remove address from dsa unit name ------The dsa node does not have a reg property, so remove the address from the unit name.

ARM: dts: armada-370-xp: Fixup memory DT warning ------memory has a reg property so the unit name should contain an address.

ARM: dts: armada-370: Fixup pcie DT warnings ------PCIe has a ranges property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-370-xp: Fixup mdio DT warning ------MDIO has a reg property so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

264 arch\arm\boot\dts\armada-370-rd.dts#0080 265 arch\arm\boot\dts\armada-370-rd.dts#0105 266 arch\arm\boot\dts\armada-370-rd.dts#0149 267 arch\arm\boot\dts\armada-370-rd.dts#0199 268 arch\arm\boot\dts\armada-370-rd.dts#0238 269 arch\arm\boot\dts\armada-370-rd.dts#0240 270 arch\arm\boot\dts\armada-370-seagate-nas-4bay.dts#0031 Repo: 8d977093bf54 Gregory Sat Nov 5 19:20:09 2016 +0100 Description: ARM: dts: armada-370: Fixup pcie DT warnings ------PCIe has a ranges property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

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ARM: dts: armada-370-xp: Fixup mdio DT warning ------MDIO has a reg property so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

271 arch\arm\boot\dts\armada-370-seagate-nas-4bay.dts#0039 272 arch\arm\boot\dts\armada-370-seagate-nas-4bay.dts#0133 273 arch\arm\boot\dts\armada-370-seagate-nas-xbay.dtsi#0026 Repo: 9e622af05c2e Gregory Sun Nov 6 10:59:19 2016 +0100 Description: ARM: dts: armada-370-xp: Remove button address and fixup names ------The gpio-key nodes do not have a reg property, so remove the address from the unit name.

ARM: dts: armada-370-xp: Fixup memory DT warning ------memory has a reg property so the unit name should contain an address.

ARM: dts: armada-370: Fixup pcie DT warnings ------PCIe has a ranges property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-370-xp: Fixup mdio DT warning ------MDIO has a reg property so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

274 arch\arm\boot\dts\armada-370-seagate-nas-xbay.dtsi#0035 275 arch\arm\boot\dts\armada-370-seagate-nas-xbay.dtsi#0054 276 arch\arm\boot\dts\armada-370-seagate-nas-xbay.dtsi#0162 277 arch\arm\boot\dts\armada-370-seagate-nas-xbay.dtsi#0168 278 arch\arm\boot\dts\armada-370-seagate-nas-xbay.dtsi#0174 279 arch\arm\boot\dts\armada-370-seagate-nas-xbay.dtsi#0211

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280 arch\arm\boot\dts\armada-370-seagate-personal-cloud.dtsi#0027 Repo: 9e622af05c2e Gregory Sun Nov 6 10:59:19 2016 +0100 Description: ARM: dts: armada-370-xp: Remove button address and fixup names ------The gpio-key nodes do not have a reg property, so remove the address from the unit name.

ARM: dts: armada-370-xp: Fixup memory DT warning ------memory has a reg property so the unit name should contain an address.

ARM: dts: armada-370: Fixup pcie DT warnings ------PCIe has a ranges property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-370-xp: Fixup mdio DT warning ------MDIO has a reg property so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

281 arch\arm\boot\dts\armada-370-seagate-personal-cloud.dtsi#0036 282 arch\arm\boot\dts\armada-370-seagate-personal-cloud.dtsi#0054 283 arch\arm\boot\dts\armada-370-seagate-personal-cloud.dtsi#0110 284 arch\arm\boot\dts\armada-370-seagate-personal-cloud.dtsi#0116 285 arch\arm\boot\dts\armada-370-seagate-personal-cloud.dtsi#0122 286 arch\arm\boot\dts\armada-370-seagate-personal-cloud.dtsi#0146 287 arch\arm\boot\dts\armada-370--ds213j.dts#0073 Repo: baa2f7447e18 Gregory Sun Nov 6 11:05:32 2016 +0100 Description: ARM: dts: armada-370-xp: Fixup regulator DT warning ------regulator has a reg property so the unit name should contain an address.

ARM: dts: armada-370-xp: Fixup memory DT warning ------memory has a reg property so the unit name should contain an address.

ARM: dts: armada-370-xp: Fixup mdio DT warning

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------MDIO has a reg property so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

288 arch\arm\boot\dts\armada-370-synology-ds213j.dts#0130 289 arch\arm\boot\dts\armada-370-synology-ds213j.dts#0195 290 arch\arm\boot\dts\armada-370-synology-ds213j.dts#0208 291 arch\arm\boot\dts\armada-370-synology-ds213j.dts#0223 292 arch\arm\boot\dts\armada-370-xp.dtsi#0053 Repo: 1cb92a98a1a5 Gregory Sat Nov 5 19:35:12 2016 +0100 Description: ARM: dts: armada-370-xp: Remove skeleton.dtsi ------The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi").

These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future:

"Node /memory has a reg or ranges property, but no unit name"

ARM: dts: armada-370-xp: Fixup mdio DT warning ------MDIO has a reg property so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-370-xp: add node labels ------As it was previously done for kirkwood, this adds missing node labels to Armada 370 and XP common and SoC specific nodes to allow to reference them more easily.

ARM: dts: armada-370-xp: move the cpurst node in the common file ------The cpurst nodes are identical in armada-370.dtsi and armada-xp.dtsi files, so move it in the common armada-370-xp.dtsi file.

ARM: dts: mvebu: armada-370-xp: Add MBus mappings for all SPI devices ------This patch adds the static MBus mappings for all supported SPI devices (8 per controller) for the direct access SPI mode. They can be configured and enabled by setting these MBus mapping in the 'ranges' property of the

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per-board 'soc' node. If nothing is changed here, the default 'normal' (indirect) SPI mode is used.

293 arch\arm\boot\dts\armada-370-xp.dtsi#0089 294 arch\arm\boot\dts\armada-370-xp.dtsi#0099 295 arch\arm\boot\dts\armada-370-xp.dtsi#0109 296 arch\arm\boot\dts\armada-370-xp.dtsi#0119 297 arch\arm\boot\dts\armada-370-xp.dtsi#0129 298 arch\arm\boot\dts\armada-370-xp.dtsi#0145 299 arch\arm\boot\dts\armada-370-xp.dtsi#0217 300 arch\arm\boot\dts\armada-370-xp.dtsi#0222 301 arch\arm\boot\dts\armada-370-xp.dtsi#0227 302 arch\arm\boot\dts\armada-370-xp.dtsi#0231 303 arch\arm\boot\dts\armada-370-xp.dtsi#0239 304 arch\arm\boot\dts\armada-370-xp.dtsi#0246 305 arch\arm\boot\dts\armada-370-xp.dtsi#0260 306 arch\arm\boot\dts\armada-370-xp.dtsi#0275 307 arch\arm\boot\dts\armada-370-xp.dtsi#0284 308 arch\arm\boot\dts\armada-370-xp.dtsi#0294 309 arch\arm\boot\dts\armada-370.dtsi#0053 Repo: 3a729d7ccfb5 Gregory Sat Nov 5 19:40:45 2016 +0100 Description: ARM: dts: armada-370-xp: Fixup l2-cache DT warning ------l2-cache which is either an aurora-outer-cache or an aurora-system-cache has a reg property so the unit name should contain an address.

ARM: dts: armada-370-xp: Remove skeleton.dtsi ------The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi").

These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future:

"Node /memory has a reg or ranges property, but no unit name"

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ARM: dts: armada-370: Fixup pcie DT warnings ------PCIe has a ranges property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-370-xp: Use the node labels ------Use the node label when possible. As a result it flattens the device tree and it makes more visible the IP blocks specific to each SoC variant.

ARM: dts: armada-370-xp: add node labels ------As it was previously done for kirkwood, this adds missing node labels to Armada 370 and XP common and SoC specific nodes to allow to reference them more easily.

ARM: dts: armada-370-xp: move the cpurst node in the common file ------The cpurst nodes are identical in armada-370.dtsi and armada-xp.dtsi files, so move it in the common armada-370-xp.dtsi file.

310 arch\arm\boot\dts\armada-370.dtsi#0056 311 arch\arm\boot\dts\armada-370.dtsi#0075 312 arch\arm\boot\dts\armada-370.dtsi#0094 313 arch\arm\boot\dts\armada-370.dtsi#0111 314 arch\arm\boot\dts\armada-370.dtsi#0130 315 arch\arm\boot\dts\armada-370.dtsi#0139 316 arch\arm\boot\dts\armada-370.dtsi#0178 317 arch\arm\boot\dts\armada-370.dtsi#0188 318 arch\arm\boot\dts\armada-370.dtsi#0211 319 arch\arm\boot\dts\armada-370.dtsi#0218 320 arch\arm\boot\dts\armada-370.dtsi#0222 321 arch\arm\boot\dts\armada-370.dtsi#0256 322 arch\arm\boot\dts\armada-370.dtsi#0283

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323 arch\arm\boot\dts\armada-370.dtsi#0302 324 arch\arm\boot\dts\armada-370.dtsi#0345 325 arch\arm\boot\dts\armada-375-db.dts#0061 Repo: 1a15dca330e8 Gregory Thu Nov 10 00:51:54 2016 +0100 Description: ARM: dts: armada-375: Fixup memory DT warning ------memory has a reg property so the unit name should contain an address.

ARM: dts: armada-375: Use the node labels ------Use the node label when possible. As a result it flattens the device tree

326 arch\arm\boot\dts\armada-375-db.dts#0072 327 arch\arm\boot\dts\armada-375-db.dts#0083 328 arch\arm\boot\dts\armada-375-db.dts#0092 329 arch\arm\boot\dts\armada-375-db.dts#0099 330 arch\arm\boot\dts\armada-375-db.dts#0106 331 arch\arm\boot\dts\armada-375-db.dts#0110 332 arch\arm\boot\dts\armada-375-db.dts#0117 333 arch\arm\boot\dts\armada-375-db.dts#0122 334 arch\arm\boot\dts\armada-375-db.dts#0133 335 arch\arm\boot\dts\armada-375-db.dts#0147 336 arch\arm\boot\dts\armada-375-db.dts#0151 337 arch\arm\boot\dts\armada-375-db.dts#0155 338 arch\arm\boot\dts\armada-375-db.dts#0163 339 arch\arm\boot\dts\armada-375-db.dts#0168 340 arch\arm\boot\dts\armada-375-db.dts#0173 341 arch\arm\boot\dts\armada-375-db.dts#0176 342 arch\arm\boot\dts\armada-375-db.dts#0182 343 arch\arm\boot\dts\armada-375-db.dts#0190 344 arch\arm\boot\dts\armada-375-db.dts#0206

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345 arch\arm\boot\dts\armada-375-db.dts#0206 346 arch\arm\boot\dts\armada-375.dtsi#0048 Repo: 2f7132852038 Gregory Thu Nov 10 00:58:18 2016 +0100 Description: ARM: dts: armada-375: Fixup ethernet child DT warning ------Child of mvpp2 ethernet do not have a reg property so the unit name should not contain an address: remove them.

ARM: dts: armada-375: Remove skeleton.dtsi ------The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi").

These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future:

"Node /memory has a reg or ranges property, but no unit name"

ARM: dts: armada-375: Fixup pinctrl DT warnings ------pinctrl has a ranges property, so the unit name should contain an address.

ARM: dts: armada-375: Fixup pcie DT warnings ------PCIe has a range property, so the unit name should contain an address.

ARM: dts: armada-375: Fixup mdio DT warning ------MDIO has a reg property so the unit name should contain an address.

ARM: dts: armada-375: Add node labels ------As it was previously done for kirkwood and for aramda 370/XP, this adds missing node labels to Armada 375 and SoC specific nodes to allow to reference them more easily.

ARM: dts: mvebu: Update comment for main PLL frequency ------The actual frequency was updated in commit ae142bd99765 ("ARM: mvebu: Fix the main PLL frequency on Armada 375, 38x and 39x SoCs") but the comment was not updated. Update it now.

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347 arch\arm\boot\dts\armada-375.dtsi#0056 348 arch\arm\boot\dts\armada-375.dtsi#0070 349 arch\arm\boot\dts\armada-375.dtsi#0089 350 arch\arm\boot\dts\armada-375.dtsi#0094 351 arch\arm\boot\dts\armada-375.dtsi#0120 352 arch\arm\boot\dts\armada-375.dtsi#0130 353 arch\arm\boot\dts\armada-375.dtsi#0140 354 arch\arm\boot\dts\armada-375.dtsi#0150 355 arch\arm\boot\dts\armada-375.dtsi#0160 356 arch\arm\boot\dts\armada-375.dtsi#0187 357 arch\arm\boot\dts\armada-375.dtsi#0192 358 arch\arm\boot\dts\armada-375.dtsi#0208 359 arch\arm\boot\dts\armada-375.dtsi#0217 360 arch\arm\boot\dts\armada-375.dtsi#0227 361 arch\arm\boot\dts\armada-375.dtsi#0233 362 arch\arm\boot\dts\armada-375.dtsi#0240 363 arch\arm\boot\dts\armada-375.dtsi#0312 364 arch\arm\boot\dts\armada-375.dtsi#0387 365 arch\arm\boot\dts\armada-375.dtsi#0420 366 arch\arm\boot\dts\armada-375.dtsi#0433 367 arch\arm\boot\dts\armada-375.dtsi#0440 368 arch\arm\boot\dts\armada-375.dtsi#0445 369 arch\arm\boot\dts\armada-375.dtsi#0450 370 arch\arm\boot\dts\armada-375.dtsi#0460 371 arch\arm\boot\dts\armada-375.dtsi#0468 372 arch\arm\boot\dts\armada-375.dtsi#0478 373 arch\arm\boot\dts\armada-375.dtsi#0498 374 arch\arm\boot\dts\armada-375.dtsi#0518 375 arch\arm\boot\dts\armada-375.dtsi#0533

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376 arch\arm\boot\dts\armada-375.dtsi#0542 377 arch\arm\boot\dts\armada-375.dtsi#0552 378 arch\arm\boot\dts\armada-375.dtsi#0564 379 arch\arm\boot\dts\armada-375.dtsi#0585 380 arch\arm\boot\dts\armada-375.dtsi#0604 381 arch\arm\boot\dts\armada-375.dtsi#0621 382 arch\arm\boot\dts\armada-38x.dtsi#0664 Repo: ad0de58bfec9 Chris Wed Oct 26 12:52:42 2016 +1300 Description: ARM: dts: mvebu: Update comment for main PLL frequency ------The actual frequency was updated in commit ae142bd99765 ("ARM: mvebu: Fix the main PLL frequency on Armada 375, 38x and 39x SoCs") but the comment was not updated. Update it now.

383 arch\arm\boot\dts\armada-39x.dtsi#0576 Repo: ad0de58bfec9 Chris Wed Oct 26 12:52:42 2016 +1300 Description: ARM: dts: mvebu: Update comment for main PLL frequency ------The actual frequency was updated in commit ae142bd99765 ("ARM: mvebu: Fix the main PLL frequency on Armada 375, 38x and 39x SoCs") but the comment was not updated. Update it now.

ARM: dts: mvebu: armada-39x: enable rtc for all Armada-39x SoCs ------Despite that FS states that rtc is present only in A395 and A398 and not in A390, the rtc is working with A390.

ARM: dts: mvebu: armada-39x: add missing nodes describing GPIO's ------The whole Armada 39x SoC family of processors has GPIO's which all can be supported with existing driver.

ARM: dts: mvebu: armada-39x: enable watchdog for all Armada-39x SoCs ------The whole Armada 39x SoC family of processors has watchdog which can be supported with existing driver.

ARM: dts: mvebu: armada-39x: enable the thermal sensor in Armada-39x SoCs ------

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The whole Armada 39x SoC family of processors has thermal sensor which can be supported with existing driver.

ARM: dts: mvebu: armada-39x: enable PMU, CA9 SoC Controller and Coherency fabric ------This commit enables: - CA9's Performance Monitor Unit - CA9 MPcore SoC Controller - Coherency fabric on Armada 39x, basing on the Armada 38x (which has the same CA9 CPU).

ARM: dts: mvebu: armada-39x: update the SDHCI node on Armada 39x ------Commit 1140011ee9d9 ("mmc: sdhci-pxav3: Modify clock settings for the SDR50 and DDR50 modes") has extended the Device Tree binding used to describe PXAv3 SDHCI controllers in order to be able to use the SDR50 and DDR50 modes.

This commit updates the Device Tree description of the Armada 39x SDHCI controller in other to take advantage of this functionality.

384 arch\arm\boot\dts\armada-xp-axpwifiap.dts#0065 Repo: 9e622af05c2e Gregory Sun Nov 6 10:59:19 2016 +0100 Description: ARM: dts: armada-370-xp: Remove button address and fixup names ------The gpio-key nodes do not have a reg property, so remove the address from the unit name.

ARM: dts: armada-370-xp: Fixup memory DT warning ------memory has a reg property so the unit name should contain an address.

ARM: dts: armada-xp: Fixup pcie DT warnings ------PCIe has a range property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-370-xp: Fixup mdio DT warning ------MDIO has a reg property so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

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385 arch\arm\boot\dts\armada-xp-axpwifiap.dts#0076 386 arch\arm\boot\dts\armada-xp-axpwifiap.dts#0114 387 arch\arm\boot\dts\armada-xp-axpwifiap.dts#0148 388 arch\arm\boot\dts\armada-xp-axpwifiap.dts#0156 389 arch\arm\boot\dts\armada-xp-db.dts#0070 Repo: 6f477f43f9de Gregory Sun Nov 6 09:29:35 2016 +0100 Description: ARM: dts: armada-370-xp: Fixup memory DT warning ------memory has a reg property so the unit name should contain an address.

ARM: dts: armada-xp: Fixup pcie DT warnings ------PCIe has a range property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-370-xp: Fixup mdio DT warning ------MDIO has a reg property so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

390 arch\arm\boot\dts\armada-xp-db.dts#0111 391 arch\arm\boot\dts\armada-xp-db.dts#0163 392 arch\arm\boot\dts\armada-xp-db.dts#0269 393 arch\arm\boot\dts\armada-xp-gp.dts#0071 Repo: 6f477f43f9de Gregory Sun Nov 6 09:29:35 2016 +0100 Description: ARM: dts: armada-370-xp: Fixup memory DT warning ------memory has a reg property so the unit name should contain an address.

ARM: dts: armada-xp: Fixup pcie DT warnings ------PCIe has a range property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-370-xp: Fixup mdio DT warning ------MDIO has a reg property so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

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394 arch\arm\boot\dts\armada-xp-gp.dts#0130 395 arch\arm\boot\dts\armada-xp-gp.dts#0178 396 arch\arm\boot\dts\armada-xp-gp.dts#0254 397 arch\arm\boot\dts\armada-xp-lenovo-ix4-300d.dts#0060 Repo: 6f477f43f9de Gregory Sun Nov 6 09:29:35 2016 +0100 Description: ARM: dts: armada-370-xp: Fixup memory DT warning ------memory has a reg property so the unit name should contain an address.

ARM: dts: armada-xp: Fixup pcie DT warnings ------PCIe has a range property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-370-xp: Fixup mdio DT warning ------MDIO has a reg property so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

398 arch\arm\boot\dts\armada-xp-lenovo-ix4-300d.dts#0071 399 arch\arm\boot\dts\armada-xp-lenovo-ix4-300d.dts#0092 400 arch\arm\boot\dts\armada-xp-lenovo-ix4-300d.dts#0298 401 arch\arm\boot\dts\armada-xp-lenovo-ix4-300d.dts#0299 402 arch\arm\boot\dts\armada-xp-linksys-mamba.dts#0065 Repo: 9e622af05c2e Gregory Sun Nov 6 10:59:19 2016 +0100 Description: ARM: dts: armada-370-xp: Remove button address and fixup names ------The gpio-key nodes do not have a reg property, so remove the address from the unit name.

ARM: dts: armada-370-xp: Remove address from dsa unit name ------The dsa node does not have a reg property, so remove the address from the unit name.

ARM: dts: armada-370-xp: Fixup memory DT warning ------memory has a reg property so the unit name should contain an address.

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ARM: dts: armada-xp: Fixup pcie DT warnings ------PCIe has a range property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

403 arch\arm\boot\dts\armada-xp-linksys-mamba.dts#0076 404 arch\arm\boot\dts\armada-xp-linksys-mamba.dts#0292 405 arch\arm\boot\dts\armada-xp-linksys-mamba.dts#0298 406 arch\arm\boot\dts\armada-xp-linksys-mamba.dts#0326 407 arch\arm\boot\dts\armada-xp-linksys-mamba.dts#0372 408 arch\arm\boot\dts\armada-xp-matrix.dts#0058 Repo: 6f477f43f9de Gregory Sun Nov 6 09:29:35 2016 +0100 Description: ARM: dts: armada-370-xp: Fixup memory DT warning ------memory has a reg property so the unit name should contain an address.

ARM: dts: armada-xp: Fixup pcie DT warnings ------PCIe has a range property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-xp-matrix: Fix the location of the pcie-controller node ------In the dts for the Marvell Armada XP Matrix board the pcie-controller was located under the internal-regs node whereas it belongs to the soc node.

It means that, until this fix, the pcie could not work for this board because it didn't match the definition of the pcie-controller node in the dtsi file. If we had a look on the decompiled dtb file we saw two different instances of the pcie-controller node: one with the all the resource set but disabled and the other without any resource but enabled.

409 arch\arm\boot\dts\armada-xp-matrix.dts#0102 410 arch\arm\boot\dts\armada-xp-matrix.dts#0116 411 arch\arm\boot\dts\armada-xp-mv78230.dtsi#0089 Repo: 007d05d89805 Gregory Sat Nov 5 19:03:50 2016 +0100 Description: ARM: dts: armada-xp: Fixup pcie DT warnings

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------PCIe has a range property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-370-xp: add node labels ------As it was previously done for kirkwood, this adds missing node labels to Armada 370 and XP common and SoC specific nodes to allow to reference them more easily.

412 arch\arm\boot\dts\armada-xp-mv78230.dtsi#0117 413 arch\arm\boot\dts\armada-xp-mv78230.dtsi#0134 414 arch\arm\boot\dts\armada-xp-mv78230.dtsi#0151 415 arch\arm\boot\dts\armada-xp-mv78230.dtsi#0168 416 arch\arm\boot\dts\armada-xp-mv78230.dtsi#0185 417 arch\arm\boot\dts\armada-xp-mv78260.dtsi#0090 Repo: 007d05d89805 Gregory Sat Nov 5 19:03:50 2016 +0100 Description: ARM: dts: armada-xp: Fixup pcie DT warnings ------PCIe has a range property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-370-xp: add node labels ------As it was previously done for kirkwood, this adds missing node labels to Armada 370 and XP common and SoC specific nodes to allow to reference them more easily.

418 arch\arm\boot\dts\armada-xp-mv78260.dtsi#0132 419 arch\arm\boot\dts\armada-xp-mv78260.dtsi#0149 420 arch\arm\boot\dts\armada-xp-mv78260.dtsi#0166 421 arch\arm\boot\dts\armada-xp-mv78260.dtsi#0183 422 arch\arm\boot\dts\armada-xp-mv78260.dtsi#0200 423 arch\arm\boot\dts\armada-xp-mv78260.dtsi#0217

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424 arch\arm\boot\dts\armada-xp-mv78260.dtsi#0234 425 arch\arm\boot\dts\armada-xp-mv78260.dtsi#0251 426 arch\arm\boot\dts\armada-xp-mv78260.dtsi#0268 427 arch\arm\boot\dts\armada-xp-mv78460.dtsi#0107 Repo: 007d05d89805 Gregory Sat Nov 5 19:03:50 2016 +0100 Description: ARM: dts: armada-xp: Fixup pcie DT warnings ------PCIe has a range property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-370-xp: add node labels ------As it was previously done for kirkwood, this adds missing node labels to Armada 370 and XP common and SoC specific nodes to allow to reference them more easily.

428 arch\arm\boot\dts\armada-xp-mv78460.dtsi#0153 429 arch\arm\boot\dts\armada-xp-mv78460.dtsi#0170 430 arch\arm\boot\dts\armada-xp-mv78460.dtsi#0187 431 arch\arm\boot\dts\armada-xp-mv78460.dtsi#0204 432 arch\arm\boot\dts\armada-xp-mv78460.dtsi#0221 433 arch\arm\boot\dts\armada-xp-mv78460.dtsi#0238 434 arch\arm\boot\dts\armada-xp-mv78460.dtsi#0255 435 arch\arm\boot\dts\armada-xp-mv78460.dtsi#0272 436 arch\arm\boot\dts\armada-xp-mv78460.dtsi#0289 437 arch\arm\boot\dts\armada-xp-mv78460.dtsi#0306 438 arch\arm\boot\dts\armada-xp-netgear-rn2120.dts#0059 Repo: 6f477f43f9de Gregory Sun Nov 6 09:29:35 2016 +0100 Description: ARM: dts: armada-370-xp: Fixup memory DT warning ------memory has a reg property so the unit name should contain an address.

ARM: dts: armada-xp: Fixup pcie DT warnings ------PCIe has a range property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

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ARM: dts: armada-370-xp: Fixup mdio DT warning ------MDIO has a reg property so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-xp-rn2120: add pinmuxing for ethernet ------Up to now working ethernet depended on the bootloader to configure the pinmuxing. Make it explicit.

As a side effect this change makes ethernet work in barebox.

ARM: dts: armada-xp-rn2120: drop wrong compatible for i2c0 ------The compatible is supposed to be "marvell,mv78230-i2c", "marvell,mv64xxx-i2c", as provided by armada-xp.dtsi.

439 arch\arm\boot\dts\armada-xp-netgear-rn2120.dts#0070 440 arch\arm\boot\dts\armada-xp-netgear-rn2120.dts#0100 441 arch\arm\boot\dts\armada-xp-netgear-rn2120.dts#0157 442 arch\arm\boot\dts\armada-xp-netgear-rn2120.dts#0168 443 arch\arm\boot\dts\armada-xp-netgear-rn2120.dts#0174 444 arch\arm\boot\dts\armada-xp-netgear-rn2120.dts#0298 445 arch\arm\boot\dts\armada-xp-openblocks-ax3-4.dts#0060 Repo: 9e622af05c2e Gregory Sun Nov 6 10:59:19 2016 +0100 Description: ARM: dts: armada-370-xp: Remove button address and fixup names ------The gpio-key nodes do not have a reg property, so remove the address from the unit name.

ARM: dts: armada-370-xp: Fixup memory DT warning ------memory has a reg property so the unit name should contain an address.

ARM: dts: armada-xp: Fixup pcie DT warnings ------PCIe has a range property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

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ARM: dts: armada-370-xp: Fixup mdio DT warning ------MDIO has a reg property so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

446 arch\arm\boot\dts\armada-xp-openblocks-ax3-4.dts#0101 447 arch\arm\boot\dts\armada-xp-openblocks-ax3-4.dts#0151 448 arch\arm\boot\dts\armada-xp-openblocks-ax3-4.dts#0158 449 arch\arm\boot\dts\armada-xp-openblocks-ax3-4.dts#0243 450 arch\arm\boot\dts\armada-xp-synology-ds414.dts#0073 Repo: baa2f7447e18 Gregory Sun Nov 6 11:05:32 2016 +0100 Description: ARM: dts: armada-370-xp: Fixup regulator DT warning ------regulator has a reg property so the unit name should contain an address.

ARM: dts: armada-370-xp: Fixup memory DT warning ------memory has a reg property so the unit name should contain an address.

ARM: dts: armada-xp: Fixup pcie DT warnings ------PCIe has a range property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

ARM: dts: armada-370-xp: Fixup mdio DT warning ------MDIO has a reg property so the unit name should contain an address. Take the opportunity to use the node label instead of the full name.

451 arch\arm\boot\dts\armada-xp-synology-ds414.dts#0084 452 arch\arm\boot\dts\armada-xp-synology-ds414.dts#0153 453 arch\arm\boot\dts\armada-xp-synology-ds414.dts#0189 454 arch\arm\boot\dts\armada-xp-synology-ds414.dts#0202 455 arch\arm\boot\dts\armada-xp-synology-ds414.dts#0215

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456 arch\arm\boot\dts\armada-xp-synology-ds414.dts#0228 457 arch\arm\boot\dts\armada-xp-synology-ds414.dts#0243 458 arch\arm\boot\dts\armada-xp.dtsi#0056 Repo: 3a729d7ccfb5 Gregory Sat Nov 5 19:40:45 2016 +0100 Description: ARM: dts: armada-370-xp: Fixup l2-cache DT warning ------l2-cache which is either an aurora-outer-cache or an aurora-system-cache has a reg property so the unit name should contain an address.

ARM: dts: armada-370-xp: Remove skeleton.dtsi ------The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi").

These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future:

"Node /memory has a reg or ranges property, but no unit name"

ARM: dts: armada-370-xp: Use the node labels ------Use the node label when possible. As a result it flattens the device tree and it makes more visible the IP blocks specific to each SoC variant.

ARM: dts: armada-370-xp: add node labels ------As it was previously done for kirkwood, this adds missing node labels to Armada 370 and XP common and SoC specific nodes to allow to reference them more easily.

ARM: dts: armada-370-xp: move the cpurst node in the common file ------The cpurst nodes are identical in armada-370.dtsi and armada-xp.dtsi files, so move it in the common armada-370-xp.dtsi file.

ARM: dts: mvebu: A37x/XP/38x/39x: Move SPI controller nodes into 'soc' node ------This patch moves all Armada 370/XP/38x/39x SPI controller nodes from the 'internal-regs' node down into the 'soc' node. This is in preparation to enable the usage of the SPI direct access mode. A follow-up patch will add the static MBus mappings for the SPI devices into the 'reg' property of the SPI controller DT node.

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By moving these SPI controller nodes, this patch also makes use of the labels rather than keeping the tree structure.

459 arch\arm\boot\dts\armada-xp.dtsi#0081 460 arch\arm\boot\dts\armada-xp.dtsi#0090 461 arch\arm\boot\dts\armada-xp.dtsi#0121 462 arch\arm\boot\dts\armada-xp.dtsi#0139 463 arch\arm\boot\dts\armada-xp.dtsi#0153 464 arch\arm\boot\dts\armada-xp.dtsi#0187 465 arch\arm\boot\dts\armada-xp.dtsi#0203 466 arch\arm\boot\dts\armada-xp.dtsi#0231 467 arch\arm\boot\dts\armada-xp.dtsi#0251 468 arch\arm\boot\dts\armada-xp.dtsi#0312 469 arch\arm\boot\dts\artpec6-devboard.dts#0049 Repo: c00f3188417f Niklas Fri Oct 14 15:09:13 2016 +0200 Description: ARM: dts: artpec: add pcie support ------Add PCIe support to the ARTPEC-6 SoC. This uses the existing pcie-artpec6 driver. So, all that is needed is device tree entries in the DTS.

470 arch\arm\boot\dts\artpec6.dtsi#0070 Repo: c00f3188417f Niklas Fri Oct 14 15:09:13 2016 +0200 Description: ARM: dts: artpec: add pcie support ------Add PCIe support to the ARTPEC-6 SoC. This uses the existing pcie-artpec6 driver. So, all that is needed is device tree entries in the DTS.

ARM: dts: artpec: set irq affinity on pmu interrupts ------The irq affinity is required for pmu interrupts.

ARM: dts: artpec: use optimized pl310 settings ------Use the cache settings that were determined to give best performance on artpec-6 typical workloads.

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471 arch\arm\boot\dts\artpec6.dtsi#0157 472 arch\arm\boot\dts\at91-sama5d4_ma5d4.dtsi#0015 Repo: e0dce187559c Marek Vasut Mon Sep 19 23:40:44 2016 +0200 Description: ARM: dts: at91: sama5d4: Add new MA5D4EVK manufacturer compat ------The board is now manufactured by Aries Embedded GmbH, update compat string.

473 arch\arm\boot\dts\at91-sama5d4_ma5d4evk.dts#0016 Repo: e0dce187559c Marek Vasut Mon Sep 19 23:40:44 2016 +0200 Description: ARM: dts: at91: sama5d4: Add new MA5D4EVK manufacturer compat ------The board is now manufactured by Aries Embedded GmbH, update compat string.

474 arch\arm\boot\dts\at91rm9200.dtsi#0484 Repo: 138c2b2f175b Sylvain Sun Oct 16 18:21:45 2016 +0200 Description: ARM: dts: at91: fixes dbgu pinctrl, set pullup on rx, clear pullup on tx ------Remove pullup on dbgu DTXD signal, it is a push-pull output thus the pullup is pointless.

Add pullup on dbgu DRXD signal, it prevents the DRXD signal to be left floating and so consuming a useless extra amount of power in crowbarred state if nothing is externally connected to dbgu.

475 arch\arm\boot\dts\at91sam9260.dtsi#0415 Repo: 138c2b2f175b Sylvain Sun Oct 16 18:21:45 2016 +0200 Description: ARM: dts: at91: fixes dbgu pinctrl, set pullup on rx, clear pullup on tx ------Remove pullup on dbgu DTXD signal, it is a push-pull output thus the pullup is pointless.

Add pullup on dbgu DRXD signal, it prevents the DRXD signal to be left floating and so consuming a useless extra amount of power in crowbarred state if nothing is externally connected to dbgu.

ARM: dts: at91: fix i2c-gpio node name ------i2c-gpio doesn't need a reg property. Change the node names to i2c-gpio-x as used in other dts to remove the unit-address.

Solves:

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Warning (unit_address_vs_reg): Node /i2c@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /i2c@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /i2c@2 has a unit name, but no reg property

476 arch\arm\boot\dts\at91sam9260ek.dts#0177 Repo: b662a9dd8a1a Sudeep Mon Nov 14 15:44:08 2016 +0000 Description: ARM: dts: at91: replace gpio-key,wakeup with wakeup-source for sam9260ek ------Though the keyboard driver for GPIO buttons(gpio-keys) will continue to check for/support the legacy "gpio-key,wakeup" boolean property to enable gpio buttons as wakeup source, "wakeup-source" is the new standard binding.

This patch replaces the legacy "gpio-key,wakeup" with the unified "wakeup-source" property in order to avoid any further copy-paste duplication.

477 arch\arm\boot\dts\at91sam9260ek.dts#0184 478 arch\arm\boot\dts\at91sam9261.dtsi#0305 Repo: 138c2b2f175b Sylvain Sun Oct 16 18:21:45 2016 +0200 Description: ARM: dts: at91: fixes dbgu pinctrl, set pullup on rx, clear pullup on tx ------Remove pullup on dbgu DTXD signal, it is a push-pull output thus the pullup is pointless.

Add pullup on dbgu DRXD signal, it prevents the DRXD signal to be left floating and so consuming a useless extra amount of power in crowbarred state if nothing is externally connected to dbgu.

479 arch\arm\boot\dts\at91sam9263.dtsi#0415 Repo: 138c2b2f175b Sylvain Sun Oct 16 18:21:45 2016 +0200 Description: ARM: dts: at91: fixes dbgu pinctrl, set pullup on rx, clear pullup on tx ------Remove pullup on dbgu DTXD signal, it is a push-pull output thus the pullup is pointless.

Add pullup on dbgu DRXD signal, it prevents the DRXD signal to be left floating and so consuming a useless extra amount of power in crowbarred state if nothing is externally connected to dbgu.

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480 arch\arm\boot\dts\at91sam9g45.dtsi#0481 Repo: 138c2b2f175b Sylvain Sun Oct 16 18:21:45 2016 +0200 Description: ARM: dts: at91: fixes dbgu pinctrl, set pullup on rx, clear pullup on tx ------Remove pullup on dbgu DTXD signal, it is a push-pull output thus the pullup is pointless.

Add pullup on dbgu DRXD signal, it prevents the DRXD signal to be left floating and so consuming a useless extra amount of power in crowbarred state if nothing is externally connected to dbgu.

ARM: dts: at91: fix i2c-gpio node name ------i2c-gpio doesn't need a reg property. Change the node names to i2c-gpio-x as used in other dts to remove the unit-address.

Solves: Warning (unit_address_vs_reg): Node /i2c@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /i2c@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /i2c@2 has a unit name, but no reg property

ARM: dts: at91: Fix USB endpoint nodes ------Endpoint nodes have a reg property. Add their mandatory unit-address.

This solves: Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep0 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep1 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep2 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep3 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep4 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep5 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep6 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep7 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep8 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep9 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep10 has a reg or ranges

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property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep11 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep12 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep13 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep14 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep15 has a reg or ranges property, but no unit name

481 arch\arm\boot\dts\at91sam9n12.dtsi#0503 Repo: 138c2b2f175b Sylvain Sun Oct 16 18:21:45 2016 +0200 Description: ARM: dts: at91: fixes dbgu pinctrl, set pullup on rx, clear pullup on tx ------Remove pullup on dbgu DTXD signal, it is a push-pull output thus the pullup is pointless.

Add pullup on dbgu DRXD signal, it prevents the DRXD signal to be left floating and so consuming a useless extra amount of power in crowbarred state if nothing is externally connected to dbgu.

482 arch\arm\boot\dts\at91sam9rl.dtsi#0441 Repo: 138c2b2f175b Sylvain Sun Oct 16 18:21:45 2016 +0200 Description: ARM: dts: at91: fixes dbgu pinctrl, set pullup on rx, clear pullup on tx ------Remove pullup on dbgu DTXD signal, it is a push-pull output thus the pullup is pointless.

Add pullup on dbgu DRXD signal, it prevents the DRXD signal to be left floating and so consuming a useless extra amount of power in crowbarred state if nothing is externally connected to dbgu.

ARM: dts: at91: fix i2c-gpio node name ------i2c-gpio doesn't need a reg property. Change the node names to i2c-gpio-x as used in other dts to remove the unit-address.

Solves: Warning (unit_address_vs_reg): Node /i2c@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /i2c@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /i2c@2 has a unit name, but no reg property

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ARM: dts: at91: Fix USB endpoint nodes ------Endpoint nodes have a reg property. Add their mandatory unit-address.

This solves: Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep0 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep1 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep2 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep3 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep4 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep5 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep6 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep7 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep8 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep9 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep10 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep11 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep12 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep13 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep14 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep15 has a reg or ranges property, but no unit name

483 arch\arm\boot\dts\at91sam9x5.dtsi#0463 Repo: 138c2b2f175b Sylvain Sun Oct 16 18:21:45 2016 +0200 Description: ARM: dts: at91: fixes dbgu pinctrl, set pullup on rx, clear pullup on tx ------Remove pullup on dbgu DTXD signal, it is a push-pull output thus the pullup is pointless.

Add pullup on dbgu DRXD signal, it prevents the DRXD signal to be left floating and so consuming a useless extra amount of power in crowbarred

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state if nothing is externally connected to dbgu.

ARM: dts: at91: fix i2c-gpio node name ------i2c-gpio doesn't need a reg property. Change the node names to i2c-gpio-x as used in other dts to remove the unit-address.

Solves: Warning (unit_address_vs_reg): Node /i2c@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /i2c@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /i2c@2 has a unit name, but no reg property

ARM: dts: at91: Fix USB endpoint nodes ------Endpoint nodes have a reg property. Add their mandatory unit-address.

This solves: Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep0 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep1 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep2 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep3 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep4 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep5 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep6 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep7 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep8 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep9 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep10 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep11 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep12 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep13 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep14 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep15 has a reg or ranges

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property, but no unit name

484 arch\arm\boot\dts\bcm-cygnus.dtsi#0094 Repo: 7fa8b51b5d2a Jonathan Mon Oct 24 12:12:04 2016 -0700 Description: ARM: dts: Add node for Broadcom OTP controller driver ------

ARM: dts: Enable interrupt support for cygnus crmu gpio driver ------

ARM: dts: Enable Broadcom iProc mailbox controller ------

ARM: dts: cygnus: fix naming of pinctrl node ------

485 arch\arm\boot\dts\bcm-cygnus.dtsi#0118 486 arch\arm\boot\dts\bcm-cygnus.dtsi#0124 487 arch\arm\boot\dts\bcm-cygnus.dtsi#0140 488 arch\arm\boot\dts\bcm-nsp.dtsi#0163 Repo: 6771e01f7965 Jon Mason Thu Jan 12 10:50:10 2017 -0500 Description: ARM: dts: NSP: Fix DT ranges error ------The range size for axi is 0x2 bytes too small, as the QSPI needs 0x11c408 + 0x004 (which is 0x0011c40c, not 0x0011c40a). No errors have been observed with this shortcoming, but fixing it for correctness.

Fixes: 329f98c1974e ("ARM: dts: NSP: Add QSPI nodes to NSPI and bcm958625k DTSes")

ARM: dts: enable GPIO-b for Broadcom NSP ------This enables the GPIO-b support for Broadcom NSP SoC

ARM: dts: NSP: Add QSPI nodes to NSPI and bcm958625k DTSes ------Adding QSPI Device Tree node compatible with the new spi-bcm-qspi driver for the Broadcom Northstar Plus SoC DTSI and bcm958625k reference board.

ARM: dts: NSP: Add PWM Support to DT ------Add PWM support to the device tree for the Broadcom Northstar Plus SoC.

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ARM: dts: NSP: Add Switch Register Access Block node ------Add the Switch Register Access Block node, this peripheral is identical to the BCM5301x Northstar SoC, but we utilize the SoC-wide "brcm,nsp-srab" compatible string to illustrate the integration difference here.

ARM: dts: NSP: Add AMAC entries ------Add Device Tree entries for the Ethernet devices (AMAC) present on the Broadcom Northstar Plus SoCs.

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Olof Johansson: "Device tree contents continue to be the largest branches we submit. This time around, some of the contents worth pointing out is:

New SoC platforms: - Freescale i.MX 7Solo - Broadcom BCM23550 - Cirrus Logic EP7209 and EP7211 (clps711x platforms)_ - Hisilicon HI3519 - Renesas R8A7792

Some of the other delta that is sticking out, line-count wise: - Exynos moves of IP blocks under an SoC bus, which causes a large delta due to indentation changes - a new Tegra K1 board: Apalis - a bunch of small updates to many Allwinner platforms; new hardware support, some cleanup, etc"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (426 commits) ARM: dts: sun8i: Add dts file for inet86dz board ARM: dts: sun8i: Add dts file for Polaroid MID2407PXE03 tablet ARM: dts: sun8i: Use sun8i-reference-design-tablet for ga10h dts ARM: dts: sun8i: Use sun8i-reference-design-tablet for polaroid mid2809pxe04 ARM: dts: sun8i: reference-design-tablet: Add drivevbus-supply ARM: dts: Copy sun8i-q8-common.dtsi sun8i-reference-design-tablet.dtsi ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for utoo p66 dts ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for dit4350 dts ARM: dts: sun5i: reference-design-tablet: Remove mention of q8 ARM: dts: sun5i: reference-design-tablet: Set lradc vref to avcc ARM: dts: sun5i: Rename sun5i-q8-common.dtsi sun5i-reference-design-tablet.dtsi ARM: dts: sun5i: Move q8 display bits to sun5i-a13-q8-tablet.dts ARM: dts: sunxi: Rename sunxi-q8-common.dtsi sunxi-reference-design-tablet.dtsi

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ARM: dts: at91: Don't build unnecessary dtbs ARM: dts: at91: sama5d3x: separate motherboard gmac and emac definitions ARM: dts: at91: at91sam9g25ek: fix isi endpoint node ARM: dts: at91: move isi definition to at91sam9g25ek ARM: dts: at91: fix i2c-gpio node name ARM: dts: at91: vinco: fix regulator name ARM: dts: at91: ariag25 : fix onewire node ...

489 arch\arm\boot\dts\bcm-nsp.dtsi#0244 490 arch\arm\boot\dts\bcm-nsp.dtsi#0267 491 arch\arm\boot\dts\bcm2835-rpi-a-plus.dts#0025 Repo: 6b9170887e1b Stefan Wed Nov 16 17:52:06 2016 +0000 Description: ARM: bcm2835: Fix names for the Raspberry Pi GPIO lines ------There are some differences between the schematics and the official firmware DTS [1]. So based on these additional information the following has been changed:

* use consistent "CAM_GPIO1" for camera LED * use consistent "CAM_GPIO0" for camera shutdown * add "USB_LIMIT" for USB current limit (0=600mA, 1=1200mA)

[1] - https://github.com/raspberrypi/firmware/blob/master/extra/dt-blob.dts

ARM: bcm2835: Add names for the Raspberry Pi GPIO lines ------The idea is to give useful names to GPIO lines that an implementer will be using from userspace, e.g. for maker type projects. These are user-visible using tools/gpio/lsgpio.c

v2: Major rewrite by anholt: Flatten each GPIO line to a line in the file for better diffing, prefix all expansion header pins with "P" or "P5HEADER_P" and drop the mostly-unused GPIO_GEN names in favor of GPIO, fix extra '[]' on a couple of lines, fix locations of SD_CARD_DETECT, CAM_GPIO and STATUS_LED, fix HDMI_HPD polarities, rewrite A+ using unreleased schematics.

v3: More changes by anholt: Drop P / P5HEADER prefixes. I had been skeptical about adding them, and was convinced to drop them by Gottfried (who probably has more experience with GPIOs in educational contexts than the rest of us). Also drop [] brackets for "is pinmuxed", which didn't seem to clarify, and were ambiguous for things like the SPI_*-labeled

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pins which may or may not actually be pinmuxed to SPI.

v4: Rename B+'s SDA0/SCL0 to match the other boards, despite the naming on its schematic.

ARM: dts: bcm283x: drop alt3 from &gpio ------As the alt3 group has no pins left drop it from &gpio.

492 arch\arm\boot\dts\bcm2835-rpi-a-plus.dts#0090 493 arch\arm\boot\dts\bcm2835-rpi-a.dts#0018 Repo: 6b9170887e1b Stefan Wed Nov 16 17:52:06 2016 +0000 Description: ARM: bcm2835: Fix names for the Raspberry Pi GPIO lines ------There are some differences between the schematics and the official firmware DTS [1]. So based on these additional information the following has been changed:

* use consistent "CAM_GPIO1" for camera LED * use consistent "CAM_GPIO0" for camera shutdown * add "USB_LIMIT" for USB current limit (0=600mA, 1=1200mA)

[1] - https://github.com/raspberrypi/firmware/blob/master/extra/dt-blob.dts

ARM: bcm2835: Add names for the Raspberry Pi GPIO lines ------The idea is to give useful names to GPIO lines that an implementer will be using from userspace, e.g. for maker type projects. These are user-visible using tools/gpio/lsgpio.c

v2: Major rewrite by anholt: Flatten each GPIO line to a line in the file for better diffing, prefix all expansion header pins with "P" or "P5HEADER_P" and drop the mostly-unused GPIO_GEN names in favor of GPIO, fix extra '[]' on a couple of lines, fix locations of SD_CARD_DETECT, CAM_GPIO and STATUS_LED, fix HDMI_HPD polarities, rewrite A+ using unreleased schematics.

v3: More changes by anholt: Drop P / P5HEADER prefixes. I had been skeptical about adding them, and was convinced to drop them by Gottfried (who probably has more experience with GPIOs in educational contexts than the rest of us). Also drop [] brackets for "is pinmuxed", which didn't seem to clarify, and were ambiguous for things like the SPI_*-labeled pins which may or may not actually be pinmuxed to SPI.

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v4: Rename B+'s SDA0/SCL0 to match the other boards, despite the naming on its schematic.

ARM: dts: bcm283x: drop alt3 from &gpio ------As the alt3 group has no pins left drop it from &gpio.

494 arch\arm\boot\dts\bcm2835-rpi-a.dts#0085 495 arch\arm\boot\dts\bcm2835-rpi-b-plus.dts#0026 Repo: 6b9170887e1b Stefan Wed Nov 16 17:52:06 2016 +0000 Description: ARM: bcm2835: Fix names for the Raspberry Pi GPIO lines ------There are some differences between the schematics and the official firmware DTS [1]. So based on these additional information the following has been changed:

* use consistent "CAM_GPIO1" for camera LED * use consistent "CAM_GPIO0" for camera shutdown * add "USB_LIMIT" for USB current limit (0=600mA, 1=1200mA)

[1] - https://github.com/raspberrypi/firmware/blob/master/extra/dt-blob.dts

ARM: bcm2835: Add names for the Raspberry Pi GPIO lines ------The idea is to give useful names to GPIO lines that an implementer will be using from userspace, e.g. for maker type projects. These are user-visible using tools/gpio/lsgpio.c

v2: Major rewrite by anholt: Flatten each GPIO line to a line in the file for better diffing, prefix all expansion header pins with "P" or "P5HEADER_P" and drop the mostly-unused GPIO_GEN names in favor of GPIO, fix extra '[]' on a couple of lines, fix locations of SD_CARD_DETECT, CAM_GPIO and STATUS_LED, fix HDMI_HPD polarities, rewrite A+ using unreleased schematics.

v3: More changes by anholt: Drop P / P5HEADER prefixes. I had been skeptical about adding them, and was convinced to drop them by Gottfried (who probably has more experience with GPIOs in educational contexts than the rest of us). Also drop [] brackets for "is pinmuxed", which didn't seem to clarify, and were ambiguous for things like the SPI_*-labeled pins which may or may not actually be pinmuxed to SPI.

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v4: Rename B+'s SDA0/SCL0 to match the other boards, despite the naming on its schematic.

ARM: dts: bcm283x: drop alt3 from &gpio ------As the alt3 group has no pins left drop it from &gpio.

496 arch\arm\boot\dts\bcm2835-rpi-b-plus.dts#0092 497 arch\arm\boot\dts\bcm2835-rpi-b-rev2.dts#0019 Repo: 731b26a6ac17 Linus Walleij Thu Oct 6 13:15:02 2016 +0200 Description: ARM: bcm2835: Add names for the Raspberry Pi GPIO lines ------The idea is to give useful names to GPIO lines that an implementer will be using from userspace, e.g. for maker type projects. These are user-visible using tools/gpio/lsgpio.c

v2: Major rewrite by anholt: Flatten each GPIO line to a line in the file for better diffing, prefix all expansion header pins with "P" or "P5HEADER_P" and drop the mostly-unused GPIO_GEN names in favor of GPIO, fix extra '[]' on a couple of lines, fix locations of SD_CARD_DETECT, CAM_GPIO and STATUS_LED, fix HDMI_HPD polarities, rewrite A+ using unreleased schematics.

v3: More changes by anholt: Drop P / P5HEADER prefixes. I had been skeptical about adding them, and was convinced to drop them by Gottfried (who probably has more experience with GPIOs in educational contexts than the rest of us). Also drop [] brackets for "is pinmuxed", which didn't seem to clarify, and were ambiguous for things like the SPI_*-labeled pins which may or may not actually be pinmuxed to SPI.

v4: Rename B+'s SDA0/SCL0 to match the other boards, despite the naming on its schematic.

ARM: dts: bcm283x: drop alt3 from &gpio ------As the alt3 group has no pins left drop it from &gpio.

498 arch\arm\boot\dts\bcm2835-rpi-b-rev2.dts#0085

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499 arch\arm\boot\dts\bcm2835-rpi-b.dts#0019 Repo: 6b9170887e1b Stefan Wed Nov 16 17:52:06 2016 +0000 Description: ARM: bcm2835: Fix names for the Raspberry Pi GPIO lines ------There are some differences between the schematics and the official firmware DTS [1]. So based on these additional information the following has been changed:

* use consistent "CAM_GPIO1" for camera LED * use consistent "CAM_GPIO0" for camera shutdown * add "USB_LIMIT" for USB current limit (0=600mA, 1=1200mA)

[1] - https://github.com/raspberrypi/firmware/blob/master/extra/dt-blob.dts

ARM: bcm2835: Add names for the Raspberry Pi GPIO lines ------The idea is to give useful names to GPIO lines that an implementer will be using from userspace, e.g. for maker type projects. These are user-visible using tools/gpio/lsgpio.c

v2: Major rewrite by anholt: Flatten each GPIO line to a line in the file for better diffing, prefix all expansion header pins with "P" or "P5HEADER_P" and drop the mostly-unused GPIO_GEN names in favor of GPIO, fix extra '[]' on a couple of lines, fix locations of SD_CARD_DETECT, CAM_GPIO and STATUS_LED, fix HDMI_HPD polarities, rewrite A+ using unreleased schematics.

v3: More changes by anholt: Drop P / P5HEADER prefixes. I had been skeptical about adding them, and was convinced to drop them by Gottfried (who probably has more experience with GPIOs in educational contexts than the rest of us). Also drop [] brackets for "is pinmuxed", which didn't seem to clarify, and were ambiguous for things like the SPI_*-labeled pins which may or may not actually be pinmuxed to SPI.

v4: Rename B+'s SDA0/SCL0 to match the other boards, despite the naming on its schematic.

ARM: dts: bcm283x: drop alt3 from &gpio ------As the alt3 group has no pins left drop it from &gpio.

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500 arch\arm\boot\dts\bcm2835-rpi-zero.dts#0029 Repo: 3a1689ea7524 Stefan Wed Nov 16 17:52:07 2016 +0000 Description: ARM: bcm2835: Add names for the RPi Zero GPIO lines ------This adds the GPIO names for the Raspberry Pi Zero. The GPIO lines of the RPi Zero are almost identical to the Model A+ except:

* GPIO 35, 38, 40 and 45 are not connected * Status LED is active low

ARM: dts: bcm283x: drop alt3 from &gpio ------As the alt3 group has no pins left drop it from &gpio.

501 arch\arm\boot\dts\bcm2835-rpi-zero.dts#0094 502 arch\arm\boot\dts\bcm2835-rpi.dtsi#0042 Repo: a6d962aeb22f Gerd Mon Sep 19 10:43:23 2016 +0200 Description: ARM: dts: bcm283x: drop alt3 from &gpio ------As the alt3 group has no pins left drop it from &gpio.

ARM: dts: bcm283x: add pinctrl group to &sdhci, drop pins from &gpio ------

ARM: dts: bcm283x: add pinctrl group to &i2c1, drop pins from &gpio ------

ARM: dts: bcm283x: add pinctrl group to &i2c0, drop pins from &gpio ------

ARM: dts: bcm283x: add pinctrl group to &pwm, drop pins from &gpio ------

503 arch\arm\boot\dts\bcm2835-rpi.dtsi#0045 504 arch\arm\boot\dts\bcm2835-rpi.dtsi#0053

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505 arch\arm\boot\dts\bcm2835-rpi.dtsi#0058 506 arch\arm\boot\dts\bcm2835-rpi.dtsi#0067 507 arch\arm\boot\dts\bcm2835-rpi.dtsi#0073 508 arch\arm\boot\dts\bcm2835.dtsi#0026 Repo: 43bac4133f40 Martin Sperl Wed Nov 2 10:18:23 2016 +0000 Description: ARM: bcm2835: dts: add thermal node to device-tree of bcm283x ------Add the node for the thermal sensor of the bcm2835-soc to the device tree.

509 arch\arm\boot\dts\bcm2836-rpi-2-b.dts#0030 Repo: a6d962aeb22f Gerd Mon Sep 19 10:43:23 2016 +0200 Description: ARM: dts: bcm283x: drop alt3 from &gpio ------As the alt3 group has no pins left drop it from &gpio.

510 arch\arm\boot\dts\bcm2836.dtsi#0079 Repo: 43bac4133f40 Martin Sperl Wed Nov 2 10:18:23 2016 +0000 Description: ARM: bcm2835: dts: add thermal node to device-tree of bcm283x ------Add the node for the thermal sensor of the bcm2835-soc to the device tree.

511 arch\arm\boot\dts\bcm283x.dtsi#0107 Repo: 43bac4133f40 Martin Sperl Wed Nov 2 10:18:23 2016 +0000 Description: ARM: bcm2835: dts: add thermal node to device-tree of bcm283x ------Add the node for the thermal sensor of the bcm2835-soc to the device tree.

ARM: dts: bcm283x: fix typo in mailbox address ------The address of the mailbox node in the bcm283x.dtsi also has a typo. So fix it accordingly.

ARM: dts: bcm283x: Define standard pinctrl groups in the gpio node. ------The BCM2835-ARM-Peripherals.pdf documentation specifies what the

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function selects do for the pins, and there are a bunch of obvious groupings to be made. With these created, we'll be able to replace bcm2835-rpi.dtsi's main "set all of these pins to alt0" with references to specific groups we want enabled.

Also add pinctrl groups for emmc and sdhost.

Based on patches by Eric Anholt, with fixups by Gerd Hoffmann.

512 arch\arm\boot\dts\bcm283x.dtsi#0135 513 arch\arm\boot\dts\bcm283x.dtsi#0393 514 arch\arm\boot\dts\bcm4709-asus-rt-ac87u.dts#0012 Repo: fa87b008da3f Rafa Miecki Wed Sep 21 22:58:33 2016 +0200 Description: ARM: BCM5301X: Enable UART on Netgear R8000 ------It was tested by LEDE users, all we need is to adjust clock frequency. While we're at it create a separated DTS include file to share code with other BCM4709 devices easier.

515 arch\arm\boot\dts\bcm4709-buffalo-wxr-1900dhp.dts#0012 Repo: fa87b008da3f Rafa Miecki Wed Sep 21 22:58:33 2016 +0200 Description: ARM: BCM5301X: Enable UART on Netgear R8000 ------It was tested by LEDE users, all we need is to adjust clock frequency. While we're at it create a separated DTS include file to share code with other BCM4709 devices easier.

516 arch\arm\boot\dts\bcm4709-netgear-r7000.dts#0012 Repo: fa87b008da3f Rafa Miecki Wed Sep 21 22:58:33 2016 +0200 Description: ARM: BCM5301X: Enable UART on Netgear R8000 ------It was tested by LEDE users, all we need is to adjust clock frequency. While we're at it create a separated DTS include file to share code with other BCM4709 devices easier.

517 arch\arm\boot\dts\bcm4709-netgear-r8000.dts#0012 Repo: fa87b008da3f Rafa Miecki Wed Sep 21 22:58:33 2016 +0200 Description: ARM: BCM5301X: Enable UART on Netgear R8000 ------It was tested by LEDE users, all we need is to adjust clock frequency.

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While we're at it create a separated DTS include file to share code with other BCM4709 devices easier.

518 arch\arm\boot\dts\bcm4709-netgear-r8000.dts#0110 519 arch\arm\boot\dts\bcm47094-dlink-dir-885l.dts#0012 Repo: 54b902a4cd02 Rafa Miecki Wed Sep 21 22:58:32 2016 +0200 Description: ARM: BCM5301X: Add separated DTS include file for BCM47094 ------Use it to store BCM47094 specific properties/values and avoid repeating them in device DTS files.

520 arch\arm\boot\dts\bcm47094-dlink-dir-885l.dts#0110 521 arch\arm\boot\dts\bcm5301x.dtsi#0152 Repo: 92b7b6ad1a09 Rafa Miecki Wed Sep 21 22:58:34 2016 +0200 Description: ARM: BCM5301X: Specify USB 3.0 PHY in DT ------Driver for Northstar USB 3.0 PHY has been recently added under the name phy-bcm-ns-usb3. Add binding for it into the DT files. The only slightly tricky part is BCM47094 which uses different PHY version and requires different compatible value.

ARM: BCM5301X: Specify PHY of USB 2.0 in DT ------Driver for Northstar USB 2.0 PHY was added in 4.7-rc1 by: commit d3feb4067335 ("phy: bcm-ns-usb2: new driver for USB 2.0 PHY on Northstar"). It should be used to let EHCI platform driver init PHY.

ARM: dts: BCM5301x: Add RNG Device Tree node ------Add the DT node for the random number generator peripheral.

ARM: dts: BCM5301X: Add SRAB interrupts ------Add interrupt mapping for the Switch Register Access Block. Only 12 interrupts are usable at the moment even though up to 32 are dedicated to the SRAB.

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522 arch\arm\boot\dts\bcm958625k.dts#0142 Repo: 329f98c1974e Kamal Dasu Wed Aug 24 18:04:27 2016 -0400 Description: ARM: dts: NSP: Add QSPI nodes to NSPI and bcm958625k DTSes ------Adding QSPI Device Tree node compatible with the new spi-bcm-qspi driver for the Broadcom Northstar Plus SoC DTSI and bcm958625k reference board.

ARM: dts: NSP: Specify RAM amount for BCM958625K board ------Add 2GB of memory starting at physical offset 0x6000_0000.

523 arch\arm\boot\dts\berlin2q-marvell-dmp.dts#0051 Repo: 0248994d7cce Masahiro Thu Oct 20 09:52:11 2016 +0900 Description: ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ------

ARM: dts: berlin2q-marvell-dmp: fix regulators' name ------

524 arch\arm\boot\dts\berlin2q-marvell-dmp.dts#0061 525 arch\arm\boot\dts\berlin2q-marvell-dmp.dts#0070 526 arch\arm\boot\dts\berlin2q-marvell-dmp.dts#0079 527 arch\arm\boot\dts\berlin2q-marvell-dmp.dts#0088 528 arch\arm\boot\dts\berlin2q-marvell-dmp.dts#0098 529 arch\arm\boot\dts\da850-evm.dts#0102 Repo: 43849785e107 Fabien Tue Jan 17 13:57:42 2017 +0100 Description: ARM: dts: da850-evm: fix read access to SPI flash ------Read access to the SPI flash are broken on da850-evm, i.e. the data read is not what is actually programmed on the flash. According to the datasheet for the M25P64 part present on the da850-evm, if the SPI frequency is higher than 20MHz then the READ command is not usable anymore and only the FAST_READ command can be used to read data.

This commit specifies in the DTS that we should use FAST_READ command instead of the READ command.

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530 arch\arm\boot\dts\da850-lcdk.dts#0016 Repo: 878e908ad956 Bartosz Thu Nov 24 10:31:24 2016 +0100 Description: ARM: dts: da850: enable memctrl and mstpri nodes per board ------Currently the memory controller and master priorities drivers are enabled in da850.dtsi. For boards for which there are no settings defined, this makes these drivers emit error messages.

Disable the nodes in da850.dtsi and only enable them for da850-lcdk - the only board that currently needs them.

ARM: dts: da850-lcdk: Add ethernet0 alias to DT ------In order to avoid Linux generating a random mac address on every boot, add an ethernet0 alias that will allow u-boot to patch the dtb with the MAC address programmed into the EEPROM.

ARM: dts: da850-lcdk: fix mmc card detect polarity ------The polarity of the card detect pin is inverted.

Change it to reflect the right polarity for the board which is ACTIVE_LOW.

ARM: dts: da850-lcdk: Enable the usb otg device node ------This enables the usb otg controller for the lcdk board.

531 arch\arm\boot\dts\da850-lcdk.dts#0126 532 arch\arm\boot\dts\da850-lcdk.dts#0162 533 arch\arm\boot\dts\da850-lcdk.dts#0231 534 arch\arm\boot\dts\da850.dtsi#0039 Repo: dd1551b65023 Olof Wed Dec 7 12:34:30 2016 -0800 Description: Merge tag 'davinci-for-v4.10/dt-4' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/dt ------Add device tree nodes for pin pull-up/pull-down bias control on DA850.

- Enable high speed support on DA850 MMC/SD

* tag 'davinci-for-v4.10/dt-4' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-

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davinci: ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf

ARM: dts: da850: enable high speed for mmc ------The mmc controller in da850 supports high speed modes so add cap-sd-highspeed and cap-mmc-highspeed.

ARM: dts: da850: Add node for pullup/pulldown pinconf ------This SoC has a separate pin controller for configuring pullup/pulldown bias on groups of pins.

Merge tag 'davinci-for-v4.10/dt-3' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/dt ------Pull "DaVinci DT updates for v4.10 (part 3)" from Sekhar Nori:

Some fixes for device-tree patches already queued. - Fix SD card detect polarity - Prevent Ethernet from picking a random mac address - Fix error messages on platforms which dont use bus master and emif priority settings.

* tag 'davinci-for-v4.10/dt-3' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux- davinci: ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: da850-lcdk: fix mmc card detect polarity

Merge tag 'davinci-for-v4.10/dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/dt ------Pull "DaVinci DT updates for v4.10 (part 2)" from Sekhar Nori:

Adds device tree nodes enabling DDR controller and bus master priority settings needed for stable LCDC operation on DA850.

Also adds support for MUSB device on DA850 providing USB OTG support.

* tag 'davinci-for-v4.10/dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux- davinci: ARM: dts: da850-lcdk: Enable the usb otg device node

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ARM: dts: da850: Add the usb otg device node ARM: dts: da850: add the mstpri and ddrctl nodes

ARM: dts: da850: enable memctrl and mstpri nodes per board ------Currently the memory controller and master priorities drivers are enabled in da850.dtsi. For boards for which there are no settings defined, this makes these drivers emit error messages.

Disable the nodes in da850.dtsi and only enable them for da850-lcdk - the only board that currently needs them.

ARM: dts: da850: Add the usb otg device node ------This adds the device tree node for the usb otg controller present in the da850 family of SoC's.

Merge tag 'omap-for-v4.10/pinctrl-cells-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt ------Add #pinctrl-cells for pinctrl-single using dts files. This allows us to use generic parser later on. Note that the driver supports handling the legacy binding also with no #pinctrl-cells so these changes can be queued separately from the driver changes.

* tag 'omap-for-v4.10/pinctrl-cells-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: Add #pinctrl-cells for pinctrl-single instances

ARM: dts: da850: add the mstpri and ddrctl nodes ------Add the nodes for the MSTPRI configuration and DDR2/mDDR memory controller drivers to da850.dtsi.

ARM: dts: Add #pinctrl-cells for pinctrl-single instances ------Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the driver changes as the driver supports also the legacy binding without #pinctrl-cells.

ARM: dts: da850: Add cfgchip syscon node

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------Add a syscon node for the SoC CFGCHIPn registers. It includes a child node for the USB PHY that is part of this range of registers.

ARM: dts: da850: Add DMA to SPI0 ------Add the bindings for DMA on SPI0

ARM: dts: da850: add a node for the LCD controller ------Add pins used by the LCD controller and a disabled LCDC node to be reused in device trees including da850.dtsi.

535 arch\arm\boot\dts\da850.dtsi#0190 536 arch\arm\boot\dts\da850.dtsi#0205 537 arch\arm\boot\dts\da850.dtsi#0213 538 arch\arm\boot\dts\da850.dtsi#0320 539 arch\arm\boot\dts\da850.dtsi#0330 540 arch\arm\boot\dts\da850.dtsi#0380 541 arch\arm\boot\dts\da850.dtsi#0396 542 arch\arm\boot\dts\da850.dtsi#0442 543 arch\arm\boot\dts\da850.dtsi#0460 544 arch\arm\boot\dts\da850.dtsi#0478 545 arch\arm\boot\dts\dm814x.dtsi#0015 Repo: 9536fd30d41a Javier Mon Dec 19 11:44:39 2016 -0300 Description: ARM: dts: dm814x: Add an empty chosen node to top level DTSI ------Commit 76155b378c59 ("ARM: dts: dm814x: Remove skeleton.dtsi usage") removed the skeleton.dtsi usage since we want to get rid of it.

But this can cause issues when booting a kernel with a boot-loader that doesn't create a chosen node if this isn't present in the DTB since the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info.

Fixes: 76155b378c59 ("ARM: dts: dm814x: Remove skeleton.dtsi usage")

ARM: dts: Add #pinctrl-cells for pinctrl-single instances ------Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while

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pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the driver changes as the driver supports also the legacy binding without #pinctrl-cells.

546 arch\arm\boot\dts\dm814x.dtsi#0377 547 arch\arm\boot\dts\dm816x.dtsi#0015 Repo: 6ed80b3a232e Javier Mon Dec 19 11:44:40 2016 -0300 Description: ARM: dts: dm816x: Add an empty chosen node to top level DTSI ------Commit 06bfb9c19957 ("ARM: dts: dm816x: Remove skeleton.dtsi usage") removed the skeleton.dtsi usage since we want to get rid of it.

But this can cause issues when booting a kernel with a boot-loader that doesn't create a chosen node if this isn't present in the DTB since the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info.

Fixes: 06bfb9c19957 ("ARM: dts: dm816x: Remove skeleton.dtsi usage")

ARM: dts: Add #pinctrl-cells for pinctrl-single instances ------Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the driver changes as the driver supports also the legacy binding without #pinctrl-cells.

548 arch\arm\boot\dts\dm816x.dtsi#0087 549 arch\arm\boot\dts\dm816x.dtsi#0095 550 arch\arm\boot\dts\dra7.dtsi#0021 Repo: 87cb12910a2a Jean- Mon Jan 9 13:22:15 2017 +0100 Description: ARM: dts: OMAP5 / DRA7: indicate that SATA port 0 is available. ------AHCI provides the register PORTS_IMPL to let the software know which port is supported. The register must be initialized by the bootloader. However in some cases u-boot doesn't properly initialize this value (if it is not compiled with SATA support for example or if the SATA initialization fails). The DTS entry "ports-implemented" can be used to override the value in PORTS_IMPL.

Without this patch the SATA will not work in the following two cases:

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* if there has been a failure to initialize SATA in u-boot.

* if ahci_platform module has been removed and re-inserted. The reason is that the content of PORTS_IMPL is lost after the module is removed. I suspect that it's because the controller is reset by the hwmod.

ARM: dts: dra7: Add an empty chosen node to top level DTSI ------Commit 55871eb6e2cc ("ARM: dts: dra7: Remove skeleton.dtsi usage") removed the skeleton.dtsi usage since we want to get rid of it.

But this can cause issues when booting a kernel with a boot-loader that doesn't create a chosen node if this isn't present in the DTB since the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info.

Fixes: 55871eb6e2cc ("ARM: dts: dra7: Remove skeleton.dtsi usage")

ARM: dts: Add #pinctrl-cells for pinctrl-single instances ------Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the driver changes as the driver supports also the legacy binding without #pinctrl-cells.

551 arch\arm\boot\dts\dra7.dtsi#0175 552 arch\arm\boot\dts\dra7.dtsi#1381 553 arch\arm\boot\dts\dra72-evm-common.dtsi#0021 Repo: 6eebfeb9cf0d Nishanth Fri Oct 21 16:08:39 2016 +0530 Description: ARM: dts: Add support for dra718-evm ------The DRA718-evm is a board based on TI's DRA718 processor targeting BOM-optimized entry infotainment systems and is a reduced pin and software compatible derivative of the DRA72 ES2.0 processor. This platform features: - 2GB of DDR3L - Dual 1Gbps Ethernet - HDMI, - uSD - 8GB eMMC - CAN - PCIe

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- USB3.0 - Video Input Port - LP873x PMIC

More information can be found here[1].

Adding support for this board while reusing the data available in dra72-evm-common.dtsi.

[1] http://www.ti.com/product/dra718

ARM: dts: dra72: Add separate dtsi for tps65917 ------dra72-evm-common.dtsi consolidates dra72-evm.dts and dra72-evm-revc.dts which also include tps65917 pmic support as both the evms uses the same pmic. But, dra71-evm has mostly similar features with a different pmic. In order to exploit dra72-evm-common.dtsi, creating a separate dtsi for tps65915 support and including it in respective board files.

ARM: dts: dra72-evm: Fix modelling of regulators ------Add proper description of input voltage regulators and update the voltage rail map for all the regulators.

ARM: dts: dra72-evm: Remove pinmux configurations for erratum i869 ------Pinmuxing for DRA7x/AM57x family of processors need to be done in IO isolation as part of initial bootloader executed from SRAM. This is done as part of iodelay configuration sequence and is required due to the limitations introduced by erratum ID: i869[1] (IO Glitches can occur when changing IO settings) and elaborated in the Technical Reference Manual[2] 18.4.6.1.7 Isolation Requirements.

Only peripheral that is permitted for dynamic pin mux configuration is MMC and DCAN. MMC is permitted to change to accommodate the requirements for varied speeds (which require IO-delay support in kernel as well). DCAN is a result of i893[1] (DCAN initialization sequence). With the exception of DCAN and MMC, all other pin mux configurations are removed from the dts.

[1] http://www.ti.com/lit/er/sprz436a/sprz436a.pdf [2] http://www.ti.com/lit/ug/spruhz7c/spruhz7c.pdf

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554 arch\arm\boot\dts\dra72-evm-common.dtsi#0056 555 arch\arm\boot\dts\dra72-evm-common.dtsi#0061 556 arch\arm\boot\dts\dra72-evm-common.dtsi#0080 557 arch\arm\boot\dts\dra72-evm-common.dtsi#0111 558 arch\arm\boot\dts\dra72-evm-common.dtsi#0173 559 arch\arm\boot\dts\dra72-evm-common.dtsi#0243 560 arch\arm\boot\dts\dra72-evm-common.dtsi#0285 561 arch\arm\boot\dts\dra72-evm-common.dtsi#0289 562 arch\arm\boot\dts\dra72-evm-common.dtsi#0426 563 arch\arm\boot\dts\dra72-evm-common.dtsi#0465 564 arch\arm\boot\dts\dra72-evm-common.dtsi#0551 565 arch\arm\boot\dts\dra72-evm-common.dtsi#0569 566 arch\arm\boot\dts\dra72-evm-common.dtsi#0575 567 arch\arm\boot\dts\dra72-evm-common.dtsi#0584 568 arch\arm\boot\dts\dra72-evm-common.dtsi#0606 569 arch\arm\boot\dts\dra72-evm-common.dtsi#0662 570 arch\arm\boot\dts\dra72-evm-common.dtsi#0667 571 arch\arm\boot\dts\dra72-evm-common.dtsi#0744 572 arch\arm\boot\dts\dra72-evm-common.dtsi#0751 573 arch\arm\boot\dts\dra72-evm-common.dtsi#0762 574 arch\arm\boot\dts\dra72-evm-common.dtsi#0783 575 arch\arm\boot\dts\dra72-evm-revc.dts#0020 Repo: 8e2329ead748 Sekhar Nori Thu Jan 12 16:24:43 2017 +0530 Description: ARM: dts: dra72-evm-revc: fix typo in ethernet-phy node ------Fix a typo in impedance setting for ethernet-phy@3

Fixes: b76db38cd8ae ("ARM: dts: dra72-evm-revc: add phy impedance settings")

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

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We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

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- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

ARM: dts: dra72: Add separate dtsi for tps65917 ------dra72-evm-common.dtsi consolidates dra72-evm.dts and dra72-evm-revc.dts which also include tps65917 pmic support as both the evms uses the same pmic. But, dra71-evm has mostly similar features with a different pmic. In order to exploit dra72-evm-common.dtsi, creating a separate dtsi for tps65915 support and including it in respective board files.

ARM: dts: dra72-evm-revc: fix correct phy delay ------The current delay settings of the phy are not the optimal value, fix it with correct values.

ARM: dts: dra72-evm-revc: add phy impedance settings ------

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The default impedance settings of the phy is not the optimal value, due to this the second ethernet is not working. Fix it with correct values which makes the second ethernet port to work.

576 arch\arm\boot\dts\dra72-evm-revc.dts#0031 577 arch\arm\boot\dts\dra72-evm-revc.dts#0067 578 arch\arm\boot\dts\dra72-evm-revc.dts#0070 579 arch\arm\boot\dts\dra72-evm-revc.dts#0075 580 arch\arm\boot\dts\dra72-evm-revc.dts#0078 581 arch\arm\boot\dts\dra72-evm.dts#0018 Repo: 5d080aa30681 Lokesh Vutla Fri Oct 21 16:08:35 2016 +0530 Description: ARM: dts: dra72: Add separate dtsi for tps65917 ------dra72-evm-common.dtsi consolidates dra72-evm.dts and dra72-evm-revc.dts which also include tps65917 pmic support as both the evms uses the same pmic. But, dra71-evm has mostly similar features with a different pmic. In order to exploit dra72-evm-common.dtsi, creating a separate dtsi for tps65915 support and including it in respective board files.

582 arch\arm\boot\dts\dra72-evm.dts#0028 583 arch\arm\boot\dts\emev2.dtsi#0011 Repo: 51b884d0e1d8 Geert Fri Oct 21 11:16:06 2016 +0200 Description: ARM: dts: emev2: Remove skeleton.dtsi inclusion ------As of commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

584 arch\arm\boot\dts\emev2.dtsi#0018 585 arch\arm\boot\dts\exynos3250-artik5-eval.dts#0031 Repo: 9adce7a44138 Jaehoon Thu Nov 3 15:21:32 2016 +0900 Description: ARM: dts: exynos: Replace "clock-freq-min-max" with "max-frequency" ------In drivers/mmc/core/host.c, there is a "max-frequency" property. Behavior should not change, so use the "max-frequency" instead of

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"clock-freq-min-max".

ARM: dts: exynos: Add MSHC2 DT node for SD card for exynos3250-artik5-eval board ------This patch adds MSHC (Mobile Storage Host Controller) DT node for Exynos3250 SoC. MSHC is an interface between the system and the SD card.

586 arch\arm\boot\dts\exynos3250-artik5.dtsi#0313 Repo: 9adce7a44138 Jaehoon Thu Nov 3 15:21:32 2016 +0900 Description: ARM: dts: exynos: Replace "clock-freq-min-max" with "max-frequency" ------In drivers/mmc/core/host.c, there is a "max-frequency" property. Behavior should not change, so use the "max-frequency" instead of "clock-freq-min-max".

ARM: dts: exynos: Add missing unit name to memory nodes in Exynos3 DTS ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

587 arch\arm\boot\dts\exynos3250-monk.dts#0438 Repo: 9adce7a44138 Jaehoon Thu Nov 3 15:21:32 2016 +0900 Description: ARM: dts: exynos: Replace "clock-freq-min-max" with "max-frequency" ------In drivers/mmc/core/host.c, there is a "max-frequency" property. Behavior should not change, so use the "max-frequency" instead of "clock-freq-min-max".

ARM: dts: exynos: Add missing unit name to memory nodes in Exynos3 DTS ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

588 arch\arm\boot\dts\exynos3250-pinctrl.dtsi#0365 Repo: 9645ab2cbc1a Krzysztof Fri Sep 16 23:41:57 2016 +0200 Description: ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos3250 ------Replace hard-coded values of type of GIC interrupt and its flags with

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respective macros from header to increase code readability.

ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos3250 ------Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and generates an error: genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)

The GIC requires shared interrupts to be edge rising or level high. Platform declares support for both. Arbitrarily choose level high everywhere hoping it will work on each platform.

ARM: dts: exynos: Use macros for pinctrl configuration on exynos3250 ------Usage of DTS macros instead of hard-coded numbers makes code easier to read. One does not have to remember which value means pull-up/down or specific driver strength.

589 arch\arm\boot\dts\exynos3250-pinctrl.dtsi#0382 590 arch\arm\boot\dts\exynos3250-rinato.dts#0652 Repo: 9adce7a44138 Jaehoon Thu Nov 3 15:21:32 2016 +0900 Description: ARM: dts: exynos: Replace "clock-freq-min-max" with "max-frequency" ------In drivers/mmc/core/host.c, there is a "max-frequency" property. Behavior should not change, so use the "max-frequency" instead of "clock-freq-min-max".

ARM: dts: exynos: Add missing unit name to memory nodes in Exynos3 DTS ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

591 arch\arm\boot\dts\exynos3250.dtsi#0023 Repo: 9645ab2cbc1a Krzysztof Fri Sep 16 23:41:57 2016 +0200 Description: ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos3250 ------Replace hard-coded values of type of GIC interrupt and its flags with respective macros from header to increase code readability.

ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos3250

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------Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and generates an error: genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)

The GIC requires shared interrupts to be edge rising or level high. Platform declares support for both. Arbitrarily choose level high everywhere hoping it will work on each platform.

592 arch\arm\boot\dts\exynos3250.dtsi#0216 593 arch\arm\boot\dts\exynos3250.dtsi#0225 594 arch\arm\boot\dts\exynos3250.dtsi#0240 595 arch\arm\boot\dts\exynos3250.dtsi#0247 596 arch\arm\boot\dts\exynos3250.dtsi#0262 597 arch\arm\boot\dts\exynos3250.dtsi#0266 598 arch\arm\boot\dts\exynos3250.dtsi#0273 599 arch\arm\boot\dts\exynos3250.dtsi#0279 600 arch\arm\boot\dts\exynos3250.dtsi#0293 601 arch\arm\boot\dts\exynos3250.dtsi#0305 602 arch\arm\boot\dts\exynos3250.dtsi#0319 603 arch\arm\boot\dts\exynos3250.dtsi#0334 604 arch\arm\boot\dts\exynos3250.dtsi#0345 605 arch\arm\boot\dts\exynos3250.dtsi#0356 606 arch\arm\boot\dts\exynos3250.dtsi#0368 607 arch\arm\boot\dts\exynos3250.dtsi#0380 608 arch\arm\boot\dts\exynos3250.dtsi#0408 609 arch\arm\boot\dts\exynos3250.dtsi#0419 610 arch\arm\boot\dts\exynos3250.dtsi#0432 611 arch\arm\boot\dts\exynos3250.dtsi#0444 612 arch\arm\boot\dts\exynos3250.dtsi#0454 613 arch\arm\boot\dts\exynos3250.dtsi#0465 614 arch\arm\boot\dts\exynos3250.dtsi#0476

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615 arch\arm\boot\dts\exynos3250.dtsi#0487 616 arch\arm\boot\dts\exynos3250.dtsi#0500 617 arch\arm\boot\dts\exynos3250.dtsi#0513 618 arch\arm\boot\dts\exynos3250.dtsi#0526 619 arch\arm\boot\dts\exynos3250.dtsi#0539 620 arch\arm\boot\dts\exynos3250.dtsi#0552 621 arch\arm\boot\dts\exynos3250.dtsi#0565 622 arch\arm\boot\dts\exynos3250.dtsi#0578 623 arch\arm\boot\dts\exynos3250.dtsi#0591 624 arch\arm\boot\dts\exynos3250.dtsi#0602 625 arch\arm\boot\dts\exynos3250.dtsi#0618 626 arch\arm\boot\dts\exynos3250.dtsi#0634 627 arch\arm\boot\dts\exynos3250.dtsi#0647 628 arch\arm\boot\dts\exynos3250.dtsi#0658 629 arch\arm\boot\dts\exynos4.dtsi#0024 Repo: b4cf33e96aea Olof Fri Nov 18 18:01:09 2016 -0800 Description: Merge tag 'samsung-dt-gic-flags-4.10' of git://git.kernel. org/pub/scm/linux/kernel/git/krzk/linux into next/dt ------Topic branch with DT changes for v4.10.

Fix invalid GIC interrupt flags - type IRQ_TYPE_NONE is not allowed for GIC interrupts. Although this was working but with error messages like: genirq: Setting trigger mode 0 for irq 16 failed

Use level high interrupt instead of type none. The choice of level high was rather an arbitrary decision hoping it will work on each platform. Tests shown no issues so far.

* tag 'samsung-dt-gic-flags-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos5440 ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos5260 ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos5 ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos4 ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos3250 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5440 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5260 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5410/exynos542x ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5250 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5

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ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos3250 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4x12 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4210 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4

ARM: dts: exynos: Add SCU device node to exynos4.dtsi ------Exynos4 like other Cortex-A9 SoC's has a Snoop Control Unit(SCU) and its SFR are used during SMP boot and S2R. Add SCU node to the device tree.

ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos4 ------Replace hard-coded values of type of GIC interrupt and its flags with respective macros from header to increase code readability.

ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4 ------Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and generates an error: genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)

The GIC requires shared interrupts to be edge rising or level high. Platform declares support for both. Arbitrarily choose level high everywhere hoping it will work on each platform.

630 arch\arm\boot\dts\exynos4.dtsi#0083 631 arch\arm\boot\dts\exynos4.dtsi#0178 632 arch\arm\boot\dts\exynos4.dtsi#0201 633 arch\arm\boot\dts\exynos4.dtsi#0213 634 arch\arm\boot\dts\exynos4.dtsi#0225 635 arch\arm\boot\dts\exynos4.dtsi#0237 636 arch\arm\boot\dts\exynos4.dtsi#0249 637 arch\arm\boot\dts\exynos4.dtsi#0264 638 arch\arm\boot\dts\exynos4.dtsi#0280 639 arch\arm\boot\dts\exynos4.dtsi#0290 640 arch\arm\boot\dts\exynos4.dtsi#0300

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641 arch\arm\boot\dts\exynos4.dtsi#0309 642 arch\arm\boot\dts\exynos4.dtsi#0318 643 arch\arm\boot\dts\exynos4.dtsi#0327 644 arch\arm\boot\dts\exynos4.dtsi#0336 645 arch\arm\boot\dts\exynos4.dtsi#0355 646 arch\arm\boot\dts\exynos4.dtsi#0366 647 arch\arm\boot\dts\exynos4.dtsi#0392 648 arch\arm\boot\dts\exynos4.dtsi#0434 649 arch\arm\boot\dts\exynos4.dtsi#0445 650 arch\arm\boot\dts\exynos4.dtsi#0456 651 arch\arm\boot\dts\exynos4.dtsi#0467 652 arch\arm\boot\dts\exynos4.dtsi#0478 653 arch\arm\boot\dts\exynos4.dtsi#0491 654 arch\arm\boot\dts\exynos4.dtsi#0504 655 arch\arm\boot\dts\exynos4.dtsi#0517 656 arch\arm\boot\dts\exynos4.dtsi#0530 657 arch\arm\boot\dts\exynos4.dtsi#0543 658 arch\arm\boot\dts\exynos4.dtsi#0556 659 arch\arm\boot\dts\exynos4.dtsi#0569 660 arch\arm\boot\dts\exynos4.dtsi#0582 661 arch\arm\boot\dts\exynos4.dtsi#0595 662 arch\arm\boot\dts\exynos4.dtsi#0609 663 arch\arm\boot\dts\exynos4.dtsi#0624 664 arch\arm\boot\dts\exynos4.dtsi#0639 665 arch\arm\boot\dts\exynos4.dtsi#0654 666 arch\arm\boot\dts\exynos4.dtsi#0675 667 arch\arm\boot\dts\exynos4.dtsi#0686 668 arch\arm\boot\dts\exynos4.dtsi#0697 669 arch\arm\boot\dts\exynos4.dtsi#0727

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670 arch\arm\boot\dts\exynos4.dtsi#0737 671 arch\arm\boot\dts\exynos4.dtsi#0746 672 arch\arm\boot\dts\exynos4.dtsi#0761 673 arch\arm\boot\dts\exynos4.dtsi#0772 674 arch\arm\boot\dts\exynos4.dtsi#0999 675 arch\arm\boot\dts\exynos4210-pinctrl.dtsi#0540 Repo: 74e2c9586b25 Krzysztof Fri Sep 16 23:41:58 2016 +0200 Description: ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos4 ------Replace hard-coded values of type of GIC interrupt and its flags with respective macros from header to increase code readability.

ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4210 ------Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and generates an error: genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)

The GIC requires shared interrupts to be edge rising or level high. Platform declares support for both. Arbitrarily choose level high everywhere hoping it will work on each platform.

ARM: dts: exynos: Fix mismatched value for SD4 pull up/down configuration on exynos4210 ------The pinctrl pull up/down register on exynos4210 is 2-bit wide for each pin and it accepts only values of 0, 1 and 3. The pins sd4-bus-width8 were configured with value of 4. The driver does not validate the value so this overflow effectively set a bit 1 in adjacent pins thus configuring them to pull down.

The author's intention was probably to set drive strength of 4x. All other bus-widths pins are configured with pull up and drive strength of 4x. Fix this one with same pattern.

Fixes: 87711d8c7c70 ("ARM: dts: Add pinctrl node entries for SAMSUNG EXYNOS4210 SoC")

ARM: dts: exynos: Use macros for pinctrl configuration on exynos4210 ------Usage of DTS macros instead of hard-coded numbers makes code easier to read. One does not have to remember which value means pull-up/down or specific driver strength.

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676 arch\arm\boot\dts\exynos4210-pinctrl.dtsi#0557 677 arch\arm\boot\dts\exynos4210.dtsi#0112 Repo: 74e2c9586b25 Krzysztof Fri Sep 16 23:41:58 2016 +0200 Description: ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos4 ------Replace hard-coded values of type of GIC interrupt and its flags with respective macros from header to increase code readability.

ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4210 ------Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and generates an error: genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)

The GIC requires shared interrupts to be edge rising or level high. Platform declares support for both. Arbitrarily choose level high everywhere hoping it will work on each platform.

678 arch\arm\boot\dts\exynos4210.dtsi#0116 679 arch\arm\boot\dts\exynos4210.dtsi#0130 680 arch\arm\boot\dts\exynos4210.dtsi#0136 681 arch\arm\boot\dts\exynos4210.dtsi#0141 682 arch\arm\boot\dts\exynos4210.dtsi#0185 683 arch\arm\boot\dts\exynos4210.dtsi#0427 684 arch\arm\boot\dts\exynos4412-odroidx.dts#0067 Repo: c9a865bd4715 Markus Fri Nov 18 10:55:04 2016 +0100 Description: ARM: dts: exynos: Add ADCs on 4412 and 5422 based odroid boards. ------Odroid-X, -X2, -XU3 and -XU4 have SOC-ADC routed to an external connector. Enable the ADC for use as iio-device.

685 arch\arm\boot\dts\exynos4415-pinctrl.dtsi#fileDeleted Repo: 46dcf0ff0de3 Krzysztof Fri Oct 21 17:15:31 2016 +0300 Description: ARM: dts: exynos: Remove exynos4415.dtsi ------There are no boards in mainline using exynos4415.dtsi. These DTSIs were not tested for long. I am also not aware of any popular out-of-tree boards using this (except consumer devices released by Samsung but those cannot use mainline).

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Keeping Exynos4415 costs some useless effort so remove it.

ARM: dts: exynos: Fix mismatched values of SD drive strengh configuration on exynos4415 ------The pinctrl drive strength register on exynos4415 is 2-bit wide for each pin. The pins for SD2 were configured with value of 4. The driver does not validate the value so this overflow effectively set a bit 1 in adjacent pins thus configuring them to drive strength 2x.

The author's intention was probably to set drive strength of 4x. All other SD pins are configured with drive strength of 4x. Fix these with same pattern.

Fixes: 9246e7ff24c5 ("ARM: dts: Add dts files for exynos4415 SoC")

ARM: dts: exynos: Use macros for pinctrl configuration on exynos4415 ------Usage of DTS macros instead of hard-coded numbers makes code easier to read. One does not have to remember which value means pull-up/down or specific driver strength.

686 arch\arm\boot\dts\exynos4415.dtsi#fileDeleted Repo: 46dcf0ff0de3 Krzysztof Fri Oct 21 17:15:31 2016 +0300 Description: ARM: dts: exynos: Remove exynos4415.dtsi ------There are no boards in mainline using exynos4415.dtsi. These DTSIs were not tested for long. I am also not aware of any popular out-of-tree boards using this (except consumer devices released by Samsung but those cannot use mainline).

Keeping Exynos4415 costs some useless effort so remove it.

687 arch\arm\boot\dts\exynos4x12-pinctrl.dtsi#0575 Repo: 74e2c9586b25 Krzysztof Fri Sep 16 23:41:58 2016 +0200 Description: ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos4 ------Replace hard-coded values of type of GIC interrupt and its flags with respective macros from header to increase code readability.

ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4x12 ------

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Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and generates an error: genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)

The GIC requires shared interrupts to be edge rising or level high. Platform declares support for both. Arbitrarily choose level high everywhere hoping it will work on each platform.

ARM: dts: exynos: Use macros for pinctrl configuration on exynos4x12 ------Usage of DTS macros instead of hard-coded numbers makes code easier to read. One does not have to remember which value means pull-up/down or specific driver strength.

688 arch\arm\boot\dts\exynos4x12-pinctrl.dtsi#0592 689 arch\arm\boot\dts\exynos4x12.dtsi#0091 Repo: b4cf33e96aea Olof Fri Nov 18 18:01:09 2016 -0800 Description: Merge tag 'samsung-dt-gic-flags-4.10' of git://git.kernel. org/pub/scm/linux/kernel/git/krzk/linux into next/dt ------Topic branch with DT changes for v4.10.

Fix invalid GIC interrupt flags - type IRQ_TYPE_NONE is not allowed for GIC interrupts. Although this was working but with error messages like: genirq: Setting trigger mode 0 for irq 16 failed

Use level high interrupt instead of type none. The choice of level high was rather an arbitrary decision hoping it will work on each platform. Tests shown no issues so far.

* tag 'samsung-dt-gic-flags-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos5440 ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos5260 ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos5 ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos4 ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos3250 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5440 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5260 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5410/exynos542x ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5250 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos3250 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4x12 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4210 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4

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ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos4 ------Replace hard-coded values of type of GIC interrupt and its flags with respective macros from header to increase code readability.

ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4x12 ------Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and generates an error: genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)

The GIC requires shared interrupts to be edge rising or level high. Platform declares support for both. Arbitrarily choose level high everywhere hoping it will work on each platform.

ARM: dts: exynos: Remove "simple-bus" compatible from fimc-is node ------The "simple-bus" compatible was originally added for fimc-is only to ensure the child devices instantiation. The child devices are now being created by the parent device driver so remove the "simple-bus" compatible.

690 arch\arm\boot\dts\exynos4x12.dtsi#0095 691 arch\arm\boot\dts\exynos4x12.dtsi#0115 692 arch\arm\boot\dts\exynos4x12.dtsi#0130 693 arch\arm\boot\dts\exynos4x12.dtsi#0141 694 arch\arm\boot\dts\exynos4x12.dtsi#0150 695 arch\arm\boot\dts\exynos4x12.dtsi#0152 696 arch\arm\boot\dts\exynos4x12.dtsi#0204 697 arch\arm\boot\dts\exynos4x12.dtsi#0465 698 arch\arm\boot\dts\exynos4x12.dtsi#0548 699 arch\arm\boot\dts\exynos4x12.dtsi#0554 700 arch\arm\boot\dts\exynos4x12.dtsi#0559 701 arch\arm\boot\dts\exynos4x12.dtsi#0573 702 arch\arm\boot\dts\exynos5.dtsi#0016 Repo: 888950b0cb49 Krzysztof Fri Sep 16 23:41:59 2016 +0200 Description: ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos5

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------Replace hard-coded values of type of GIC interrupt and its flags with respective macros from header to increase code readability.

ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5 ------Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and generates an error: genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)

The GIC requires shared interrupts to be edge rising or level high. Platform declares support for both. Arbitrarily choose level high everywhere hoping it will work on each platform.

703 arch\arm\boot\dts\exynos5.dtsi#0058 704 arch\arm\boot\dts\exynos5.dtsi#0100 705 arch\arm\boot\dts\exynos5.dtsi#0112 706 arch\arm\boot\dts\exynos5.dtsi#0118 707 arch\arm\boot\dts\exynos5.dtsi#0124 708 arch\arm\boot\dts\exynos5.dtsi#0130 709 arch\arm\boot\dts\exynos5.dtsi#0136 710 arch\arm\boot\dts\exynos5.dtsi#0146 711 arch\arm\boot\dts\exynos5.dtsi#0156 712 arch\arm\boot\dts\exynos5.dtsi#0166 713 arch\arm\boot\dts\exynos5.dtsi#0183 714 arch\arm\boot\dts\exynos5250-snow-common.dtsi#0526 Repo: 4cf986348522 Javier Thu Oct 27 14:11:41 2016 -0300 Description: ARM: dts: exynos: Document eMMC/SD/SDIO devices in Snow and Peach boards ------There's a cognitive load to figure out which mmc device node corresponds to the eMMC flash, uSD card and WiFI SDIO module on the Snow, Peach Pi and Pit boards.

So it's better to have comments in the DTS to make this more clear.

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715 arch\arm\boot\dts\exynos5250-snow-common.dtsi#0540 716 arch\arm\boot\dts\exynos5250-snow-common.dtsi#0558 717 arch\arm\boot\dts\exynos5250.dtsi#0184 Repo: 888950b0cb49 Krzysztof Fri Sep 16 23:41:59 2016 +0200 Description: ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos5 ------Replace hard-coded values of type of GIC interrupt and its flags with respective macros from header to increase code readability.

ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5250 ------Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and generates an error: genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)

The GIC requires shared interrupts to be edge rising or level high. Platform declares support for both. Arbitrarily choose level high everywhere hoping it will work on each platform.

ARM: dts: exynos: Move Exynos5250 and Exynos5420 nodes under soc ------The conventions is to put SoC devices under 'soc' node. In fact other our DTSes (like exynos3250.dtsi or exynos5410.dtsi) already follow it. Adjust exynos5250 and exynos5420 DTSI to follow this convention. This is also necessary for the upcoming change in exynos5410.dtsi to inherit from common exynos5.dtsi.

718 arch\arm\boot\dts\exynos5250.dtsi#0198 719 arch\arm\boot\dts\exynos5250.dtsi#0203 720 arch\arm\boot\dts\exynos5250.dtsi#0210 721 arch\arm\boot\dts\exynos5250.dtsi#0216 722 arch\arm\boot\dts\exynos5250.dtsi#0222 723 arch\arm\boot\dts\exynos5250.dtsi#0239 724 arch\arm\boot\dts\exynos5250.dtsi#0248 725 arch\arm\boot\dts\exynos5250.dtsi#0257 726 arch\arm\boot\dts\exynos5250.dtsi#0268

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727 arch\arm\boot\dts\exynos5250.dtsi#0277 728 arch\arm\boot\dts\exynos5250.dtsi#0287 729 arch\arm\boot\dts\exynos5250.dtsi#0309 730 arch\arm\boot\dts\exynos5250.dtsi#0322 731 arch\arm\boot\dts\exynos5250.dtsi#0335 732 arch\arm\boot\dts\exynos5250.dtsi#0348 733 arch\arm\boot\dts\exynos5250.dtsi#0361 734 arch\arm\boot\dts\exynos5250.dtsi#0383 735 arch\arm\boot\dts\exynos5250.dtsi#0399 736 arch\arm\boot\dts\exynos5250.dtsi#0415 737 arch\arm\boot\dts\exynos5250.dtsi#0429 738 arch\arm\boot\dts\exynos5250.dtsi#0441 739 arch\arm\boot\dts\exynos5250.dtsi#0453 740 arch\arm\boot\dts\exynos5250.dtsi#0466 741 arch\arm\boot\dts\exynos5250.dtsi#0529 742 arch\arm\boot\dts\exynos5250.dtsi#0547 743 arch\arm\boot\dts\exynos5250.dtsi#0562 744 arch\arm\boot\dts\exynos5250.dtsi#0594 745 arch\arm\boot\dts\exynos5250.dtsi#0605 746 arch\arm\boot\dts\exynos5250.dtsi#0616 747 arch\arm\boot\dts\exynos5250.dtsi#0627 748 arch\arm\boot\dts\exynos5250.dtsi#0639 749 arch\arm\boot\dts\exynos5250.dtsi#0649 750 arch\arm\boot\dts\exynos5250.dtsi#0659 751 arch\arm\boot\dts\exynos5250.dtsi#0669 752 arch\arm\boot\dts\exynos5250.dtsi#0680 753 arch\arm\boot\dts\exynos5250.dtsi#0693 754 arch\arm\boot\dts\exynos5250.dtsi#0709 755 arch\arm\boot\dts\exynos5250.dtsi#0721

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756 arch\arm\boot\dts\exynos5260.dtsi#0013 Repo: 7184c42c5712 Krzysztof Fri Sep 16 23:42:01 2016 +0200 Description: ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos5260 ------Replace hard-coded values of type of GIC interrupt and its flags with respective macros from header to increase code readability.

ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5260 ------Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and generates an error: genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)

The GIC requires shared interrupts to be edge rising or level high. Platform declares support for both. Arbitrarily choose level high everywhere hoping it will work on each platform.

757 arch\arm\boot\dts\exynos5260.dtsi#0173 758 arch\arm\boot\dts\exynos5260.dtsi#0187 759 arch\arm\boot\dts\exynos5260.dtsi#0224 760 arch\arm\boot\dts\exynos5260.dtsi#0229 761 arch\arm\boot\dts\exynos5260.dtsi#0236 762 arch\arm\boot\dts\exynos5260.dtsi#0242 763 arch\arm\boot\dts\exynos5260.dtsi#0253 764 arch\arm\boot\dts\exynos5260.dtsi#0262 765 arch\arm\boot\dts\exynos5260.dtsi#0271 766 arch\arm\boot\dts\exynos5260.dtsi#0280 767 arch\arm\boot\dts\exynos5260.dtsi#0289 768 arch\arm\boot\dts\exynos5260.dtsi#0301 769 arch\arm\boot\dts\exynos5260.dtsi#0313 770 arch\arm\boot\dts\exynos5410-odroidxu.dts#0018 Repo: ad3b5ef7ee99 Sylwester Fri Sep 16 13:22:00 2016 +0200 Description: ARM: dts: exynos: Add entries for sound support on Odroid-XU board ------This patch adds device nodes for the AUDSS clock controller, peripheral DMA 0/1 controllers and the Audio Subsystem I2S controller. These entries are required for sound support on Odroid-XU board.

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771 arch\arm\boot\dts\exynos5410-odroidxu.dts#0061 772 arch\arm\boot\dts\exynos5410-odroidxu.dts#0093 773 arch\arm\boot\dts\exynos5410-odroidxu.dts#0499 774 arch\arm\boot\dts\exynos5410-pinctrl.dtsi#0618 Repo: ad3b5ef7ee99 Sylwester Fri Sep 16 13:22:00 2016 +0200 Description: ARM: dts: exynos: Add entries for sound support on Odroid-XU board ------This patch adds device nodes for the AUDSS clock controller, peripheral DMA 0/1 controllers and the Audio Subsystem I2S controller. These entries are required for sound support on Odroid-XU board.

ARM: dts: exynos: Use macros for pinctrl configuration on exynos5410 ------Usage of DTS macros instead of hard-coded numbers makes code easier to read. One does not have to remember which value means pull-up/down or specific driver strength.

775 arch\arm\boot\dts\exynos5410.dtsi#0019 Repo: 9782979e5a61 Arnd Wed Nov 30 22:30:32 2016 +0100 Description: Merge tag 'samsung-dt-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt ------Pull "Samsung DeviceTree second update for v4.10" from Krzysztof Kozowski:

1. Cleanups in MSHC nodes. 2. Enable ADC on Odroid boards. 3. Fix interrupt flags on recently added DMA sound nodes in Exynos5410.

* tag 'samsung-dt-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Remove the cd-gpios property for eMMC of Odroid XU3/4 ARM: dts: exynos: Specify snps, dwmac in compatible string for gmac ARM: dts: exynos: Fix invalid GIC interrupt flags in audio block of Exynos5410 ARM: dts: exynos: Add ADCs on 4412 and 5422 based odroid boards. ARM: dts: exynos: Replace "clock-freq-min-max" with "max-frequency"

Merge tag 'samsung-dt-gic-flags-4.10' of git://git.kernel. org/pub/scm/linux/kernel/git/krzk/linux into next/dt ------Topic branch with DT changes for v4.10.

Fix invalid GIC interrupt flags - type IRQ_TYPE_NONE is not allowed for GIC interrupts. Although this was working but with error messages like: genirq: Setting trigger mode 0 for irq 16 failed

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Use level high interrupt instead of type none. The choice of level high was rather an arbitrary decision hoping it will work on each platform. Tests shown no issues so far.

* tag 'samsung-dt-gic-flags-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos5440 ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos5260 ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos5 ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos4 ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos3250 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5440 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5260 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5410/exynos542x ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5250 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos3250 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4x12 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4210 ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4

ARM: dts: exynos: Fix invalid GIC interrupt flags in audio block of Exynos5410 ------Recently added audio block of Exynos5410 missed global fixup of GIC interrupt flags. Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts so use level high.

ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos5 ------Replace hard-coded values of type of GIC interrupt and its flags with respective macros from header to increase code readability.

ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5410/exynos542x ------Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and generates an error: genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)

The GIC requires shared interrupts to be edge rising or level high. Platform declares support for both. Arbitrarily choose level high everywhere hoping it will work on each platform.

ARM: dts: exynos: Add entries for sound support on Odroid-XU board ------This patch adds device nodes for the AUDSS clock controller, peripheral DMA 0/1 controllers and the Audio Subsystem I2S controller.

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These entries are required for sound support on Odroid-XU board.

ARM: dts: exynos: Add watchdog and Security SubSystem to Exynos5410 ------Move watchdog and Security SubSystem nodes from exynos5420.dtsi to file shared with Exynos5410 and configure the clocks on the latter.

ARM: dts: exynos: Add Thermal Management Unit to Exynos5410 ------Add nodes for Thermal Management Unit to exynos5410.dtsi. Use the same compatible as for Exynos5420 however without second base for TRIMINFO register and without TMU for GPU.

776 arch\arm\boot\dts\exynos5410.dtsi#0086 777 arch\arm\boot\dts\exynos5410.dtsi#0097 778 arch\arm\boot\dts\exynos5410.dtsi#0106 779 arch\arm\boot\dts\exynos5410.dtsi#0115 780 arch\arm\boot\dts\exynos5410.dtsi#0124 781 arch\arm\boot\dts\exynos5410.dtsi#0133 782 arch\arm\boot\dts\exynos5410.dtsi#0145 783 arch\arm\boot\dts\exynos5410.dtsi#0157 784 arch\arm\boot\dts\exynos5410.dtsi#0169 785 arch\arm\boot\dts\exynos5410.dtsi#0174 786 arch\arm\boot\dts\exynos5410.dtsi#0181 787 arch\arm\boot\dts\exynos5410.dtsi#0187 788 arch\arm\boot\dts\exynos5410.dtsi#0193 789 arch\arm\boot\dts\exynos5410.dtsi#0195 790 arch\arm\boot\dts\exynos5410.dtsi#0391 791 arch\arm\boot\dts\exynos5420-peach-pit.dts#0700 Repo: 4cf986348522 Javier Thu Oct 27 14:11:41 2016 -0300 Description: ARM: dts: exynos: Document eMMC/SD/SDIO devices in Snow and Peach boards ------There's a cognitive load to figure out which mmc device node corresponds to the eMMC flash, uSD card and WiFI SDIO module on the Snow, Peach Pi and Pit boards.

So it's better to have comments in the DTS to make this more clear.

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792 arch\arm\boot\dts\exynos5420-peach-pit.dts#0718 793 arch\arm\boot\dts\exynos5420-peach-pit.dts#0738 794 arch\arm\boot\dts\exynos5420.dtsi#0196 Repo: 6abdf8d135b7 Krzysztof Fri Sep 16 21:42:49 2016 +0200 Description: ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5410/exynos542x ------Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and generates an error: genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)

The GIC requires shared interrupts to be edge rising or level high. Platform declares support for both. Arbitrarily choose level high everywhere hoping it will work on each platform.

795 arch\arm\boot\dts\exynos5420.dtsi#0206 796 arch\arm\boot\dts\exynos5420.dtsi#0218 797 arch\arm\boot\dts\exynos5420.dtsi#0230 798 arch\arm\boot\dts\exynos5420.dtsi#0323 799 arch\arm\boot\dts\exynos5420.dtsi#0328 800 arch\arm\boot\dts\exynos5420.dtsi#0335 801 arch\arm\boot\dts\exynos5420.dtsi#0341 802 arch\arm\boot\dts\exynos5420.dtsi#0347 803 arch\arm\boot\dts\exynos5420.dtsi#0353 804 arch\arm\boot\dts\exynos5420.dtsi#0366 805 arch\arm\boot\dts\exynos5420.dtsi#0377 806 arch\arm\boot\dts\exynos5420.dtsi#0388 807 arch\arm\boot\dts\exynos5420.dtsi#0399 808 arch\arm\boot\dts\exynos5420.dtsi#0410 809 arch\arm\boot\dts\exynos5420.dtsi#0482 810 arch\arm\boot\dts\exynos5420.dtsi#0498 811 arch\arm\boot\dts\exynos5420.dtsi#0514 812 arch\arm\boot\dts\exynos5420.dtsi#0542

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813 arch\arm\boot\dts\exynos5420.dtsi#0555 814 arch\arm\boot\dts\exynos5420.dtsi#0567 815 arch\arm\boot\dts\exynos5420.dtsi#0580 816 arch\arm\boot\dts\exynos5420.dtsi#0593 817 arch\arm\boot\dts\exynos5420.dtsi#0606 818 arch\arm\boot\dts\exynos5420.dtsi#0625 819 arch\arm\boot\dts\exynos5420.dtsi#0636 820 arch\arm\boot\dts\exynos5420.dtsi#0645 821 arch\arm\boot\dts\exynos5420.dtsi#0655 822 arch\arm\boot\dts\exynos5420.dtsi#0665 823 arch\arm\boot\dts\exynos5420.dtsi#0674 824 arch\arm\boot\dts\exynos5420.dtsi#0694 825 arch\arm\boot\dts\exynos5420.dtsi#0703 826 arch\arm\boot\dts\exynos5420.dtsi#0712 827 arch\arm\boot\dts\exynos5420.dtsi#0721 828 arch\arm\boot\dts\exynos5420.dtsi#0730 829 arch\arm\boot\dts\exynos5420.dtsi#0802 830 arch\arm\boot\dts\exynos5420.dtsi#0811 831 arch\arm\boot\dts\exynos5420.dtsi#0870 832 arch\arm\boot\dts\exynos5420.dtsi#1448 833 arch\arm\boot\dts\exynos5422-odroidxu3-common.dtsi#0150 Repo: 79700041b37f Jaehoon Mon Nov 21 16:10:32 2016 +0900 Description: ARM: dts: exynos: Remove the cd-gpios property for eMMC of Odroid XU3/4 ------Odroid XU3/4 didn't need to use the cd-gpios for detecting card. Because host controller has the CDETECT register through SDx_CDN line. Host controller can know whether card is inserted or not with this register.

When I have checked the Odroid XU3/4, they are using CDETECT register (not using exteranl cd-gpio).

ARM: dts: exynos: Add ADCs on 4412 and 5422 based odroid boards. ------Odroid-X, -X2, -XU3 and -XU4 have SOC-ADC routed to an external connector. Enable the ADC for use as iio-device.

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834 arch\arm\boot\dts\exynos5422-odroidxu3-common.dtsi#0301 835 arch\arm\boot\dts\exynos5422-odroidxu3-common.dtsi#0513 836 arch\arm\boot\dts\exynos5440.dtsi#0013 Repo: 9782979e5a61 Arnd Wed Nov 30 22:30:32 2016 +0100 Description: Merge tag 'samsung-dt-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt ------Pull "Samsung DeviceTree second update for v4.10" from Krzysztof Kozowski:

1. Cleanups in MSHC nodes. 2. Enable ADC on Odroid boards. 3. Fix interrupt flags on recently added DMA sound nodes in Exynos5410.

* tag 'samsung-dt-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Remove the cd-gpios property for eMMC of Odroid XU3/4 ARM: dts: exynos: Specify snps, dwmac in compatible string for gmac ARM: dts: exynos: Fix invalid GIC interrupt flags in audio block of Exynos5410 ARM: dts: exynos: Add ADCs on 4412 and 5422 based odroid boards. ARM: dts: exynos: Replace "clock-freq-min-max" with "max-frequency"

ARM: dts: exynos: Specify snps, dwmac in compatible string for gmac ------devicetree binding for stmmac states: - compatible: Should be "snps,dwmac-", "snps,dwmac" For backwards compatibility: "st,spear600-gmac" is also supported.

No functional change intended.

ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos5440 ------Replace hard-coded values of type of GIC interrupt and its flags with respective macros from header to increase code readability.

ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5440 ------Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and generates an error: genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)

The GIC requires shared interrupts to be edge rising or level high. Platform declares support for both. Arbitrarily choose level high everywhere hoping it will work on each platform.

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837 arch\arm\boot\dts\exynos5440.dtsi#0046 838 arch\arm\boot\dts\exynos5440.dtsi#0078 839 arch\arm\boot\dts\exynos5440.dtsi#0087 840 arch\arm\boot\dts\exynos5440.dtsi#0097 841 arch\arm\boot\dts\exynos5440.dtsi#0114 842 arch\arm\boot\dts\exynos5440.dtsi#0122 843 arch\arm\boot\dts\exynos5440.dtsi#0130 844 arch\arm\boot\dts\exynos5440.dtsi#0142 845 arch\arm\boot\dts\exynos5440.dtsi#0174 846 arch\arm\boot\dts\exynos5440.dtsi#0184 847 arch\arm\boot\dts\exynos5440.dtsi#0194 848 arch\arm\boot\dts\exynos5440.dtsi#0200 849 arch\arm\boot\dts\exynos5440.dtsi#0203 850 arch\arm\boot\dts\exynos5440.dtsi#0221 851 arch\arm\boot\dts\exynos5440.dtsi#0230 852 arch\arm\boot\dts\exynos5440.dtsi#0239 853 arch\arm\boot\dts\exynos5440.dtsi#0248 854 arch\arm\boot\dts\exynos5440.dtsi#0272 855 arch\arm\boot\dts\exynos5440.dtsi#0280 856 arch\arm\boot\dts\exynos5440.dtsi#0288 857 arch\arm\boot\dts\exynos5440.dtsi#0298 858 arch\arm\boot\dts\exynos5440.dtsi#0321 859 arch\arm\boot\dts\exynos54xx.dtsi#0065 Repo: 888950b0cb49 Krzysztof Fri Sep 16 23:41:59 2016 +0200 Description: ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos5 ------Replace hard-coded values of type of GIC interrupt and its flags with respective macros from header to increase code readability.

ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5410/exynos542x ------Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and generates an error: genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)

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The GIC requires shared interrupts to be edge rising or level high. Platform declares support for both. Arbitrarily choose level high everywhere hoping it will work on each platform.

860 arch\arm\boot\dts\exynos54xx.dtsi#0079 861 arch\arm\boot\dts\exynos54xx.dtsi#0085 862 arch\arm\boot\dts\exynos54xx.dtsi#0092 863 arch\arm\boot\dts\exynos54xx.dtsi#0101 864 arch\arm\boot\dts\exynos54xx.dtsi#0110 865 arch\arm\boot\dts\exynos54xx.dtsi#0119 866 arch\arm\boot\dts\exynos54xx.dtsi#0134 867 arch\arm\boot\dts\exynos54xx.dtsi#0169 868 arch\arm\boot\dts\exynos54xx.dtsi#0182 869 arch\arm\boot\dts\exynos5800-peach-pi.dts#0668 Repo: 4cf986348522 Javier Thu Oct 27 14:11:41 2016 -0300 Description: ARM: dts: exynos: Document eMMC/SD/SDIO devices in Snow and Peach boards ------There's a cognitive load to figure out which mmc device node corresponds to the eMMC flash, uSD card and WiFI SDIO module on the Snow, Peach Pi and Pit boards.

So it's better to have comments in the DTS to make this more clear.

870 arch\arm\boot\dts\exynos5800-peach-pi.dts#0687 871 arch\arm\boot\dts\exynos5800-peach-pi.dts#0707 872 arch\arm\boot\dts\hi3620.dtsi#0014 Repo: f3dcae8f4d36 Olof Fri Nov 18 10:38:47 2016 -0800 Description: Merge tag 'hisi-armv7-soc-dt-for-4.10' of git://github.com/hisilicon/linux-hisi into next/dt ------ARM: DT: Hisilicon ARMv7 SoC DT updates for 4.10

- Remove skeleton.dtsi inclusion for the Hip01, Hi3620 and Hix5hd2

* tag 'hisi-armv7-soc-dt-for-4.10' of git://github.com/hisilicon/linux-hisi: ARM: dts: hisi-x5hd2: Remove skeleton.dtsi inclusion ARM: dts: hi3620: Remove skeleton.dtsi inclusion ARM: dts: hip01: Remove skeleton.dtsi inclusion

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ARM: dts: hi3620: Remove skeleton.dtsi inclusion ------Since commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), remove deprecated skeleton.dtsi.

ARM: dts: Add #pinctrl-cells for pinctrl-single instances ------Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the driver changes as the driver supports also the legacy binding without #pinctrl-cells.

873 arch\arm\boot\dts\hi3620.dtsi#0018 874 arch\arm\boot\dts\hi3620.dtsi#0542 875 arch\arm\boot\dts\hi3620.dtsi#0564 876 arch\arm\boot\dts\hip01.dtsi#0014 Repo: ca34ab20255d Kefeng Mon Oct 24 16:31:28 2016 +0800 Description: ARM: dts: hip01: Remove skeleton.dtsi inclusion ------Since commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), remove deprecated skeleton.dtsi.

877 arch\arm\boot\dts\hisi-x5hd2.dtsi#0010 Repo: 48fed73ab6d2 Dongpo Li Tue Dec 20 10:09:29 2016 +0800 Description: ARM: dts: hix5hd2: don't change the existing compatible string ------The SoC hix5hd2 compatible string has the suffix "-gmac" and we should not change it. We should only add the generic compatible string "hisi-gmac-v1".

Fixes: 0855950ba580 ("ARM: dts: hix5hd2: add gmac generic compatible and clock names")

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

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We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

- The old STiH415/416 SoC support gets removed, these never made it

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into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

ARM: dts: hix5hd2: add gmac generic compatible and clock names ------Add gmac generic compatible and clock names.

ARM: dts: hisi-x5hd2: Remove skeleton.dtsi inclusion ------Since commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), remove deprecated skeleton.dtsi.

878 arch\arm\boot\dts\hisi-x5hd2.dtsi#0014 879 arch\arm\boot\dts\hisi-x5hd2.dtsi#0441

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880 arch\arm\boot\dts\hisi-x5hd2.dtsi#0445 881 arch\arm\boot\dts\hisi-x5hd2.dtsi#0450 882 arch\arm\boot\dts\hisi-x5hd2.dtsi#0454 883 arch\arm\boot\dts\imx1.dtsi#0012 Repo: a971c5545c3d Fabio Mon Jan 23 14:54:10 2017 -0200 Description: ARM: dts: imx: Pass 'chosen' and 'memory' nodes ------Commit 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi") causes boot issues when the bootloader does not create a 'chosen' node if such node is not present in the dtb.

The reason for the boot failure is well explained by Javier Martinez Canillas: "the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info."

, so pass an empty 'chosen' node to fix the boot problem.

This issue has been seen in the kernelci reports with Barebox as bootloader.

Also pass the 'memory' node in order to fix boot issues on the SolidRun iMX6 platforms.

Fixes: 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi")

ARM: dts: imx: Remove skeleton.dtsi ------As explained by commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

884 arch\arm\boot\dts\imx1.dtsi#0020 885 arch\arm\boot\dts\imx23.dtsi#0012 Repo: a971c5545c3d Fabio Mon Jan 23 14:54:10 2017 -0200 Description: ARM: dts: imx: Pass 'chosen' and 'memory' nodes ------Commit 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi") causes boot issues when the bootloader does not create a 'chosen' node if such node is not present in the dtb.

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The reason for the boot failure is well explained by Javier Martinez Canillas: "the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info."

, so pass an empty 'chosen' node to fix the boot problem.

This issue has been seen in the kernelci reports with Barebox as bootloader.

Also pass the 'memory' node in order to fix boot issues on the SolidRun iMX6 platforms.

Fixes: 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi")

ARM: dts: imx: Remove skeleton.dtsi ------As explained by commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

ARM: dts: imx: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx23, imx51, imx53, imx6dl, imx6q and imx6sx dtsi and dts files.

ARM: dts: mxs: add missing reg properties for GPIO banks ------This patch adds the missing reg properties for the MXS GPIO banks in order to fix the dtc warnings.

ARM: dts: mxs: Add AUART2 pinmux ------Add 2-pin pinmux settings for AUART2.

886 arch\arm\boot\dts\imx23.dtsi#0016 887 arch\arm\boot\dts\imx23.dtsi#0019 888 arch\arm\boot\dts\imx23.dtsi#0477

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889 arch\arm\boot\dts\imx25.dtsi#0012 Repo: a971c5545c3d Fabio Mon Jan 23 14:54:10 2017 -0200 Description: ARM: dts: imx: Pass 'chosen' and 'memory' nodes ------Commit 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi") causes boot issues when the bootloader does not create a 'chosen' node if such node is not present in the dtb.

The reason for the boot failure is well explained by Javier Martinez Canillas: "the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info."

, so pass an empty 'chosen' node to fix the boot problem.

This issue has been seen in the kernelci reports with Barebox as bootloader.

Also pass the 'memory' node in order to fix boot issues on the SolidRun iMX6 platforms.

Fixes: 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi")

ARM: dts: imx: Remove skeleton.dtsi ------As explained by commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

890 arch\arm\boot\dts\imx25.dtsi#0016 891 arch\arm\boot\dts\imx27.dtsi#0012 Repo: a971c5545c3d Fabio Mon Jan 23 14:54:10 2017 -0200 Description: ARM: dts: imx: Pass 'chosen' and 'memory' nodes ------Commit 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi") causes boot issues when the bootloader does not create a 'chosen' node if such node is not present in the dtb.

The reason for the boot failure is well explained by Javier Martinez Canillas: "the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info."

, so pass an empty 'chosen' node to fix the boot problem.

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This issue has been seen in the kernelci reports with Barebox as bootloader.

Also pass the 'memory' node in order to fix boot issues on the SolidRun iMX6 platforms.

Fixes: 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi")

ARM: dts: imx: Remove skeleton.dtsi ------As explained by commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

892 arch\arm\boot\dts\imx27.dtsi#0021 893 arch\arm\boot\dts\imx28-m28.dtsi#0015 Repo: 8df0547fb11f Marek Vasut Mon Sep 19 23:40:41 2016 +0200 Description: ARM: dts: mxs: Add new M28EVK manufacturer compat ------The board is now manufactured by Aries Embedded GmbH, update compat string.

894 arch\arm\boot\dts\imx28-m28evk.dts#0016 Repo: 8df0547fb11f Marek Vasut Mon Sep 19 23:40:41 2016 +0200 Description: ARM: dts: mxs: Add new M28EVK manufacturer compat ------The board is now manufactured by Aries Embedded GmbH, update compat string.

895 arch\arm\boot\dts\imx28.dtsi#0013 Repo: a971c5545c3d Fabio Mon Jan 23 14:54:10 2017 -0200 Description: ARM: dts: imx: Pass 'chosen' and 'memory' nodes ------Commit 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi") causes boot issues when the bootloader does not create a 'chosen' node if such node is not present in the dtb.

The reason for the boot failure is well explained by Javier Martinez Canillas: "the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info."

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, so pass an empty 'chosen' node to fix the boot problem.

This issue has been seen in the kernelci reports with Barebox as bootloader.

Also pass the 'memory' node in order to fix boot issues on the SolidRun iMX6 platforms.

Fixes: 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi")

ARM: dts: imx: Remove skeleton.dtsi ------As explained by commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

896 arch\arm\boot\dts\imx28.dtsi#0017 897 arch\arm\boot\dts\imx28.dtsi#0020 898 arch\arm\boot\dts\imx31.dtsi#0012 Repo: a971c5545c3d Fabio Mon Jan 23 14:54:10 2017 -0200 Description: ARM: dts: imx: Pass 'chosen' and 'memory' nodes ------Commit 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi") causes boot issues when the bootloader does not create a 'chosen' node if such node is not present in the dtb.

The reason for the boot failure is well explained by Javier Martinez Canillas: "the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info."

, so pass an empty 'chosen' node to fix the boot problem.

This issue has been seen in the kernelci reports with Barebox as bootloader.

Also pass the 'memory' node in order to fix boot issues on the SolidRun iMX6 platforms.

Fixes: 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi")

ARM: dts: imx31: fix AVIC base address

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------On i.MX31 AVIC interrupt controller base address is at 0x68000000.

The problem was shadowed by the AVIC driver, which takes the correct base address from a SoC specific header file.

Fixes: d2a37b3d91f4 ("ARM i.MX31: Add devicetree support")

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board

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- AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

ARM: dts: imx: Remove skeleton.dtsi ------

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As explained by commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

ARM: dts: imx31: move CCM device node to AIPS2 bus devices ------i.MX31 Clock Control Module controller is found on AIPS2 bus, move it there from SPBA bus to avoid a conflict of device IO space mismatch.

Fixes: ef0e4a606fb6 ("ARM: mx31: Replace clk_register_clkdev with clock DT lookup")

ARM: dts: imx31: fix clock control module interrupts description ------The type of AVIC interrupt controller found on i.MX31 is one-cell, namely 31 for CCM DVFS and 53 for CCM, however for clock control module its interrupts are specified as 3-cells, fix it.

Fixes: ef0e4a606fb6 ("ARM: mx31: Replace clk_register_clkdev with clock DT lookup")

899 arch\arm\boot\dts\imx31.dtsi#0015 900 arch\arm\boot\dts\imx31.dtsi#0042 901 arch\arm\boot\dts\imx31.dtsi#0046 902 arch\arm\boot\dts\imx31.dtsi#0130 903 arch\arm\boot\dts\imx31.dtsi#0139 904 arch\arm\boot\dts\imx35.dtsi#0011 Repo: a971c5545c3d Fabio Mon Jan 23 14:54:10 2017 -0200 Description: ARM: dts: imx: Pass 'chosen' and 'memory' nodes ------Commit 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi") causes boot issues when the bootloader does not create a 'chosen' node if such node is not present in the dtb.

The reason for the boot failure is well explained by Javier Martinez Canillas: "the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info."

, so pass an empty 'chosen' node to fix the boot problem.

This issue has been seen in the kernelci reports with Barebox as bootloader.

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Also pass the 'memory' node in order to fix boot issues on the SolidRun iMX6 platforms.

Fixes: 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi")

ARM: dts: imx: Remove skeleton.dtsi ------As explained by commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

905 arch\arm\boot\dts\imx35.dtsi#0015 906 arch\arm\boot\dts\imx50.dtsi#0014 Repo: a971c5545c3d Fabio Mon Jan 23 14:54:10 2017 -0200 Description: ARM: dts: imx: Pass 'chosen' and 'memory' nodes ------Commit 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi") causes boot issues when the bootloader does not create a 'chosen' node if such node is not present in the dtb.

The reason for the boot failure is well explained by Javier Martinez Canillas: "the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info."

, so pass an empty 'chosen' node to fix the boot problem.

This issue has been seen in the kernelci reports with Barebox as bootloader.

Also pass the 'memory' node in order to fix boot issues on the SolidRun iMX6 platforms.

Fixes: 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi")

ARM: dts: imx: Remove skeleton.dtsi ------As explained by commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

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ARM: dts: imx: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx23, imx51, imx53, imx6dl, imx6q and imx6sx dtsi and dts files.

907 arch\arm\boot\dts\imx50.dtsi#0019 908 arch\arm\boot\dts\imx50.dtsi#0116 909 arch\arm\boot\dts\imx50.dtsi#0128 910 arch\arm\boot\dts\imx50.dtsi#0140 911 arch\arm\boot\dts\imx50.dtsi#0152 912 arch\arm\boot\dts\imx50.dtsi#0177 913 arch\arm\boot\dts\imx50.dtsi#0189 914 arch\arm\boot\dts\imx50.dtsi#0292 915 arch\arm\boot\dts\imx50.dtsi#0311 916 arch\arm\boot\dts\imx50.dtsi#0321 917 arch\arm\boot\dts\imx50.dtsi#0331 918 arch\arm\boot\dts\imx50.dtsi#0341 919 arch\arm\boot\dts\imx50.dtsi#0396 920 arch\arm\boot\dts\imx50.dtsi#0414 921 arch\arm\boot\dts\imx50.dtsi#0433 922 arch\arm\boot\dts\imx50.dtsi#0443 923 arch\arm\boot\dts\imx50.dtsi#0455 924 arch\arm\boot\dts\imx50.dtsi#0505 925 arch\arm\boot\dts\imx51.dtsi#0013 Repo: a971c5545c3d Fabio Mon Jan 23 14:54:10 2017 -0200 Description: ARM: dts: imx: Pass 'chosen' and 'memory' nodes ------Commit 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi") causes boot issues when the bootloader does not create a 'chosen' node if such node is not present in the dtb.

The reason for the boot failure is well explained by Javier Martinez Canillas: "the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info."

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, so pass an empty 'chosen' node to fix the boot problem.

This issue has been seen in the kernelci reports with Barebox as bootloader.

Also pass the 'memory' node in order to fix boot issues on the SolidRun iMX6 platforms.

Fixes: 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi")

ARM: dts: imx: Remove skeleton.dtsi ------As explained by commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

ARM: dts: imx: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx23, imx51, imx53, imx6dl, imx6q and imx6sx dtsi and dts files.

926 arch\arm\boot\dts\imx51.dtsi#0021 927 arch\arm\boot\dts\imx51.dtsi#0143 928 arch\arm\boot\dts\imx51.dtsi#0182 929 arch\arm\boot\dts\imx51.dtsi#0193 930 arch\arm\boot\dts\imx51.dtsi#0205 931 arch\arm\boot\dts\imx51.dtsi#0217 932 arch\arm\boot\dts\imx51.dtsi#0242 933 arch\arm\boot\dts\imx51.dtsi#0254 934 arch\arm\boot\dts\imx51.dtsi#0377 935 arch\arm\boot\dts\imx51.dtsi#0391 936 arch\arm\boot\dts\imx51.dtsi#0401 937 arch\arm\boot\dts\imx51.dtsi#0411

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938 arch\arm\boot\dts\imx51.dtsi#0421 939 arch\arm\boot\dts\imx51.dtsi#0469 940 arch\arm\boot\dts\imx51.dtsi#0479 941 arch\arm\boot\dts\imx51.dtsi#0492 942 arch\arm\boot\dts\imx51.dtsi#0595 943 arch\arm\boot\dts\imx53-m53.dtsi#0015 Repo: 982742913275 Marek Vasut Mon Sep 19 23:40:42 2016 +0200 Description: ARM: dts: mx5: Add new M53EVK manufacturer compat ------The board is now manufactured by Aries Embedded GmbH, update compat string.

944 arch\arm\boot\dts\imx53-m53evk.dts#0016 Repo: 982742913275 Marek Vasut Mon Sep 19 23:40:42 2016 +0200 Description: ARM: dts: mx5: Add new M53EVK manufacturer compat ------The board is now manufactured by Aries Embedded GmbH, update compat string.

945 arch\arm\boot\dts\imx53.dtsi#0013 Repo: a971c5545c3d Fabio Mon Jan 23 14:54:10 2017 -0200 Description: ARM: dts: imx: Pass 'chosen' and 'memory' nodes ------Commit 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi") causes boot issues when the bootloader does not create a 'chosen' node if such node is not present in the dtb.

The reason for the boot failure is well explained by Javier Martinez Canillas: "the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info."

, so pass an empty 'chosen' node to fix the boot problem.

This issue has been seen in the kernelci reports with Barebox as bootloader.

Also pass the 'memory' node in order to fix boot issues on the SolidRun iMX6 platforms.

Fixes: 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi")

ARM: dts: imx: Remove skeleton.dtsi ------

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As explained by commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

ARM: dts: imx: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx23, imx51, imx53, imx6dl, imx6q and imx6sx dtsi and dts files.

ARM: dts: imx53: Add IPU nodes for csi ------We have the following messages that tell csi devices are not used: imx-ipuv3 18000000.ipu: no port@0 node in /soc/ipu@18000000, not using CSI0 imx-ipuv3 18000000.ipu: no port@1 node in /soc/ipu@18000000, not using CSI1

So we add them in the common device tree to make CSI ports available on imx53 boards.

946 arch\arm\boot\dts\imx53.dtsi#0021 947 arch\arm\boot\dts\imx53.dtsi#0144 948 arch\arm\boot\dts\imx53.dtsi#0212 949 arch\arm\boot\dts\imx53.dtsi#0224 950 arch\arm\boot\dts\imx53.dtsi#0236 951 arch\arm\boot\dts\imx53.dtsi#0250 952 arch\arm\boot\dts\imx53.dtsi#0277 953 arch\arm\boot\dts\imx53.dtsi#0289 954 arch\arm\boot\dts\imx53.dtsi#0432 955 arch\arm\boot\dts\imx53.dtsi#0453 956 arch\arm\boot\dts\imx53.dtsi#0499 957 arch\arm\boot\dts\imx53.dtsi#0509 958 arch\arm\boot\dts\imx53.dtsi#0519

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959 arch\arm\boot\dts\imx53.dtsi#0531 960 arch\arm\boot\dts\imx53.dtsi#0543 961 arch\arm\boot\dts\imx53.dtsi#0553 962 arch\arm\boot\dts\imx53.dtsi#0616 963 arch\arm\boot\dts\imx53.dtsi#0648 964 arch\arm\boot\dts\imx53.dtsi#0669 965 arch\arm\boot\dts\imx53.dtsi#0679 966 arch\arm\boot\dts\imx53.dtsi#0692 967 arch\arm\boot\dts\imx53.dtsi#0768 968 arch\arm\boot\dts\imx53.dtsi#0779 969 arch\arm\boot\dts\imx53.dtsi#0795 970 arch\arm\boot\dts\imx53.dtsi#0806 971 arch\arm\boot\dts\imx6dl-riotboard.dts#0393 Repo: 46311707939f Jagan Teki Wed Oct 26 15:31:01 2016 +0530 Description: ARM: dts: imx: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx23, imx51, imx53, imx6dl, imx6q and imx6sx dtsi and dts files.

972 arch\arm\boot\dts\imx6dl-tx6dl-comtft.dts#0108 Repo: 46311707939f Jagan Teki Wed Oct 26 15:31:01 2016 +0530 Description: ARM: dts: imx: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx23, imx51, imx53, imx6dl, imx6q and imx6sx dtsi and dts files.

973 arch\arm\boot\dts\imx6dl-tx6u-801x.dts#0202 Repo: 46311707939f Jagan Teki Wed Oct 26 15:31:01 2016 +0530 Description: ARM: dts: imx: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx23, imx51, imx53, imx6dl, imx6q and imx6sx dtsi and dts files.

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Review der Linux Kernel Sourcen von 4.9 auf 4.10

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974 arch\arm\boot\dts\imx6dl.dtsi#0140 Repo: 7f59b319111b Sébastien Wed Jan 18 11:09:51 2017 +0100 Description: ARM: dts: imx6dl: fix GPIO4 range ------GPIO4_11 is on pin 152(MX6DL_PAD_KEY_ROW2) and not on pin 151(MX6DL_PAD_KEY_ROW1).

I found the error while booting a mainline kernel on APF6S SoM and noticed the following message:

[ 2.609337] imx6dl-pinctrl 20e0000.iomuxc: pin MX6DL_PAD_KEY_ROW1 already requested by 20a8000.gpio:105; cannot claim for 20a8000.gpio:107 [ 2.621884] imx6dl-pinctrl 20e0000.iomuxc: pin-151 (20a8000.gpio:107) status -22 [ 2.629303] spi_imx 2008000.ecspi: Can't get CS GPIO 107

With this patch, the message is gone and spi_imx driver probes correctly.

Fixes: bb728d662bed ("ARM: dts: add gpio-ranges property to iMX GPIO controllers")

975 arch\arm\boot\dts\imx6q-apalis-ixora.dts#0150 Repo: aacf62465aca Sanchayan Mon Sep 19 10:41:52 2016 +0530 Description: ARM: dts: imx6q-apalis-ixora: Remove use of pwm-leds ------Remove use of pwm-leds and use the standard /sys/class/pwm interface from PWM subsystem.

976 arch\arm\boot\dts\imx6q-b650v3.dts#0101 Repo: 371a8dd6fa75 Jaret Cantu Wed Sep 14 17:14:49 2016 -0400 Description: ARM: dts: imx: b650v3: Calibrate USB PHY to pass eye diagram test ------Calibrate the USB PHY TX settings to pass the eye diagram signal integrity test. The settings are taken from the i.MX6 reference manual's recommended configuration for USB certification (66.2.6).

977 arch\arm\boot\dts\imx6q-cm-fx6.dts#0186 Repo: 72649a460679 Christopher Fri Nov 11 16:59:38 2016 +0100 Description: ARM: dts: imx6q-cm-fx6: fix fec pinctrl ------According to the schematics of CompuLab's sbc-fx6 baseboard and the vendor devicetree GPIO_16 is *not* muxed to ENET_REF_CLK but to SPDIF_IN.

Remove the wrong pinctrl setting.

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Fixes: 682d055e6ac5 ("ARM: dts: Add initial support for cm-fx6.")

978 arch\arm\boot\dts\imx6q-evi.dts#0235 Repo: 1be81ea58607 Joshua Tue Nov 1 16:51:45 2016 -0700 Description: ARM: dts: imx6: Add imx-weim parameters to dtsi's ------imx-weim should always set address-cells to 2, and size_cells to 1. On imx6, fsl,weim-cs-gpr will always be &gpr

Set these common parameters in the dtsi file, rather than in a downstream dts.

979 arch\arm\boot\dts\imx6q-evi.dts#0238 980 arch\arm\boot\dts\imx6q-novena.dts#0454 Repo: 95a36c119781 Marek Vasut Mon Oct 17 18:34:49 2016 +0200 Description: ARM: dts: novena: Enable PWM1 ------Enable PWM1, otherwise the backlight cannot work.

981 arch\arm\boot\dts\imx6q-phytec-pbab01.dts#0026 Repo: 46311707939f Jagan Teki Wed Oct 26 15:31:01 2016 +0530 Description: ARM: dts: imx: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx23, imx51, imx53, imx6dl, imx6q and imx6sx dtsi and dts files.

ARM: dts: Add stdout-path property to i.MX boards ------This adds the stdout-path property to various i.MX boards. Values of the property have been taken from barebox, so they should be correct. Also, the older linux,stdout-path property is converted to stdout-path.

982 arch\arm\boot\dts\imx6q-tx6q-1010-comtft.dts#0108 Repo: 46311707939f Jagan Teki Wed Oct 26 15:31:01 2016 +0530 Description: ARM: dts: imx: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx23, imx51, imx53, imx6dl, imx6q and imx6sx dtsi and dts files.

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983 arch\arm\boot\dts\imx6q-tx6q-1010.dts#0202 Repo: 46311707939f Jagan Teki Wed Oct 26 15:31:01 2016 +0530 Description: ARM: dts: imx: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx23, imx51, imx53, imx6dl, imx6q and imx6sx dtsi and dts files.

984 arch\arm\boot\dts\imx6q-tx6q-1020-comtft.dts#0108 Repo: 46311707939f Jagan Teki Wed Oct 26 15:31:01 2016 +0530 Description: ARM: dts: imx: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx23, imx51, imx53, imx6dl, imx6q and imx6sx dtsi and dts files.

ARM: dts: imx6-tx6: remove container node around pinctrl nodes ------Remove the function node around the pinctrl nodes that was obsoleted by commit 5fcdf6a7ed95 ("pinctrl: imx: Allow parsing DT without function nodes"), we can save this container node.

Also move the iomux node to the bottom of the file to improve readability of the file.

985 arch\arm\boot\dts\imx6q-tx6q-1020.dts#0202 Repo: 46311707939f Jagan Teki Wed Oct 26 15:31:01 2016 +0530 Description: ARM: dts: imx: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx23, imx51, imx53, imx6dl, imx6q and imx6sx dtsi and dts files.

ARM: dts: imx6-tx6: remove container node around pinctrl nodes ------Remove the function node around the pinctrl nodes that was obsoleted by commit 5fcdf6a7ed95 ("pinctrl: imx: Allow parsing DT without function nodes"), we can save this container node.

Also move the iomux node to the bottom of the file to improve readability of the file.

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986 arch\arm\boot\dts\imx6q-utilite-pro.dts#0071 Repo: 70e105ad35ac Sudeep Mon Nov 14 15:44:09 2016 +0000 Description: ARM: dts: imx6q: replace gpio-key,wakeup with wakeup-source for Utilite Pro ------Though the keyboard driver for GPIO buttons(gpio-keys) will continue to check for/support the legacy "gpio-key,wakeup" boolean property to enable gpio buttons as wakeup source, "wakeup-source" is the new standard binding.

This patch replaces the legacy "gpio-key,wakeup" with the unified "wakeup-source" property in order to avoid any further copy-paste duplication.

ARM: dts: imx6q-utilite-pro: i2c1 is muxed ------It turns out that the i2c1 adapter is connected to a multiplexer controlled by a gpio line. The first (default) mux option connects i2c1 to a bus connected to the already known peripherals. The other one connects the adapter to the ddc pins of the DVI port.

987 arch\arm\boot\dts\imx6q-utilite-pro.dts#0074 988 arch\arm\boot\dts\imx6q-utilite-pro.dts#0119 989 arch\arm\boot\dts\imx6q-utilite-pro.dts#0141 990 arch\arm\boot\dts\imx6qdl-apalis.dtsi#0052 Repo: ebedca04ec6f Sanchayan Mon Sep 19 10:41:53 2016 +0530 Description: ARM: dts: imx6qdl-apalis: Use enable-gpios property for backlight ------Use enable-gpios property of PWM backlight driver for backlight control.

991 arch\arm\boot\dts\imx6qdl-apalis.dtsi#0055 992 arch\arm\boot\dts\imx6qdl-apalis.dtsi#0626 993 arch\arm\boot\dts\imx6qdl-apf6dev.dtsi#0350 Repo: 05c183e44be7 Jagan Teki Fri Oct 14 15:09:28 2016 +0530 Description: ARM: dts: imx6qdl: Fix "WARNING: please, no space before tabs" ------Fixed no space before tabs warnings in respetcive imx6qdl dtsi files.

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994 arch\arm\boot\dts\imx6qdl-gw52xx.dtsi#0156 Repo: bf5393c5ec9c Jagan Teki Fri Oct 14 15:09:29 2016 +0530 Description: ARM: dts: imx6qdl: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx6qdl dtsi files.

995 arch\arm\boot\dts\imx6qdl-gw52xx.dtsi#0158 996 arch\arm\boot\dts\imx6qdl-gw53xx.dtsi#0157 Repo: bf5393c5ec9c Jagan Teki Fri Oct 14 15:09:29 2016 +0530 Description: ARM: dts: imx6qdl: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx6qdl dtsi files.

997 arch\arm\boot\dts\imx6qdl-gw53xx.dtsi#0159 998 arch\arm\boot\dts\imx6qdl-gw54xx.dtsi#0147 Repo: bf5393c5ec9c Jagan Teki Fri Oct 14 15:09:29 2016 +0530 Description: ARM: dts: imx6qdl: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx6qdl dtsi files.

999 arch\arm\boot\dts\imx6qdl-gw54xx.dtsi#0149 1000 arch\arm\boot\dts\imx6qdl-gw552x.dtsi#0294 Repo: bf5393c5ec9c Jagan Teki Fri Oct 14 15:09:29 2016 +0530 Description: ARM: dts: imx6qdl: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx6qdl dtsi files.

1001 arch\arm\boot\dts\imx6qdl-nit6xlite.dtsi#0100 Repo: 241f8f6fec2f Gary Bisson Tue Nov 1 18:10:05 2016 +0100 Description: ARM: dts: imx6qdl-nit6xlite: use hyphens for nodes name ------Therefore aligning the panel nodes name across all platforms.

Also removing the bt_rfkill node since the mainline rfkill-gpio driver doesn't support device trees.

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1002 arch\arm\boot\dts\imx6qdl-nit6xlite.dtsi#0163 1003 arch\arm\boot\dts\imx6qdl-nit6xlite.dtsi#0172 1004 arch\arm\boot\dts\imx6qdl-nit6xlite.dtsi#0181 1005 arch\arm\boot\dts\imx6qdl-nit6xlite.dtsi#0331 1006 arch\arm\boot\dts\imx6qdl-nit6xlite.dtsi#0377 1007 arch\arm\boot\dts\imx6qdl-nit6xlite.dtsi#0460 1008 arch\arm\boot\dts\imx6qdl-nitrogen6_max.dtsi#0232 Repo: 6ab5c2b662e2 Gary Bisson Tue Jan 3 12:22:46 2017 +0100 Description: ARM: dts: imx6qdl-nitrogen6_max: fix sgtl5000 pinctrl init ------This patch fixes the following error: sgtl5000 0-000a: Error reading chip id -6 imx-sgtl5000 sound: ASoC: CODEC DAI sgtl5000 not registered imx-sgtl5000 sound: snd_soc_register_card failed (-517)

The problem was that the pinctrl group was linked to the sound driver instead of the codec node. Since the codec is probed first, the sys_mclk was missing and it would therefore fail to initialize.

Fixes: b32e700256bc ("ARM: dts: imx: add Boundary Devices Nitrogen6_Max board")

ARM: dts: imx6qdl-nitrogen6_max: use hyphens for nodes name ------Therefore aligning the panel nodes name across all platforms.

1009 arch\arm\boot\dts\imx6qdl-nitrogen6_max.dtsi#0241 1010 arch\arm\boot\dts\imx6qdl-nitrogen6_max.dtsi#0250 1011 arch\arm\boot\dts\imx6qdl-nitrogen6_max.dtsi#0285 1012 arch\arm\boot\dts\imx6qdl-nitrogen6_max.dtsi#0296 1013 arch\arm\boot\dts\imx6qdl-nitrogen6_max.dtsi#0307 1014 arch\arm\boot\dts\imx6qdl-nitrogen6_max.dtsi#0322 1015 arch\arm\boot\dts\imx6qdl-nitrogen6_max.dtsi#0405 1016 arch\arm\boot\dts\imx6qdl-nitrogen6_max.dtsi#0450 1017 arch\arm\boot\dts\imx6qdl-nitrogen6_max.dtsi#0507 1018 arch\arm\boot\dts\imx6qdl-nitrogen6_max.dtsi#0723

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1019 arch\arm\boot\dts\imx6qdl-nitrogen6x.dtsi#0170 Repo: db9e188674ec Gary Bisson Fri Nov 25 00:42:47 2016 +0100 Description: ARM: dts: imx6qdl-nitrogen6x: remove duplicate iomux entry ------The NANDF_CS2 pad is also part of the wlan-vmmcgrp iomux group.

Removing is from the usdhc2grp group avoids the following error: imx6q-pinctrl 20e0000.iomuxc: pin MX6Q_PAD_NANDF_CS2 already requested by regulators:regulator@4; cannot claim for 2194000.usdhc imx6q-pinctrl 20e0000.iomuxc: pin-187 (2194000.usdhc) status -22 imx6q-pinctrl 20e0000.iomuxc: could not request pin 187 (MX6Q_PAD_NANDF_CS2) from group usdhc2grp on device 20e0000.iomuxc

ARM: dts: imx6qdl-nitrogen6x: use hyphens for nodes name ------Also aligning the panel nodes name across all platforms.

1020 arch\arm\boot\dts\imx6qdl-nitrogen6x.dtsi#0179 1021 arch\arm\boot\dts\imx6qdl-nitrogen6x.dtsi#0214 1022 arch\arm\boot\dts\imx6qdl-nitrogen6x.dtsi#0225 1023 arch\arm\boot\dts\imx6qdl-nitrogen6x.dtsi#0416 1024 arch\arm\boot\dts\imx6qdl-nitrogen6x.dtsi#0536 1025 arch\arm\boot\dts\imx6qdl-nitrogen6x.dtsi#0564 1026 arch\arm\boot\dts\imx6qdl-phytec-pfla02.dtsi#0430 Repo: bf5393c5ec9c Jagan Teki Fri Oct 14 15:09:29 2016 +0530 Description: ARM: dts: imx6qdl: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx6qdl dtsi files.

ARM: i.MX6 Phytec PFLA02: Add supplies for the SoC internal regulators ------The SoC internal regulators for the CPU and the SoC come from the DA9063 vdd_core and vdd_soc. Add this relationship to the device tree so that the voltage drop on the SoC internal LDO regulators can be minimized.

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1027 arch\arm\boot\dts\imx6qdl-phytec-pfla02.dtsi#0435 1028 arch\arm\boot\dts\imx6qdl-sabreauto.dtsi#0286 Repo: 1be81ea58607 Joshua Tue Nov 1 16:51:45 2016 -0700 Description: ARM: dts: imx6: Add imx-weim parameters to dtsi's ------imx-weim should always set address-cells to 2, and size_cells to 1. On imx6, fsl,weim-cs-gpr will always be &gpr

Set these common parameters in the dtsi file, rather than in a downstream dts.

ARM: dts: imx6qdl: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx6qdl dtsi files.

1029 arch\arm\boot\dts\imx6qdl-sabreauto.dtsi#0616 1030 arch\arm\boot\dts\imx6qdl-sabrelite.dtsi#0156 Repo: 4abe28eaae69 Gary Bisson Tue Nov 1 18:10:03 2016 +0100 Description: ARM: dts: imx6qdl-sabrelite: use hyphens for nodes name ------Also aligning the panel nodes name across all platforms.

1031 arch\arm\boot\dts\imx6qdl-sabrelite.dtsi#0165 1032 arch\arm\boot\dts\imx6qdl-sabrelite.dtsi#0200 1033 arch\arm\boot\dts\imx6qdl-sabrelite.dtsi#0211 1034 arch\arm\boot\dts\imx6qdl-sabrelite.dtsi#0381 1035 arch\arm\boot\dts\imx6qdl-sabresd.dtsi#0132 Repo: bf5393c5ec9c Jagan Teki Fri Oct 14 15:09:29 2016 +0530 Description: ARM: dts: imx6qdl: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx6qdl dtsi files.

1036 arch\arm\boot\dts\imx6qdl-tx6.dtsi#0432 Repo: 05c183e44be7 Jagan Teki Fri Oct 14 15:09:28 2016 +0530 Description: ARM: dts: imx6qdl: Fix "WARNING: please, no space before tabs" ------Fixed no space before tabs warnings in respetcive imx6qdl dtsi files.

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1037 arch\arm\boot\dts\imx6qdl-tx6.dtsi#0484 1038 arch\arm\boot\dts\imx6qdl-tx6.dtsi#0488 1039 arch\arm\boot\dts\imx6qdl-wandboard-revb1.dtsi#0031 Repo: 49bc67b61c60 Jagan Teki Fri Oct 14 15:09:30 2016 +0530 Description: ARM: dts: imx6qdl-wandboard-revb: Fix "ERROR: trailing whitespace" ------Fixed error in trailing whitespace in wandboard-rev1 dtsi.

1040 arch\arm\boot\dts\imx6qdl-wandboard.dtsi#0132 Repo: 05c183e44be7 Jagan Teki Fri Oct 14 15:09:28 2016 +0530 Description: ARM: dts: imx6qdl: Fix "WARNING: please, no space before tabs" ------Fixed no space before tabs warnings in respetcive imx6qdl dtsi files.

1041 arch\arm\boot\dts\imx6qdl.dtsi#0016 Repo: a971c5545c3d Fabio Mon Jan 23 14:54:10 2017 -0200 Description: ARM: dts: imx: Pass 'chosen' and 'memory' nodes ------Commit 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi") causes boot issues when the bootloader does not create a 'chosen' node if such node is not present in the dtb.

The reason for the boot failure is well explained by Javier Martinez Canillas: "the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info."

, so pass an empty 'chosen' node to fix the boot problem.

This issue has been seen in the kernelci reports with Barebox as bootloader.

Also pass the 'memory' node in order to fix boot issues on the SolidRun iMX6 platforms.

Fixes: 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi")

ARM: dts: imx6: Disable "weim" node in the dtsi files ------Commit 1be81ea5860744520 ("ARM: dts: imx6: Add imx-weim parameters to dtsi's") causes the following probe error when the weim node is not present on the board dts (such as imx6q-sabresd):

imx-weim 21b8000.weim: Invalid 'ranges' configuration

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imx-weim: probe of 21b8000.weim failed with error -22

There is no need to always enable the "weim" node on mx6. Do the same as in the other i.MX dtsi files where "weim" is disabled and only gets enabled on a per dts basis.

All the imx6 weim dts users explicitily provide 'status = "okay"', so this change has no impact on current imx6 weim users.

If a board does not use the weim driver it will not describe its 'ranges' property, so simply disable the 'weim' node in the imx6 dtsi files to avoid such probe error message.

Fixes: 1be81ea5860744520 ("ARM: dts: imx6: Add imx-weim parameters to dtsi's")

ARM: dts: imx: Remove skeleton.dtsi ------As explained by commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

ARM: dts: imx6: Add imx-weim parameters to dtsi's ------imx-weim should always set address-cells to 2, and size_cells to 1. On imx6, fsl,weim-cs-gpr will always be &gpr

Set these common parameters in the dtsi file, rather than in a downstream dts.

ARM: dts: imx6qdl: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx6qdl dtsi files.

1042 arch\arm\boot\dts\imx6qdl.dtsi#0019 1043 arch\arm\boot\dts\imx6qdl.dtsi#0216 1044 arch\arm\boot\dts\imx6qdl.dtsi#1104

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1045 arch\arm\boot\dts\imx6qdl.dtsi#1110 1046 arch\arm\boot\dts\imx6qp.dtsi#0088 Repo: 786a72d79140 Linus Thu Dec 15 15:50:24 2016 -0800 Description: Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6)

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- Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

ARM: dts: imx6qp: correct LDB clock inputs ------On i.MX6QP the LDB clock tree has changed to move the clk gate before the divider, to prevent clock glitches propagating downstream.

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A consequence of this change is that the clk divider is now the parent of the LDB inputs. Reflect this change in the devicetree to allow the LDB driver to properly configure the display clocks.

ARM: dts: add new compatible string for i.MX6QP mmdc ------MMDC has a slightly different programming model between imx6q and imx6qp in terms of perf support, it's exactly same for suspend support, so we have fsl,imx6q-mmdc here to save patching suspend driver with the new compatible.

1047 arch\arm\boot\dts\imx6qp.dtsi#0097 1048 arch\arm\boot\dts\imx6sl.dtsi#0011 Repo: a971c5545c3d Fabio Mon Jan 23 14:54:10 2017 -0200 Description: ARM: dts: imx: Pass 'chosen' and 'memory' nodes ------Commit 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi") causes boot issues when the bootloader does not create a 'chosen' node if such node is not present in the dtb.

The reason for the boot failure is well explained by Javier Martinez Canillas: "the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info."

, so pass an empty 'chosen' node to fix the boot problem.

This issue has been seen in the kernelci reports with Barebox as bootloader.

Also pass the 'memory' node in order to fix boot issues on the SolidRun iMX6 platforms.

Fixes: 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi")

ARM: dts: imx6: Disable "weim" node in the dtsi files ------Commit 1be81ea5860744520 ("ARM: dts: imx6: Add imx-weim parameters to dtsi's") causes the following probe error when the weim node is not present on the board dts (such as imx6q-sabresd):

imx-weim 21b8000.weim: Invalid 'ranges' configuration imx-weim: probe of 21b8000.weim failed with error -22

There is no need to always enable the "weim" node on mx6. Do the same as in the other i.MX dtsi files where "weim" is disabled and only gets enabled on a per dts basis.

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All the imx6 weim dts users explicitily provide 'status = "okay"', so this change has no impact on current imx6 weim users.

If a board does not use the weim driver it will not describe its 'ranges' property, so simply disable the 'weim' node in the imx6 dtsi files to avoid such probe error message.

Fixes: 1be81ea5860744520 ("ARM: dts: imx6: Add imx-weim parameters to dtsi's")

ARM: dts: imx: Remove skeleton.dtsi ------As explained by commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

ARM: dts: imx6: Add imx-weim parameters to dtsi's ------imx-weim should always set address-cells to 2, and size_cells to 1. On imx6, fsl,weim-cs-gpr will always be &gpr

Set these common parameters in the dtsi file, rather than in a downstream dts.

1049 arch\arm\boot\dts\imx6sl.dtsi#0016 1050 arch\arm\boot\dts\imx6sl.dtsi#0906 1051 arch\arm\boot\dts\imx6sl.dtsi#0910 1052 arch\arm\boot\dts\imx6sx-sdb.dtsi#0195 Repo: 67cb5d52ea2c Peter Chen Mon Oct 31 10:58:28 2016 +0800 Description: ARM: dts: imx6sx-sdb: update TX D_CAL for USBPHY ------We need to change trimming value (as a percentage) of the 17.78mA TX reference current for better signal quality. With this change, we can pass the eye-diagram test on this board.

ARM: dts: imx: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx23, imx51, imx53, imx6dl, imx6q and imx6sx dtsi and dts files.

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1053 arch\arm\boot\dts\imx6sx-sdb.dtsi#0293 1054 arch\arm\boot\dts\imx6sx.dtsi#0014 Repo: a971c5545c3d Fabio Mon Jan 23 14:54:10 2017 -0200 Description: ARM: dts: imx: Pass 'chosen' and 'memory' nodes ------Commit 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi") causes boot issues when the bootloader does not create a 'chosen' node if such node is not present in the dtb.

The reason for the boot failure is well explained by Javier Martinez Canillas: "the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info."

, so pass an empty 'chosen' node to fix the boot problem.

This issue has been seen in the kernelci reports with Barebox as bootloader.

Also pass the 'memory' node in order to fix boot issues on the SolidRun iMX6 platforms.

Fixes: 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi")

ARM: dts: imx6: Disable "weim" node in the dtsi files ------Commit 1be81ea5860744520 ("ARM: dts: imx6: Add imx-weim parameters to dtsi's") causes the following probe error when the weim node is not present on the board dts (such as imx6q-sabresd):

imx-weim 21b8000.weim: Invalid 'ranges' configuration imx-weim: probe of 21b8000.weim failed with error -22

There is no need to always enable the "weim" node on mx6. Do the same as in the other i.MX dtsi files where "weim" is disabled and only gets enabled on a per dts basis.

All the imx6 weim dts users explicitily provide 'status = "okay"', so this change has no impact on current imx6 weim users.

If a board does not use the weim driver it will not describe its 'ranges' property, so simply disable the 'weim' node in the imx6 dtsi files to avoid such probe error message.

Fixes: 1be81ea5860744520 ("ARM: dts: imx6: Add imx-weim parameters to dtsi's")

ARM: dts: imx: Remove skeleton.dtsi ------As explained by commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark

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skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

ARM: dts: imx6: Add imx-weim parameters to dtsi's ------imx-weim should always set address-cells to 2, and size_cells to 1. On imx6, fsl,weim-cs-gpr will always be &gpr

Set these common parameters in the dtsi file, rather than in a downstream dts.

ARM: dts: imx: Fix "ERROR: code indent should use tabs where possible" ------Fixed code indent tabs in respetcive imx23, imx51, imx53, imx6dl, imx6q and imx6sx dtsi and dts files.

ARM: dts: imx6sx: Fix LCDIF interrupt type ------The LCDIF interrupt should be triggered by the rising edge of the IRQ line because we only want the interrupt to trigger once per each frame. It seems the LCDIF IRQ line cannot be explicitly de-asserted by software, so the previous behavior before this patch, where the interrupt was triggered by level-high status of the IRQ line, caused the interrupt to fire again immediatelly after it was handled, which caused the system to lock up due to the high rate of interrupts.

1055 arch\arm\boot\dts\imx6sx.dtsi#0017 1056 arch\arm\boot\dts\imx6sx.dtsi#0871 1057 arch\arm\boot\dts\imx6sx.dtsi#0981 1058 arch\arm\boot\dts\imx6sx.dtsi#0987 1059 arch\arm\boot\dts\imx6sx.dtsi#1160 1060 arch\arm\boot\dts\imx6sx.dtsi#1171 1061 arch\arm\boot\dts\imx6sx.dtsi#1198

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1062 arch\arm\boot\dts\imx6sx.dtsi#1209 1063 arch\arm\boot\dts\imx6ul-14x14-evk.dts#0228 Repo: 901725b7902e Peter Chen Mon Oct 31 10:58:29 2016 +0800 Description: ARM: dts: imx6ul-14x14-evk: update TX D_CAL for USBPHY ------We need to change trimming value (as a percentage) of the 17.78mA TX reference current for better signal quality. With this change, we can pass the eye-diagram test on this board.

ARM: dts: imx6ul-14x14-evk: add USB dual-role support ------With commit 851ce932242d ("usb: chipidea: otg: don't wait vbus drops below BSV when starts host"), the driver can support enabling vbus output without software control, so this board (control vbus output through ID pin) can support dual-role now.

1064 arch\arm\boot\dts\imx6ul-14x14-evk.dts#0238 1065 arch\arm\boot\dts\imx6ul.dtsi#0014 Repo: a971c5545c3d Fabio Mon Jan 23 14:54:10 2017 -0200 Description: ARM: dts: imx: Pass 'chosen' and 'memory' nodes ------Commit 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi") causes boot issues when the bootloader does not create a 'chosen' node if such node is not present in the dtb.

The reason for the boot failure is well explained by Javier Martinez Canillas: "the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info."

, so pass an empty 'chosen' node to fix the boot problem.

This issue has been seen in the kernelci reports with Barebox as bootloader.

Also pass the 'memory' node in order to fix boot issues on the SolidRun iMX6 platforms.

Fixes: 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi")

ARM: dts: imx: Remove skeleton.dtsi ------As explained by commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.

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This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

1066 arch\arm\boot\dts\imx6ul.dtsi#0017 1067 arch\arm\boot\dts\imx7d-pinfunc.h#0046 Repo: 3cdcd2e841ab Stefan Agner Tue Nov 8 18:44:56 2016 -0800 Description: ARM: dts: imx7d-pinfunc: fix UART pinmux defines ------The UART pinmux defines for the pins which are part of the LPSR pinmux controller are wrong: Output signals configure the input sel value and the pinmux defines allow not to distinguish between DCE/DTE mode. Follow the usual pattern using DTE/DCE as part of the define to denote the two UART configuration options.

1068 arch\arm\boot\dts\imx7d-pinfunc.h#0053 1069 arch\arm\boot\dts\imx7d-pinfunc.h#0060 1070 arch\arm\boot\dts\imx7d-pinfunc.h#0068 1071 arch\arm\boot\dts\imx7s.dtsi#0049 Repo: a971c5545c3d Fabio Mon Jan 23 14:54:10 2017 -0200 Description: ARM: dts: imx: Pass 'chosen' and 'memory' nodes ------Commit 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi") causes boot issues when the bootloader does not create a 'chosen' node if such node is not present in the dtb.

The reason for the boot failure is well explained by Javier Martinez Canillas: "the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info."

, so pass an empty 'chosen' node to fix the boot problem.

This issue has been seen in the kernelci reports with Barebox as bootloader.

Also pass the 'memory' node in order to fix boot issues on the SolidRun iMX6 platforms.

Fixes: 7f107887d199 ("ARM: dts: imx: Remove skeleton.dtsi")

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------

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Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti,

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mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

1072 arch\arm\boot\dts\imx7s.dtsi#0052 1073 arch\arm\boot\dts\integratorap.dts#0013 Repo: 964971c8a3ef Linus Walleij Thu Aug 4 16:21:57 2016 +0200 Description: ARM: dts: Add Integrator/AP cpus node and operating points ------This adds the cpus node to the Integrator/AP device tree so that we have a proper placeholder to put in the DT-defined operating points for the generic DT/OPP cpufreq driver, along with the proper operating points.

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The old Integrator cpufreq driver would resolve the max frequency to 71MHz, and the min frequency to 12 MHz, but the clock driver can actually handle any frequency inbetween so I picked a few select frequencies as OPPs. The cpufreq framework doesn't seem to deal with sliding frequency scales, only fixed points so 7 OPPs is better than 2 atleast.

We define a CPU node since this is required for cpufreq-dt, however we do not define any compatible string for the CPU since this architecture has pluggable CPU modules and we do not know which one will be used. If necessary, the CPU compatible can be filled in by the boot loader, but for just cpufreq-dt it is not required.

1074 arch\arm\boot\dts\integratorcp.dts#0016 Repo: 426610dd8cc5 Linus Walleij Wed Aug 10 10:38:27 2016 +0200 Description: ARM: dts: Add Integrator/CP cpus node and operating points ------This adds the cpus node to the Integrator/CP device tree so that we have a proper placeholder to put in the DT-defined operating points for the generic DT/OPP cpufreq driver, along with two working operating points.

I have only put in 48 and 50 MHz because going to e.g. 36 MHz hangs the system when CLCD graphics are active. Presumably the memory bus gets to slow to feed the display and the systems hangs for this reason. The ideal solution would be for the display controller to put constraints on the memory bus frequency, but that need to be a separate longer-term project.

We define a CPU node since this is required for cpufreq-dt, however we do not define any compatible string for the CPU since this architecture has pluggable CPU modules and we do not know which one will be used. If necessary, the CPU compatible can be filled in by the boot loader, but for just cpufreq-dt it is not required.

1075 arch\arm\boot\dts\keystone-k2g.dtsi#0075 Repo: be76fd3197df Tony Mon Nov 7 08:27:49 2016 -0700 Description: ARM: dts: Add #pinctrl-cells for pinctrl-single instances ------Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while pinctrl-single,bits need #pinctrl-cells = <2>.

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Note that this patch can be optionally applied separately from the driver changes as the driver supports also the legacy binding without #pinctrl-cells.

1076 arch\arm\boot\dts\keystone-k2l.dtsi#0062 Repo: be76fd3197df Tony Mon Nov 7 08:27:49 2016 -0700 Description: ARM: dts: Add #pinctrl-cells for pinctrl-single instances ------Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the driver changes as the driver supports also the legacy binding without #pinctrl-cells.

1077 arch\arm\boot\dts\kirkwood-topkick.dts#0007 Repo: 95430414c7ed Paul Wassi Thu Nov 17 21:29:47 2016 +0100 Description: ARM: dts: kirkwood: fix spelling mistake ------Fix a spelling mistake in arch/arm/boot/dts/kirkwood-topkick.dts. The manufacturer's name is Univer*s*al Scientific Industrial... Compare with footer of page here: http://www.usish.com/english/products_topkick1281p2.php

1078 arch\arm\boot\dts\logicpd-som-lv-37xx-devkit.dts#0161 Repo: 1ea6af3216b0 Adam Ford Tue Jan 17 13:34:06 2017 -0600 Description: ARM: dts: omap3: Fix Card Detect and Write Protect on Logic PD SOM-LV ------This fixes commit ab8dd3aed011 ("ARM: DTS: Add minimal Support for Logic PD DM3730 SOM-LV") where the Card Detect and Write Protect pins were improperly configured.

Fixes: ab8dd3aed011 ("ARM: DTS: Add minimal Support for Logic PD DM3730 SOM-LV")

1079 arch\arm\boot\dts\logicpd-som-lv-37xx-devkit.dts#0196 1080 arch\arm\boot\dts\logicpd-som-lv-37xx-devkit.dts#0246 1081 arch\arm\boot\dts\lpc32xx.dtsi#0482 Repo: 1754906fffca Sylvain Thu Sep 8 13:47:53 2016 -0400 Description: ARM: dts: lpc32xx: set default parent clock for pwm1 & pwm2 ------

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The change setup the peripheral clock (PERIPH_CLK) as the default parent clock for PWM1 & PWM2.

1082 arch\arm\boot\dts\lpc32xx.dtsi#0491 1083 arch\arm\boot\dts\ls1021a.dtsi#0050 Repo: 4d9e9cbb61fd Hongtao Jia Sun Oct 9 14:47:04 2016 +0800 Description: ARM: dts: ls1021a: Add TMU device tree support for LS1021A ------Also add nodes and properties for thermal management support.

1084 arch\arm\boot\dts\ls1021a.dtsi#0074 1085 arch\arm\boot\dts\ls1021a.dtsi#0079 1086 arch\arm\boot\dts\ls1021a.dtsi#0082 1087 arch\arm\boot\dts\ls1021a.dtsi#0256 1088 arch\arm\boot\dts\Makefile#0078 Repo: a47b3fca62a3 Arnd Mon Feb 6 17:33:51 2017 +0100 Description: Merge tag 'mvebu-fixes-4.10-1' of git://git.infradead.org/linux-mvebu into fixes ------Pull "mvebu fixes for 4.10 (part 1)" from Gregory CLEMENT:

More consistent naming for some orion5x based boards helping the switch to device tree for debian users.

* tag 'mvebu-fixes-4.10-1' of git://git.infradead.org/linux-mvebu: ARM: orion5x: fix Makefile for linkstation-lschl.dtb ARM: dts: orion5x-lschl: More consistent naming on linkstation series ARM: dts: orion5x-lschl: Fix model name

ARM: orion5x: fix Makefile for linkstation-lschl.dtb ------The rename of orion5x-lschl.dts needs to be reflected in the Makefile:

make[3]: *** No rule to make target 'arch/arm/boot/dts/orion5x-lschl.dtb', needed by '__build'.

Fixes: 6cfd3cd8d836 ("ARM: dts: orion5x-lschl: More consistent naming on linkstation series")

Merge tag 'sunxi-fixes-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into fixes ------Allwinner fixes for 4.10

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A few fixes here and there to enable the build of some DT leftover, prevent display issues or setup a proper muxing.

* tag 'sunxi-fixes-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: ARM: dts: sunxi: Change node name for pwrseq pin on Olinuxino-lime2-emmc ARM: dts: sun8i: Support DTB build for NanoPi M1 ARM: dts: sun6i: hummingbird: Enable display engine again ARM: dts: sun6i: Disable display pipeline by default

ARM: dts: sun8i: Support DTB build for NanoPi M1 ------The commit 10efbf5f1633 ("ARM: dts: sun8i: Add dts file for NanoPi M1 SBC") introduced NanoPi M1 board but it's missing in Allwinner H3 DTB build.

ARM: dts: omap3: Add DTS for Logic PD SOM-LV 37xx Dev Kit ------Fixes: ("ab8dd3aed011 ARM: DTS: Add minimal Support for Logic PD DM3730 SOM-LV")

This adds the dts file into the Makefile. This should have been included in the original patch.

V2: Update patch description - same V1: Original patch

Merge tag 'zynq-dt-for-4.10' of https://github.com/Xilinx/linux-xlnx into next/dt ------arm: Xilinx Zynq dt patches for v4.10

- Remove skeleton.dtsi - Fix DTC warnings - Coding style changes - Microzed support

* tag 'zynq-dt-for-4.10' of https://github.com/Xilinx/linux-xlnx: arm: dts: zynq: Add MicroZed board support ARM: zynq: Fix pmu register description coding style ARM: zynq: Fix W=1 dtc 1.4 warnings ARM: zynq: Remove skeleton.dtsi

arm: dts: zynq: Add MicroZed board support ------Added basic dts support for MicroZed board.

- UART

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- SDHCI - Ethernet

Merge tag 'omap-for-v4.10/dt-late-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt ------Pull "omap dts changes for v4.10, part 2" from Tony Lindgren:

Second set of device tree changes for omaps for v4.10 merge window:

- Fix up new instances of gpio-key,wakeup to use wakeup-source

- Add beaglebone LCDC blue-and-red-wiring property to make use of the new driver features

- Add bindings for IIO support for am335x and am437x

- Add palmas PMIC overide powerhold property for am57xx

- Update am335x-baltos to use phy-handle property

- Add initial support for am571x-idk

* tag 'omap-for-v4.10/dt-late-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: AM571x-IDK Initial Support ARM: dts: am335x-baltos: use phy-phandle declarations ARM: dts: am57xx-idk-common: Add overide powerhold property ARM: dts: am57xx-beagle-x15-common: Add overide powerhold property ARM: dts: am57xx-idk: Add Industrial output support ARM: dts: am57xx-idk: Add Industrial input support ARM: dts: am437x-idk: Add Industrial output support ARM: dts: am437x-idk: Add Industrial input support ARM: dts: am335x-icev2: Add ADC support ARM: dts: am335x-icev2: Disable Industrial I/O LEDs and fix naming ARM: dts: am335x-icev2: Add Industrial input support ARM: dts: am335x-boneblack: Add blue-and-red-wiring -property to LCDC node ARM: dts: omap5: replace gpio-key,wakeup with wakeup-source property

Merge tag 'mvebu-dt-4.10-2' of git://git.infradead.org/linux-mvebu into next/dt ------Pull "mvebu dt for 4.10 (part 1)" from Gregory CLEMENT:

Add Turris Omnia support, an open hardware router Armada 385 based

* tag 'mvebu-dt-4.10-2' of git://git.infradead.org/linux-mvebu: ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC

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Merge tag 'v4.10-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt ------Pull "Rockchip dts32 changes for 4.10" from Heiko Stübner:

A bit of attention for the rk3066, fixed tsadc reset node as well as enabling the dma for uart and mmc controllers.

And one new soc, the rk1108 combining a single-core Cortex-A7 with a separate DSP core.

* tag 'v4.10-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux- rockchip: ARM: dts: rockchip: add the sdmmc pinctrl for rk1108 ARM: dts: rockchip: add rockchip RK1108 Evaluation board ARM: dts: rockchip: add basic support for RK1108 SOC clk: rockchip: add dt-binding header for rk1108 dt-bindings: rockchip-dw-mshc: add RK1108 dw-mshc description ARM: dts: rockchip: enable dma for uart and mmc on rk3066a ARM: dts: rockchip: fix TSADC reset node for rk3066a

Merge tag 'arm-soc/for-4.10/devicetree' of http://github.com/Broadcom/stblinux into next/dt ------Pull "Broadcom devicetree changes for 4.10" from Florian Fainelli:

This pull request contains Broadcom ARM-based SoC Device Tree changes for 4.10, please pull the following:

- Rafal adds support for the Netgear R8500 routers, adds basic support for the Tenda AC9 router which uses the new BCM53573 SoC (single core Cortex A7). He also enables the UART on the Netgear R8000 and restructures the include files a bit for the BCM47094 SoC, finally he adds USB 3.0 PHY nodes which enables USB 3.0 on BCM5301X devices that support it. Finally he adds support for the TP-LINK Archer C9 V1 router.

- Kamal adds support for the QSPI controller on the Northstar Plus SoCs and updates the bcm958625k reference board to have it enabled

- Dan adds support for the Luxul XAP-1510 (using a BCM4708) and XWR-3100 (using a BCM47094)

- Scott fixes the pinctrl names in the Cygnus DTS files

- Jonathan enables the Broadcom iProc mailbox controller for Broadcom Cygnus/iProc SoCs, he adds interrupt support for the GPIO CRMU hardware block and finally adds the node for the OTP controller found on Cygnus SoCs

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- Dhananjay enables the GPIO B controller on Norstarh Plus SoCs

- Eric defines standard pinctrl groups in the BCM2835 GPIO node

- Gerd adds definitions for the pinctrl groups and updates the PWM, I2C and SDHCI nodes to use their appropriate pinctrl functions

- Linus adds names for the Raspberry Pi GPIO lines based on the datasheet

- Martin adds the DT binding and nodes for the Raspberry Pi firmware thermal block

- Stefan fixes a few typos with respect to the BCM2835 mailbox binding example and Device Tree nodes he also fixes the Raspberry Pi GPIO lines names and finally adds names for the Raspberry Zero GPIO lines

* tag 'arm-soc/for-4.10/devicetree' of http://github.com/Broadcom/stblinux: (29 commits) ARM: bcm2835: Add names for the RPi Zero GPIO lines ARM: bcm2835: Fix names for the Raspberry Pi GPIO lines ARM: dts: enable GPIO-b for Broadcom NSP ARM: BCM5301X: Add DT for TP-LINK Archer C9 V1 ARM: dts: Add node for Broadcom OTP controller driver ARM: dts: Enable interrupt support for cygnus crmu gpio driver ARM: dts: Enable Broadcom iProc mailbox controller ARM: bcm2835: Add names for the Raspberry Pi GPIO lines ARM: bcm2835: dts: add thermal node to device-tree of bcm283x dt: bindings: add thermal device driver for bcm2835 ARM: dts: bcm283x: fix typo in mailbox address DT: binding: bcm2835-mbox: fix address typo in example ARM: dts: cygnus: fix naming of pinctrl node ARM: BCM53573: Specify PMU and its ILP clock in the DT ARM: BCM5301X: Add DT for Luxul XWR-3100 ARM: BCM5301X: Add DT for Luxul XAP-1510 ARM: BCM5301X: Specify USB 3.0 PHY in DT ARM: BCM5301X: Enable UART on Netgear R8000 ARM: BCM5301X: Add separated DTS include file for BCM47094 ARM: dts: NSP: Add QSPI nodes to NSPI and bcm958625k DTSes ...

Merge tag 'renesas-dt2-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt ------Pull "Second Round of Renesas ARM Based SoC DT Updates for v4.10" from Simon Horman:

Enhancements: * Add device nodes for PRR * Add r8a7745 SoC and sk-rzg1e board

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* Add r8a7743 SoC and sk-rzg1m board * Enable SDR-104 and I2C demuxer on alt, koelsch and lager boards

Corrections: * Use SYSC "always-on" PM Domain for sound on r8a7794 SoC * Correct hsusb parent clock on r8a7794 SoC * Correct PFC names for DU on alt board

* tag 'renesas-dt2-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (33 commits) ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ARM: dts: r8a7745: add IRQC support ARM: dts: r8a7745: add Ether support ARM: dts: r8a7745: add [H]SCIF{|A|B} support ARM: dts: r8a7745: add SYS-DMAC support ARM: dts: r8a7745: initial SoC device tree ARM: dts: sk-rzg1m: add Ether support ARM: dts: sk-rzg1m: initial device tree ARM: dts: r8a7743: add IRQC support ARM: dts: r8a7743: add Ether support ARM: dts: r8a7743: add [H]SCIF{A|B} support ARM: dts: r8a7743: add SYS-DMAC support ...

Merge tag 'sunxi-dt-for-4.10-bis' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt ------Pull "Allwinner DT additions for 4.10, bis" from Maxime Ripard:

The usual bunch of DT additions, but most notably: - A31 DRM driver - A31 audio codec - WiFi for the A80-Based boards and the CHIP - Support for the NextThing Co CHIP Pro (the first board with NAND enabled) - New board: NanoPi M1

* tag 'sunxi-dt-for-4.10-bis' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (41 commits) ARM: dts: sun6i: hummingbird-a31: Enable display output through VGA bridge ARM: dts: sun5i: Add touchscreen node to reference-design-tablet.dtsi

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ARM: sunxi: Add the missing clocks to the pinctrl nodes ARM: dts: sun7i: bananapi-m1-plus: Enable USB OTG ARM: dts: sun7i: bananapi-m1-plus: Add PMIC regulators ARM: dts: sun7i: bananapi-m1-plus: Enable USB PHY for USB host support ARM: sun8i: sina33: Enable USB gadget ARM: dts: sun8i: reference-design-tablet: ldo_io1 is vcc-touchscreen ARM: dts: sun8i: replace enable-sdio-wakeup with wakeup-source for BananaPi M1+ ARM: gr8: evb: Add i2s codec ARM: dts: sun6i: sina31s: Enable internal audio codec ARM: dts: sun6i: hummingbird: Enable internal audio codec ARM: dts: sun6i: Add audio codec device node ARM: gr8: evb: Enable SPDIF ARM: dts: sun8i: Add SPI controller node in H3 ARM: dts: sun8i: Add SPI pinctrl node in H3 ARM: dts: sun8i: Add dts file for NanoPi M1 SBC ARM: dts: sun8i: Use the common file in NanoPi NEO SBC ARM: dts: sun8i: Add common dtsi file for NanoPi SBCs ARM: dts: sun9i: cubieboard4: Enable AP6330 WiFi ...

Merge tag 'mvebu-dt-4.10-1' of git://git.infradead.org/linux-mvebu into next/dt ------Pull "mvebu dt for 4.10 (part 1)" from Gregory CLEMENT:

Add missing pinmux declaration for netgear NASes Fix i2c compatible string for netgear NASes Fix on a wrong comment about PLL frequency Fix spelling mistake of the manufacturer's name of the Topkick Add dt support for the orion5x ls-chl Linkstation device First step of fixing DTC warning for Armada 370, 375 and XP

* tag 'mvebu-dt-4.10-1' of git://git.infradead.org/linux-mvebu: (30 commits) ARM: dts: armada-375: Fixup ethernet child DT warning ARM: dts: armada-375: Fixup memory DT warning ARM: dts: armada-375: Remove skeleton.dtsi ARM: dts: armada-375: Fixup pinctrl DT warnings ARM: dts: armada-375: Fixup pcie DT warnings ARM: dts: armada-375: Fixup mdio DT warning ARM: dts: armada-375: Use the node labels ARM: dts: armada-375: Add node labels ARM: dts: armada-370-xp: Fixup regulator DT warning ARM: dts: armada-370-xp: Remove button address and fixup names ARM: dts: armada-370-xp: Remove address from dsa unit name ARM: dts: armada-370-xp: Fixup memory DT warning ARM: dts: armada-370-xp: Fixup l2-cache DT warning ARM: dts: armada-370-xp: Remove skeleton.dtsi ARM: dts: armada-370: Fixup pcie DT warnings ARM: dts: armada-xp: Fixup pcie DT warnings ARM: dts: armada-370-xp: Fixup mdio DT warning

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ARM: dts: armada-370-xp: Use the node labels ARM: dts: armada-370-xp: add node labels ARM: dts: armada-370-xp: move the cpurst node in the common file ...

Merge tag 'qcom-dts-for-4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt ------Pull "Qualcomm Device Tree Changes for v4.10 - v2" from Andy Gross:

* Add EBI2 support to MSM8660 * Add SMSC ethernet support to APQ8060 * Add support for display, pstore, iommu, and hdmi to APQ8064 * Add SDHCI node to MSM8974 Hammerhead * Add WP8548 MangOH board support (MDM9615)

* tag 'qcom-dts-for-4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard ARM: dts: add EBI2 to the Qualcomm MSM8660 DTSI arm: dts: qcom: apq8064-nexus7: Add pstore support to nexus7 arm: dts: qcom: apq8064-nexus7: Add DSI and panel nodes arm: dts: qcom: apq8064: Add dsi, gpu and iommu nodes arm: dts: qcom: apq8064-ifc6410: Add HDMI support arm: dts: qcom: apq8064: Add display DT nodes ARM: dts: qcom: msm8974-hammerhead: Add sdhci1 node dt-bindings: arm: Add Sierra Wireless modules bindings ARM: dts: Add WP8548 based MangOH Green board DTS ARM: dts: Add Sierra Wireless WP8548 dtsi dt-bindings: qcom: Add MDM9615 bindings ARM: dts: Add MDM9615 dtsi

Merge tag 'oxnas-arm-soc-dt-for-4.10' of https://github.com/OXNAS/linux into next/dt ------Pull "ARM: OXNAS SoC DT updates for 4.10" from Neil Armstrong:

- Add DTSI for Oxford Semiconductor OX820 - Add DTS for Cloud Engines PogoPlug v3 board - Fix MAINTAINERS Oxnas entry for dts files from http://lkml.kernel.org/r/[email protected]

* tag 'oxnas-arm-soc-dt-for-4.10' of https://github.com/OXNAS/linux: MAINTAINERS: oxnas: Add new files definitions ARM: dts: Add support for OX820 and Pogoplug V3

ARM: dts: add support for Turris Omnia ------This machine is an open hardware router by cz.nic driven by a

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Marvell Armada 385.

ARM: dts: sk-rzg1e: initial device tree ------Add the initial device tree for the R8A7745 SoC based SK-RZG1E board. The board has 1 debug serial port (SCIF2); include support for it, so that the serial console can work.

Based on the original (and large) patch by Dmitry Shifrin .

ARM: dts: sk-rzg1m: initial device tree ------Add the initial device tree for the R8A7743 SoC based SK-RZG1M board. The board has one debug serial port (SCIF0); include support for it, so that the serial console can work.

Based on the original (and large) patch by Dmitry Shifrin .

ARM: dts: AM571x-IDK Initial Support ------The AM571x-IDK board is a board based on TI's AM5718 SOC which has a single core 1.5GHz A15 processor. This board is a development platform for the Industrial market with: - 1GB of DDR3L - Dual 1Gbps Ethernet - HDMI, - PRU-ICSS - uSD - 16GB eMMC - CAN - RS-485 - PCIe - USB3.0 - Video Input Port - Industrial IO port and expansion connector

The link to the data sheet and TRM can be found here:

http://www.ti.com/product/AM5718

Initial support is only for basic peripherals.

ARM: gr8: Add CHIP Pro support ------

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The CHIP Pro is a small embeddable board. It features a GR8, an AXP209 PMIC, a 512MB SLC NAND and a WiFi/BT chip.

1089 arch\arm\boot\dts\Makefile#0090 1090 arch\arm\boot\dts\Makefile#0092 1091 arch\arm\boot\dts\Makefile#0098 1092 arch\arm\boot\dts\Makefile#0145 1093 arch\arm\boot\dts\Makefile#0340 1094 arch\arm\boot\dts\Makefile#0351 1095 arch\arm\boot\dts\Makefile#0393 1096 arch\arm\boot\dts\Makefile#0398 1097 arch\arm\boot\dts\Makefile#0430 1098 arch\arm\boot\dts\Makefile#0437 1099 arch\arm\boot\dts\Makefile#0441 1100 arch\arm\boot\dts\Makefile#0504 1101 arch\arm\boot\dts\Makefile#0581 1102 arch\arm\boot\dts\Makefile#0609 1103 arch\arm\boot\dts\Makefile#0612 1104 arch\arm\boot\dts\Makefile#0620 1105 arch\arm\boot\dts\Makefile#0628 1106 arch\arm\boot\dts\Makefile#0645 1107 arch\arm\boot\dts\Makefile#0661 1108 arch\arm\boot\dts\Makefile#0666 1109 arch\arm\boot\dts\Makefile#0668 1110 arch\arm\boot\dts\Makefile#0706 1111 arch\arm\boot\dts\Makefile#0721 1112 arch\arm\boot\dts\Makefile#0728 1113 arch\arm\boot\dts\Makefile#0745 1114 arch\arm\boot\dts\Makefile#0749 1115 arch\arm\boot\dts\Makefile#0789

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1116 arch\arm\boot\dts\Makefile#0849 1117 arch\arm\boot\dts\Makefile#0928 1118 arch\arm\boot\dts\Makefile#0952 1119 arch\arm\boot\dts\mps2-an385.dts#0062 Repo: 7f43049b4050 Vladimir Mon Oct 17 12:47:29 2016 +0100 Description: ARM: dts: mps2: remove skeleton.dtsi include and fix unit address warnings ------Removale of skeleton.dtsi allows us also to fix the following warning from the dts compiler: Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

by adding proper unit addresses to the memory nodes.

1120 arch\arm\boot\dts\mps2-an399.dts#0062 Repo: 7f43049b4050 Vladimir Mon Oct 17 12:47:29 2016 +0100 Description: ARM: dts: mps2: remove skeleton.dtsi include and fix unit address warnings ------Removale of skeleton.dtsi allows us also to fix the following warning from the dts compiler: Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

by adding proper unit addresses to the memory nodes.

1121 arch\arm\boot\dts\mps2.dtsi#0045 Repo: 7f43049b4050 Vladimir Mon Oct 17 12:47:29 2016 +0100 Description: ARM: dts: mps2: remove skeleton.dtsi include and fix unit address warnings ------Removale of skeleton.dtsi allows us also to fix the following warning from the dts compiler: Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

by adding proper unit addresses to the memory nodes.

1122 arch\arm\boot\dts\mps2.dtsi#0049

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1123 arch\arm\boot\dts\mt2701.dtsi#0015 Repo: 28d6e3647bd7 Erin Lo Fri Nov 4 15:43:08 2016 +0800 Description: arm: dts: mt2701: Use real clock for UARTs ------We used to use a fixed rate clock for the UARTs. Now that we have clock support we can associate the correct clocks to the UARTs and drop the 26MHz fixed rate UART clock.

arm: dts: mt2701: Add clock controller device nodes ------Add clock controller nodes for MT2701, include topckgen, infracfg, pericfg and apmixedsys. This patch also add two oscillators that provide clocks for MT2701.

arm: dts: Add pinctrl/GPIO/EINT node for mt2701 ------Add pinctrl and GPIO node to mt2701.dtsi

Revert "arm: dts: Add pinctrl/GPIO/EINT node for mt2701" ------This reverts commit 8ba671efdbe5be3e5d691a8b7f77b0d68459b874.

As reported by kbuild test robot :

In file included from arch/arm/boot/dts/mt2701-evb.dts:16:0: >> arch/arm/boot/dts/mt2701.dtsi:18:28: fatal error: mt2701-pinfunc.h: No such file or directory #include "mt2701-pinfunc.h" ^

arm: dts: Add pinctrl/GPIO/EINT node for mt2701 ------Add pinctrl and GPIO node to mt2701.dtsi

1124 arch\arm\boot\dts\mt2701.dtsi#0018 1125 arch\arm\boot\dts\mt2701.dtsi#0076 1126 arch\arm\boot\dts\mt2701.dtsi#0078 1127 arch\arm\boot\dts\mt2701.dtsi#0080

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1128 arch\arm\boot\dts\mt2701.dtsi#0086 1129 arch\arm\boot\dts\mt2701.dtsi#0117 1130 arch\arm\boot\dts\mt2701.dtsi#0161 1131 arch\arm\boot\dts\mt2701.dtsi#0183 1132 arch\arm\boot\dts\mt2701.dtsi#0193 1133 arch\arm\boot\dts\mt2701.dtsi#0203 1134 arch\arm\boot\dts\mt2701.dtsi#0213 1135 arch\arm\boot\dts\omap2.dtsi#0020 Repo: 3d37d41a148c Javier Mon Dec 19 11:44:33 2016 -0300 Description: ARM: dts: omap2: Add an empty chosen node to top level DTSI ------Commit d1f3156fc8c7 ("ARM: dts: omap2: Remove skeleton.dtsi usage") removed the skeleton.dtsi usage since we want to get rid of it.

But this can cause issues when booting a kernel with a boot-loader that doesn't create a chosen node if this isn't present in the DTB since the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info.

Fixes: d1f3156fc8c7 ("ARM: dts: omap2: Remove skeleton.dtsi usage")

1136 arch\arm\boot\dts\omap2420.dtsi#0041 Repo: be76fd3197df Tony Mon Nov 7 08:27:49 2016 -0700 Description: ARM: dts: Add #pinctrl-cells for pinctrl-single instances ------Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the driver changes as the driver supports also the legacy binding without #pinctrl-cells.

1137 arch\arm\boot\dts\omap2420.dtsi#0050 1138 arch\arm\boot\dts\omap2430.dtsi#0041 Repo: be76fd3197df Tony Mon Nov 7 08:27:49 2016 -0700 Description: ARM: dts: Add #pinctrl-cells for pinctrl-single instances ------Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the

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driver changes as the driver supports also the legacy binding without #pinctrl-cells.

ARM: dts: omap24xx: Enable gpio and interrupt controller for GPMC ------GPMC driver provides interrupts and gpio for the GPMC_WAIT pins. Mark it as gpio and interrupt capable.

1139 arch\arm\boot\dts\omap2430.dtsi#0050 1140 arch\arm\boot\dts\omap3-n900.dts#0737 Repo: 4cf48f1d7520 Pali Rohár Wed Dec 14 22:29:44 2016 +0100 Description: ARM: dts: n900: Mark eMMC slot with no-sdio and no-sd flags ------Trying to initialize eMMC slot as SDIO or SD cause failure in n900 port of qemu. eMMC itself is not detected and is not working.

Real harware does not have this problem. As eMMC is really not SDIO or SD based such change is harmless and will fix support for qemu.

1141 arch\arm\boot\dts\omap3.dtsi#0020 Repo: 23ab4c6183ac Javier Mon Dec 19 11:44:34 2016 -0300 Description: ARM: dts: omap3: Add an empty chosen node to top level DTSI ------Commit 008a2ebcd677 ("ARM: dts: omap3: Remove skeleton.dtsi usage") removed the skeleton.dtsi usage since we want to get rid of it.

But this can cause issues when booting a kernel with a boot-loader that doesn't create a chosen node if this isn't present in the DTB since the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info.

Fixes: 008a2ebcd677 ("ARM: dts: omap3: Remove skeleton.dtsi usage")

ARM: dts: Add #pinctrl-cells for pinctrl-single instances ------Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the driver changes as the driver supports also the legacy binding without #pinctrl-cells.

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1142 arch\arm\boot\dts\omap3.dtsi#0110 1143 arch\arm\boot\dts\omap3.dtsi#0150 1144 arch\arm\boot\dts\omap34xx.dtsi#0037 Repo: be76fd3197df Tony Mon Nov 7 08:27:49 2016 -0700 Description: ARM: dts: Add #pinctrl-cells for pinctrl-single instances ------Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the driver changes as the driver supports also the legacy binding without #pinctrl-cells.

1145 arch\arm\boot\dts\omap36xx.dtsi#0069 Repo: be76fd3197df Tony Mon Nov 7 08:27:49 2016 -0700 Description: ARM: dts: Add #pinctrl-cells for pinctrl-single instances ------Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the driver changes as the driver supports also the legacy binding without #pinctrl-cells.

1146 arch\arm\boot\dts\omap4.dtsi#0018 Repo: 6c565d1a63ce Javier Mon Dec 19 11:44:35 2016 -0300 Description: ARM: dts: omap4: Add an empty chosen node to top level DTSI ------Commit da6269e7e3dd ("ARM: dts: omap4: Remove skeleton.dtsi usage") removed the skeleton.dtsi usage since we want to get rid of it.

But this can cause issues when booting a kernel with a boot-loader that doesn't create a chosen node if this isn't present in the DTB since the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info.

Fixes: da6269e7e3dd ("ARM: dts: omap4: Remove skeleton.dtsi usage")

ARM: dts: Add #pinctrl-cells for pinctrl-single instances ------Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while pinctrl-single,bits need #pinctrl-cells = <2>.

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Note that this patch can be optionally applied separately from the driver changes as the driver supports also the legacy binding without #pinctrl-cells.

1147 arch\arm\boot\dts\omap4.dtsi#0188 1148 arch\arm\boot\dts\omap4.dtsi#0261 1149 arch\arm\boot\dts\omap5-uevm.dts#0030 Repo: 66579e29f7ab Sudeep Mon Nov 14 15:44:07 2016 +0000 Description: ARM: dts: omap5: replace gpio-key,wakeup with wakeup-source property ------Though the keyboard driver for GPIO buttons(gpio-keys) will continue to check for/support the legacy "gpio-key,wakeup" boolean property to enable gpio buttons as wakeup source, "wakeup-source" is the new standard binding.

This patch replaces the legacy "gpio-key,wakeup" with the unified "wakeup-source" property in order to avoid any further copy-paste duplication.

ARM: dts: omap5 uevm: add USR1 button ------Add USR1 button.

ARM: dts: omap5 uevm: add LEDs ------Add LEDs.

ARM: dts: omap5 uevm: add EEPROM ------Add EEPROM.

ARM: dts: Add support for more than 2GB of memory for omap5 ------Some omap5 variants have more than 2GB of memory available as optional models. Let's update the dts files to use two address cells similar to what dra7 is using with commit dae320ec3173 ("ARM: dts: DRA7: change address-cells and size-cells").

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1150 arch\arm\boot\dts\omap5-uevm.dts#0115 1151 arch\arm\boot\dts\omap5-uevm.dts#0137 1152 arch\arm\boot\dts\omap5.dtsi#0020 Repo: 87cb12910a2a Jean- Mon Jan 9 13:22:15 2017 +0100 Description: ARM: dts: OMAP5 / DRA7: indicate that SATA port 0 is available. ------AHCI provides the register PORTS_IMPL to let the software know which port is supported. The register must be initialized by the bootloader. However in some cases u-boot doesn't properly initialize this value (if it is not compiled with SATA support for example or if the SATA initialization fails). The DTS entry "ports-implemented" can be used to override the value in PORTS_IMPL.

Without this patch the SATA will not work in the following two cases:

* if there has been a failure to initialize SATA in u-boot.

* if ahci_platform module has been removed and re-inserted. The reason is that the content of PORTS_IMPL is lost after the module is removed. I suspect that it's because the controller is reset by the hwmod.

ARM: dts: omap5: Add an empty chosen node to top level DTSI ------Commit 76a8548ea987 ("ARM: dts: omap5: Remove skeleton.dtsi usage") removed the skeleton.dtsi usage since we want to get rid of it.

But this can cause issues when booting a kernel with a boot-loader that doesn't create a chosen node if this isn't present in the DTB since the decompressor relies on a pre-existing chosen node to be available to insert the command line and merge other ATAGS info.

Fixes: 76a8548ea987 ("ARM: dts: omap5: Remove skeleton.dtsi usage")

ARM: dts: Add #pinctrl-cells for pinctrl-single instances ------Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the driver changes as the driver supports also the legacy binding without #pinctrl-cells.

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1153 arch\arm\boot\dts\omap5.dtsi#0175 1154 arch\arm\boot\dts\omap5.dtsi#0275 1155 arch\arm\boot\dts\omap5.dtsi#0991 1156 arch\arm\boot\dts\pxa27x.dtsi#0140 Repo: 74e382b870ca Robert Mon Oct 31 20:54:55 2016 +0100 Description: ARM: dts: pxa: add pxa27x cpu operating points ------Add the relevant data taken from the PXA27x Electrical, Mechanical, and Thermal Specfication. This will be input data for cpufreq-dt driver.

1157 arch\arm\boot\dts\pxa2xx.dtsi#0057 Repo: 4852a25eab45 Robert Mon Sep 26 09:22:11 2016 +0200 Description: ARM: dts: pxa: fix gpio0 and gpio1 interrupts ------Since gpio-pxa was redesigned to differenciate gpio0, gpio1 and the gpio-mux interrupt as in the hardware IP, the device-tree description should be amended so that interrupts from gpio0 and gpio1 can be mapped to consumers.

This is especially true on lubbock and mainstone devices where gpio0 is multiplexed on pxa_cplds for ethernet, sa1111, usb udc, and other devices.

1158 arch\arm\boot\dts\pxa3xx.dtsi#0141 Repo: be76fd3197df Tony Mon Nov 7 08:27:49 2016 -0700 Description: ARM: dts: Add #pinctrl-cells for pinctrl-single instances ------Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the driver changes as the driver supports also the legacy binding without #pinctrl-cells.

ARM: dts: pxa3xx: add pincontrol helpers ------The various pxa3xx variants have a really weird pin scheme assignement, when you want the pin number relative to a known gpio pin.

This change adds the various tools to ease up writing the pinmux and pinconf devicetree parts.

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ARM: dts: pxa: add pinctrl to pxa3xx ------Add pincontrol to pxa3xx, based on pinconf-simple.

ARM: dts: pxa: fix the ohci clock for pxa3xx ------Fix the USB host clock, which is CLK_USBH. CLK_USBHOST is the clock of the usb host of pxa27x SoCs.

1159 arch\arm\boot\dts\qcom-apq8060-dragonboard.dts#0054 Repo: 4c52ffc708c9 Linus Walleij Tue Oct 25 00:22:20 2016 +0200 Description: ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard ------The SMSC9112 ethernet controller is connected to chip select 2 on the EBI2 bus on the APQ8060 Dragonboard. We set this up by activating EBI2, creating a chipselect entry as a subnode, and then putting the ethernet controller in a subnode of the chipselect.

After the chipselect is configured, the SMSC device will be instantiated.

1160 arch\arm\boot\dts\qcom-apq8060-dragonboard.dts#0193 1161 arch\arm\boot\dts\qcom-apq8060-dragonboard.dts#0257 1162 arch\arm\boot\dts\qcom-apq8060-dragonboard.dts#0303 1163 arch\arm\boot\dts\qcom-apq8060-dragonboard.dts#0395 1164 arch\arm\boot\dts\qcom-apq8064-asus-nexus7-flo.dts#0018 Repo: 663286e7e63c John Stultz Fri Sep 23 17:13:33 2016 -0700 Description: arm: dts: qcom: apq8064-nexus7: Add pstore support to nexus7 ------Add pstore support for the nexus7. This was useful in debugging a crash where the cpus were getting stuck with irqs off and serial output wasn't reliably working.

arm: dts: qcom: apq8064-nexus7: Add DSI and panel nodes ------Add DSI and panel nodes to get graphics up and running on the Nexus7.

This still depends on the panel driver being present along with the rpmclk code.

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Feedback would be greatly appreciated!

device-tree: nexus7: Add IMEM syscon and reboot reason support ------This patch add the IMEM syscon memory region to the DT, as well as addds support for the magic reboot reason values that are written to the address for each mode.

1165 arch\arm\boot\dts\qcom-apq8064-asus-nexus7-flo.dts#0116 1166 arch\arm\boot\dts\qcom-apq8064-asus-nexus7-flo.dts#0151 1167 arch\arm\boot\dts\qcom-apq8064-asus-nexus7-flo.dts#0157 1168 arch\arm\boot\dts\qcom-apq8064-asus-nexus7-flo.dts#0203 1169 arch\arm\boot\dts\qcom-apq8064-ifc6410.dts#0046 Repo: c809801d4ceb Archit TanejaFri Sep 23 12:03:07 2016 +0530 Description: arm: dts: qcom: apq8064-ifc6410: Add HDMI support ------Add HDMI support on IFC6410. Populate the regulators required by HDMI-TX and PHY. Establish the link between the MDP4 DTV encoder and HDMI. Create a generic micro HDMI connector DT node. The msm drm driver doesn't parse for HDMI connectors in DT, but it will do so later.

ARM: dts: ifc6410: add correct aliases to the i2c and spi bus ------This patch adds correct aliases to spi and i2c buses so that they get correct matching bus numbers.

ARM: dts: ifc6410: enable cam i2c device ------This patch enables i2c bus for camera via mipi-csi connector on ifc6410.

ARM: dts: ifc6410: enable spi device on expansion ------This patch enables spi device on the 30 pin expansion connector.

1170 arch\arm\boot\dts\qcom-apq8064-ifc6410.dts#0078

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1171 arch\arm\boot\dts\qcom-apq8064-ifc6410.dts#0362 1172 arch\arm\boot\dts\qcom-apq8064.dtsi#0007 Repo: 542b9f0759ed Bjorn Thu Dec 29 04:06:11 2016 -0800 Description: ARM: dts: qcom: apq8064: Add missing scm clock ------As per the device tree binding the apq8064 scm node requires the core clock to be specified, so add this.

arm: dts: qcom: apq8064: Add dsi, gpu and iommu nodes ------Adds the core gpu, and dsi nodes for the apq8064 needed to get graphics working on the nexus7 and other devices.

These apply on top of Archit's patch set that enables HDMI for IFC6410

Feedback would be greatly appreciated!

arm: dts: qcom: apq8064: Add display DT nodes ------APQ8064 contains a MDP4 based display controller. It contains a HDMI, LVDS and 2 DSI outputs.

Add display DT nodes for MDP4, HDMI TX and HDMI PHY. MDP4 based display blocks have a flat device hierarchy.

Nodes for other outputs will be added later.

arm: dts: apq8064: Add thermal zones, tsens and qfprom nodes ------TSENS is part of GCC, hence add TSENS properties as part of GCC node. Also add thermal zones and qfprom nodes. Update GCC bindings doc to mention the possibility of optional TSENS properties that can be part of GCC node.

ARM: dts: MSM8064 remove flags from SPMI/MPP IRQs ------The Qualcomm PMIC GPIO and MPP lines are problematic: the are fetched from the main MFD driver with platform_get_irq() which means that at this point they will all be assigned the flags set up for the interrupts in the device tree.

That is problematic since these are flagged as rising edge and an this point the interrupt descriptor is assigned a rising edge, while the only thing the GPIO/MPP drivers really

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do is issue irq_get_irqchip_state() on the line to read it out and to provide a .to_irq() helper for *other* IRQ consumers.

If another device tree node tries to flag the same IRQ for use as something else than rising edge, the kernel irqdomain core will protest like this:

type mismatch, failed to map hwirq-NN for !

Which is what happens when the device tree defines two contradictory flags for the same interrupt line.

To work around this and alleviate the problem, assign 0 as flag for the interrupts taken by the PM GPIO and MPP drivers. This will lead to the flag being unset, and a second consumer requesting rising, falling, both or level interrupts will be respected. This is what the qcom-pm*.dtsi files already do.

Switched to using the symbolic name IRQ_TYPE_NONE so that we get this more readable.

1173 arch\arm\boot\dts\qcom-apq8064.dtsi#0307 1174 arch\arm\boot\dts\qcom-apq8064.dtsi#1067 1175 arch\arm\boot\dts\qcom-apq8064.dtsi#1327 1176 arch\arm\boot\dts\qcom-apq8084.dtsi#0185 Repo: a91b2e690d40 Ritesh Mon Nov 21 12:07:14 2016 +0530 Description: ARM: dts: Add xo to sdhc clock node on qcom platforms ------Add xo entry to sdhc clock node on all qcom platforms.

1177 arch\arm\boot\dts\qcom-apq8084.dtsi#0191 1178 arch\arm\boot\dts\qcom-apq8084.dtsi#0419 1179 arch\arm\boot\dts\qcom-apq8084.dtsi#0432 1180 arch\arm\boot\dts\qcom-msm8660.dtsi#0144 Repo: e3770594c4c8 Linus Walleij Tue Oct 25 00:22:12 2016 +0200 Description: ARM: dts: add EBI2 to the Qualcomm MSM8660 DTSI ------This adds the external bus interface EBI2 to the MSM8660 device tree, albeit with status = "disabled" so that devices actually using EBI2 can turn it on if needed.

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1181 arch\arm\boot\dts\qcom-msm8974-lge-nexus5-hammerhead.dts#0227 Repo: a511e97c495f Bhushan Wed Jul 20 11:56:10 2016 +0530 Description: ARM: dts: qcom: msm8974-hammerhead: Add sdhci1 node ------This introduces the eMMC sdhci node and its pinctrl state

ARM: dts: msm8974-hammerhead: Introduce gpio-keys nodes ------This introduces the gpio-keys node for keys of hammerhead and pinctrl state associated with it.

ARM: dts: msm8974-hammerhead: Add regulator nodes for hammerhead ------

1182 arch\arm\boot\dts\qcom-msm8974.dtsi#0223 Repo: a91b2e690d40 Ritesh Mon Nov 21 12:07:14 2016 +0530 Description: ARM: dts: Add xo to sdhc clock node on qcom platforms ------Add xo entry to sdhc clock node on all qcom platforms.

ARM: dts: msm8974: Move vreg_boost node from the honami to msm8974 ------vreg_boost is Qualcomm platform specific and is also used in hammerhead device.

ARM: dts: qcom: msm8974: Add fixed regulator node for vph-pwr-reg ------

arm: dts: msm8974: Add thermal zones, tsens and qfprom nodes ------Add thermal zones, tsens and qfprom nodes

1183 arch\arm\boot\dts\qcom-msm8974.dtsi#0229 1184 arch\arm\boot\dts\qcom-msm8974.dtsi#0561 1185 arch\arm\boot\dts\qcom-msm8974.dtsi#0574

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1186 arch\arm\boot\dts\r7s72100-rskrza1.dts#0059 Repo: bba1b7ea9a1c Chris Brandt Mon Sep 26 16:40:32 2016 -0400 Description: ARM: dts: rskrza1: add sdhi1 DT support ------

ARM: dts: rskrza1: add ethernet DT support ------

1187 arch\arm\boot\dts\r7s72100.dtsi#0120 Repo: 66474697923c Chris Brandt Mon Sep 26 16:40:31 2016 -0400 Description: ARM: dts: r7s72100: add sdhi to device tree ------

ARM: dts: r7s72100: add sdhi clock to device tree ------

ARM: dts: r7s72100: add mmcif to device tree ------

ARM: dts: r7s72100: add mmcif clock to device tree ------

ARM: dts: r7s72100: add ethernet to device tree ------

1188 arch\arm\boot\dts\r7s72100.dtsi#0152 1189 arch\arm\boot\dts\r7s72100.dtsi#0461 1190 arch\arm\boot\dts\r8a73a4.dtsi#0754 Repo: f02703320698 Geert Mon Nov 14 19:37:09 2016 +0100 Description: ARM: dts: r8a73a4: Add device node for PRR ------Add a device node for the Product Register, which provides SoC product and revision information.

1191 arch\arm\boot\dts\r8a7740.dtsi#0011 Repo: d0b54c54f1a2 Geert Fri Oct 21 11:16:09 2016 +0200 Description: ARM: dts: r8a7740: Remove skeleton.dtsi inclusion ------As of commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

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Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

1192 arch\arm\boot\dts\r8a7740.dtsi#0020 1193 arch\arm\boot\dts\r8a7778.dtsi#0017 Repo: 786a72d79140 Linus Thu Dec 15 15:50:24 2016 -0800 Description: Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget

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- NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

ARM: dts: r8a7778: Remove skeleton.dtsi inclusion

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------As of commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

ARM: dts: r8a7778: Add device node for RESET/WDT module ------Add a device node for the RESET/WDT module, which provides a.o. reset control, mode pin monitoring, and watchdog control.

1194 arch\arm\boot\dts\r8a7778.dtsi#0026 1195 arch\arm\boot\dts\r8a7778.dtsi#0629 1196 arch\arm\boot\dts\r8a7779-marzen.dts#0173 Repo: 8698d83dcf1b Laurent Fri Oct 21 15:27:43 2016 +0300 Description: ARM: dts: r8a7779: marzen: Configure pinmuxing for the DU0 input clock ------DU0 uses an externally provided clock, but the corresponding pin isn't correctly muxed. Fix it.

1197 arch\arm\boot\dts\r8a7779.dtsi#0012 Repo: 786a72d79140 Linus Thu Dec 15 15:50:24 2016 -0800 Description: Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor

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- ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support

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ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

ARM: dts: r8a7779: Add device node for PRR ------Add a device node for the Product Register, which provides SoC product and revision information.

ARM: dts: r8a7779: Remove skeleton.dtsi inclusion ------As of commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

ARM: dts: r8a7779: Fix DU reg property ------The system uses one address cell and one size cell, not two. Fix the DU DT node.

ARM: dts: r8a7779: Add device node for RESET/WDT module ------Add a device node for the RESET/WDT module, which provides a.o. reset control, mode pin monitoring, and watchdog control.

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1198 arch\arm\boot\dts\r8a7779.dtsi#0022 1199 arch\arm\boot\dts\r8a7779.dtsi#0423 1200 arch\arm\boot\dts\r8a7779.dtsi#0593 1201 arch\arm\boot\dts\r8a7790-lager.dts#0053 Repo: dcc2fe783d53 Simon Thu Nov 3 16:07:23 2016 +0100 Description: ARM: dts: lager: Enable UHS-I SDR-104 ------Add the sd-uhs-sdr104 property to SDHI0.

ARM: dts: lager: use demuxer for IIC1/I2C1 ------Make it possible to select which I2C1 IP core you want to run on the EXIO-A connector.

This is based on reference work for the I2C0 core of the lager board by Wolfram Sang.

ARM: dts: lager: rename and reindex i2cexio ------The rename from i2cexio to i2cexio0 is in preparation for adding i2cexio1 which will use the demuxer for IIC1/I2C1.

The reindexing from i2c8 to i2c10 is to allow space for grouping of additional GPIO buses to be added by follow-up patches to support demuxing of other i2c buses.

Also note that fallback to GPIO is not provided by the hardware for IIC0/I2C0.

ARM: dts: lager: Add entries for VIN HDMI input support ------Add DT entries for vin0, vin0_pins, and adv7612.

Sets the 'default-input' property for ADV7612, enabling image and video capture without the need to have userspace specifying routing.

ARM: dts: lager: Name vin pfc subnode after device name ------Name the Pin Function Controller subnode for VIN1 after its device name, instead of using the generic and indexless "vin".

This avoids conflicts when enabling support for more video inputs later, either here or in a DT overlay.

Review_4.10_0_to_1000.pdf Page 269 of 793 May 04, 2018

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ARM: dts: lager: Name spi pfc subnodes after device names ------Name the Pin Function Controller subnodes for QSPI and MSIOF1 after their device names, instead of after the spi interface aliases.

This avoids conflicts when enabling support for more spi interfaces later, either here or in a DT overlay.

1202 arch\arm\boot\dts\r8a7790-lager.dts#0236 1203 arch\arm\boot\dts\r8a7790-lager.dts#0252 1204 arch\arm\boot\dts\r8a7790-lager.dts#0270 1205 arch\arm\boot\dts\r8a7790-lager.dts#0289 1206 arch\arm\boot\dts\r8a7790-lager.dts#0292 1207 arch\arm\boot\dts\r8a7790-lager.dts#0295 1208 arch\arm\boot\dts\r8a7790-lager.dts#0299 1209 arch\arm\boot\dts\r8a7790-lager.dts#0434 1210 arch\arm\boot\dts\r8a7790-lager.dts#0474 1211 arch\arm\boot\dts\r8a7790-lager.dts#0611 1212 arch\arm\boot\dts\r8a7790-lager.dts#0633 1213 arch\arm\boot\dts\r8a7790-lager.dts#0638 1214 arch\arm\boot\dts\r8a7790-lager.dts#0641 1215 arch\arm\boot\dts\r8a7790-lager.dts#0647 1216 arch\arm\boot\dts\r8a7790-lager.dts#0648 1217 arch\arm\boot\dts\r8a7790-lager.dts#0703 1218 arch\arm\boot\dts\r8a7790-lager.dts#0708 1219 arch\arm\boot\dts\r8a7790-lager.dts#0806 1220 arch\arm\boot\dts\r8a7790.dtsi#0714 Repo: 786a72d79140 Linus Thu Dec 15 15:50:24 2016 -0800 Description: Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

Review_4.10_0_to_1000.pdf Page 270 of 793 May 04, 2018

Review der Linux Kernel Sourcen von 4.9 auf 4.10

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We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

- The old STiH415/416 SoC support gets removed, these never made it

Review_4.10_0_to_1000.pdf Page 271 of 793 May 04, 2018

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into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

ARM: dts: r8a7790: Add device node for PRR ------Add a device node for the Product Register, which provides SoC product and revision information.

ARM: dts: r8a7790: Correct SCIFB reg properties to cover all registers ------Several SCIFB registers reside outside the reported register ranges. Fortunately this works (on Linux), due to the PAGE_SIZE granularity of ioremap().

Extend the sizes from 64 to 0x100 bytes to fix this, like is done on SH/R-Mobile SoCs.

ARM: dts: r8a7790: Add device node for RST module ------

Review_4.10_0_to_1000.pdf Page 272 of 793 May 04, 2018

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Add a device node for the RST module, which provides a.o. reset control and mode pin monitoring.

1221 arch\arm\boot\dts\r8a7790.dtsi#0728 1222 arch\arm\boot\dts\r8a7790.dtsi#0742 1223 arch\arm\boot\dts\r8a7790.dtsi#1474 1224 arch\arm\boot\dts\r8a7791-koelsch.dts#0053 Repo: 0726729a4c68 Simon Thu Nov 3 16:07:24 2016 +0100 Description: ARM: dts: koelsch: Enable UHS-I SDR-104 ------And the sd-uhs-sdr104 property to SDHI0.

ARM: dts: koelsch: use demuxer for I2C1 ------Make it possible to fallback to GPIO for I2C1 on the EXIO-C connector.

This is based on reference work for the I2C0 core of the lager/r8a7790 by Wolfram Sang.

ARM: dts: koelsch: add HDMI input ------Add support in the dts for the HDMI input. Based on the Lager dts patch from Ulrich Hecht.

ARM: dts: koelsch: enable UHS for SDHI 0, 1 & 3 ------Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI{0,1,2}.

ARM: dts: koelsch: Name spi pfc subnodes after device names ------Name the Pin Function Controller subnodes for QSPI and MSIOF0 after their device names, instead of after the spi interface aliases.

This avoids conflicts when enabling support for more spi interfaces later, either here or in a DT overlay.

1225 arch\arm\boot\dts\r8a7791-koelsch.dts#0270

Review_4.10_0_to_1000.pdf Page 273 of 793 May 04, 2018

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1226 arch\arm\boot\dts\r8a7791-koelsch.dts#0286 1227 arch\arm\boot\dts\r8a7791-koelsch.dts#0303 1228 arch\arm\boot\dts\r8a7791-koelsch.dts#0361 1229 arch\arm\boot\dts\r8a7791-koelsch.dts#0404 1230 arch\arm\boot\dts\r8a7791-koelsch.dts#0407 1231 arch\arm\boot\dts\r8a7791-koelsch.dts#0416 1232 arch\arm\boot\dts\r8a7791-koelsch.dts#0419 1233 arch\arm\boot\dts\r8a7791-koelsch.dts#0428 1234 arch\arm\boot\dts\r8a7791-koelsch.dts#0431 1235 arch\arm\boot\dts\r8a7791-koelsch.dts#0458 1236 arch\arm\boot\dts\r8a7791-koelsch.dts#0524 1237 arch\arm\boot\dts\r8a7791-koelsch.dts#0531 1238 arch\arm\boot\dts\r8a7791-koelsch.dts#0538 1239 arch\arm\boot\dts\r8a7791-koelsch.dts#0545 1240 arch\arm\boot\dts\r8a7791-koelsch.dts#0551 1241 arch\arm\boot\dts\r8a7791-koelsch.dts#0557 1242 arch\arm\boot\dts\r8a7791-koelsch.dts#0615 1243 arch\arm\boot\dts\r8a7791-koelsch.dts#0672 1244 arch\arm\boot\dts\r8a7791-koelsch.dts#0678 1245 arch\arm\boot\dts\r8a7791-koelsch.dts#0781 1246 arch\arm\boot\dts\r8a7791.dtsi#0587 Repo: 786a72d79140 Linus Thu Dec 15 15:50:24 2016 -0800 Description: Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant

Review_4.10_0_to_1000.pdf Page 274 of 793 May 04, 2018

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- Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

Review_4.10_0_to_1000.pdf Page 275 of 793 May 04, 2018

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* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

ARM: dts: r8a7791: Add device node for PRR ------Add a device node for the Product Register, which provides SoC product and revision information.

ARM: dts: r8a7791: Correct SCIFB reg properties to cover all registers ------Several SCIFB registers reside outside the reported register ranges. Fortunately this works (on Linux), due to the PAGE_SIZE granularity of ioremap().

Extend the sizes from 64 to 0x100 bytes to fix this, like is done on SH/R-Mobile SoCs.

ARM: dts: r8a7791: Add device node for RST module ------Add a device node for the RST module, which provides a.o. reset control and mode pin monitoring.

ARM: dts: r8a7791: set maximum frequency for SDHI clocks ------Define the upper limit otherwise the driver cannot utilize max speeds.

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1247 arch\arm\boot\dts\r8a7791.dtsi#0600 1248 arch\arm\boot\dts\r8a7791.dtsi#0613 1249 arch\arm\boot\dts\r8a7791.dtsi#0705 1250 arch\arm\boot\dts\r8a7791.dtsi#0719 1251 arch\arm\boot\dts\r8a7791.dtsi#0733 1252 arch\arm\boot\dts\r8a7791.dtsi#1488 1253 arch\arm\boot\dts\r8a7792-wheat.dts#0089 Repo: f6eea82a87db Sergei Fri Sep 23 00:06:43 2016 +0300 Description: ARM: dts: wheat: add DU support ------Define the Wheat board dependent part of the DU device node. Add the device nodes for the Analog Devices ADV7513 HDMI transmitters connected to DU0/1. Add the necessary subnodes to interconnect DU with HDMI transmitters/connectors.

ARM: dts: wheat: add support for tactile switches ------Add support for the tactile switches SW2/3 (on the debug board) as a virtual keyboard like it was done with the Blanche board).

1254 arch\arm\boot\dts\r8a7792-wheat.dts#0159 1255 arch\arm\boot\dts\r8a7792-wheat.dts#0238 1256 arch\arm\boot\dts\r8a7792.dtsi#0029 Repo: 786a72d79140 Linus Thu Dec 15 15:50:24 2016 -0800 Description: Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets

Review_4.10_0_to_1000.pdf Page 277 of 793 May 04, 2018

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- Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits)

Review_4.10_0_to_1000.pdf Page 278 of 793 May 04, 2018

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arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

ARM: dts: r8a7792: Add device node for PRR ------Add a device node for the Product Register, which provides SoC product and revision information.

ARM: dts: r8a7792: add MSIOF support ------Define the generic R8A7792 parts of the MSIOF0/1 device nodes.

Based on the original (and large) patch by Vladimir Barinov .

ARM: dts: r8a7792: add MSIOF clocks ------Describe the MSIOF0/1 clocks and their parent, MP clock in the R8A7792 device tree.

Based on the original (and large) patch by Vladimir Barinov .

ARM: dts: r8a7792: Add device node for RST module ------Add a device node for the RST module, which provides a.o. reset control and mode pin monitoring.

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ARM: dts: r8a7792: add QSPI support ------Define the generic R8A7792 part of the QSPI device node.

Based on the original (and large) patch by Vladimir Barinov .

1257 arch\arm\boot\dts\r8a7792.dtsi#0123 1258 arch\arm\boot\dts\r8a7792.dtsi#0587 1259 arch\arm\boot\dts\r8a7792.dtsi#0806 1260 arch\arm\boot\dts\r8a7792.dtsi#0843 1261 arch\arm\boot\dts\r8a7792.dtsi#0870 1262 arch\arm\boot\dts\r8a7792.dtsi#0873 1263 arch\arm\boot\dts\r8a7792.dtsi#0876 1264 arch\arm\boot\dts\r8a7793-gose.dts#0349 Repo: af897250ea54 Simon Fri Sep 16 12:04:54 2016 +0200 Description: ARM: dts: gose: use generic pinctrl properties in SDHI nodes ------Since 16ccaf5bb5a5 ("pinctrl: sh-pfc: Accept standard function, pins and groups properties") renesas pfc drivers accept generic "function", "pins" and "groups" properties.

ARM: dts: gose: Name spi pfc subnode after device name ------Name the Pin Function Controller subnode for QSPI after its device name, instead of after the spi interface alias.

This avoids conflicts when enabling support for more spi interfaces later, either here or in a DT overlay.

1265 arch\arm\boot\dts\r8a7793-gose.dts#0354 1266 arch\arm\boot\dts\r8a7793-gose.dts#0359 1267 arch\arm\boot\dts\r8a7793.dtsi#0669 Repo: 786a72d79140 Linus Thu Dec 15 15:50:24 2016 -0800 Description: Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann:

Review_4.10_0_to_1000.pdf Page 280 of 793 May 04, 2018

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"Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm,

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mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

ARM: dts: r8a7793: Add device node for PRR ------Add a device node for the Product Register, which provides SoC product and revision information.

ARM: dts: r8a7793: Enable VIN0-VIN2 ------

ARM: dts: r8a7793: Correct SCIFB reg properties to cover all registers ------Several SCIFB registers reside outside the reported register ranges.

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Fortunately this works (on Linux), due to the PAGE_SIZE granularity of ioremap().

Extend the sizes from 64 to 0x100 bytes to fix this, like is done on SH/R-Mobile SoCs.

ARM: dts: r8a7793: Add device node for RST module ------Add a device node for the RST module, which provides a.o. reset control and mode pin monitoring.

1268 arch\arm\boot\dts\r8a7793.dtsi#0683 1269 arch\arm\boot\dts\r8a7793.dtsi#0697 1270 arch\arm\boot\dts\r8a7793.dtsi#0855 1271 arch\arm\boot\dts\r8a7793.dtsi#1309 1272 arch\arm\boot\dts\r8a7794-alt.dts#0021 Repo: f9f2fc0b8d65 Simon Thu Nov 3 16:07:25 2016 +0100 Description: ARM: dts: alt: Enable UHS-I SDR-104 ------And the sd-uhs-sdr104 property to SDHI0.

ARM: dts: alt: use demuxer for I2C4 ------Make it possible to fallback to GPIO for I2C4 on the EXIO-B connector.

This is based on reference work for the I2C0 core of the lager/r8a7790 by Wolfram Sang.

ARM: dts: alt: Fix PFC names for DU ------Update the PFC pin groups and function names of DU interface for r8a7794 ALT board.

The currently specified pin groups and function names prevented PFC and DU interfaces from being correctly configured:

sh-pfc e6060000.pin-controller: function 'du' not supported sh-pfc e6060000.pin-controller: invalid function du in map table sh-pfc e6060000.pin-controller: function 'du' not supported sh-pfc e6060000.pin-controller: invalid function du in map table sh-pfc e6060000.pin-controller: function 'du' not supported sh-pfc e6060000.pin-controller: invalid function du in map table

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sh-pfc e6060000.pin-controller: function 'du' not supported sh-pfc e6060000.pin-controller: invalid function du in map table rcar-du: probe of feb00000.display failed with error -22

ARM: dts: alt: enable UHS for SDHI 0 & 1 ------Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI{0,1}.

ARM: dts: alt: add MMCIF support ------Define the Alt board dependent part of the MMCIF device node.

Like the Silk the board has eMMC chip along with the necessary voltage regulator (note that the Vcc/Vccq regulator is dummy -- it's required by the MMCIF driver but doesn't actually exist on the board).

Based on work for the Silk board by Vladimir Barinov and Sergei Shtylyov.

1273 arch\arm\boot\dts\r8a7794-alt.dts#0140 1274 arch\arm\boot\dts\r8a7794-alt.dts#0193 1275 arch\arm\boot\dts\r8a7794-alt.dts#0222 1276 arch\arm\boot\dts\r8a7794-alt.dts#0240 1277 arch\arm\boot\dts\r8a7794-alt.dts#0243 1278 arch\arm\boot\dts\r8a7794-alt.dts#0252 1279 arch\arm\boot\dts\r8a7794-alt.dts#0254 1280 arch\arm\boot\dts\r8a7794-alt.dts#0302 1281 arch\arm\boot\dts\r8a7794-alt.dts#0309 1282 arch\arm\boot\dts\r8a7794-alt.dts#0316 1283 arch\arm\boot\dts\r8a7794-alt.dts#0323 1284 arch\arm\boot\dts\r8a7794-alt.dts#0348 1285 arch\arm\boot\dts\r8a7794.dtsi#0322 Repo: 786a72d79140 Linus Thu Dec 15 15:50:24 2016 -0800 Description: Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where

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things come together.

We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

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- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

ARM: dts: r8a7794: Add device node for PRR ------Add a device node for the Product Register, which provides SoC product and revision information.

ARM: dts: r8a7794: Use SYSC "always-on" PM Domain for sound ------Hook up the Audio-DMAC and sound device nodes to the SYSC "always-on" PM Domain, for a more consistent device-power-area description in DT.

Cfr. commit 0761ff2ad0c581f3 ("ARM: dts: r8a7794: Add SYSC PM Domains").

Fixes: 320d6c5a08a4abd3 ("ARM: dts: r8a7794: add sound support") Fixes: 298e4ee3d213a076 ("ARM: dts: r8a7794: add Audio-DMAC support")

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ARM: dts: r8a7794: Correct hsusb parent clock ------The parent clock of the HSUSB clock is the HP clock, not the MP clock.

Fixes: c7bab9f929e51761 ("ARM: shmobile: r8a7794: Add USB clocks to device tree")

ARM: dts: r8a7794: remove Z clock ------R8A7794 doesn't have Cortex-A15 CPUs, thus there's no Z clock...

Fixes: 0dce5454d5c2 ("ARM: shmobile: Initial r8a7794 SoC device tree")

ARM: dts: r8a7794: Fix W=1 dtc warnings ------Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,dvc/dvc@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,dvc/dvc@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,mix/mix@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,mix/mix@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@6 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ctu/ctu@7 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@5 has a unit name, but no reg property

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Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,src/src@6 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@2 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@3 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@6 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@7 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@8 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /sound@ec500000/rcar_sound,ssi/ssi@9 has a unit name, but no reg property

ARM: dts: r8a7794: Correct SCIFB reg properties to cover all registers ------Several SCIFB registers reside outside the reported register ranges. Fortunately this works (on Linux), due to the PAGE_SIZE granularity of ioremap().

Extend the sizes from 64 to 0x100 bytes to fix this, like is done on SH/R-Mobile SoCs.

ARM: dts: r8a7794: set maximum frequency for SDHI clocks ------Define the upper limit otherwise the driver cannot utilize max speeds.

ARM: dts: r8a7794: Add device node for RST module ------Add a device node for the RST module, which provides a.o. reset control and mode pin monitoring.

1286 arch\arm\boot\dts\r8a7794.dtsi#0414

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1287 arch\arm\boot\dts\r8a7794.dtsi#0428 1288 arch\arm\boot\dts\r8a7794.dtsi#0442 1289 arch\arm\boot\dts\r8a7794.dtsi#0734 1290 arch\arm\boot\dts\r8a7794.dtsi#0747 1291 arch\arm\boot\dts\r8a7794.dtsi#0760 1292 arch\arm\boot\dts\r8a7794.dtsi#1031 1293 arch\arm\boot\dts\r8a7794.dtsi#1265 1294 arch\arm\boot\dts\r8a7794.dtsi#1380 1295 arch\arm\boot\dts\r8a7794.dtsi#1498 1296 arch\arm\boot\dts\r8a7794.dtsi#1503 1297 arch\arm\boot\dts\r8a7794.dtsi#1507 1298 arch\arm\boot\dts\r8a7794.dtsi#1514 1299 arch\arm\boot\dts\r8a7794.dtsi#1519 1300 arch\arm\boot\dts\r8a7794.dtsi#1530 1301 arch\arm\boot\dts\r8a7794.dtsi#1533 1302 arch\arm\boot\dts\r8a7794.dtsi#1538 1303 arch\arm\boot\dts\r8a7794.dtsi#1543 1304 arch\arm\boot\dts\r8a7794.dtsi#1548 1305 arch\arm\boot\dts\r8a7794.dtsi#1553 1306 arch\arm\boot\dts\r8a7794.dtsi#1558 1307 arch\arm\boot\dts\r8a7794.dtsi#1566 1308 arch\arm\boot\dts\r8a7794.dtsi#1572 1309 arch\arm\boot\dts\r8a7794.dtsi#1578 1310 arch\arm\boot\dts\r8a7794.dtsi#1584 1311 arch\arm\boot\dts\r8a7794.dtsi#1590 1312 arch\arm\boot\dts\r8a7794.dtsi#1596 1313 arch\arm\boot\dts\r8a7794.dtsi#1602 1314 arch\arm\boot\dts\r8a7794.dtsi#1608 1315 arch\arm\boot\dts\r8a7794.dtsi#1614

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1316 arch\arm\boot\dts\r8a7794.dtsi#1620 1317 arch\arm\boot\dts\rk3036-evb.dts#0049 Repo: 4c2b306f69cd Javier Fri Sep 9 10:01:06 2016 -0400 Description: ARM: dts: rockchip: Add missing unit name to memory nodes in rk3036 boards ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

1318 arch\arm\boot\dts\rk3036-kylin.dts#0049 Repo: 4c2b306f69cd Javier Fri Sep 9 10:01:06 2016 -0400 Description: ARM: dts: rockchip: Add missing unit name to memory nodes in rk3036 boards ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

1319 arch\arm\boot\dts\rk3036.dtsi#0047 Repo: 786a72d79140 Linus Thu Dec 15 15:50:24 2016 -0800 Description: Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066

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- Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC

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ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

usb: dwc2: Deprecate g-use-dma binding ------This is not needed as the gadget now fully supports DMA and it can autodetect it. This was initially added because gadget DMA mode was only partially implemented so could not be automatically enabled.

ARM: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max" ------In drivers/mmc/core/host.c, there is "max-frequency" property. It should be same behavior. So use the "max-frequency" instead of "clock-freq-min-max".

ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk3036.dtsi ------The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi").

These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future:

"Node /memory has a reg or ranges property, but no unit name"

The disassembled DTB are almost the same, besides empty chosen nodes being removed. So the change should not have a functional impact.

1320 arch\arm\boot\dts\rk3036.dtsi#0050 1321 arch\arm\boot\dts\rk3036.dtsi#0209

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1322 arch\arm\boot\dts\rk3036.dtsi#0248 1323 arch\arm\boot\dts\rk3036.dtsi#0259 1324 arch\arm\boot\dts\rk3036.dtsi#0275 1325 arch\arm\boot\dts\rk3066a-bqcurie2.dts#0052 Repo: adc9e3a68840 Javier Fri Sep 9 10:01:09 2016 -0400 Description: ARM: dts: rockchip: Add missing unit name to memory nodes in rk3xxx boards ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

1326 arch\arm\boot\dts\rk3066a-marsboard.dts#0050 Repo: adc9e3a68840 Javier Fri Sep 9 10:01:09 2016 -0400 Description: ARM: dts: rockchip: Add missing unit name to memory nodes in rk3xxx boards ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

1327 arch\arm\boot\dts\rk3066a-rayeager.dts#0051 Repo: adc9e3a68840 Javier Fri Sep 9 10:01:09 2016 -0400 Description: ARM: dts: rockchip: Add missing unit name to memory nodes in rk3xxx boards ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

1328 arch\arm\boot\dts\rk3066a.dtsi#0154 Repo: 8ce0eda30aea Pawe Jarosz Mon Nov 14 07:52:06 2016 +0100 Description: ARM: dts: rockchip: enable dma for uart and mmc on rk3066a ------DMA controller driver is in good shape these days on rockchip platforms. So lets enable DMA for uart and mmc.

ARM: dts: rockchip: fix TSADC reset node for rk3066a ------This patch fixes incorectly assigned rk3066a TSADC node

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ARM: dts: rockchip: Set sdmmc frequency at boot time for rk3066a ------Currently driver leaves sdmmc frequency at its default. So lets set this to 50MHz. This gives us performance boost in mmc transfers.

ARM: dts: rockchip: initialize rk3066 PLL clock rate ------Initialize PLL, cpu bus and peripherial bus rate while kernel init. No other module does than.

This gives us performance boost observable for example in mmc transfers.

ARM: dts: rockchip: update compatible strings for Rockchip efuse ------

1329 arch\arm\boot\dts\rk3066a.dtsi#0173 1330 arch\arm\boot\dts\rk3066a.dtsi#0208 1331 arch\arm\boot\dts\rk3066a.dtsi#0639 1332 arch\arm\boot\dts\rk3066a.dtsi#0648 1333 arch\arm\boot\dts\rk3066a.dtsi#0654 1334 arch\arm\boot\dts\rk3066a.dtsi#0690 1335 arch\arm\boot\dts\rk3066a.dtsi#0697 1336 arch\arm\boot\dts\rk3066a.dtsi#0704 1337 arch\arm\boot\dts\rk3066a.dtsi#0711 1338 arch\arm\boot\dts\rk3188-radxarock.dts#0051 Repo: adc9e3a68840 Javier Fri Sep 9 10:01:09 2016 -0400 Description: ARM: dts: rockchip: Add missing unit name to memory nodes in rk3xxx boards ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

1339 arch\arm\boot\dts\rk3188.dtsi#0150 Repo: 85b72602df53 Finley Xiao Thu Sep 1 20:16:55 2016 -0700 Description: ARM: dts: rockchip: update compatible strings for Rockchip efuse ------

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ARM: dts: rockchip: add missing unitname to cpu_leakage efuse ------

1340 arch\arm\boot\dts\rk3228-evb.dts#0049 Repo: 09fbc4a08e8c Javier Fri Sep 9 10:01:07 2016 -0400 Description: ARM: dts: rockchip: Add missing unit name to memory nodes in rk322x boards ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

1341 arch\arm\boot\dts\rk3229-evb.dts#0049 Repo: 09fbc4a08e8c Javier Fri Sep 9 10:01:07 2016 -0400 Description: ARM: dts: rockchip: Add missing unit name to memory nodes in rk322x boards ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

1342 arch\arm\boot\dts\rk322x.dtsi#0047 Repo: 6a8883d614c7 Jaehoon Thu Nov 3 15:21:33 2016 +0900 Description: ARM: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max" ------In drivers/mmc/core/host.c, there is "max-frequency" property. It should be same behavior. So use the "max-frequency" instead of "clock-freq-min-max".

ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk322x.dtsi ------The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi").

These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future:

"Node /memory has a reg or ranges property, but no unit name"

The disassembled DTB are almost the same, besides empty chosen nodes being removed. So the change should not have a functional impact.

ARM: dts: rockchip: add GMAC nodes for RK322x SoCs ------

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This patch add the GMAC dt nodes for rk322x SoCs.

ARM: dts: rockchip: add i2s nodes for RK322x SoCs ------This patch add the i2s dt nodes for rk322x SoCs.

1343 arch\arm\boot\dts\rk322x.dtsi#0050 1344 arch\arm\boot\dts\rk322x.dtsi#0407 1345 arch\arm\boot\dts\rk3288-evb.dtsi#0046 Repo: 0b639b815f15 Javier Fri Sep 9 10:01:08 2016 -0400 Description: ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288 boards ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

1346 arch\arm\boot\dts\rk3288-fennec.dts#0049 Repo: 0b639b815f15 Javier Fri Sep 9 10:01:08 2016 -0400 Description: ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288 boards ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

1347 arch\arm\boot\dts\rk3288-firefly-reload-core.dtsi#0048 Repo: 0b639b815f15 Javier Fri Sep 9 10:01:08 2016 -0400 Description: ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288 boards ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

1348 arch\arm\boot\dts\rk3288-firefly.dtsi#0047 Repo: 0b639b815f15 Javier Fri Sep 9 10:01:08 2016 -0400 Description: ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288 boards ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

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1349 arch\arm\boot\dts\rk3288-miqi.dts#0055 Repo: 0b639b815f15 Javier Fri Sep 9 10:01:08 2016 -0400 Description: ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288 boards ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

1350 arch\arm\boot\dts\rk3288-popmetal.dts#0051 Repo: c959ab8be233 Andy Yan Wed Sep 7 09:02:13 2016 +0800 Description: ARM: dts: rockchip: use pin constants to describe gpios on Popmetal-RK3288 ------Use definition in rockchip pinctrl header to describe gpios, this will make it more clear.

ARM: dts: rockchip: enable HS200/DDR52 mode for emmc on rk3288-popmetal ------Enable these two modes to speed up the booting and improve the performance.

ARM: dts: rockchip: Support UHS mode for SD card on PopMetal-RK3288 board ------PopMetal-RK3288 board could enable SD3.0 card but need vccio_sd to support the voltage range from 1V8 to 3V3 and we also need to add more UHS mode here.

ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288 boards ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

ARM: dts: rockchip: Add sensor-supplies on PopMetal-RK3288 board ------Add power supply reference for L3G3200D and the 3-axis Electronic Compass AK8963.

ARM: dts: rockchip: fix L3G4200D i2c address on PopMetal-RK3288 board ------The i2c address of the three-axis digital gyroscope L3G4200D should be 0x69 according to hardware design.

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1351 arch\arm\boot\dts\rk3288-popmetal.dts#0071 1352 arch\arm\boot\dts\rk3288-popmetal.dts#0082 1353 arch\arm\boot\dts\rk3288-popmetal.dts#0097 1354 arch\arm\boot\dts\rk3288-popmetal.dts#0131 1355 arch\arm\boot\dts\rk3288-popmetal.dts#0150 1356 arch\arm\boot\dts\rk3288-popmetal.dts#0170 1357 arch\arm\boot\dts\rk3288-popmetal.dts#0183 1358 arch\arm\boot\dts\rk3288-popmetal.dts#0289 1359 arch\arm\boot\dts\rk3288-popmetal.dts#0452 1360 arch\arm\boot\dts\rk3288-popmetal.dts#0458 1361 arch\arm\boot\dts\rk3288-popmetal.dts#0464 1362 arch\arm\boot\dts\rk3288-popmetal.dts#0470 1363 arch\arm\boot\dts\rk3288-popmetal.dts#0476 1364 arch\arm\boot\dts\rk3288-popmetal.dts#0482 1365 arch\arm\boot\dts\rk3288-popmetal.dts#0488 1366 arch\arm\boot\dts\rk3288-r89.dts#0051 Repo: 0b639b815f15 Javier Fri Sep 9 10:01:08 2016 -0400 Description: ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288 boards ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

1367 arch\arm\boot\dts\rk3288-rock2-som.dtsi#0045 Repo: 0b639b815f15 Javier Fri Sep 9 10:01:08 2016 -0400 Description: ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288 boards ------This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

1368 arch\arm\boot\dts\rk3288-veyron.dtsi#0050 Repo: 0b639b815f15 Javier Fri Sep 9 10:01:08 2016 -0400 Description: ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288 boards ------

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This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

ARM: dts: rockchip: move rk3288 io-domain nodes to the grf ------io-voltage control is actually part of the grf, so move the node under the newly available grf simple-mfd.

To minimize duplicate code, the core node and compatible property gets placed in the core rk3288.dtsi while the individual boards now only need to enable it and add the necessary supply properties.

1369 arch\arm\boot\dts\rk3288.dtsi#0049 Repo: 786a72d79140 Linus Thu Dec 15 15:50:24 2016 -0800 Description: Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

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And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR

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ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

usb: dwc2: Deprecate g-use-dma binding ------This is not needed as the gadget now fully supports DMA and it can autodetect it. This was initially added because gadget DMA mode was only partially implemented so could not be automatically enabled.

ARM: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max" ------In drivers/mmc/core/host.c, there is "max-frequency" property. It should be same behavior. So use the "max-frequency" instead of "clock-freq-min-max".

ARM: dts: rockchip: update compatible strings for Rockchip efuse ------

ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk3288.dtsi ------The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi").

These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future:

"Node /memory has a reg or ranges property, but no unit name"

The disassembled DTB are almost the same, besides empty chosen nodes being removed. So the change should not have a functional impact.

1370 arch\arm\boot\dts\rk3288.dtsi#0052 1371 arch\arm\boot\dts\rk3288.dtsi#0232 1372 arch\arm\boot\dts\rk3288.dtsi#0244 1373 arch\arm\boot\dts\rk3288.dtsi#0256

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1374 arch\arm\boot\dts\rk3288.dtsi#0268 1375 arch\arm\boot\dts\rk3288.dtsi#0601 1376 arch\arm\boot\dts\rk3288.dtsi#1120 1377 arch\arm\boot\dts\rk3xxx.dtsi#0047 Repo: 786a72d79140 Linus Thu Dec 15 15:50:24 2016 -0800 Description: Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board

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- AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

usb: dwc2: Deprecate g-use-dma binding ------

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This is not needed as the gadget now fully supports DMA and it can autodetect it. This was initially added because gadget DMA mode was only partially implemented so could not be automatically enabled.

ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk3xxx.dtsi ------The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi").

These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future:

"Node /memory has a reg or ranges property, but no unit name"

The disassembled DTB are almost the same, besides empty chosen nodes being removed. So the change should not have a functional impact.

1378 arch\arm\boot\dts\rk3xxx.dtsi#0050 1379 arch\arm\boot\dts\rk3xxx.dtsi#0186 1380 arch\arm\boot\dts\sama5d2.dtsi#0738 Repo: d4ce5f44d440 Alexandre Thu Sep 22 00:09:39 2016 +0200 Description: ARM: dts: at91: sama5d2: Add securam node ------The sama5d2 has some static RAM that can be erased by the security module, add its node

ARM: dts: at91: sama5d2: Add secumod node ------The sama5d2 has a security module, add its node.

ARM: dts: at91: sama5d2: use correct sckc compatible ------the sama5d2 sckc is actually sama5d4 compatible

ARM: dts: at91: sama5d2: enable FIFOs for high-speed i2c controllers ------This patch enables the RX and TX FIFOs (16 data each) of the two high-speed i2c controllers (i2c0 and i2c1).

ARM: dts: at91: sama5d2: add ETM and ETB nodes ------

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Add node to support SAMA5D2 Embedded Trace Macrocell and Embedded Trace Buffer.

This patch depends on coresight-etm3x: Add ARM ETM-A5 peripheral ID for proper coresight functionality. It also depends on clocksource: timer-atmel-pit: enable mck to not stall SAMA5D2 on bootup.

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Olof Johansson: "Device tree contents continue to be the largest branches we submit. This time around, some of the contents worth pointing out is:

New SoC platforms: - Freescale i.MX 7Solo - Broadcom BCM23550 - Cirrus Logic EP7209 and EP7211 (clps711x platforms)_ - Hisilicon HI3519 - Renesas R8A7792

Some of the other delta that is sticking out, line-count wise: - Exynos moves of IP blocks under an SoC bus, which causes a large delta due to indentation changes - a new Tegra K1 board: Apalis - a bunch of small updates to many Allwinner platforms; new hardware support, some cleanup, etc"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (426 commits) ARM: dts: sun8i: Add dts file for inet86dz board ARM: dts: sun8i: Add dts file for Polaroid MID2407PXE03 tablet ARM: dts: sun8i: Use sun8i-reference-design-tablet for ga10h dts ARM: dts: sun8i: Use sun8i-reference-design-tablet for polaroid mid2809pxe04 ARM: dts: sun8i: reference-design-tablet: Add drivevbus-supply ARM: dts: Copy sun8i-q8-common.dtsi sun8i-reference-design-tablet.dtsi ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for utoo p66 dts ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for dit4350 dts ARM: dts: sun5i: reference-design-tablet: Remove mention of q8 ARM: dts: sun5i: reference-design-tablet: Set lradc vref to avcc ARM: dts: sun5i: Rename sun5i-q8-common.dtsi sun5i-reference-design-tablet.dtsi ARM: dts: sun5i: Move q8 display bits to sun5i-a13-q8-tablet.dts ARM: dts: sunxi: Rename sunxi-q8-common.dtsi sunxi-reference-design-tablet.dtsi ARM: dts: at91: Don't build unnecessary dtbs ARM: dts: at91: sama5d3x: separate motherboard gmac and emac definitions ARM: dts: at91: at91sam9g25ek: fix isi endpoint node ARM: dts: at91: move isi definition to at91sam9g25ek ARM: dts: at91: fix i2c-gpio node name ARM: dts: at91: vinco: fix regulator name

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ARM: dts: at91: ariag25 : fix onewire node ...

1381 arch\arm\boot\dts\sama5d2.dtsi#1038 1382 arch\arm\boot\dts\sama5d2.dtsi#1067 1383 arch\arm\boot\dts\sama5d2.dtsi#1106 1384 arch\arm\boot\dts\sama5d2.dtsi#1110 1385 arch\arm\boot\dts\sama5d2.dtsi#1234 1386 arch\arm\boot\dts\sama5d2.dtsi#1263 1387 arch\arm\boot\dts\sama5d3.dtsi#0552 Repo: 138c2b2f175b Sylvain Sun Oct 16 18:21:45 2016 +0200 Description: ARM: dts: at91: fixes dbgu pinctrl, set pullup on rx, clear pullup on tx ------Remove pullup on dbgu DTXD signal, it is a push-pull output thus the pullup is pointless.

Add pullup on dbgu DRXD signal, it prevents the DRXD signal to be left floating and so consuming a useless extra amount of power in crowbarred state if nothing is externally connected to dbgu.

ARM: dts: at91: Fix USB endpoint nodes ------Endpoint nodes have a reg property. Add their mandatory unit-address.

This solves: Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep0 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep1 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep2 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep3 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep4 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep5 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep6 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep7 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep8 has a reg or ranges property, but no unit name

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Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep9 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep10 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep11 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep12 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep13 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep14 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep15 has a reg or ranges property, but no unit name

1388 arch\arm\boot\dts\sama5d4.dtsi#1317 Repo: da32081ffa0f Alexandre Tue Sep 20 22:58:32 2016 +0200 Description: ARM: dts: at91: sama5d4: use proper sckc compatible ------Now that there is support for the sama5d4 slow clock controller, use its driver.

ARM: dts: at91: fixes dbgu pinctrl, set pullup on rx, clear pullup on tx ------Remove pullup on dbgu DTXD signal, it is a push-pull output thus the pullup is pointless.

Add pullup on dbgu DRXD signal, it prevents the DRXD signal to be left floating and so consuming a useless extra amount of power in crowbarred state if nothing is externally connected to dbgu.

ARM: dts: at91: Fix USB endpoint nodes ------Endpoint nodes have a reg property. Add their mandatory unit-address.

This solves: Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep0 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep1 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep2 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep3 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep4 has a reg or ranges property, but no unit name

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Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep5 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep6 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep7 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep8 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep9 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep10 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep11 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep12 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep13 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep14 has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /ahb/gadget@00400000/ep15 has a reg or ranges property, but no unit name

1389 arch\arm\boot\dts\sama5d4.dtsi#1320 1390 arch\arm\boot\dts\sama5d4.dtsi#1464 1391 arch\arm\boot\dts\sh73a0.dtsi#0011 Repo: cbdcf396fc86 Geert Fri Oct 21 11:16:10 2016 +0200 Description: ARM: dts: sh73a0: Remove skeleton.dtsi inclusion ------As of commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.

This fixes the following warning with W=1:

Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

1392 arch\arm\boot\dts\sh73a0.dtsi#0020 1393 arch\arm\boot\dts\socfpga.dtsi#0689 Repo: 7c38dc624bc4 Marek Vasut Mon Nov 21 09:23:31 2016 -0600 Description: ARM: dts: socfpga: fine-tune L2 cache configuration ------Enable double-linefill and increase prefetch offset, which gives considerable read performance boost. The following numbers were

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obtained using lmbench 3.0 bw_mem tool, for easier comparison, the numbers are pasted in two columns. The test machine has Cyclone V SoC running at 800MHz MPU clock and 512MiB 333MHz 16bit DDR3 DRAM.

Without patch | With patch $ for i in rd wr rdwr cp fwr frd fcp bzero bcopy ; do echo $i ; bw_mem 64M $i ; done rd | rd 64.00 526.46 | 64.00 1151.06 wr | wr 64.00 329.95 | 64.00 346.14 rdwr | rdwr 64.00 342.07 | 64.00 367.24 cp | cp 64.00 239.79 | 64.00 322.47 fwr | fwr 64.00 1027.90 | 64.00 1025.38 frd | frd 64.00 322.36 | 64.00 641.89 fcp | fcp 64.00 256.99 | 64.00 408.41 bzero | bzero 64.00 1028.43 | 64.00 1025.07 bcopy | bcopy 64.00 294.73 | 64.00 357.19

ARM: dts: socfpga: add nand controller nodes ------Add the denali nand controller to the socfpga dtsi.

ARM: dts: socfpga: add qspi node ------Add the qspi node to the socfpga dtsi file.

ARM: dts: socfpga: enable arm,shared-override in the pl310 ------Enable the bit(22) shared-override bit for the SoCFPGA family. While at it, enable the prefetch-data and prefetch-instr settings for the Arria10.

1394 arch\arm\boot\dts\socfpga.dtsi#0709 1395 arch\arm\boot\dts\socfpga.dtsi#0727 1396 arch\arm\boot\dts\socfpga_arria10.dtsi#0565 Repo: 5d662bf15dcb Dinh Nguyen Wed Oct 19 10:56:33 2016 -0500 Description: ARM: dts: socfpga: Add QSPI node for the Arria10

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------Add the QSPI device node for Arria10 SOC.

ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chip ------Add the Altera Arria10 SPI Master Node in preparation for the A10SR MFD node.

ARM: dts: socfpga: enable arm,shared-override in the pl310 ------Enable the bit(22) shared-override bit for the SoCFPGA family. While at it, enable the prefetch-data and prefetch-instr settings for the Arria10.

ARM: dts: Add Arria10 USB EDAC devicetree entry ------Add the device tree entries needed to support the Altera USB FIFO buffer EDAC on the Arria10 chip.

ARM: dts: Add Arria10 DMA EDAC devicetree entry ------Add the device tree entries needed to support the Altera DMA FIFO buffer EDAC on the Arria10 chip.

1397 arch\arm\boot\dts\socfpga_arria10.dtsi#0591 1398 arch\arm\boot\dts\socfpga_arria10.dtsi#0678 1399 arch\arm\boot\dts\socfpga_arria10_socdk.dtsi#0039 Repo: acf3b20c2386 Thor Thayer Thu Jun 2 17:52:28 2016 +0000 Description: ARM: dts: socfpga: Add LED framework to A10-SR GPIO ------Add the LED framework to the Arria10 chip GPIO hooks.

ARM: dts: socfpga: Enable GPIO parent for Arria10 SR chip ------Enable the Altera Arria10 GPIO parent for MFD operation.

ARM: dts: socfpga: Add Devkit A10-SR fields for Arria10 ------Add the Altera Arria10 System Resource node. This is a Multi-Function device with GPIO expander support.

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ARM: dts: socfpga: fix definitions of serial console ------The notion of which uart instance is serial0 or serial1 is board specific rather than generic to the chip. This patch removes the serial aliases from generic chip dtsi and adds an appropriate alias to the board specific dtsi. By making the alias for serial0 point to uart1 for the arria10_socdk, the linux boot command line supports specifying console=ttyS0,115200 for backwards compatibility, and it supports not specifying the console at all.

1400 arch\arm\boot\dts\socfpga_arria10_socdk.dtsi#0102 1401 arch\arm\boot\dts\socfpga_arria5_socdk.dts#0085 Repo: 47d5c5ffa33d Dinh Nguyen Wed Oct 19 15:48:07 2016 -0500 Description: ARM: dts: socfpga: Enable QSPI on the Arria5 devkit ------Enable the QSPI node and add the flash chip.

1402 arch\arm\boot\dts\socfpga_cyclone5_de0_sockit.dts#0021 Repo: d1da66351749 Dinh Nguyen Tue Nov 1 09:57:06 2016 -0500 Description: ARM: dts: socfpga: add specific compatible strings for boards ------Add a more specific board compatible entry for all of the SOCFPGA Cyclone 5 based boards.

1403 arch\arm\boot\dts\socfpga_cyclone5_mcv.dtsi#0021 Repo: 587aed72c6b9 Marek Vasut Mon Sep 19 21:40:43 2016 +0000 Description: ARM: dts: socfpga: Add new MCVEVK manufacturer compat ------The board is now manufactured by Aries Embedded GmbH, update compat string.

1404 arch\arm\boot\dts\socfpga_cyclone5_mcvevk.dts#0021 Repo: d1da66351749 Dinh Nguyen Tue Nov 1 09:57:06 2016 -0500 Description: ARM: dts: socfpga: add specific compatible strings for boards ------Add a more specific board compatible entry for all of the SOCFPGA Cyclone 5 based boards.

ARM: dts: socfpga: Add new MCVEVK manufacturer compat

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------The board is now manufactured by Aries Embedded GmbH, update compat string.

1405 arch\arm\boot\dts\socfpga_cyclone5_socdk.dts#0022 Repo: e8f0ff58330b Dinh Nguyen Tue Oct 18 22:51:42 2016 -0500 Description: ARM: dts: socfpga: enable qspi on the Cyclone5 devkit ------Enable the qspi controller on the devkit and add the flash chip.

ARM: dts: socfpga: add specific compatible strings for boards ------Add a more specific board compatible entry for all of the SOCFPGA Cyclone 5 based boards.

1406 arch\arm\boot\dts\socfpga_cyclone5_socdk.dts#0090 1407 arch\arm\boot\dts\socfpga_cyclone5_sockit.dts#0022 Repo: 466e90ca2138 Dinh Nguyen Wed Oct 19 14:55:54 2016 -0500 Description: ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit ------Enable the QSPI node and add the flash chip.

ARM: dts: socfpga: add specific compatible strings for boards ------Add a more specific board compatible entry for all of the SOCFPGA Cyclone 5 based boards.

ARM: dts: socfpga: Add support for HPS KEYs/SWs on SoCKit ------Add support for the keys and flip-switches on the SoCFPGA SoCkit board.

1408 arch\arm\boot\dts\socfpga_cyclone5_sockit.dts#0178 1409 arch\arm\boot\dts\socfpga_cyclone5_socrates.dts#0083 Repo: c96f5919e6b0 Steffen Tue Oct 18 07:43:03 2016 +0000 Description: ARM: dts: socfpga: socrates: enable qspi ------Enable the qspi controller on the socrates and add the flash chip.

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1410 arch\arm\boot\dts\socfpga_cyclone5_vining_fpga.dts#0054 Repo: d1da66351749 Dinh Nguyen Tue Nov 1 09:57:06 2016 -0500 Description: ARM: dts: socfpga: add specific compatible strings for boards ------Add a more specific board compatible entry for all of the SOCFPGA Cyclone 5 based boards.

1411 arch\arm\boot\dts\spear13xx.dtsi#0121 Repo: bd2c6636cc59 Eugeniy Fri Nov 25 17:59:07 2016 +0300 Description: dmaengine: DW DMAC: add multi-block property to device tree ------Several versions of DW DMAC have multi block transfers hardware support. Hardware support of multi block transfers is disabled by default if we use DT to configure DMAC and software emulation of multi block transfers used instead. Add multi-block property, so it is possible to enable hardware multi block transfers (if present) via DT.

Switch from per device is_nollp variable to multi_block array to be able enable/disable multi block transfers separately per channel.

1412 arch\arm\boot\dts\spear13xx.dtsi#0138 1413 arch\arm\boot\dts\stih407-clock.dtsi#0104 Repo: e614a121c434 Peter Griffin Fri Oct 21 11:08:00 2016 +0200 Description: ARM: dts: stih407-clocks: Identify critical clocks ------Lots of platforms contain clocks which if turned off would prove fatal. The only way to recover is to restart the board(s). This driver takes references to clocks which are required to be always-on. The Common Clk Framework will then take references to them. This way they will not be turned off during the clk_disabled_unused() procedure.

In this patch we are identifying clocks, which if gated would render the STiH407 development board unserviceable.

ARM: dts: STiH407: Enable synchronous clock mode for video clocks ------This patch enables the synchronous clock mode for video clocks on STiH407 board.

ARM: dts: STiH407: Enable clock propagation for audio clocks

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------This patch is used in the clock driver to apply a clock propagation flag on the audio clocks of STiH407

1414 arch\arm\boot\dts\stih407-clock.dtsi#0116 1415 arch\arm\boot\dts\stih407-clock.dtsi#0131 1416 arch\arm\boot\dts\stih407-clock.dtsi#0145 1417 arch\arm\boot\dts\stih407-clock.dtsi#0201 1418 arch\arm\boot\dts\stih407-family.dtsi#0683 Repo: 8413299cb393 Patrice Fri Jan 27 15:45:11 2017 +0100 Description: ARM: dts: STiH407-family: set snps,dis_u3_susphy_quirk ------Since v4.10-rc1, the following logs appears in loop : [ 801.953836] usb usb6-port1: Cannot enable. Maybe the USB cable is bad? [ 801.960455] xhci-hcd xhci-hcd.0.auto: Cannot set link state. [ 801.966611] usb usb6-port1: cannot disable (err = -32) [ 806.083772] usb usb6-port1: Cannot enable. Maybe the USB cable is bad? [ 806.090370] xhci-hcd xhci-hcd.0.auto: Cannot set link state. [ 806.096494] usb usb6-port1: cannot disable (err = -32)

After analysis, xhci try to set link in U3 and returns an error. Using snps,dis_u3_susphy_quirk fix this issue.

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

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These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board

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ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

1419 arch\arm\boot\dts\stih407-family.dtsi#0920 1420 arch\arm\boot\dts\stih407-family.dtsi#0930 1421 arch\arm\boot\dts\stih407-family.dtsi#0931 1422 arch\arm\boot\dts\stih407-family.dtsi#0939 1423 arch\arm\boot\dts\stih407-family.dtsi#0949 1424 arch\arm\boot\dts\stih407-family.dtsi#0951 1425 arch\arm\boot\dts\stih407-family.dtsi#0959 1426 arch\arm\boot\dts\stih407-family.dtsi#0969 1427 arch\arm\boot\dts\stih407-family.dtsi#0971 1428 arch\arm\boot\dts\stih407-family.dtsi#0979 1429 arch\arm\boot\dts\stih407-family.dtsi#0990 1430 arch\arm\boot\dts\stih407-family.dtsi#0999 1431 arch\arm\boot\dts\stih407-family.dtsi#1006 1432 arch\arm\boot\dts\stih407-family.dtsi#1013 1433 arch\arm\boot\dts\stih407-family.dtsi#1020 1434 arch\arm\boot\dts\stih407-pinctrl.dtsi#1160 Repo: fd166a3e0534 Geert Fri Oct 21 10:51:00 2016 +0200 Description: ARM: dts: STiH407: DT fix s/interrupts-names/interrupt-names/ ------

ARM: DT: STiH407: Add spdif_out pinctrl config

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------

ARM: DT: STiH407: Add i2s_in pinctrl configuration ------

ARM: DT: STiH407: Add i2s_out pinctrl configuration ------

1435 arch\arm\boot\dts\stih407.dtsi#0105 Repo: eec7f93f6c65 Arnaud Tue Oct 4 18:11:00 2016 +0200 Description: ARM: dts: STiH407: Add label for sti-hdmi node ------Needed to declare HDMI device in sound card

1436 arch\arm\boot\dts\stih410-b2260.dts#0168 Repo: 786a72d79140 Linus Thu Dec 15 15:50:24 2016 -0800 Description: Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point

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- Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR

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ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

1437 arch\arm\boot\dts\stih410-b2260.dts#0180 1438 arch\arm\boot\dts\stih410-clock.dtsi#0211 Repo: 97a0b97f9e81 Peter Griffin Tue Oct 18 17:35:00 2016 +0200 Description: ARM: dts: stih410-clocks: Add PROC_STFE as a critical clock ------Once the ST frontend demux HW IP has been enabled, the clock can't be disabled otherwise the system will hang and the board will be unserviceable.

To allow balanced clock enable/disable calls in the driver we use the critical clock infrastructure to take an extra reference on the clock so the clock will never actually be disabled.

ARM: dts: STiH410: Enable synchronous clock mode for video clocks ------This patch enables the synchronous clock mode for video clocks on STiH410 board.

ARM: dts: STiH410: Enable clock propagation for audio clocks ------This patch is used in the clock driver to apply a clock propagation flag on the audio clocks of STiH410

1439 arch\arm\boot\dts\stih410.dtsi#0196 Repo: 24595472ff96 Arnaud Tue Oct 4 18:11:00 2016 +0200 Description: ARM: dts: STiH410: Add label for sti-hdmi node ------Needed to declare HDMI device in sound card

1440 arch\arm\boot\dts\stih415-b2000.dts#fileDeleted Repo: ce1dfb381752 Patrice Thu Oct 20 15:21:07 2016 +0200 Description: ARM: dts: remove STiH415-b2000.dts ------

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Since v4.8, STiH415/416 clock support has been removed [1], these platform doesn't boot. We can remove DTS files related to these socs.

[1] https://patchwork.kernel.org/patch/9157571/

1441 arch\arm\boot\dts\stih415-b2020.dts#fileDeleted Repo: 1a770b724d2d Patrice Thu Oct 20 15:20:50 2016 +0200 Description: ARM: dts: remove STiH415-b2020.dts ------Since v4.8, STiH415/416 clock support has been removed [1], these platform doesn't boot. We can remove DTS files related to these socs.

[1] https://patchwork.kernel.org/patch/9157571/

1442 arch\arm\boot\dts\stih415-clock.dtsi#fileDeleted Repo: e92e2f324b8f Patrice Thu Oct 20 15:21:30 2016 +0200 Description: ARM: dts: remove STiH415-clock.dtsi ------Since v4.8, STiH415/416 clock support has been removed [1], these platform doesn't boot. We can remove DTS files related to these socs.

[1] https://patchwork.kernel.org/patch/9157571/

ARM: STi: DT: STiH415: 415 DT Entry for clockgen A9 ------Patch adds DT entries for clockgen A9

ARM: STi: DT: STiH415: Remove unused CLK_S_GMAC0_PHY & CLK_S_ETH1_PHY fixed clocks ------CLK_S_GMAC0_PHY & CLK_S_ETH1_PH clocks are no longer used.

ARM: STi: DT: STiH415: Remove unused CLK_S_ICN_REG_0 fixed clock ------CLK_S_ICN_REG_0 clock is no longer used.

ARM: STi: DT: STiH415: 415 DT Entry for clockgen A0/1/10/11/12 ------

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Patch adds DT entries for clockgen A0/1/10/11/12

1443 arch\arm\boot\dts\stih415-pinctrl.dtsi#fileDeleted Repo: ebdce1119e8a Patrice Thu Oct 20 15:21:45 2016 +0200 Description: ARM: dts: remove STiH415-pinctrl.dtsi ------Since v4.8, STiH415/416 clock support has been removed [1], these platform doesn't boot. We can remove DTS files related to these socs.

[1] https://patchwork.kernel.org/patch/9157571/

1444 arch\arm\boot\dts\stih415.dtsi#fileDeleted Repo: 5e7f8d1619ef Patrice Thu Oct 20 15:22:36 2016 +0200 Description: ARM: dts: remove STiH415.dtsi ------Since v4.8, STiH415/416 clock support has been removed [1], these platform doesn't boot. We can remove DTS files related to these socs.

[1] https://patchwork.kernel.org/patch/9157571/

1445 arch\arm\boot\dts\stih416-b2000.dts#fileDeleted Repo: 495075275949 Patrice Thu Oct 20 15:16:33 2016 +0200 Description: ARM: dts: remove STiH416-b2000.dts ------Since v4.8, STiH415/416 clock support has been removed [1], these platform doesn't boot. We can remove DTS files related to these socs.

[1] https://patchwork.kernel.org/patch/9157571/

1446 arch\arm\boot\dts\stih416-b2020.dts#fileDeleted Repo: ee6310e8b209 Patrice Thu Oct 20 15:15:43 2016 +0200 Description: ARM: dts: remove STiH416-b2020.dts ------Since v4.8, STiH415/416 clock support has been removed [1], these platform doesn't boot. We can remove DTS files related to these socs.

[1] https://patchwork.kernel.org/patch/9157571/

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1447 arch\arm\boot\dts\stih416-b2020e.dts#fileDeleted Repo: d724f9459589 Patrice Thu Oct 20 15:15:02 2016 +0200 Description: ARM: dts: remove STiH416-b2020e.dts ------Since v4.8, STiH415/416 clock support has been removed [1], these platform doesn't boot. We can remove DTS files related to these socs.

[1] https://patchwork.kernel.org/patch/9157571/

1448 arch\arm\boot\dts\stih416-clock.dtsi#fileDeleted Repo: 1047121a1ced Patrice Thu Oct 20 15:17:33 2016 +0200 Description: ARM: dts: remove STiH416-clock.dtsi ------Since v4.8, STiH415/416 clock support has been removed [1], these platform doesn't boot. We can remove DTS files related to these socs.

[1] https://patchwork.kernel.org/patch/9157571/

ARM: STi: DT: STiH416: 416 DT Entry for clockgen A9/DDR/GPU ------Patch adds DT entries for clockgen A9/DDR/GPU

ARM: STi: DT: STiH416: 416 DT Entry for clockgen B/C/D/E/F ------Patch adds DT entries for clockgen B/C/D/E/F

ARM: STi: DT: STiH416: Remove unused CLK_S_GMAC0_PHY & CLK_S_ETH1_PHY fixed clocks ------CLK_S_GMAC0_PHY & CLK_S_ETH1_PH clocks are no longer used.

ARM: STi: DT: STiH416: Remove unused CLK_S_ICN_REG_0 fixed clock ------CLK_S_ICN_REG_0 clock is no longer used.

ARM: STi: DT: STiH416: 416 DT Entry for clockgen A0/1/10/11/12 ------Patch adds DT entries for clockgen A0/1/10/11/12

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1449 arch\arm\boot\dts\stih416-pinctrl.dtsi#fileDeleted Repo: 3b3deba776d6 Patrice Thu Oct 20 15:18:10 2016 +0200 Description: ARM: dts: remove STiH416-pinctrl.dtsi ------Since v4.8, STiH415/416 clock support has been removed [1], these platform doesn't boot. We can remove DTS files related to these socs.

[1] https://patchwork.kernel.org/patch/9157571/

ARM: dts: STiH416: Declare PWM Capture data lines via Pinctrl ------

1450 arch\arm\boot\dts\stih416.dtsi#fileDeleted Repo: 27356509813d Patrice Thu Oct 20 15:22:49 2016 +0200 Description: ARM: dts: remove STiH416.dtsi ------Since v4.8, STiH415/416 clock support has been removed [1], these platform doesn't boot. We can remove DTS files related to these socs.

[1] https://patchwork.kernel.org/patch/9157571/

ARM: dts: STiH416: Define the number of PWM Capture channels ------

ARM: dts: STiH416: Define PWM Capture clock ------

1451 arch\arm\boot\dts\stih41x-b2000.dtsi#fileDeleted Repo: 8690d17e5716 Patrice Thu Oct 20 15:25:10 2016 +0200 Description: ARM: dts: remove STiH41x-b2000.dtsi ------Since v4.8, STiH415/416 clock support has been removed [1], these platform doesn't boot. We can remove DTS files related to these socs.

[1] https://patchwork.kernel.org/patch/9157571/

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1452 arch\arm\boot\dts\stih41x-b2020.dtsi#fileDeleted Repo: 11079647c20e Patrice Thu Oct 20 15:25:35 2016 +0200 Description: ARM: dts: remove STiH41x-b2020.dtsi ------Since v4.8, STiH415/416 clock support has been removed [1], these platform doesn't boot. We can remove DTS files related to these socs.

[1] https://patchwork.kernel.org/patch/9157571/

1453 arch\arm\boot\dts\stih41x-b2020x.dtsi#fileDeleted Repo: 10da42c9001c Patrice Thu Oct 20 15:24:06 2016 +0200 Description: ARM: dts: remove STiH41x-b2020.dtsi ------Since v4.8, STiH415/416 clock support has been removed [1], these platform doesn't boot. We can remove DTS files related to these socs.

[1] https://patchwork.kernel.org/patch/9157571/

1454 arch\arm\boot\dts\stih41x.dtsi#fileDeleted Repo: 01a66a33d0fb Patrice Thu Oct 20 15:23:47 2016 +0200 Description: ARM: dts: remove STiH41x.dtsi ------Since v4.8, STiH415/416 clock support has been removed [1], these platform doesn't boot. We can remove DTS files related to these socs.

[1] https://patchwork.kernel.org/patch/9157571/

1455 arch\arm\boot\dts\stihxxx-b2120.dtsi#0138 Repo: 64783ea7de0b Arnaud Fri Nov 4 11:44:00 2016 +0100 Description: ARM: dts: STiHxxx-b2120: change sound card name ------Rename sound card to differentiate B2120 and B2260 sound card. Sound card name is used by alsa-lib to load associated card configuration file.

ARM: dts: STiHxxx-b2120: Add support of HDMI audio ------Add new dai link in sound card to support HDMI output

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ARM: DT: STi: stihxxx-b2120: Add DT nodes for STi audio card ------This patch enables the uniperif players 2 & 3 for b2120 boards and also adds the "simple-audio-card" device node to interconnect the SoC sound device and the codec.

1456 arch\arm\boot\dts\stihxxx-b2120.dtsi#0158 1457 arch\arm\boot\dts\stihxxx-b2120.dtsi#0162 1458 arch\arm\boot\dts\stihxxx-b2120.dtsi#0177 1459 arch\arm\boot\dts\stihxxx-b2120.dtsi#0186 1460 arch\arm\boot\dts\stm32429i-eval.dts#0050 Repo: 682d77cf0a9b Alexandre Wed Sep 7 12:28:17 2016 +0200 Description: ARM: dts: stm32f429: Fix Ethernet node on Eval Board ------"phy-handle" entry is mandatory when mdio subnode is used in Ethernet node.

ARM: dts: stm32f429: Align Ethernet node with new bindings properties ------This patch aligns clocks names and node reference according to new stm32-dwmac glue binding. It also renames Ethernet pinctrl phandle (indeed there is no need to add 0 as Ethernet instance as there is only one IP in SOC).

ARM: DT: stm32: move dma translation to board files ------stm32f469-disco and stm32f429-eval boards use SDRAM start address remapping (to @0) to boost performances. A DMA translation through "dma-ranges" property was needed for other masters than the M4 CPU. stm32f429-disco doesn't use remapping so doesn't need this DMA translation. This patches moves this DMA translation definition from stm32f429 soc file to board files.

ARM: dts: Declare push button as GPIO key on stm32f429 boards ------

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1461 arch\arm\boot\dts\stm32429i-eval.dts#0069 1462 arch\arm\boot\dts\stm32429i-eval.dts#0090 1463 arch\arm\boot\dts\stm32429i-eval.dts#0119 1464 arch\arm\boot\dts\stm32429i-eval.dts#0121 1465 arch\arm\boot\dts\stm32429i-eval.dts#0123 1466 arch\arm\boot\dts\stm32f429-disco.dts#0050 Repo: 5670501c9969 Maxime Fri Sep 2 15:45:53 2016 +0200 Description: ARM: dts: Declare push button as GPIO key on stm32f429 boards ------

ARM: dts: Add leds support to STM32F429 boards ------

ARM: dts: Add USART1 pin config to STM32F429 boards ------

ARM: dts: Use stdout-path in STM32F429 Discovery board ------

ARM: dts: stm32f429: Adopt STM32F4 clock driver ------

1467 arch\arm\boot\dts\stm32f429-disco.dts#0079 1468 arch\arm\boot\dts\stm32f429.dtsi#0059 Repo: f6dbbff4f0af Gabriel Fri Oct 14 11:18:00 2016 +0200 Description: ARM: dts: stm32f429: add LSI and LSE clocks ------This patch adds lsi / lse oscillators. These clocks can be use by RTC clocks. The clock drivers needs to disable the power domain write protection using syscon / regmap to enable these clocks.

ARM: dts: stm32f429: remove Ethernet wake on Lan support ------This patch removes WoL (Wake on Lan) support as it is not yet fully supported and tested.

ARM: dts: stm32f429: Align Ethernet node with new bindings properties ------This patch aligns clocks names and node reference according to new stm32-dwmac glue binding. It also renames Ethernet pinctrl phandle (indeed there is no need to add 0 as Ethernet instance as there is only

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one IP in SOC).

ARM: DT: stm32: move dma translation to board files ------stm32f469-disco and stm32f429-eval boards use SDRAM start address remapping (to @0) to boost performances. A DMA translation through "dma-ranges" property was needed for other masters than the M4 CPU. stm32f429-disco doesn't use remapping so doesn't need this DMA translation. This patches moves this DMA translation definition from stm32f429 soc file to board files.

ARM: DT: STM32: add dma for usart3 on F429 ------Add DMA support for USART3 on STM32F429 MCU.

ARM: DT: STM32: add dma for usart1 on F429 ------

ARM: dts: Add GPIO irq support to STM32F429 ------

1469 arch\arm\boot\dts\stm32f429.dtsi#0074 1470 arch\arm\boot\dts\stm32f429.dtsi#0135 1471 arch\arm\boot\dts\stm32f429.dtsi#0178 1472 arch\arm\boot\dts\stm32f429.dtsi#0204 1473 arch\arm\boot\dts\stm32f429.dtsi#0214 1474 arch\arm\boot\dts\stm32f429.dtsi#0339 1475 arch\arm\boot\dts\stm32f429.dtsi#0366 1476 arch\arm\boot\dts\stm32f429.dtsi#0400 1477 arch\arm\boot\dts\stm32f429.dtsi#0404 1478 arch\arm\boot\dts\stm32f429.dtsi#0411 1479 arch\arm\boot\dts\stm32f429.dtsi#0416 1480 arch\arm\boot\dts\stm32f469-disco.dts#0067 Repo: 2ecaa477b404 Gabriel Fri Nov 4 09:52:00 2016 +0100 Description: ARM: dts: stm32f429: Add QSPI clock ------This patch adds the QSPI clock for stm32f469 discovery board.

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ARM: DT: stm32: move dma translation to board files ------stm32f469-disco and stm32f429-eval boards use SDRAM start address remapping (to @0) to boost performances. A DMA translation through "dma-ranges" property was needed for other masters than the M4 CPU. stm32f429-disco doesn't use remapping so doesn't need this DMA translation. This patches moves this DMA translation definition from stm32f429 soc file to board files.

1481 arch\arm\boot\dts\stm32f469-disco.dts#0073 1482 arch\arm\boot\dts\sun4i-a10.dtsi#0970 Repo: be7bc6b98781 Maxime Wed Oct 19 11:15:27 2016 +0200 Description: ARM: sunxi: Add the missing clocks to the pinctrl nodes ------The pin controllers also use the two oscillators for debouncing. Add them to the DTs.

ARM: dts: sun4i: Add NFC node to Allwinner A10 SoC ------Add NAND Flash controller node definition to the A10 SoC.

ARM: dts: sun4i: Re-order pinctrl nodes alphabetically ------No functional change. Re-order sun4i pinctrl nodes alphabetically.

ARM: dts: sun4i: HDMI and the tv-encoder use tcon ch1 not ch0 ------Update the simplefb nodes for hdmi / tv-encoder out to point to tcon0_ch1 instead of tcon0_ch0 as tcon clock.

While at it fix the clocks lines being longer than 80 chars.

ARM: sun4i: A10: Add display and TCON clocks ------Enable the display and TCON clocks that are needed to drive the display engine, tcon and TV encoders.

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1483 arch\arm\boot\dts\sun5i-a10s-olinuxino-micro.dts#0253 Repo: 915688621ba4 Maxime Fri Oct 14 16:32:26 2016 +0200 Description: ARM: sun5i: Rename A10s pins ------The SPI2 pins on the sun5i PB bank are only available on the A10s. Rename the A10s only bank so that it doesn't confuse people on the other SoCs whose indexing would start at b.

1484 arch\arm\boot\dts\sun5i-a10s.dtsi#0246 Repo: 915688621ba4 Maxime Fri Oct 14 16:32:26 2016 +0200 Description: ARM: sun5i: Rename A10s pins ------The SPI2 pins on the sun5i PB bank are only available on the A10s. Rename the A10s only bank so that it doesn't confuse people on the other SoCs whose indexing would start at b.

ARM: dts: sun5i: a10s: add spi2 pins ------Used on A10s Olinuxino.

1485 arch\arm\boot\dts\sun5i-a10s.dtsi#0253 1486 arch\arm\boot\dts\sun5i-a13-olinuxino.dts#0075 Repo: 960eb12dc5c0 Maxime Thu May 12 10:23:41 2016 +0200 Description: ARM: sun5i: a13-olinuxino: Enable VGA bridge ------Now that we have support for the VGA bridges using our DRM driver, enable the display engine for the Olimex A13-Olinuxino.

1487 arch\arm\boot\dts\sun5i-a13-olinuxino.dts#0114 1488 arch\arm\boot\dts\sun5i-a13-olinuxino.dts#0255 1489 arch\arm\boot\dts\sun5i-a13-utoo-p66.dts#0086 Repo: 9bfe7c8d1af5 Hans de Wed Nov 16 14:15:08 2016 +0100 Description: ARM: dts: sun5i: Add touchscreen node to reference-design-tablet.dtsi ------Just like on sun8i all sun5i tablets use the same interrupt and power gpios for their touchscreens. I've checked all known a13 fex files and only the UTOO P66 uses a different gpio for the interrupt.

Add a touchscreen node to sun5i-reference-design-tablet.dtsi, which

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fills in the necessary gpios to avoid duplication in the tablet dts files, just like we do in sun8i-reference-design-tablet.dtsi.

This will make future patches adding touchscreen nodes to a13 tablets simpler.

1490 arch\arm\boot\dts\sun5i-a13-utoo-p66.dts#0124 1491 arch\arm\boot\dts\sun5i-a13-utoo-p66.dts#0138 1492 arch\arm\boot\dts\sun5i-gr8-evb.dts#0078 Repo: b9b8daa203d8 Maxime Mon Aug 29 21:59:46 2016 +0200 Description: ARM: gr8: evb: Add i2s codec ------The GR8-EVB comes with a wm8978 codec connected to the i2s bus.

Add a card in order to have it working

ARM: gr8: evb: Enable SPDIF ------The GR8-EVB has a SPDIF out connector. Enable it.

1493 arch\arm\boot\dts\sun5i-gr8.dtsi#0795 Repo: 15df8ad971f4 Maxime Thu Oct 20 09:01:41 2016 +0200 Description: ARM: gr8: Add UART3 pins ------The UART3 pins were missing from the DTSI. Add them.

ARM: gr8: Add UART2 pins ------The UART2 pins were missing from the DTSI. Add them.

ARM: gr8: Add missing pwm channel 1 pin ------The PWM controller has two different channels, but only the first pin was exposed in the DTSI. Add the other one.

ARM: gr8: Fix typo in the i2s mclk pin group ------There was a dumb copy and paste mistake here, fix it.

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ARM: gr8: Add the UART3 ------The GR8 has access to the UART3 controller, which was missing in the DTSI. Add it.

1494 arch\arm\boot\dts\sun5i-gr8.dtsi#0857 1495 arch\arm\boot\dts\sun5i-gr8.dtsi#0884 1496 arch\arm\boot\dts\sun5i-gr8.dtsi#1016 1497 arch\arm\boot\dts\sun5i-r8-chip.dts#0059 Repo: 77df9d66b0b1 Maxime Fri Oct 14 17:39:10 2016 +0200 Description: ARM: sun5i: chip: Add optional buses ------The I2C1 and SPI2 buses are exposed on the CHIP headers, and are not explicitly dedicated to anything.

Add them to the DTS with the muxing already set, but keep them disabled.

ARM: sun5i: chip: add a node for the w1 gpio controller ------The CHIP uses a 1-Wire bus to discover the DIPs. Enable the bus in the DT.

ARM: sun5i: chip: Enable Wi-Fi SDIO chip ------The WiFi chip is powered through a GPIO and two regulators in parallel. Since that case is not supported yet, just set them as always on before we rework the regulator framework to deal with those.

ARM: sun5i: chip: Add status LED ------The CHIP has a status LED connected to one of the AXP GPIOs. Add the gpio-leds node to be able to use the proper LED framework to control it.

ARM: sunxi/dt: make the CHIP inherit from allwinner,sun5i-a13 ------The sun4i-timer driver registers its sched_clock only if the machine is compatible with "allwinner,sun5i-a13", "allwinner,sun5i-a10s" or "allwinner,sun4i-a10". Add the missing "allwinner,sun5i-a13" string to the machine compatible.

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1498 arch\arm\boot\dts\sun5i-r8-chip.dts#0063 1499 arch\arm\boot\dts\sun5i-r8-chip.dts#0079 1500 arch\arm\boot\dts\sun5i-r8-chip.dts#0131 1501 arch\arm\boot\dts\sun5i-r8-chip.dts#0156 1502 arch\arm\boot\dts\sun5i-r8-chip.dts#0164 1503 arch\arm\boot\dts\sun5i-r8-chip.dts#0186 1504 arch\arm\boot\dts\sun5i-r8-chip.dts#0199 1505 arch\arm\boot\dts\sun5i-r8-chip.dts#0233 1506 arch\arm\boot\dts\sun5i-r8-chip.dts#0268 1507 arch\arm\boot\dts\sun5i-reference-design-tablet.dtsi#0044 Repo: 9bfe7c8d1af5 Hans de Wed Nov 16 14:15:08 2016 +0100 Description: ARM: dts: sun5i: Add touchscreen node to reference-design-tablet.dtsi ------Just like on sun8i all sun5i tablets use the same interrupt and power gpios for their touchscreens. I've checked all known a13 fex files and only the UTOO P66 uses a different gpio for the interrupt.

Add a touchscreen node to sun5i-reference-design-tablet.dtsi, which fills in the necessary gpios to avoid duplication in the tablet dts files, just like we do in sun8i-reference-design-tablet.dtsi.

This will make future patches adding touchscreen nodes to a13 tablets simpler.

ARM: dts: sun5i: reference-design-tablet: Remove mention of q8 ------Remove all mention of q8 from sun5i-reference-design-tablet.dtsi.

ARM: dts: sun5i: reference-design-tablet: Set lradc vref to avcc ------Set lradc vref to the actual avcc ldo, rather then to the fixed 3v0 regulator from common-regulators.dtsi.

1508 arch\arm\boot\dts\sun5i-reference-design-tablet.dtsi#0088 1509 arch\arm\boot\dts\sun5i-reference-design-tablet.dtsi#0146

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1510 arch\arm\boot\dts\sun5i.dtsi#0550 Repo: be7bc6b98781 Maxime Wed Oct 19 11:15:27 2016 +0200 Description: ARM: sunxi: Add the missing clocks to the pinctrl nodes ------The pin controllers also use the two oscillators for debouncing. Add them to the DTs.

ARM: sun5i: Add RGB 565 LCD pins ------Some boards use the LCD in RGB565. Enable the pin muxing option.

ARM: sun5i: Add SPI2 pins ------All the sun5i have the SPI2 pins exposed on the PE bank. Add them to the DT.

1511 arch\arm\boot\dts\sun5i.dtsi#0578 1512 arch\arm\boot\dts\sun5i.dtsi#0605 1513 arch\arm\boot\dts\sun6i-a31-hummingbird.dts#0066 Repo: 6b546c2a15f9 Chen-Yu Thu Nov 24 14:43:39 2016 +0800 Description: ARM: dts: sun6i: hummingbird: Enable display engine again ------Now that we disable the display engine by default, we need to re-enable it for the Hummingbird A31, which already had its display pipeline enabled.

ARM: dts: sun6i: hummingbird-a31: Enable display output through VGA bridge ------The Hummingbird A31 board has a VGA DAC which converts RGB output from the LCD interface to VGA analog signals.

Add nodes for the VGA DAC, its power supply, and enable this part of the display pipeline.

ARM: dts: sun6i: hummingbird: Enable internal audio codec ------The Hummingbird A31 has headset and line in audio jacks and an onboard mic routed to the pins for the SoC's internal codec. The line out pins are routed to an onboard speaker amp, whose output is available on a pin header.

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ARM: dts: sun6i: hummingbird: Enable AXP221 DC5LDO regulator as "vdd-cpus" ------The DC5LDO regulator supplies VDD-CPUS, which is for the embedded controller in the A31 SoC.

ARM: dts: sun6i: hummingbird: Use axp22x.dtsi for AXP221 regulators ------Now that we have axp22x.dtsi describing common axp22x hardware, use it and reference the nodes instead of declaring the whole tree.

Also drop the "always-on" from the vdd-gpu regulator, since we don't support the GPU anyway.

And add a regulator reference for cpu0.

1514 arch\arm\boot\dts\sun6i-a31-hummingbird.dts#0126 1515 arch\arm\boot\dts\sun6i-a31-hummingbird.dts#0143 1516 arch\arm\boot\dts\sun6i-a31-hummingbird.dts#0319 1517 arch\arm\boot\dts\sun6i-a31.dtsi#0234 Repo: 205ac7b33e55 Chen-Yu Thu Nov 24 14:43:38 2016 +0800 Description: ARM: dts: sun6i: Disable display pipeline by default ------While we now support the internal display pipeline found on sun6i, it is possible that we are unable to enable the display for some boards, due to a lack of drivers for the panels or bridges found on them. If the display pipeline is enabled, the driver will try to enable, and possibly screw up the simple framebuffer U-boot had configured.

Disable the display pipeline by default.

Fixes: 6d0e5b70be13 ("ARM: dts: sun6i: Add device nodes for first display pipeline")

ARM: sunxi: Add the missing clocks to the pinctrl nodes ------The pin controllers also use the two oscillators for debouncing. Add them to the DTs.

ARM: dts: sun6i: Add audio codec device node ------The A31 SoC includes the Allwinner audio codec, capable of 24-bit playback up to 192 kHz and 24-bit capture up to 48 kHz.

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ARM: dts: sun6i: Add A31 LCD0 RGB888 pins ------The LCD0 controller on the A31 can do RGB output up to 8 bits per channel. Add the pins for RGB888 output.

ARM: dts: sun6i: Add device nodes for first display pipeline ------The A31 has 2 parallel display pipelines, which can be intermixed. However the driver currently only supports one of them.

ARM: dts: sun6i: Sort pinmux setting nodes ------The pinmux setting nodes for the A31 were added out of alphabetical order. Sort them.

1518 arch\arm\boot\dts\sun6i-a31.dtsi#0255 1519 arch\arm\boot\dts\sun6i-a31.dtsi#0475 1520 arch\arm\boot\dts\sun6i-a31.dtsi#0482 1521 arch\arm\boot\dts\sun6i-a31.dtsi#0510 1522 arch\arm\boot\dts\sun6i-a31.dtsi#0545 1523 arch\arm\boot\dts\sun6i-a31.dtsi#0602 1524 arch\arm\boot\dts\sun6i-a31.dtsi#0608 1525 arch\arm\boot\dts\sun6i-a31.dtsi#0789 1526 arch\arm\boot\dts\sun6i-a31.dtsi#0873 1527 arch\arm\boot\dts\sun6i-a31.dtsi#1069 1528 arch\arm\boot\dts\sun6i-a31s-sina31s.dts#0068 Repo: caed8b581578 Chen-Yu Mon Nov 7 18:07:03 2016 +0800 Description: ARM: dts: sun6i: sina31s: Enable internal audio codec ------The SinA31s routes the SoC's LINEOUT pins to a line out jack, and MIC1 to a microphone jack, with MBIAS providing phantom power.

1529 arch\arm\boot\dts\sun6i-a31s.dtsi#0051 Repo: 6d0e5b70be13 Chen-Yu Thu Oct 20 11:43:42 2016 +0800 Description: ARM: dts: sun6i: Add device nodes for first display pipeline ------The A31 has 2 parallel display pipelines, which can be intermixed.

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However the driver currently only supports one of them.

1530 arch\arm\boot\dts\sun6i-a31s.dtsi#0058 1531 arch\arm\boot\dts\sun7i-a20-bananapi-m1-plus.dts#0108 Repo: 82f2e1884eba Chen-Yu Tue Nov 15 21:51:06 2016 +0800 Description: ARM: dts: sun7i: bananapi-m1-plus: Enable USB OTG ------The Bananapi M1+ supports USB OTG, with the PMIC doing VBUS sensing. Enable the USB OTG related functions.

ARM: dts: sun7i: bananapi-m1-plus: Add PMIC regulators ------The Bananapi M1+, like other Allwinner A20 based boards, uses the AXP209 PMIC to supply its power.

Add the AXP209 regulators.

ARM: dts: sun7i: bananapi-m1-plus: Enable USB PHY for USB host support ------The 2 USB host ports are directly tied to the 2 USB hosts in the SoC. The 2 host pairs were already enabled, but the USB PHY wasn't. VBUS on the 2 ports are always on.

Enable the USB PHY.

Fixes: 04c85ecad32a ("ARM: dts: sun7i: Add dts file for Bananapi M1 Plus board")

ARM: dts: sun8i: replace enable-sdio-wakeup with wakeup-source for BananaPi M1+ ------Though the mmc core driver will continue to support the legacy "enable-sdio-wakeup" property to enable SDIO as the wakeup source, "wakeup-source" is the new standard binding.

This patch replaces the legacy "enable-sdio-wakeup" with the unified "wakeup-source" property in order to avoid any further copy-paste duplication.

ARM: dts: sun7i: bananapi-m1-plus: red LED is power LED ------The red led on the Bananapi M1+ is wired to light up as soon as the board is powered, and continues to be lit while the GPIO is floating.

Rename the LED to "pwr", remove the default trigger, and mark it as

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default on.

Also fix the pinmux node that was specifying a different pin for this LED.

ARM: dts: sun7i: bananapi-m1-plus: Unify suffix for board specific labels ------The dts file uses "bananapi" for some labels and "bananapim1plus" for other. Use the shortened "bpi_m1p" suffix for all board specific labels.

1532 arch\arm\boot\dts\sun7i-a20-bananapi-m1-plus.dts#0139 1533 arch\arm\boot\dts\sun7i-a20-bananapi-m1-plus.dts#0142 1534 arch\arm\boot\dts\sun7i-a20-bananapi-m1-plus.dts#0145 1535 arch\arm\boot\dts\sun7i-a20-bananapi-m1-plus.dts#0172 1536 arch\arm\boot\dts\sun7i-a20-bananapi-m1-plus.dts#0197 1537 arch\arm\boot\dts\sun7i-a20-bananapi-m1-plus.dts#0231 1538 arch\arm\boot\dts\sun7i-a20-bananapi-m1-plus.dts#0265 1539 arch\arm\boot\dts\sun7i-a20-olimex-som-evb.dts#0091 Repo: f19802bd4dd1 Emmanuel Sat Oct 15 17:23:40 2016 +0200 Description: ARM: dts: sunxi: Add cpu-supply for Olimex A20 EVB ------sun7i-a20-olimex-som-evb.dts doesn't contain cpu-supply needed for voltage-scaling with cpufreq-dt so define it. The default voltages are defined in sun7i-a20.dtsi.

1540 arch\arm\boot\dts\sun7i-a20-olinuxino-lime2-emmc.dts#0059 Repo: 3116d37651d7 Emmanuel Wed Dec 14 15:57:24 2016 +0100 Description: ARM: dts: sunxi: Change node name for pwrseq pin on Olinuxino-lime2-emmc ------The node name for the power seq pin is mmc2@0 like the mmc2_pins_a one. This makes the original node (mmc2_pins_a) scrapped out of the dtb and result in a unusable eMMC if U-Boot didn't configured the pins to the correct functions.

1541 arch\arm\boot\dts\sun7i-a20.dtsi#1088 Repo: be7bc6b98781 Maxime Wed Oct 19 11:15:27 2016 +0200 Description: ARM: sunxi: Add the missing clocks to the pinctrl nodes ------

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The pin controllers also use the two oscillators for debouncing. Add them to the DTs.

1542 arch\arm\boot\dts\sun8i-a23-a33.dtsi#0269 Repo: be7bc6b98781 Maxime Wed Oct 19 11:15:27 2016 +0200 Description: ARM: sunxi: Add the missing clocks to the pinctrl nodes ------The pin controllers also use the two oscillators for debouncing. Add them to the DTs.

1543 arch\arm\boot\dts\sun8i-a23-a33.dtsi#0579 1544 arch\arm\boot\dts\sun8i-a23-polaroid-mid2407pxe03.dts#0101 Repo: 6a08816d9b78 Hans de Sun Nov 13 20:22:03 2016 +0100 Description: ARM: dts: sun8i: reference-design-tablet: ldo_io1 is vcc-touchscreen ------On some Q8 and other tablets ldo_io1 is used as vcc-touchscreen, config at as such in sun8i-reference-design-tablet.dtsi.

Note that it will only be enabled when it us actually referenced by a foo-supply property in the touchscreen node, so for tablets which do not use ldo_io1 as vcc-touchscreen, it will be disabled.

ARM: dts: sun8i: Add accelerometer to polaroid-mid2407pxe03 ------Add a dt node describing the mma7660 accelerometer on the polaroid-mid2407pxe03 tablet.

1545 arch\arm\boot\dts\sun8i-a33-sinlinx-sina33.dts#0216 Repo: daa4c2603aea Maxime Fri Nov 4 15:44:39 2016 +0100 Description: ARM: sun8i: sina33: Enable USB gadget ------The micro-USB on the SinA33 has a somewhat interesting design in the sense that it has a micro USB connector, but the VBUS is (supposed to be) controlled through an (unpopulated) jumper.

Obviously, that doesn't work really well, and only the peripheral mode really works. Still enable it.

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1546 arch\arm\boot\dts\sun8i-h3-nanopi-neo.dts#0043 Repo: f10239ea378e Milo Kim Fri Oct 28 15:59:02 2016 +0900 Description: ARM: dts: sun8i: Use the common file in NanoPi NEO SBC ------NanoPi common dtsi supports all components of NEO SBC, so just include it.

1547 arch\arm\boot\dts\sun8i-h3-nanopi-neo.dts#0047 1548 arch\arm\boot\dts\sun8i-h3-nanopi-neo.dts#0053 1549 arch\arm\boot\dts\sun8i-h3-nanopi-neo.dts#0079 1550 arch\arm\boot\dts\sun8i-h3.dtsi#0324 Repo: 786a72d79140 Linus Thu Dec 15 15:50:24 2016 -0800 Description: Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or

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industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR

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ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

1551 arch\arm\boot\dts\sun8i-h3.dtsi#0385 1552 arch\arm\boot\dts\sun8i-h3.dtsi#0443 1553 arch\arm\boot\dts\sun8i-h3.dtsi#0618 1554 arch\arm\boot\dts\sun8i-reference-design-tablet.dtsi#0212 Repo: 6a08816d9b78 Hans de Sun Nov 13 20:22:03 2016 +0100 Description: ARM: dts: sun8i: reference-design-tablet: ldo_io1 is vcc-touchscreen ------On some Q8 and other tablets ldo_io1 is used as vcc-touchscreen, config at as such in sun8i-reference-design-tablet.dtsi.

Note that it will only be enabled when it us actually referenced by a foo-supply property in the touchscreen node, so for tablets which do not use ldo_io1 as vcc-touchscreen, it will be disabled.

1555 arch\arm\boot\dts\sun9i-a80-cubieboard4.dts#0079 Repo: e62c46bcdd53 Chen-Yu Fri Oct 28 18:11:54 2016 +0800 Description: ARM: dts: sun9i: cubieboard4: Enable AP6330 WiFi ------The board has a Ampak AP6330 WiFi/BT/FM module. Inside it is a Broadcom BCM4330 WiFi/BT/FM combo IC. The WiFi portion is connected to mmc1, with the enabling pin connected to PL2. The AC100 RTC provides a low power clock signal.

ARM: dts: sun9i: cubieboard4: Add AXP806 PMIC device node and regulators ------The AXP806 PMIC is the secondary PMIC. It provides various supply voltages for the SoC and other peripherals. The PMIC's interrupt line is connected to NMI pin of the SoC.

1556 arch\arm\boot\dts\sun9i-a80-cubieboard4.dts#0099 1557 arch\arm\boot\dts\sun9i-a80-cubieboard4.dts#0154 1558 arch\arm\boot\dts\sun9i-a80-optimus.dts#0108 Repo: 6cf4eaef12f1 Chen-Yu Fri Oct 28 18:11:53 2016 +0800 Description: ARM: dts: sun9i: a80-optimus: Enable AP6330 WiFi

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------The board has a Ampak AP6330 WiFi/BT/FM module. Inside it is a Broadcom BCM4330 WiFi/BT/FM combo IC. The WiFi portion is connected to mmc1, with the enabling pin connected to PL2. The AC100 RTC provides a low power clock signal.

ARM: dts: sun9i: a80-optimus: Disable EHCI1 ------EHCI1 provides an HSIC interface. This interface is exposed on the board through two pins among the GPIO header.

With the PHY now powered up and responding, enabling the interface when nothing is connected results in a lot of error messages:

usb 2-1: device descriptor read/64, error -71 usb 2-1: device descriptor read/64, error -71 usb 2-1: new high-speed USB device number 3 using ehci-platform usb 2-1: device descriptor read/64, error -71 usb 2-1: device descriptor read/64, error -71 usb 2-1: new high-speed USB device number 4 using ehci-platform usb 2-1: device not accepting address 4, error -71 usb 2-1: new high-speed USB device number 5 using ehci-platform usb 2-1: device not accepting address 5, error -71 usb usb2-port1: unable to enumerate USB device

Disable it by default, but leave the entries in the board DTS.

ARM: dts: sun9i: a80-optimus: Add AXP806 PMIC device node and regulators ------The AXP806 PMIC is the secondary PMIC. It provides various supply voltages for the SoC and other peripherals. The PMIC's interrupt line is connected to NMI pin of the SoC.

1559 arch\arm\boot\dts\sun9i-a80-optimus.dts#0141 1560 arch\arm\boot\dts\sun9i-a80-optimus.dts#0225 1561 arch\arm\boot\dts\sun9i-a80.dtsi#0681 Repo: be7bc6b98781 Maxime Wed Oct 19 11:15:27 2016 +0200 Description: ARM: sunxi: Add the missing clocks to the pinctrl nodes ------The pin controllers also use the two oscillators for debouncing. Add them to the DTs.

ARM: dts: sun9i: Add mmc1 pinmux setting

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------On the A80, mmc1 is available on pingroup G. Designs mostly use this to connect to an SDIO WiFi chip.

1562 arch\arm\boot\dts\sun9i-a80.dtsi#0704 1563 arch\arm\boot\dts\sun9i-a80.dtsi#0906 1564 arch\arm\boot\dts\tegra124-apalis.dtsi#1598 Repo: 5e8a724d1433 Thierry Mon Nov 7 14:46:59 2016 +0100 Description: ARM: tegra: apalis-tk1: Drop leading 0 from unit-address ------According to the latest best practices, unit-addresses should be represented without any leading zeroes.

1565 arch\arm\boot\dts\tegra124-nyan.dtsi#0045 Repo: 5d831dd5e2ee Paul Sun Sep 18 16:13:11 2016 +0200 Description: ARM: tegra: nyan: Enable GPU node and related supply ------This enables the GPU node for tegra124 nyan boards, which is required to get graphics acceleration with nouveau on these devices.

1566 arch\arm\boot\dts\tegra124-nyan.dtsi#0223 1567 arch\arm\boot\dts\tegra20.dtsi#0379 Repo: c1700644dd38 Mirza Krak Mon Nov 7 09:30:04 2016 +0100 Description: ARM: tegra: Add Tegra20 GMI support ------Add a device node for the GMI controller found on Tegra20.

ARM: tegra: Correct interrupt type for ARM TWD ------The ARM TWD interrupt is a private peripheral interrupt (PPI) and per the ARM GIC documentation, whether the type for PPIs can be set is IMPLEMENTATION DEFINED. For Tegra20/30 devices the PPI type cannot be set and so when we attempt to set the type for the ARM TWD interrupt it fails. This has gone unnoticed because it fails silently and because we cannot re-configure the type it has had no impact. Nevertheless fix the type for the TWD interrupt so that it matches the hardware configuration.

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1568 arch\arm\boot\dts\tegra30-apalis.dtsi#0051 Repo: 8948e7468ab9 Marcel Sun Jun 19 03:00:01 2016 +0200 Description: ARM: tegra: apalis/colibri t30: Integrate audio ------Integrate Freescale SGTL5000 analogue audio codec support.

ARM: tegra: Add spaces around = in properties ------This seems to have been copied and pasted since the beginning of time, though only until Tegra124, likely because that DT was written from scratch or it was fixed along the way.

1569 arch\arm\boot\dts\tegra30-apalis.dtsi#0450 1570 arch\arm\boot\dts\tegra30-apalis.dtsi#0690 1571 arch\arm\boot\dts\tegra30-apalis.dtsi#0769 1572 arch\arm\boot\dts\tegra30-colibri.dtsi#0032 Repo: 8948e7468ab9 Marcel Sun Jun 19 03:00:01 2016 +0200 Description: ARM: tegra: apalis/colibri t30: Integrate audio ------Integrate Freescale SGTL5000 analogue audio codec support.

1573 arch\arm\boot\dts\tegra30-colibri.dtsi#0228 1574 arch\arm\boot\dts\tegra30-colibri.dtsi#0426 1575 arch\arm\boot\dts\tegra30-colibri.dtsi#0507 1576 arch\arm\boot\dts\tegra30.dtsi#0442 Repo: 5e35c1f037ce Mirza Krak Mon Nov 7 09:30:03 2016 +0100 Description: ARM: tegra: Add Tegra30 GMI support ------Add a device node for the GMI controller found on Tegra30.

ARM: tegra: Correct interrupt type for ARM TWD ------The ARM TWD interrupt is a private peripheral interrupt (PPI) and per the ARM GIC documentation, whether the type for PPIs can be set is IMPLEMENTATION DEFINED. For Tegra20/30 devices the PPI type cannot be set and so when we attempt to set the type for the ARM TWD interrupt it fails. This has gone unnoticed because it fails silently and because we cannot re-configure the type it has had no impact. Nevertheless fix the type for the TWD interrupt so that it matches the hardware configuration.

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1577 arch\arm\boot\dts\tps65217.dtsi#0016 Repo: e598c4418097 Milo Kim Fri Oct 28 21:36:57 2016 +0900 Description: ARM: dts: tps65217: Add the power button device ------Support the power button driver and disable it by default.

ARM: dts: tps65217: Add the charger device ------Support the charger driver and disable it by default.

ARM: dts: tps65217: Specify the interrupt controller ------TPS65217 MFD driver supports the IRQ domain to handle the charger input interrupts and push button status event. The interrupt controller enables corresponding IRQ handling in the charger[*] and power button driver[**].

[*] drivers/power/supply/tps65217_charger.c [**] drivers/input/misc/tps65218-pwrbutton.c

1578 arch\arm\boot\dts\tps65217.dtsi#0019 1579 arch\arm\boot\dts\uniphier-common32.dtsi#fileDeleted Repo: 2752bcaa1a94 Masahiro Mon Oct 31 16:29:24 2016 +0900 Description: ARM: dts: uniphier: make 32bit SoC DTSI linear ------I notice some mistakes in the SoC DTSI; wrong interrupts properties of timer nodes, mismatch between the node name and the compatible for sdctrl block. Given those problems fixed, the common parts among SoCs are less than I had first expected. The more and more property overrides are making the SoC DTSI unreadable.

Stretch out the SoC DTSI files and fix the following:

- Fix the 3rd cell of the interrupts property of the timer nodes for Pro4, Pro5, PXs2

- Fix the node name mioctrl to sdctrl for Pro5, PXs2

- Fix the second region of l2 node for PXs2

ARM: dts: uniphier: increase register region size of sysctrl node ------The System Control node has 0x10000 byte of registers. The current reg size must be expanded to use the cpufreq driver because the

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registers controlling CPU frequency are located at offset 0x8000.

ARM: dts: uniphier: add specific compatible to SoC-Glue node ------This is a simple MFD, but add a specific compatible just in case.

1580 arch\arm\boot\dts\uniphier-ld4.dtsi#0046 Repo: 2752bcaa1a94 Masahiro Mon Oct 31 16:29:24 2016 +0900 Description: ARM: dts: uniphier: make 32bit SoC DTSI linear ------I notice some mistakes in the SoC DTSI; wrong interrupts properties of timer nodes, mismatch between the node name and the compatible for sdctrl block. Given those problems fixed, the common parts among SoCs are less than I had first expected. The more and more property overrides are making the SoC DTSI unreadable.

Stretch out the SoC DTSI files and fix the following:

- Fix the 3rd cell of the interrupts property of the timer nodes for Pro4, Pro5, PXs2

- Fix the node name mioctrl to sdctrl for Pro5, PXs2

- Fix the second region of l2 node for PXs2

ARM: dts: uniphier: use clock/reset controllers ------The UniPhier reset controller driver has been merged. Enable it. Also, replace the fixed-rate clocks with the dedicated clock drivers.

ARM: dts: uniphier: switch over to PSCI ------Use PSCI for enable-method instead of SoC specific implementation.

1581 arch\arm\boot\dts\uniphier-ld4.dtsi#0064 1582 arch\arm\boot\dts\uniphier-ld4.dtsi#0070 1583 arch\arm\boot\dts\uniphier-ld4.dtsi#0082

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1584 arch\arm\boot\dts\uniphier-ld4.dtsi#0083 1585 arch\arm\boot\dts\uniphier-ld4.dtsi#0090 1586 arch\arm\boot\dts\uniphier-ld4.dtsi#0098 1587 arch\arm\boot\dts\uniphier-ld4.dtsi#0111 1588 arch\arm\boot\dts\uniphier-ld4.dtsi#0124 1589 arch\arm\boot\dts\uniphier-ld4.dtsi#0137 1590 arch\arm\boot\dts\uniphier-ld4.dtsi#0148 1591 arch\arm\boot\dts\uniphier-ld4.dtsi#0159 1592 arch\arm\boot\dts\uniphier-ld4.dtsi#0170 1593 arch\arm\boot\dts\uniphier-ld4.dtsi#0172 1594 arch\arm\boot\dts\uniphier-ld4.dtsi#0181 1595 arch\arm\boot\dts\uniphier-ld4.dtsi#0194 1596 arch\arm\boot\dts\uniphier-ld4.dtsi#0204 1597 arch\arm\boot\dts\uniphier-ld4.dtsi#0209 1598 arch\arm\boot\dts\uniphier-ld4.dtsi#0214 1599 arch\arm\boot\dts\uniphier-ld4.dtsi#0219 1600 arch\arm\boot\dts\uniphier-ld4.dtsi#0225 1601 arch\arm\boot\dts\uniphier-ld4.dtsi#0230 1602 arch\arm\boot\dts\uniphier-ld4.dtsi#0326 1603 arch\arm\boot\dts\uniphier-pro4.dtsi#0046 Repo: 2752bcaa1a94 Masahiro Mon Oct 31 16:29:24 2016 +0900 Description: ARM: dts: uniphier: make 32bit SoC DTSI linear ------I notice some mistakes in the SoC DTSI; wrong interrupts properties of timer nodes, mismatch between the node name and the compatible for sdctrl block. Given those problems fixed, the common parts among SoCs are less than I had first expected. The more and more property overrides are making the SoC DTSI unreadable.

Stretch out the SoC DTSI files and fix the following:

- Fix the 3rd cell of the interrupts property of the timer nodes for Pro4, Pro5, PXs2

- Fix the node name mioctrl to sdctrl for Pro5, PXs2

- Fix the second region of l2 node for PXs2

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ARM: dts: uniphier: use clock/reset controllers ------The UniPhier reset controller driver has been merged. Enable it. Also, replace the fixed-rate clocks with the dedicated clock drivers.

ARM: dts: uniphier: switch over to PSCI ------Use PSCI for enable-method instead of SoC specific implementation.

1604 arch\arm\boot\dts\uniphier-pro4.dtsi#0072 1605 arch\arm\boot\dts\uniphier-pro4.dtsi#0078 1606 arch\arm\boot\dts\uniphier-pro4.dtsi#0090 1607 arch\arm\boot\dts\uniphier-pro4.dtsi#0091 1608 arch\arm\boot\dts\uniphier-pro4.dtsi#0098 1609 arch\arm\boot\dts\uniphier-pro4.dtsi#0106 1610 arch\arm\boot\dts\uniphier-pro4.dtsi#0119 1611 arch\arm\boot\dts\uniphier-pro4.dtsi#0132 1612 arch\arm\boot\dts\uniphier-pro4.dtsi#0145 1613 arch\arm\boot\dts\uniphier-pro4.dtsi#0147 1614 arch\arm\boot\dts\uniphier-pro4.dtsi#0158 1615 arch\arm\boot\dts\uniphier-pro4.dtsi#0169 1616 arch\arm\boot\dts\uniphier-pro4.dtsi#0180 1617 arch\arm\boot\dts\uniphier-pro4.dtsi#0192 1618 arch\arm\boot\dts\uniphier-pro4.dtsi#0202 1619 arch\arm\boot\dts\uniphier-pro4.dtsi#0204 1620 arch\arm\boot\dts\uniphier-pro4.dtsi#0215 1621 arch\arm\boot\dts\uniphier-pro4.dtsi#0226 1622 arch\arm\boot\dts\uniphier-pro4.dtsi#0236 1623 arch\arm\boot\dts\uniphier-pro4.dtsi#0241

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1624 arch\arm\boot\dts\uniphier-pro4.dtsi#0246 1625 arch\arm\boot\dts\uniphier-pro4.dtsi#0346 1626 arch\arm\boot\dts\uniphier-pro5.dtsi#0046 Repo: 2752bcaa1a94 Masahiro Mon Oct 31 16:29:24 2016 +0900 Description: ARM: dts: uniphier: make 32bit SoC DTSI linear ------I notice some mistakes in the SoC DTSI; wrong interrupts properties of timer nodes, mismatch between the node name and the compatible for sdctrl block. Given those problems fixed, the common parts among SoCs are less than I had first expected. The more and more property overrides are making the SoC DTSI unreadable.

Stretch out the SoC DTSI files and fix the following:

- Fix the 3rd cell of the interrupts property of the timer nodes for Pro4, Pro5, PXs2

- Fix the node name mioctrl to sdctrl for Pro5, PXs2

- Fix the second region of l2 node for PXs2

ARM: dts: uniphier: add CPU clocks and OPP table for Pro5 SoC ------Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver.

1627 arch\arm\boot\dts\uniphier-pro5.dtsi#0059 1628 arch\arm\boot\dts\uniphier-pro5.dtsi#0062 1629 arch\arm\boot\dts\uniphier-pro5.dtsi#0069 1630 arch\arm\boot\dts\uniphier-pro5.dtsi#0072 1631 arch\arm\boot\dts\uniphier-pro5.dtsi#0076 1632 arch\arm\boot\dts\uniphier-pro5.dtsi#0152 1633 arch\arm\boot\dts\uniphier-pro5.dtsi#0164 1634 arch\arm\boot\dts\uniphier-pro5.dtsi#0165 1635 arch\arm\boot\dts\uniphier-pro5.dtsi#0172 1636 arch\arm\boot\dts\uniphier-pro5.dtsi#0185

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1637 arch\arm\boot\dts\uniphier-pro5.dtsi#0197 1638 arch\arm\boot\dts\uniphier-pro5.dtsi#0207 1639 arch\arm\boot\dts\uniphier-pro5.dtsi#0217 1640 arch\arm\boot\dts\uniphier-pro5.dtsi#0227 1641 arch\arm\boot\dts\uniphier-pro5.dtsi#0237 1642 arch\arm\boot\dts\uniphier-pro5.dtsi#0250 1643 arch\arm\boot\dts\uniphier-pro5.dtsi#0263 1644 arch\arm\boot\dts\uniphier-pro5.dtsi#0276 1645 arch\arm\boot\dts\uniphier-pro5.dtsi#0289 1646 arch\arm\boot\dts\uniphier-pro5.dtsi#0291 1647 arch\arm\boot\dts\uniphier-pro5.dtsi#0302 1648 arch\arm\boot\dts\uniphier-pro5.dtsi#0313 1649 arch\arm\boot\dts\uniphier-pro5.dtsi#0323 1650 arch\arm\boot\dts\uniphier-pro5.dtsi#0328 1651 arch\arm\boot\dts\uniphier-pro5.dtsi#0409 1652 arch\arm\boot\dts\uniphier-pxs2.dtsi#0046 Repo: 2752bcaa1a94 Masahiro Mon Oct 31 16:29:24 2016 +0900 Description: ARM: dts: uniphier: make 32bit SoC DTSI linear ------I notice some mistakes in the SoC DTSI; wrong interrupts properties of timer nodes, mismatch between the node name and the compatible for sdctrl block. Given those problems fixed, the common parts among SoCs are less than I had first expected. The more and more property overrides are making the SoC DTSI unreadable.

Stretch out the SoC DTSI files and fix the following:

- Fix the 3rd cell of the interrupts property of the timer nodes for Pro4, Pro5, PXs2

- Fix the node name mioctrl to sdctrl for Pro5, PXs2

- Fix the second region of l2 node for PXs2

ARM: dts: uniphier: add CPU clocks and OPP table for PXs2 SoC ------Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver.

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1653 arch\arm\boot\dts\uniphier-pxs2.dtsi#0059 1654 arch\arm\boot\dts\uniphier-pxs2.dtsi#0062 1655 arch\arm\boot\dts\uniphier-pxs2.dtsi#0069 1656 arch\arm\boot\dts\uniphier-pxs2.dtsi#0072 1657 arch\arm\boot\dts\uniphier-pxs2.dtsi#0079 1658 arch\arm\boot\dts\uniphier-pxs2.dtsi#0082 1659 arch\arm\boot\dts\uniphier-pxs2.dtsi#0089 1660 arch\arm\boot\dts\uniphier-pxs2.dtsi#0092 1661 arch\arm\boot\dts\uniphier-pxs2.dtsi#0096 1662 arch\arm\boot\dts\uniphier-pxs2.dtsi#0140 1663 arch\arm\boot\dts\uniphier-pxs2.dtsi#0152 1664 arch\arm\boot\dts\uniphier-pxs2.dtsi#0153 1665 arch\arm\boot\dts\uniphier-pxs2.dtsi#0156 1666 arch\arm\boot\dts\uniphier-pxs2.dtsi#0160 1667 arch\arm\boot\dts\uniphier-pxs2.dtsi#0172 1668 arch\arm\boot\dts\uniphier-pxs2.dtsi#0182 1669 arch\arm\boot\dts\uniphier-pxs2.dtsi#0192 1670 arch\arm\boot\dts\uniphier-pxs2.dtsi#0202 1671 arch\arm\boot\dts\uniphier-pxs2.dtsi#0212 1672 arch\arm\boot\dts\uniphier-pxs2.dtsi#0225 1673 arch\arm\boot\dts\uniphier-pxs2.dtsi#0238 1674 arch\arm\boot\dts\uniphier-pxs2.dtsi#0251 1675 arch\arm\boot\dts\uniphier-pxs2.dtsi#0264 1676 arch\arm\boot\dts\uniphier-pxs2.dtsi#0275 1677 arch\arm\boot\dts\uniphier-pxs2.dtsi#0286 1678 arch\arm\boot\dts\uniphier-pxs2.dtsi#0297 1679 arch\arm\boot\dts\uniphier-pxs2.dtsi#0307 1680 arch\arm\boot\dts\uniphier-pxs2.dtsi#0393 1681 arch\arm\boot\dts\uniphier-sld3.dtsi#0138 Repo: 13b4a6190b25 Masahiro Sat Nov 5 16:28:26 2016 +0900 Description: ARM: dts: uniphier: make compatible of syscon nodes SoC-specific ------

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These hardware blocks are SoC-specific, so their compatible strings should be SoC-specific as well. This change has no impact on the actual behavior since it is controlled by the generic "simple-mfd", "syscon" compatible strings.

ARM: dts: uniphier: add clocks/resets to EHCI nodes of sLD3 SoC ------Now, the clock/reset controller driver is available for this SoC.

ARM: dts: uniphier: remove redundant serial fifo-size properties ------These are the default of the optional property. No need to describe them explicitly.

ARM: dts: uniphier: increase register region size of sysctrl node ------The System Control node has 0x10000 byte of registers. The current reg size must be expanded to use the cpufreq driver because the registers controlling CPU frequency are located at offset 0x8000.

ARM: dts: uniphier: use clock/reset controllers ------The UniPhier reset controller driver has been merged. Enable it. Also, replace the fixed-rate clocks with the dedicated clock drivers.

ARM: dts: uniphier: switch over to PSCI ------Use PSCI for enable-method instead of SoC specific implementation.

1682 arch\arm\boot\dts\uniphier-sld3.dtsi#0147 1683 arch\arm\boot\dts\uniphier-sld3.dtsi#0156 1684 arch\arm\boot\dts\uniphier-sld3.dtsi#0228 1685 arch\arm\boot\dts\uniphier-sld3.dtsi#0248 1686 arch\arm\boot\dts\uniphier-sld3.dtsi#0255 1687 arch\arm\boot\dts\uniphier-sld3.dtsi#0265 1688 arch\arm\boot\dts\uniphier-sld3.dtsi#0275

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1689 arch\arm\boot\dts\uniphier-sld3.dtsi#0281 1690 arch\arm\boot\dts\uniphier-sld3.dtsi#0283 1691 arch\arm\boot\dts\uniphier-sld8.dtsi#0046 Repo: 2752bcaa1a94 Masahiro Mon Oct 31 16:29:24 2016 +0900 Description: ARM: dts: uniphier: make 32bit SoC DTSI linear ------I notice some mistakes in the SoC DTSI; wrong interrupts properties of timer nodes, mismatch between the node name and the compatible for sdctrl block. Given those problems fixed, the common parts among SoCs are less than I had first expected. The more and more property overrides are making the SoC DTSI unreadable.

Stretch out the SoC DTSI files and fix the following:

- Fix the 3rd cell of the interrupts property of the timer nodes for Pro4, Pro5, PXs2

- Fix the node name mioctrl to sdctrl for Pro5, PXs2

- Fix the second region of l2 node for PXs2

ARM: dts: uniphier: use clock/reset controllers ------The UniPhier reset controller driver has been merged. Enable it. Also, replace the fixed-rate clocks with the dedicated clock drivers.

ARM: dts: uniphier: switch over to PSCI ------Use PSCI for enable-method instead of SoC specific implementation.

1692 arch\arm\boot\dts\uniphier-sld8.dtsi#0064 1693 arch\arm\boot\dts\uniphier-sld8.dtsi#0070 1694 arch\arm\boot\dts\uniphier-sld8.dtsi#0082 1695 arch\arm\boot\dts\uniphier-sld8.dtsi#0083 1696 arch\arm\boot\dts\uniphier-sld8.dtsi#0090 1697 arch\arm\boot\dts\uniphier-sld8.dtsi#0098

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1698 arch\arm\boot\dts\uniphier-sld8.dtsi#0111 1699 arch\arm\boot\dts\uniphier-sld8.dtsi#0124 1700 arch\arm\boot\dts\uniphier-sld8.dtsi#0137 1701 arch\arm\boot\dts\uniphier-sld8.dtsi#0148 1702 arch\arm\boot\dts\uniphier-sld8.dtsi#0159 1703 arch\arm\boot\dts\uniphier-sld8.dtsi#0171 1704 arch\arm\boot\dts\uniphier-sld8.dtsi#0175 1705 arch\arm\boot\dts\uniphier-sld8.dtsi#0181 1706 arch\arm\boot\dts\uniphier-sld8.dtsi#0194 1707 arch\arm\boot\dts\uniphier-sld8.dtsi#0204 1708 arch\arm\boot\dts\uniphier-sld8.dtsi#0209 1709 arch\arm\boot\dts\uniphier-sld8.dtsi#0214 1710 arch\arm\boot\dts\uniphier-sld8.dtsi#0219 1711 arch\arm\boot\dts\uniphier-sld8.dtsi#0225 1712 arch\arm\boot\dts\uniphier-sld8.dtsi#0326 1713 arch\arm\boot\dts\vexpress-v2p-ca15-tc1.dts#0084 Repo: 368400e242dc Christoffer Sat Dec 10 21:13:51 2016 +0100 Description: ARM: dts: vexpress: Support GICC_DIR operations ------The GICv2 CPU interface registers span across 8K, not 4K as indicated in the DT. Only the GICC_DIR register is located after the initial 4K boundary, leaving a functional system but without support for separately EOI'ing and deactivating interrupts.

After this change the system supports split priority drop and interrupt deactivation.

ARM: dts: vexpress: Add external expansion bus to DT ------The VExpress development platform has an external expansion bus which can be used for additional hardware (e.g. LogicTile Express daughter boards).

Add this bus to the VExpress CoreTile device-trees.The bus is described for a CoreTile occupying site 1.

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1714 arch\arm\boot\dts\vexpress-v2p-ca15_a7.dts#0042 Repo: 368400e242dc Christoffer Sat Dec 10 21:13:51 2016 +0100 Description: ARM: dts: vexpress: Support GICC_DIR operations ------The GICv2 CPU interface registers span across 8K, not 4K as indicated in the DT. Only the GICC_DIR register is located after the initial 4K boundary, leaving a functional system but without support for separately EOI'ing and deactivating interrupts.

After this change the system supports split priority drop and interrupt deactivation.

ARM: dts: vexpress: add TC2 cpu capacity-dmips-mhz information ------Add TC2 cpu capacity information.

ARM: dts: vexpress: Add external expansion bus to DT ------The VExpress development platform has an external expansion bus which can be used for additional hardware (e.g. LogicTile Express daughter boards).

Add this bus to the VExpress CoreTile device-trees.The bus is described for a CoreTile occupying site 1.

1715 arch\arm\boot\dts\vexpress-v2p-ca15_a7.dts#0051 1716 arch\arm\boot\dts\vexpress-v2p-ca15_a7.dts#0060 1717 arch\arm\boot\dts\vexpress-v2p-ca15_a7.dts#0069 1718 arch\arm\boot\dts\vexpress-v2p-ca15_a7.dts#0078 1719 arch\arm\boot\dts\vexpress-v2p-ca15_a7.dts#0134 1720 arch\arm\boot\dts\vf-colibri.dtsi#0111 Repo: 14c416336820 Sanchayan Mon Oct 3 18:20:37 2016 +0530 Description: ARM: dts: vfxxx: Enable DMA for DSPI on Vybrid ------Enable DMA for DSPI on Vybrid.

1721 arch\arm\boot\dts\vf610-zii-dev-rev-b.dts#0091 Repo: 4c51de4570d6 Andreas Sun Nov 27 20:54:44 2016 +0100 Description: ARM: dts: vf610-zii-dev-rev-b: Add missing newline

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------Found while reviewing Marvell dsa bindings usage.

Fixes: f283745b3caf ("arm: vf610: zii devel b: Add support for switch interrupts")

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6)

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- Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

ARM: dts: vf610-zii-dev-rev-b: Remove I2C3 ------I2C3 bus was only brought out in revision A1 of the board and revision B1 only brings out 3 I2C busses (I2C0, I2C1 and I2C2).

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arm: vf610: zii devel b: Add support for switch interrupts ------The Switches use GPIO lines to indicate interrupts from two of the switches.

With these interrupts in place, we can make use of the interrupt controllers within the switch to indicate when the internal PHYs generate an interrupt. Use standard PHY properties to do this.

1722 arch\arm\boot\dts\vf610-zii-dev-rev-b.dts#0097 1723 arch\arm\boot\dts\vf610-zii-dev-rev-b.dts#0108 1724 arch\arm\boot\dts\vf610-zii-dev-rev-b.dts#0114 1725 arch\arm\boot\dts\vf610-zii-dev-rev-b.dts#0120 1726 arch\arm\boot\dts\vf610-zii-dev-rev-b.dts#0145 1727 arch\arm\boot\dts\vf610-zii-dev-rev-b.dts#0174 1728 arch\arm\boot\dts\vf610-zii-dev-rev-b.dts#0180 1729 arch\arm\boot\dts\vf610-zii-dev-rev-b.dts#0233 1730 arch\arm\boot\dts\vf610-zii-dev-rev-b.dts#0238 1731 arch\arm\boot\dts\vf610-zii-dev-rev-b.dts#0243 1732 arch\arm\boot\dts\vf610-zii-dev-rev-b.dts#0542 1733 arch\arm\boot\dts\vf610-zii-dev-rev-b.dts#0672 1734 arch\arm\boot\dts\vf610-zii-dev-rev-b.dts#0711 1735 arch\arm\boot\dts\vfxxx.dtsi#0197 Repo: 4743ced99130 Sanchayan Mon Nov 14 18:07:01 2016 +0530 Description: ARM: dts: vfxxx: Enable DMA for DSPI2 and DSPI3 ------Enable DMA for DSPI2 and DSPI3 on Vybrid.

ARM: dts: vfxxx: Enable DMA for DSPI on Vybrid ------Enable DMA for DSPI on Vybrid.

ARM: dts: vfxxx: Add node corresponding to OCOTP ------Add node corresponding to OCOTP IP block.

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1736 arch\arm\boot\dts\vfxxx.dtsi#0212 1737 arch\arm\boot\dts\vfxxx.dtsi#0529 1738 arch\arm\boot\dts\vfxxx.dtsi#0576 1739 arch\arm\boot\dts\vfxxx.dtsi#0591 1740 arch\arm\boot\dts\zynq-7000.dtsi#0013 Repo: 995966ccde55 Michal SimekWed Nov 16 09:29:57 2016 +0100 Description: ARM: zynq: Fix pmu register description coding style ------Drop the space before/after '<' and '>'; and separate the entries to be a bit more readable.

ARM: zynq: Fix W=1 dtc 1.4 warnings ------The patch removes these warnings reported by dtc 1.4: Warning (unit_address_vs_reg): Node /pmu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

ARM: zynq: Remove skeleton.dtsi ------Based on "ARM: dts: explicitly mark skeleton.dtsi as deprecated" (sha1: 9c0da3cc61f1233c2782e2d3d91e3d0707dd4ba5) skeleton.dtsi is deprecated. Move address and size-cells directly to zynq-7000.dtsi.

ARM: dt: zynq: Add labels to cpu nodes to allow overriding OPPs. ------By adding labels to the cpu nodes in the dtsi, a dts that includes it can change the OPPs by referencing the cpu0 through the label.

ARM: dts: zynq: describe SLCR as simple-mfd rather than simple-bus ------The SLCR (System-Level Control Registers) block is an MFD (Multi Function Device) rather than a bus.

"simple-mfd" seems a more suitable compatible string than "simple-bus".

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1741 arch\arm\boot\dts\zynq-7000.dtsi#0016 1742 arch\arm\boot\dts\zynq-7000.dtsi#0045 1743 arch\arm\boot\dts\zynq-7000.dtsi#0049 1744 arch\arm\boot\dts\zynq-7000.dtsi#0053 1745 arch\arm\boot\dts\zynq-parallella.dts#0031 Repo: da457d57594b Michal SimekTue Nov 15 15:02:18 2016 +0100 Description: ARM: zynq: Fix W=1 dtc 1.4 warnings ------The patch removes these warnings reported by dtc 1.4: Warning (unit_address_vs_reg): Node /pmu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

1746 arch\arm\boot\dts\zynq-zc702.dts#0027 Repo: da457d57594b Michal SimekTue Nov 15 15:02:18 2016 +0100 Description: ARM: zynq: Fix W=1 dtc 1.4 warnings ------The patch removes these warnings reported by dtc 1.4: Warning (unit_address_vs_reg): Node /pmu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

1747 arch\arm\boot\dts\zynq-zc706.dts#0027 Repo: da457d57594b Michal SimekTue Nov 15 15:02:18 2016 +0100 Description: ARM: zynq: Fix W=1 dtc 1.4 warnings ------The patch removes these warnings reported by dtc 1.4: Warning (unit_address_vs_reg): Node /pmu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

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1748 arch\arm\boot\dts\zynq-zed.dts#0026 Repo: da457d57594b Michal SimekTue Nov 15 15:02:18 2016 +0100 Description: ARM: zynq: Fix W=1 dtc 1.4 warnings ------The patch removes these warnings reported by dtc 1.4: Warning (unit_address_vs_reg): Node /pmu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

1749 arch\arm\boot\dts\zynq-zybo.dts#0026 Repo: da457d57594b Michal SimekTue Nov 15 15:02:18 2016 +0100 Description: ARM: zynq: Fix W=1 dtc 1.4 warnings ------The patch removes these warnings reported by dtc 1.4: Warning (unit_address_vs_reg): Node /pmu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

1750 arch\arm\boot\dts\am571x-idk.dts#newFile Repo: 10d27dfaf6b6 Roger Mon Dec 12 11:58:04 2016 +0200 Description: ARM: dts: am57xx-idk: Support VBUS detection on USB2 port ------VBUS detection is available on the board via the palmas PMIC. Use extcon-palmas driver instead of extcon-gpio-usb driver.

1751 arch\arm\boot\dts\armada-385-turris-omnia.dts#newFile Repo: 26ca8b52d6e1 Uwe Kleine- Fri Nov 25 15:26:58 2016 +0100 Description: ARM: dts: add support for Turris Omnia ------This machine is an open hardware router by cz.nic driven by a Marvell Armada 385.

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1752 arch\arm\boot\dts\bcm4708-luxul-xap-1510.dts#newFile Repo: fe91846397ca Dan Haab Tue Sep 27 11:27:10 2016 -0600 Description: ARM: BCM5301X: Add DT for Luxul XAP-1510 ------Luxul XAP-1510 is an AP device based on BCM4708 SoC with 2 x BCM4360 chipsets on PCB connected using PCIe.

1753 arch\arm\boot\dts\bcm4709-tplink-archer-c9-v1.dts#newFile Repo: 41182beb217c Rafa Miecki Sun Nov 13 11:12:09 2016 +0100 Description: ARM: BCM5301X: Add DT for TP-LINK Archer C9 V1 ------It's BCM4709A0 based device with 16 MiB flash, 128 MiB of RAM and two PCIe based on-PCB BCM4360 chipsets.

1754 arch\arm\boot\dts\bcm4709.dtsi#newFile Repo: fa87b008da3f Rafa Miecki Wed Sep 21 22:58:33 2016 +0200 Description: ARM: BCM5301X: Enable UART on Netgear R8000 ------It was tested by LEDE users, all we need is to adjust clock frequency. While we're at it create a separated DTS include file to share code with other BCM4709 devices easier.

1755 arch\arm\boot\dts\bcm47094-luxul-xwr-3100.dts#newFile Repo: 4335e6fd58b8 Dan Haab Tue Sep 27 11:27:11 2016 -0600 Description: ARM: BCM5301X: Add DT for Luxul XWR-3100 ------Luxul XWR-3100 is a wireless router based on BCM47094 SoC with two 4366c0 FullMAC PCIe cards on the PCB. It uses NAND with BCH-4 ECC algorithm.

1756 arch\arm\boot\dts\bcm47094-netgear-r8500.dts#newFile Repo: 54b902a4cd02 Rafa Miecki Wed Sep 21 22:58:32 2016 +0200 Description: ARM: BCM5301X: Add separated DTS include file for BCM47094 ------Use it to store BCM47094 specific properties/values and avoid repeating them in device DTS files.

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1757 arch\arm\boot\dts\bcm47094.dtsi#newFile Repo: 92b7b6ad1a09 Rafa Miecki Wed Sep 21 22:58:34 2016 +0200 Description: ARM: BCM5301X: Specify USB 3.0 PHY in DT ------Driver for Northstar USB 3.0 PHY has been recently added under the name phy-bcm-ns-usb3. Add binding for it into the DT files. The only slightly tricky part is BCM47094 which uses different PHY version and requires different compatible value.

1758 arch\arm\boot\dts\bcm47189-tenda-ac9.dts#newFile Repo: e90d2d51c412 Rafa Miecki Tue Aug 23 07:37:43 2016 +0200 Description: ARM: BCM5301X: Add basic dts for BCM53573 based Tenda AC9 ------BCM53573 seems to be low priced alternative for Northstar chipsts. It uses single core Cortex-A7 and doesn't have SDU or local (TWD) timer. It was also stripped out of independent SPI controller and 2 GMACs.

DTS for Tenda AC9 isn't completed yet. It misses e.g. switch entry (we still need some b53 fixes) and probably some clocks. It adds support for basic features however and can be improved later.

1759 arch\arm\boot\dts\bcm5301x-nand-cs0-bch4.dtsi#newFile Repo: 4335e6fd58b8 Dan Haab Tue Sep 27 11:27:11 2016 -0600 Description: ARM: BCM5301X: Add DT for Luxul XWR-3100 ------Luxul XWR-3100 is a wireless router based on BCM47094 SoC with two 4366c0 FullMAC PCIe cards on the PCB. It uses NAND with BCH-4 ECC algorithm.

1760 arch\arm\boot\dts\bcm53573.dtsi#newFile Repo: 547f23183d9d Rafa Miecki Sat Sep 17 22:13:46 2016 +0200 Description: ARM: BCM53573: Specify PMU and its ILP clock in the DT ------ILP clock (sometimes called a "slow clock") is a part of PMU (Power Management Unit). There has been recently added a driver for it, so add a proper entry in the DT as well.

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1761 arch\arm\boot\dts\cloudengines-pogoplug-series-3.dts#newFile Repo: 38d4a53733f5 Neil Fri Sep 9 12:24:38 2016 +0200 Description: ARM: dts: Add support for OX820 and Pogoplug V3 ------Add device tree for the Oxford Seminconductor OX820 SoC and the Cloud Engines PogoPlug v3 board. Add the SoC and board compatible strings to oxnas bindings.

1762 arch\arm\boot\dts\dra71-evm.dts#newFile Repo: 6eebfeb9cf0d Nishanth Fri Oct 21 16:08:39 2016 +0530 Description: ARM: dts: Add support for dra718-evm ------The DRA718-evm is a board based on TI's DRA718 processor targeting BOM-optimized entry infotainment systems and is a reduced pin and software compatible derivative of the DRA72 ES2.0 processor. This platform features: - 2GB of DDR3L - Dual 1Gbps Ethernet - HDMI, - uSD - 8GB eMMC - CAN - PCIe - USB3.0 - Video Input Port - LP873x PMIC

More information can be found here[1].

Adding support for this board while reusing the data available in dra72-evm-common.dtsi.

[1] http://www.ti.com/product/dra718

1763 arch\arm\boot\dts\dra72-evm-tps65917.dtsi#newFile Repo: 1a177cf72b3a Lokesh Vutla Wed Dec 14 14:27:03 2016 +0530 Description: ARM: dts: dra72-evm-tps65917: Add voltage supplies to usb_phy, mmc, dss ------Commit 5d080aa30681 ("ARM: dts: dra72: Add separate dtsi for tps65917") added a separate dtsi for dra72-evm-tps65917 moving all the voltage supplies to this file. But it missed adding voltage supplies to usb_phy, mmc, dss and deleted from dra72-evm-common.dtsi. Adding the voltage supply phandles to these nodes in dra72-evm-tps65917.dtsi

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Fixes: 5d080aa30681 ("ARM: dts: dra72: Add separate dtsi for tps65917")

1764 arch\arm\boot\dts\exynos4412-itop-elite.dts#newFile Repo: 339b2fb36a67 Randy Li Wed Oct 19 01:18:49 2016 +0800 Description: ARM: dts: exynos: Add TOPEET itop elite based board ------The TOPEET itop Exynos4412 has three versions of base boards. The Elite version is the cheap one without too much peripheral devices on it.

Currently supported are serial console, wired networking (USB), USB OTG in peripheral mode, USB host, SD storage, GPIO buttons, PWM beeper, ADC and LEDs. The WM8960 analog audio codec is also enabled.

The FIMC is not used for camera currently, I enabled it just for a colorspace converter.

1765 arch\arm\boot\dts\exynos4412-itop-scp-core.dtsi#newFile Repo: accc477c9c30 Randy Li Wed Oct 19 01:18:48 2016 +0800 Description: ARM: dts: exynos: Add TOPEET itop core board SCP package version ------The TOPEET itop is a Samsung Exynos4412 core board, which has two package versions. This patch adds the support for SCP version.

Currently supported are USB3503A HSIC, USB OTG, eMMC, RTC and PMIC. The future features are in the based board. Also MFC and watchdog have been enabled.

1766 arch\arm\boot\dts\imx6dl-colibri-eval-v3.dts#newFile Repo: fc48e76489fd Sanchayan Wed Sep 21 16:54:38 2016 +0530 Description: ARM: dts: imx6: Add support for Toradex Colibri iMX6 module ------Add support for Toradex Colibri iMX6 module.

1767 arch\arm\boot\dts\imx6dl-icore.dts#newFile Repo: 9daee3076940 Jagan Teki Fri Oct 21 13:35:52 2016 +0530 Description: ARM: dts: imx6q: Add Engicam i.CoreM6 DualLite/Solo initial support ------i.CoreM6 DualLite/Solo modules are system on module solutions manufactured by Engicam with following characteristics: CPU NXP i.MX6 DL, 800MHz RAM 1GB, 32, 64 bit, DDR3-800/1066

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NAND SLC,512MB Power supply Single 5V MAX LCD RES FULLHD

and more info at http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q

1768 arch\arm\boot\dts\imx6q-icore.dts#newFile Repo: 6df11287f7c9 Jagan Teki Fri Oct 21 13:35:51 2016 +0530 Description: ARM: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual initial support ------i.CoreM6 Quad/Dual modules are system on module solutions manufactured by Engicam with following characteristics: CPU NXP i.MX6 DQ, 800MHz RAM 1GB, 32, 64 bit, DDR3-800/1066 NAND SLC,512MB Power supply Single 5V MAX LCD RES FULLHD

and more info at http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q

1769 arch\arm\boot\dts\imx6q-nitrogen6_som2.dts#newFile Repo: 3faa1bb2e89c Gary Bisson Tue Nov 1 18:10:02 2016 +0100 Description: ARM: dts: imx: add Boundary Devices Nitrogen6_SOM2 support ------SoM based on i.MX6 Quad with 1GB of DDR3.

https://boundarydevices.com/product/nit6x-som-v2/

1770 arch\arm\boot\dts\imx6qdl-colibri.dtsi#newFile Repo: fc48e76489fd Sanchayan Wed Sep 21 16:54:38 2016 +0530 Description: ARM: dts: imx6: Add support for Toradex Colibri iMX6 module ------Add support for Toradex Colibri iMX6 module.

1771 arch\arm\boot\dts\imx6qdl-icore.dtsi#newFile Repo: 801173fe6f48 Jagan Teki Fri Oct 21 13:35:53 2016 +0530 Description: ARM: dts: imx6qdl-icore: Add FEC support ------Add FEC support for Engicam i.CoreM6 dql modules.

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Observed similar 'eth0: link is not ready' issue which was discussed in [1] due rmii mode with external ref_clk, so added clock node along with the properties mentioned by Shawn in [2]

FEC link log: ------$ ifconfig eth0 up [ 27.905187] SMSC LAN8710/LAN8720 2188000.ethernet:00: attached PHY driver [SMSC LAN8710/LAN8720] (mii_bus:phy_addr=2188000.ethernet:00, irq=-1) [ 27.918982] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready

[1] https://patchwork.kernel.org/patch/3491061/ [2] https://patchwork.kernel.org/patch/3490511/

1772 arch\arm\boot\dts\imx6qdl-nitrogen6_som2.dtsi#newFile Repo: 37530e74609a Gary Bisson Tue Jan 3 12:22:47 2017 +0100 Description: ARM: dts: imx6qdl-nitrogen6_som2: fix sgtl5000 pinctrl init ------Since the codec is probed first, the pinctrl node should be under the codec node.

The codec init was working for this board since U-Boot was already setting GPIO_0 as CLKO1 but better fix it anyway.

Fixes: 3faa1bb2e89c ("ARM: dts: imx: add Boundary Devices Nitrogen6_SOM2 support")

1773 arch\arm\boot\dts\imx6sx-udoo-neo-basic.dts#newFile Repo: 841310d00a76 Fabio Tue Nov 1 15:38:12 2016 -0200 Description: ARM: dts: imx6sx-udoo: Add board specific compatible strings ------Add a compatible entry for the specific board versions.

1774 arch\arm\boot\dts\imx6sx-udoo-neo-extended.dts#newFile Repo: 841310d00a76 Fabio Tue Nov 1 15:38:12 2016 -0200 Description: ARM: dts: imx6sx-udoo: Add board specific compatible strings ------Add a compatible entry for the specific board versions.

1775 arch\arm\boot\dts\imx6sx-udoo-neo-full.dts#newFile Repo: 841310d00a76 Fabio Tue Nov 1 15:38:12 2016 -0200 Description: ARM: dts: imx6sx-udoo: Add board specific compatible strings

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------Add a compatible entry for the specific board versions.

1776 arch\arm\boot\dts\imx6sx-udoo-neo.dtsi#newFile Repo: 76e691fc7653 Andreas Sun Oct 16 16:44:23 2016 +0200 Description: ARM: dts: imx6sx: Add UDOO Neo support ------Add initial device trees for UDOO Neo Basic, Extended and Full boards: * Serial console is enabled, other serial ports are prepared. * I2C based PMIC is enabled. * Ethernet is enabled for Basic and Full. * SDHC is enabled, with the SDIO_PWR GPIO modeled as a regulator. * Both user LEDs are enabled, with the orange one reserved for the M4 and with the SD card as default trigger for the red LED.

The decision on a board compatible string is deferred to later.

1777 arch\arm\boot\dts\imx6ul-liteboard.dts#newFile Repo: 478c9440b328 Marcin Fri Oct 21 17:07:17 2016 +0200 Description: ARM: dts: imx6ul: Add DTS for liteBoard ------liteBoard is a development board which uses liteSOM as its base.

Hardware specification: * liteSOM (i.MX6UL, DRAM, eMMC) * Ethernet PHY (id 0) * USB host (usb_otg1) * MicroSD slot (uSDHC1)

1778 arch\arm\boot\dts\imx6ul-litesom.dtsi#newFile Repo: 1317efa1699f Marcin Fri Oct 21 17:07:16 2016 +0200 Description: ARM: dts: imx6ul: Add DTS for liteSOM module ------This is a SOM (System on Module), so it will be part of another boards. Hence, this is a "dtsi" file that will be included from another device tree files.

Hardware specification: * Freescale i.MX6UL SoC * up to 512 MB RAM * eMMC on uSDHC2

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1779 arch\arm\boot\dts\imx6ull-14x14-evk.dts#newFile Repo: c201369d4aa5 Peter Chen Mon Nov 14 15:04:20 2016 +0800 Description: ARM: dts: imx6ull: add imx6ull support ------It is the 10th processor in the well-known imx6 series, and derived from imx6ul but cost optimized. The more information about imx6ull can be found at:

http://www.nxp.com/products/microcontrollers-and-processors/ arm-processors/i.mx-applications-processors/i.mx-6-processors /i.mx6qp/i.mx-6ull-single-core-processor-with-arm-cortex-a7-core :i.MX6ULL

imx6ul.dtsi is the SoC common stuff for both imx6ul and imx6ull; imx6ul-14x14-evk.dts is the board common stuff for both imx6ul and imx6ull 14x14 evk. In this patch, for SoC part, the imx6ull.dtsi includes imx6ul.dtsi; for board part, imx6ull-14x14-evk.dts includes imx6ul-14x14-evk.dts.

1780 arch\arm\boot\dts\imx6ull-pinfunc.h#newFile Repo: c201369d4aa5 Peter Chen Mon Nov 14 15:04:20 2016 +0800 Description: ARM: dts: imx6ull: add imx6ull support ------It is the 10th processor in the well-known imx6 series, and derived from imx6ul but cost optimized. The more information about imx6ull can be found at:

http://www.nxp.com/products/microcontrollers-and-processors/ arm-processors/i.mx-applications-processors/i.mx-6-processors /i.mx6qp/i.mx-6ull-single-core-processor-with-arm-cortex-a7-core :i.MX6ULL

imx6ul.dtsi is the SoC common stuff for both imx6ul and imx6ull; imx6ul-14x14-evk.dts is the board common stuff for both imx6ul and imx6ull 14x14 evk. In this patch, for SoC part, the imx6ull.dtsi includes imx6ul.dtsi; for board part, imx6ull-14x14-evk.dts includes imx6ul-14x14-evk.dts.

1781 arch\arm\boot\dts\imx6ull.dtsi#newFile Repo: c201369d4aa5 Peter Chen Mon Nov 14 15:04:20 2016 +0800 Description: ARM: dts: imx6ull: add imx6ull support ------It is the 10th processor in the well-known imx6 series, and derived from imx6ul but cost optimized. The more information about imx6ull

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can be found at:

http://www.nxp.com/products/microcontrollers-and-processors/ arm-processors/i.mx-applications-processors/i.mx-6-processors /i.mx6qp/i.mx-6ull-single-core-processor-with-arm-cortex-a7-core :i.MX6ULL

imx6ul.dtsi is the SoC common stuff for both imx6ul and imx6ull; imx6ul-14x14-evk.dts is the board common stuff for both imx6ul and imx6ull 14x14 evk. In this patch, for SoC part, the imx6ull.dtsi includes imx6ul.dtsi; for board part, imx6ull-14x14-evk.dts includes imx6ul-14x14-evk.dts.

1782 arch\arm\boot\dts\omap4-droid4-xt894.dts#newFile Repo: 7e2f8c0ae670 Tony Sat Nov 12 08:57:59 2016 -0800 Description: ARM: dts: Add minimal support for motorola droid 4 xt894 ------Let's add minimal support for droid 4 with MMC and WLAN working. It can be booted with appended dtb using kexec to a state where MMC and WLAN work with currently no support for it's PMIC or display.

Note that we are currently using fixed regulators as we don't have support for it's cpcap PMIC. I'll be posting regmap_spi based minimal cpcap patches later on for USB and the debug UART on droid 4 multiplexed with the USB connector.

1783 arch\arm\boot\dts\orion5x-linkstation-lschl.dts#newFile Repo: 6cfd3cd8d836 Roger Mon Jan 30 20:07:30 2017 +0900 Description: ARM: dts: orion5x-lschl: More consistent naming on linkstation series ------DTS files, which includes orion5x-linkstation.dtsi, are named: orion5x-linkstation-*.dts

So we rename the file below: arch/arm/boot/dts/orion5x-lschl.dts to the new name: arch/arm/boot/dts/orion5x-linkstation-lschl.dts

Because DTS conversion of this device was just introduced in 4.9, Debian is still using legacy device support, other distros are the same, so here we won't expect any impact actually.

Fixes: f94f268979a2 ("ARM: dts: orion5x: convert ls-chl to FDT")

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1784 arch\arm\boot\dts\ox820.dtsi#newFile Repo: 38d4a53733f5 Neil Fri Sep 9 12:24:38 2016 +0200 Description: ARM: dts: Add support for OX820 and Pogoplug V3 ------Add device tree for the Oxford Seminconductor OX820 SoC and the Cloud Engines PogoPlug v3 board. Add the SoC and board compatible strings to oxnas bindings.

1785 arch\arm\boot\dts\pxa25x.dtsi#newFile Repo: 93ab7c84863e Robert Mon Oct 31 20:54:54 2016 +0100 Description: ARM: dts: pxa: add pxa25x cpu operating points ------Add the relevant data taken from the PXA 25x Electrical, Mechanical, and Thermal Specfication. This will be input data for cpufreq-dt driver.

1786 arch\arm\boot\dts\qcom-mdm9615-wp8548-mangoh-green.dts#newFile Repo: 8ab8a8c3945b Neil Tue Aug 23 13:39:06 2016 +0200 Description: ARM: dts: Add WP8548 based MangOH Green board DTS ------Add support for the Sierra Wireless MangOH Green board with the Sierra Wireless WP8548 Module.

1787 arch\arm\boot\dts\qcom-mdm9615-wp8548.dtsi#newFile Repo: 3106dba69640 Neil Tue Aug 23 13:39:05 2016 +0200 Description: ARM: dts: Add Sierra Wireless WP8548 dtsi ------In order to support the Sierra Wireless WP8548 module based on the Qualcomm MDM9615 SoC, add a dtsi file.

1788 arch\arm\boot\dts\qcom-mdm9615.dtsi#newFile Repo: 64cbff449a8a Masahiro Wed Dec 28 00:51:26 2016 +0900 Description: ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus" part 3 ------Tree-wide replacement was done by commit 2ef7d5f342c1 ("ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"), then the 2nd round by commit 15b7cc78f095 ("arm64: dts: drop "arm,amba-bus" in favor of "simple-bus" part 2").

Here, some new users have appeared for Linux v4.10-rc1. Eliminate them now.

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1789 arch\arm\boot\dts\r8a7743-sk-rzg1m.dts#newFile Repo: d05ab65b1d0b Sergei Mon Oct 31 23:00:03 2016 +0300 Description: ARM: dts: sk-rzg1m: add Ether support ------Define the SK-RZG1M board dependent part of the Ether device node. Enable DHCP and NFS root for the kernel booting.

Based on the original (and large) patch by Dmitry Shifrin .

1790 arch\arm\boot\dts\r8a7743.dtsi#newFile Repo: ef0ca5077449 Sergei Mon Oct 31 22:58:12 2016 +0300 Description: ARM: dts: r8a7743: add IRQC support ------Describe the IRQC interrupt controller in the R8A7743 device tree.

ARM: dts: r8a7743: add Ether support ------Define the generic R8A7743 part of the Ether device node.

Based on the original (and large) patch by Dmitry Shifrin .

ARM: dts: r8a7743: add [H]SCIF{A|B} support ------Describe [H]SCIF{|A|B} ports in the R8A7743 device tree.

Based on the original (and large) patch by Dmitry Shifrin .

ARM: dts: r8a7743: add SYS-DMAC support ------Describe SYS-DMAC0/1 in the R8A7743 device tree.

Based on the original (and large) patch by Dmitry Shifrin .

1791 arch\arm\boot\dts\r8a7745-sk-rzg1e.dts#newFile Repo: 6b334366e636 Sergei Sat Nov 5 01:05:28 2016 +0300 Description: ARM: dts: sk-rzg1e: add Ether support ------

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Define the SK-RZG1E board dependent part of the Ether device node. Enable DHCP and NFS root for the kernel booting.

Based on the original (and large) patch by Dmitry Shifrin .

1792 arch\arm\boot\dts\r8a7745.dtsi#newFile Repo: 28c43fbb3ca0 Sergei Sat Nov 5 00:59:37 2016 +0300 Description: ARM: dts: r8a7745: add IRQC support ------Describe the IRQC interrupt controller in the R8A7745 device tree.

Based on the original (and large) patch by Dmitry Shifrin .

ARM: dts: r8a7745: add Ether support ------Define the generic R8A7745 part of the Ether device node.

Based on the original (and large) patch by Dmitry Shifrin .

ARM: dts: r8a7745: add [H]SCIF{|A|B} support ------Describe [H]SCIF{|A|B} ports in the R8A7745 device tree.

Based on the original (and large) patch by Dmitry Shifrin .

ARM: dts: r8a7745: add SYS-DMAC support ------Describe SYS-DMAC0/1 in the R8A7745 device tree.

Based on the original (and large) patch by Dmitry Shifrin .

1793 arch\arm\boot\dts\rk1108-evb.dts#newFile Repo: f35597ac4906 Andy Yan Mon Nov 14 20:17:43 2016 +0800 Description: ARM: dts: rockchip: add rockchip RK1108 Evaluation board ------RK1108 EVB is designed by Rockchip for CVR field. This patch add basic support for it, which can boot with

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initramfs into .

1794 arch\arm\boot\dts\rk1108.dtsi#newFile Repo: c458e1b504a6 Jacob Chen Sun Nov 13 16:13:18 2016 +0800 Description: ARM: dts: rockchip: add the sdmmc pinctrl for rk1108 ------

1795 arch\arm\boot\dts\rk3066a-mk808.dts#newFile Repo: cbab82029c87 Pawe Jarosz Sat Oct 8 22:22:30 2016 +0200 Description: ARM: dts: rockchip: Add rk3066 MK808 board ------MK808 is a tv stick which has rockchip rk3066 CPU inside, two usb ports - host and otg, micro sd card slot and onboard wifi RK901.

1796 arch\arm\boot\dts\rk3188-px3-evb.dts#newFile Repo: 3a2766cc68e7 Shawn Lin Fri Sep 23 08:09:10 2016 +0800 Description: ARM: dts: rockchip: remove always-on and boot-on from vcc_sd for px3-evb ------Please don't add these for vcc_sd, and mmc-core/driver will control it. Otherwise, it will waste energy even without sdmmc in slot.

Moreover, it will causes a bug: If we insert/remove sd card, we could see [9.337271] mmc0: new ultra high speed SDR25 SDHC card at address 0007 [9.345144] mmcblk0: mmc0:0007 SD32G 29.3 GiB

This is okay for normal sd insert/remove test, but when I debug some issues for sdmmc, I did unbind/bind test. And there is a interesting phenomenon when we bind the driver again: [58.314069] mmc0: new high speed SDHC card at address 0007 [58.320282] mmcblk0: mmc0:0007 SD32G 29.3 GiB

So the sd card could just support high speed without power cycle since the vcc_sd is always on, which makes the sd card fail to reinit its internal ocr mask.

1797 arch\arm\boot\dts\socfpga_arria10_socdk_qspi.dts#newFile Repo: 1df99da8953a Dinh Nguyen Wed Oct 19 10:07:48 2016 -0500 Description: ARM: dts: socfpga: Enable QSPI in Arria10 devkit ------Enable the QSPI node and add the flash chip.

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1798 arch\arm\boot\dts\socfpga_cyclone5_sodia.dts#newFile Repo: d1da66351749 Dinh Nguyen Tue Nov 1 09:57:06 2016 -0500 Description: ARM: dts: socfpga: add specific compatible strings for boards ------Add a more specific board compatible entry for all of the SOCFPGA Cyclone 5 based boards.

1799 arch\arm\boot\dts\stm32746g-eval.dts#newFile Repo: ec2f9b10f33f Alexandre Tue Nov 15 12:01:57 2016 +0100 Description: ARM: dts: Add STM32F746 MCU and STM32746g-EVAL board ------The STMicrolectornics's STM32F746 MCU has the following main features: - Cortex-M7 core running up to @216MHz - 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM) - FMC controller to connect SDRAM, NOR and NAND memories - Dual mode QSPI - SD/MMC/SDIO support - Ethernet controller - USB OTFG FS & HS controllers - I2C, SPI, CAN busses support - Several 16 & 32 bits general purpose timers - Serial Audio interface - LCD controller - HDMI-CEC - SPDIFRX

1800 arch\arm\boot\dts\stm32f746.dtsi#newFile Repo: ec2f9b10f33f Alexandre Tue Nov 15 12:01:57 2016 +0100 Description: ARM: dts: Add STM32F746 MCU and STM32746g-EVAL board ------The STMicrolectornics's STM32F746 MCU has the following main features: - Cortex-M7 core running up to @216MHz - 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM) - FMC controller to connect SDRAM, NOR and NAND memories - Dual mode QSPI - SD/MMC/SDIO support - Ethernet controller - USB OTFG FS & HS controllers - I2C, SPI, CAN busses support - Several 16 & 32 bits general purpose timers - Serial Audio interface - LCD controller - HDMI-CEC - SPDIFRX

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1801 arch\arm\boot\dts\sun5i-gr8-chip-pro.dts#newFile Repo: e63604933ec7 Maxime Thu Sep 1 18:27:21 2016 +0200 Description: ARM: gr8: Add CHIP Pro support ------The CHIP Pro is a small embeddable board. It features a GR8, an AXP209 PMIC, a 512MB SLC NAND and a WiFi/BT chip.

1802 arch\arm\boot\dts\sun8i-h3-nanopi-m1.dts#newFile Repo: 10efbf5f1633 Milo Kim Fri Oct 28 15:59:03 2016 +0900 Description: ARM: dts: sun8i: Add dts file for NanoPi M1 SBC ------NanoPi M1 is the Allwinner H3 based board. This patch enables UART for debug console, LEDs, GPIO key switch, 3 USB host ports, a micro SD slot and related power and pin controls by using NanoPi common dtsi file.

1803 arch\arm\boot\dts\sun8i-h3-nanopi.dtsi#newFile Repo: 49f01c9e14b3 Milo Kim Fri Oct 28 15:59:01 2016 +0900 Description: ARM: dts: sun8i: Add common dtsi file for NanoPi SBCs ------This patch provides a common file for NanoPi M1 and Neo SBC.

Those have common features below. * UART0 * 2 LEDs * USB host (EHCI3, OHCI3) and PHY * MicroSD * GPIO key switch

1804 arch\arm\boot\dts\zynq-microzed.dts#newFile Repo: df2f3c48b9cd Jagan Teki Fri Sep 23 15:18:33 2016 +0530 Description: arm: dts: zynq: Add MicroZed board support ------Added basic dts support for MicroZed board.

- UART - SDHCI - Ethernet

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Line Link NR. Descriptions arch\arm\common\ 1805 arch\arm\common\bL_switcher.c#0760 Repo: a3c9b14f6f15 Sebastian Thu Nov 17 19:35:35 2016 +0100 Description: arm/bL_switcher: Convert to hotplug state machine ------Install the callbacks via the state machine.

arm/bL_switcher: Kill tick suspend hackery ------Use the new tick_suspend/resume_local() and get rid of the homebrewn implementation of these in the ARM bL switcher. The check for the cpumask is completely pointless. There is no harm to suspend a per cpu tick device unconditionally. If that's a real issue then we fix it proper at the core level and not with some completely undocumented hacks in some random core code.

Move the tick internals to the core code, now that this nuisance is gone.

1806 arch\arm\common\bL_switcher.c#0763 1807 arch\arm\common\bL_switcher.c#0785 1808 arch\arm\common\bL_switcher_dummy_if.c#0018 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

1809 arch\arm\common\dmabounce.c#0246 Repo: fc1b138de791 Alexander Wed Dec 14 15:04:32 2016 -0800 Description: arch/arm: add option to skip sync on DMA map and unmap ------The use of DMA_ATTR_SKIP_CPU_SYNC was not consistent across all of the DMA APIs in the arch/arm folder. This change is meant to correct that so that we get consistent behavior.

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Link: http://lkml.kernel.org/r/20161110113424.76501.2715.stgit@ahduyck-blue- test.jf.intel.com

1810 arch\arm\common\dmabounce.c#0266 1811 arch\arm\common\dmabounce.c#0277 1812 arch\arm\common\dmabounce.c#0289 1813 arch\arm\common\dmabounce.c#0341 1814 arch\arm\common\dmabounce.c#0364 arch\arm\configs\ 1815 arch\arm\configs\am200epdkit_defconfig#0058 Repo: 752a47ef73ba Bartlomiej Wed Oct 26 18:43:32 2016 +0200 Description: arm: am200epdkit_defconfig: convert to use libata PATA drivers ------IDE subsystem has been deprecated since 2009 and the majority (if not all) of Linux distributions have switched to use libata for ATA support exclusively. However there are still some users (mostly old or/and embedded non-x86 systems) that have not converted from using IDE subsystem to libata PATA drivers. This doesn't seem to be good thing in the long-term for Linux as while there is less and less PATA systems left in use:

* testing efforts are divided between two subsystems

* having duplicate drivers for same hardware confuses users

This patch converts am200epdkit_defconfig to use libata PATA drivers.

1816 arch\arm\configs\assabet_defconfig#0037 Repo: 9b9c96649bac Bartlomiej Wed Oct 26 18:43:31 2016 +0200 Description: arm: assabet_defconfig: disable IDE subsystem ------This patch disables deprecated IDE subsystem in assabet_defconfig (no IDE host drivers are selected in this config so there is no valid reason to enable IDE subsystem itself).

1817 arch\arm\configs\badge4_defconfig#0045 Repo: 241680cb3717 Bartlomiej Wed Oct 26 18:43:31 2016 +0200 Description: arm: badge4_defconfig: disable IDE subsystem ------

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This patch disables deprecated IDE subsystem in badge4_defconfig (no IDE host drivers are selected in this config so there is no valid reason to enable IDE subsystem itself).

1818 arch\arm\configs\bcm2835_defconfig#0076 Repo: bab0cb905504 Martin Sperl Wed Nov 2 10:18:25 2016 +0000 Description: ARM: bcm2835: add thermal driver to default config ------Add the thermal driver to list of compiled modules in the default config for bcm2835.

ARM: bcm2835: Enable NFS root support. ------This is also present in multi_v7_defconfig, and means that I can test the pi1 with the 2835 defconfig in my normal environment.

ARM: bcm2835: Enable the VC4 graphics driver in the defconfig ------Combined with the queued DT changes, we now get HDMI and 3D support.

ARM: bcm2835: Enable CONFIG_PM. ------The power domain driver we've enabled doesn't actually do anything without it, and we need it to do its job for VC4 to initialize successfully.

1819 arch\arm\configs\cerfcube_defconfig#0042 Repo: ff9c6cb34633 Bartlomiej Wed Oct 26 18:43:31 2016 +0200 Description: arm: cerfcube_defconfig: disable IDE subsystem ------This patch disables deprecated IDE subsystem in cerfcube_defconfig (no IDE host drivers are selected in this config so there is no valid reason to enable IDE subsystem itself).

1820 arch\arm\configs\collie_defconfig#0046 Repo: fb93fdab98e5 Bartlomiej Wed Oct 26 18:43:32 2016 +0200 Description: arm: collie_defconfig: convert to use libata PATA drivers ------IDE subsystem has been deprecated since 2009 and the majority (if not all) of Linux distributions have switched to use

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libata for ATA support exclusively. However there are still some users (mostly old or/and embedded non-x86 systems) that have not converted from using IDE subsystem to libata PATA drivers. This doesn't seem to be good thing in the long-term for Linux as while there is less and less PATA systems left in use:

* testing efforts are divided between two subsystems

* having duplicate drivers for same hardware confuses users

This patch converts collie_defconfig to use libata PATA drivers.

1821 arch\arm\configs\corgi_defconfig#0102 Repo: f3514095ff90 Bartlomiej Wed Oct 26 18:43:32 2016 +0200 Description: arm: corgi_defconfig: convert to use libata PATA drivers ------IDE subsystem has been deprecated since 2009 and the majority (if not all) of Linux distributions have switched to use libata for ATA support exclusively. However there are still some users (mostly old or/and embedded non-x86 systems) that have not converted from using IDE subsystem to libata PATA drivers. This doesn't seem to be good thing in the long-term for Linux as while there is less and less PATA systems left in use:

* testing efforts are divided between two subsystems

* having duplicate drivers for same hardware confuses users

This patch converts corgi_defconfig to use libata PATA drivers.

1822 arch\arm\configs\corgi_defconfig#0111 1823 arch\arm\configs\davinci_all_defconfig#0010 Repo: 47d03e48efa5 Alexandre Mon Nov 28 17:30:54 2016 +0100 Description: ARM: davinci_all_defconfig: Enable da8xx usb otg ------The musb driver is enabled but the phy and the glue for the da8xx are not enabled.

Enable them.

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ARM: davinci_all_defconfig: Enable OHCI as module ------Enable the davinci ohci driver as a module for usb tested with the omap138-lcdk board.

ARM: davinci_all_defconfig: add missing options for ------Some kernel configuration options required for systemd support are missing in davinci_all_defconfig. Add them.

This is based on recommendations in:

http://cgit.freedesktop.org/systemd/systemd/tree/README

Options which kernel enables by default (and will thus be removed upon next savedefconfig update) are not included.

Tested on OMAP-L138 LCDK board with fully up to date armv5 archlinux filesystem.

ARM: davinci_all_defconfig: enable the mstpri and ddrctl drivers ------With the da8xx memory controller and master peripheral priority drivers merged and corresponding device tree changes in place we can now enable appropriate options by default.

ARM: davinci_all_defconfig: enable LED default-on trigger ------The LEDs default-on trigger is nice to have. For example, it can be used to configure a LED as a power indicator.

ARM: davinci_all_defconfig: build MMC into kernel ------This changes the davinci default configuration to build the davinci MMC driver into the kernel. This allows booting from an SD card without requiring an initrd containing the kernel module.

ARM: davinci_all_defconfig: enable gpio poweroff driver ------The gpio-poweroff driver is needed by LEGO MINDSTORMS EV3 (AM1808 based board).

ARM: davinci_all_defconfig: enable LCDC DRM driver ------

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With the device tree changes for tilcdc in place, we can now enable the driver by default in the davinci_all defconfig file.

1824 arch\arm\configs\davinci_all_defconfig#0017 1825 arch\arm\configs\davinci_all_defconfig#0037 1826 arch\arm\configs\davinci_all_defconfig#0056 1827 arch\arm\configs\davinci_all_defconfig#0059 1828 arch\arm\configs\davinci_all_defconfig#0120 1829 arch\arm\configs\davinci_all_defconfig#0129 1830 arch\arm\configs\davinci_all_defconfig#0161 1831 arch\arm\configs\davinci_all_defconfig#0164 1832 arch\arm\configs\davinci_all_defconfig#0167 1833 arch\arm\configs\davinci_all_defconfig#0178 1834 arch\arm\configs\davinci_all_defconfig#0180 1835 arch\arm\configs\davinci_all_defconfig#0187 1836 arch\arm\configs\davinci_all_defconfig#0194 1837 arch\arm\configs\davinci_all_defconfig#0197 1838 arch\arm\configs\davinci_all_defconfig#0203 1839 arch\arm\configs\exynos_defconfig#0158 Repo: d1c7d9b668f6 Javier Wed Oct 5 11:24:28 2016 -0300 Description: ARM: exynos_defconfig: Enable exynos-gsc driver as module ------Exynos5 SoCs have a General SCALER (GSCALER) IP block that can be used to do video streams scaling and color space conversions by hardware. Enable support for its driver as a module so the GSCALER can be tested.

1840 arch\arm\configs\ezx_defconfig#0067 Repo: 5aff1d245e8c Arnd Fri Feb 3 09:58:24 2017 +0100 Description: ARM: defconfigs: make NF_CT_PROTO_SCTP and NF_CT_PROTO_UDPLITE built-in ------The symbols can no longer be used as loadable modules, leading to a harmless Kconfig warning:

arch/arm/configs/imote2_defconfig:60:warning: symbol value 'm' invalid for NF_CT_PROTO_UDPLITE arch/arm/configs/imote2_defconfig:59:warning: symbol value 'm' invalid for NF_CT_PROTO_SCTP

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arch/arm/configs/ezx_defconfig:68:warning: symbol value 'm' invalid for NF_CT_PROTO_UDPLITE arch/arm/configs/ezx_defconfig:67:warning: symbol value 'm' invalid for NF_CT_PROTO_SCTP

Let's make them built-in.

1841 arch\arm\configs\h3600_defconfig#0042 Repo: 8b7f25bb8123 Bartlomiej Wed Oct 26 18:43:32 2016 +0200 Description: arm: h3600_defconfig: convert to use libata PATA drivers ------IDE subsystem has been deprecated since 2009 and the majority (if not all) of Linux distributions have switched to use libata for ATA support exclusively. However there are still some users (mostly old or/and embedded non-x86 systems) that have not converted from using IDE subsystem to libata PATA drivers. This doesn't seem to be good thing in the long-term for Linux as while there is less and less PATA systems left in use:

* testing efforts are divided between two subsystems

* having duplicate drivers for same hardware confuses users

This patch converts h3600_defconfig to use libata PATA drivers.

1842 arch\arm\configs\imote2_defconfig#0059 Repo: 5aff1d245e8c Arnd Fri Feb 3 09:58:24 2017 +0100 Description: ARM: defconfigs: make NF_CT_PROTO_SCTP and NF_CT_PROTO_UDPLITE built-in ------The symbols can no longer be used as loadable modules, leading to a harmless Kconfig warning:

arch/arm/configs/imote2_defconfig:60:warning: symbol value 'm' invalid for NF_CT_PROTO_UDPLITE arch/arm/configs/imote2_defconfig:59:warning: symbol value 'm' invalid for NF_CT_PROTO_SCTP arch/arm/configs/ezx_defconfig:68:warning: symbol value 'm' invalid for NF_CT_PROTO_UDPLITE arch/arm/configs/ezx_defconfig:67:warning: symbol value 'm' invalid for NF_CT_PROTO_SCTP

Let's make them built-in.

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1843 arch\arm\configs\imx_v6_v7_defconfig#0089 Repo: 3252e255371a Marek Vasut Mon Oct 17 18:34:33 2016 +0200 Description: ARM: imx_v6_v7_defconfig: Select the es8328 codec driver ------Select CONFIG_SND_SOC_ES8328 so that we can have audio functional by default on Kosagi Novena boards.

ARM: imx_v6_v7_defconfig: Increase CMA size ------Increase the CMA size to 64 MiB, otherwise it isn't possible to use etnaviv driver on systems with 1920x1080 panel due to insufficient memory .

1844 arch\arm\configs\imx_v6_v7_defconfig#0260 1845 arch\arm\configs\integrator_defconfig#0029 Repo: 672806a5f168 Linus Walleij Wed Aug 10 10:47:11 2016 +0200 Description: ARM: defconfig: turn on the DT cpufreq for Integrator ------The Integrators are now migrated to handle the CPUfreq scaling using the generic devicetree CPUfreq driver using the common clock framework and have the required device tree modifications, so turn off the old driver and turn on the new generic driver.

1846 arch\arm\configs\ixp4xx_defconfig#0130 Repo: 150a55a46dba Bartlomiej Wed Oct 26 18:43:32 2016 +0200 Description: arm: ixp4xx_defconfig: convert to use libata PATA drivers ------IDE subsystem has been deprecated since 2009 and the majority (if not all) of Linux distributions have switched to use libata for ATA support exclusively. However there are still some users (mostly old or/and embedded non-x86 systems) that have not converted from using IDE subsystem to libata PATA drivers. This doesn't seem to be good thing in the long-term for Linux as while there is less and less PATA systems left in use:

* testing efforts are divided between two subsystems

* having duplicate drivers for same hardware confuses users

This patch converts ixp4xx_defconfig to use libata PATA drivers.

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1847 arch\arm\configs\ixp4xx_defconfig#0140 1848 arch\arm\configs\jornada720_defconfig#0032 Repo: 26d14eb3a9c1 Bartlomiej Wed Oct 26 18:43:33 2016 +0200 Description: arm: jornada720_defconfig: convert to use libata PATA drivers ------IDE subsystem has been deprecated since 2009 and the majority (if not all) of Linux distributions have switched to use libata for ATA support exclusively. However there are still some users (mostly old or/and embedded non-x86 systems) that have not converted from using IDE subsystem to libata PATA drivers. This doesn't seem to be good thing in the long-term for Linux as while there is less and less PATA systems left in use:

* testing efforts are divided between two subsystems

* having duplicate drivers for same hardware confuses users

This patch converts jornada720_defconfig to use libata PATA drivers.

1849 arch\arm\configs\lart_defconfig#0039 Repo: 5d9283de34d2 Bartlomiej Wed Oct 26 18:43:32 2016 +0200 Description: arm: lart_defconfig: disable IDE subsystem ------This patch disables deprecated IDE subsystem in lart_defconfig (no IDE host drivers are selected in this config so there is no valid reason to enable IDE subsystem itself).

1850 arch\arm\configs\mainstone_defconfig#0030 Repo: a17d7bf2c3bf Bartlomiej Wed Oct 26 18:43:32 2016 +0200 Description: arm: mainstone_defconfig: disable IDE subsystem ------This patch disables deprecated IDE subsystem in mainstone_defconfig (no IDE host drivers are selected in this config so there is no valid reason to enable IDE subsystem itself).

1851 arch\arm\configs\multi_v5_defconfig#0153 Repo: a0910d72afc6 Linus Walleij Thu Nov 24 15:57:52 2016 +0100 Description: ARM: defconfig: drop GPIO_SYSFS on multiplatforms ------The sysfs ABI to GPIO is marked obsolete and should not be

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encouraged. Users should be encouraged to switch to using the character device.

Let's begin by removing it from the multi defconfigs. Then as time goes by I can aggressively remove it from other defconfigs.

1852 arch\arm\configs\multi_v7_defconfig#0176 Repo: 69e05170ef0d Andy Gross Mon Jan 2 14:35:05 2017 -0600 Description: ARM: multi_v7_defconfig: enable Qualcomm RPMCC ------This patch enables the Qualcomm RPM based Clock Controller present on A-family boards.

ARM: multi_v7_defconfig: set bcm47xx watchdog ------Correct the bcm47xx watchdog option. The convention of bcm watchdogs is the _WDT suffix.

Fixes: 8dace3040426 ("ARM: multi_v7_defconfig: Enable BCM47xx/BCM5301x drivers")

ARM: multi_v7_defconfig: fix config typo ------s/CONFIG_CONFIG_BCM47XX_NVRAM/CONFIG_BCM47XX_NVRAM/

Fixes: 8dace3040426 ("ARM: multi_v7_defconfig: Enable BCM47xx/BCM5301x drivers")

Merge tag 'armsoc-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM SoC defconfig updates from Arnd Bergmann: "Defconfig additions, removals, etc. Most of these are small changes adding the options for newly upstreamed drivers, or drivers needed for new board support.

Bartlomiej Zolnierkiewicz has done a series of patches reducing the use of CONFIG_IDE from 19 to 3 in favor of CONFIG_ATA.

Overall more patches than usual, but nothing big"

* tag 'armsoc-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (54 commits) ARM: davinci_all_defconfig: Enable da8xx usb otg ARM: defconfig: drop GPIO_SYSFS on multiplatforms ARM: multi_v7_defconfig: enable STMicroelectronics HVA driver ARM: configs: Add new config fragment to change RAM start point ARM: davinci_all_defconfig: Enable OHCI as module ARM: defconfig: turn on the DT cpufreq for Integrator

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ARM: omap2plus_defconfig: Run make savedefconfig to save some space ARM: davinci_all_defconfig: add missing options for systemd ARM: davinci_all_defconfig: enable the mstpri and ddrctl drivers ARM: bcm2835: add thermal driver to default config ARM: omap2plus_defconfig: Enable LP873X support ARM: omap2plus_defconfig: Enable REGULATOR_GPIO ARM: omap2plus_defconfig: Enable TOUCHSCREEN_TSC2004 ARM: socfpga_defconfig: enable FS configs to support Angstrom filesystem ARM: config: Enable GPIO Key driver in stm32_defconfig ARM: tegra: Enable GMI driver in default configuration ARM: tegra: Enable SGTL5000 audio ARM: tegra: Update default configuration for v4.9-rc1 ARM: socfpga: updates for socfpga_defconfig ARM: davinci_all_defconfig: enable LED default-on trigger ...

Merge tag 'rproc-v4.10' of git://github.com/andersson/remoteproc ------Pull remoteproc updates from Bjorn Andersson:

- introduce remoteproc "subdevice" support, which allows remoteproc driver to associate devices to the "running" state of the remoteproc, allowing devices to be probed and removed as the remote processor is booted, shut down or recovering from a crash.

- handling of virtio device resources was improved, vring memory is now allocated as part of other memory allocation. This ensures that all vrings for all virtio devices are allocated before we boot the remote processor.

- the debugfs mechanism for starting and stopping remoteproc instances was replaced with a sysfs interface, also providing a mechanism for specifying firmware to use by the instance. This allows user space to load and boot use case specific firmware on remote processors.

- new drivers for the ST Slimcore and Qualcomm Hexagon DSP as well as removal of the unused StE modem loader.

- finally support for crash recovery in the Qualcomm Wirelss subsystem (used for WiFi/BT/FM on a number of platforms) and a number of bug fixes and cleanups

* tag 'rproc-v4.10' of git://github.com/andersson/remoteproc: (49 commits) remoteproc: qcom_adsp_pil: select qcom_scm remoteproc: Drop wait in __rproc_boot() remoteproc/ste: Delete unused driver remoteproc: Remove "experimental" warning remoteproc: qcom_adsp_pil: select qcom_scm dt-binding: soc: qcom: smd: Add label property

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remoteproc: qcom: mdt_loader: add include for sizes remoteproc: Update last rproc_put users to rproc_free remoteproc: qcom: adsp: Add missing MODULE_DEVICE_TABLE remoteproc: wcnss-pil: add QCOM_SMD dependency dmaengine: st_fdma: Revert: "Revert: Update st_fdma to 'depends on REMOTEPROC'" remoteproc: Add support for xo clock remoteproc: adsp-pil: fix recursive dependency remoteproc: Introduce Qualcomm ADSP PIL dt-binding: remoteproc: Introduce ADSP loader binding remoteproc: qcom_wcnss: Fix circular module dependency remoteproc: Merge table_ptr and cached_table pointers remoteproc: Remove custom vdev handler list remoteproc: Update max_notifyid as we allocate vrings remoteproc: Decouple vdev resources and devices ...

Merge tag 'leds_for_4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/j.anaszewski/linux-leds ------Pull LED updates from Jacek Anaszewski:

- userspace LED class driver - it can be useful for testing triggers and can also be used to implement virtual LEDs

- LED class driver for NIC78bx device

- LED core fixes for preventing potential races while setting brightness when software blinking is enabled

- improvements in LED documentation to mention semantics on changing brightness while trigger is active

* tag 'leds_for_4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/j.anaszewski/linux-leds: leds: pca955x: Add ACPI support leds: netxbig: fix module autoload for OF registration leds: pca963x: Add ACPI support leds: leds-cobalt-raq: use builtin_platform_driver led: core: Fix blink_brightness setting race led: core: Use atomic bit-field for the blink-flags leds: Add user LED driver for NIC78bx device leds: verify vendor and change license in mlxcpld driver leds: pca963x: enable low-power state leds: pca9532: Use default trigger value from platform data leds: pca963x: workaround group blink scaling issue cleanup LED documentation and make it match reality leds: lp3952: Export I2C module alias information for module autoload leds: mc13783: Fix MC13892 keypad led access ledtrig-cpu.c: fix english leds/leds-lp5523.txt: make documentation match reality

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tools/leds: Add uledmon program for monitoring userspace LEDs leds: Use macro for max device node name size leds: Introduce userspace LED class driver mfd: qcom-pm8xxx: Clean up PM8XXX namespace

Merge tag 'sti-defconfig-for-4.10-round3' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into next/defconfig ------Pull "STi defconfig fix" from Patrice Chotard:

Enable HVA (Hardware Video Accelerator) video encoder driver for STMicroelectronics SoC.

* tag 'sti-defconfig-for-4.10-round3' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti: ARM: multi_v7_defconfig: enable STMicroelectronics HVA driver

ARM: defconfig: drop GPIO_SYSFS on multiplatforms ------The sysfs ABI to GPIO is marked obsolete and should not be encouraged. Users should be encouraged to switch to using the character device.

Let's begin by removing it from the multi defconfigs. Then as time goes by I can aggressively remove it from other defconfigs.

Merge tag 'arm-soc/for-4.10/defconfig' of http://github.com/Broadcom/stblinux into next/defconfig ------Pull "Broadcom defconfig changes for 4.10" from Florian Fainelli:

This pull request contains Broadcom ARM-based defconfig changes for 4.10, please pull the following:

- Florian updates the multi_v7_defconfig with the relevant basic drivers needed for the Broadcom BCM5301x (Northstar) SoCs to reboot, have PCIe, and Ethernet

- Martin enables the Raspberry Pi thermal driver in bcm2835_defconfig

* tag 'arm-soc/for-4.10/defconfig' of http://github.com/Broadcom/stblinux: ARM: bcm2835: add thermal driver to default config ARM: multi_v7_defconfig: Enable BCM47xx/BCM5301x drivers

ARM: multi_v7_defconfig: enable STMicroelectronics HVA driver ------

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Enable HVA (Hardware Video Accelerator) video encoder driver for STMicroelectronics SoC.

mfd: qcom-pm8xxx: Clean up PM8XXX namespace ------The Kconfig and file naming for the PM8xxx driver is totally confusing:

- Kconfig options MFD_PM8XXX and MFD_PM8921_CORE, some in-kernel users depending on or selecting either at random. - A driver file named pm8921-core.c even if it is indeed used by the whole PM8xxx family of chips. - An irqchip named pm8xxx since it was (I guess) realized that the driver was generic for all pm8xxx PMICs.

As I may want to add support for PM8901 this is starting to get really messy. Fix this situation by:

- Remove the MFD_PM8921_CORE symbol and rely solely on MFD_PM8XXX and convert all users, including LEDs Kconfig and ARM defconfigs for qcom and multi_v7 to use that single symbol. - Renaming the driver to qcom-pm8xxx.c to fit along the two other qcom* prefixed drivers. - Rename functions withing the driver from 8921 to 8xxx to indicate it is generic. - Just drop the =m config from the pxa_defconfig, I have no clue why it is even there, it is not a Qualcomm platform. (Possibly older Kconfig noise from saveconfig.)

Merge tag 'sunxi-defconfig-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/defconfig ------Allwinner defconfig changes for 4.10

Two patches to enable the dumb VGA bridges in the multi_v7 and sunxi defconfig.

* tag 'sunxi-defconfig-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: ARM: multi_v7: enable VGA bridge ARM: sunxi: Enable VGA bridge

Merge branch 'sti-defconfig-for-4.10-round2' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into next/defconfig ------* 'sti-defconfig-for-4.10-round2' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti: ARM: multi_v7_defconfig: Remove ST_THERMAL_SYSCFG Kconfig symbol

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Merge tag 'samsung-defconfig-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/defconfig ------Samsung defconfig update for v4.10: 1. Enable the Exynos gscaler driver on multi_v7 and exynos defconfigs.

* tag 'samsung-defconfig-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: multi_v7_defconfig: Enable exynos-gsc driver as module ARM: exynos_defconfig: Enable exynos-gsc driver as module

ARM: multi_v7_defconfig: Remove ST_THERMAL_SYSCFG Kconfig symbol ------STiH415/6 SoC support is being removed from the kernel and was the only platform using this Kconfig symbol

ARM: multi_v7_defconfig: Remove stih41x phy Kconfig symbol. ------This IP is only found on STiH415/6 silicon and support for these SoCs is being removed from the kernel.

ARM: multi_v7_defconfig: Remove miphy365 phy Kconfig symbol. ------This IP is only found on STiH415/6 silicon and support for these SoCs is being removed from the kernel.

ARM: multi_v7_defconfig: Enable BCM47xx/BCM5301x drivers ------Add a bunch of required drivers and subsystems:

- BCMA is the on-chip discoverable bus which registers a bunch of peripherals - Enable the BCM47xx watchdog driver to get working system reboot - Enable the BCM47xx NVRAM/SPROM drivers to be able to fetch MAC addresses and other variables needed for system operation - Make BGMAC (built-in Ethernet adapter) a module

ARM: multi_v7_defconfig: Enable STi and simple-card drivers. ------This patch enables the STi ALSA drivers found on STi platforms as well as the simple-card driver which is a dependency to have working sound.

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ARM: multi_v7_defconfig: Enable STi FDMA driver ------This DMA controller is found on all STi chipsets.

ARM: multi_v7_defconfig: Enable st_remoteproc driver. ------The st231 remote coprocessors are found on all STi chipsets.

ARM: multi_v7_defconfig: Enable remoteproc core ------Now that remoteproc core is selectable it needs to be enabled in the multi_v7 build.

ARM: multi_v7_defconfig: Enable Intel e1000e driver ------Enable support for the Intel e1000e driver

ARM: multi_v7_defconfig: Enable exynos-gsc driver as module ------Exynos5 SoCs have a General SCALER (GSCALER) IP block that can be used to do video streams scaling and color space conversions by hardware. Enable support for its driver as a module so the GSCALER can be tested.

1853 arch\arm\configs\multi_v7_defconfig#0243 1854 arch\arm\configs\multi_v7_defconfig#0413 1855 arch\arm\configs\multi_v7_defconfig#0458 1856 arch\arm\configs\multi_v7_defconfig#0474 1857 arch\arm\configs\multi_v7_defconfig#0497 1858 arch\arm\configs\multi_v7_defconfig#0569 1859 arch\arm\configs\multi_v7_defconfig#0571 1860 arch\arm\configs\multi_v7_defconfig#0582 1861 arch\arm\configs\multi_v7_defconfig#0660 1862 arch\arm\configs\multi_v7_defconfig#0804 1863 arch\arm\configs\multi_v7_defconfig#0813 1864 arch\arm\configs\multi_v7_defconfig#0827

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1865 arch\arm\configs\multi_v7_defconfig#0843 1866 arch\arm\configs\multi_v7_defconfig#0884 1867 arch\arm\configs\multi_v7_defconfig#0885 1868 arch\arm\configs\multi_v7_defconfig#0897 1869 arch\arm\configs\netwinder_defconfig#0011 Repo: 4289ab7ad650 Bartlomiej Wed Oct 26 18:43:33 2016 +0200 Description: arm: netwinder_defconfig: convert to use libata PATA drivers ------IDE subsystem has been deprecated since 2009 and the majority (if not all) of Linux distributions have switched to use libata for ATA support exclusively. However there are still some users (mostly old or/and embedded non-x86 systems) that have not converted from using IDE subsystem to libata PATA drivers. This doesn't seem to be good thing in the long-term for Linux as while there is less and less PATA systems left in use:

* testing efforts are divided between two subsystems

* having duplicate drivers for same hardware confuses users

This patch converts netwinder_defconfig to use libata PATA drivers.

1870 arch\arm\configs\netwinder_defconfig#0030 1871 arch\arm\configs\omap1_defconfig#0099 Repo: ff1719664127 Bartlomiej Wed Oct 26 18:43:32 2016 +0200 Description: arm: omap1_defconfig: convert to use libata PATA drivers ------IDE subsystem has been deprecated since 2009 and the majority (if not all) of Linux distributions have switched to use libata for ATA support exclusively. However there are still some users (mostly old or/and embedded non-x86 systems) that have not converted from using IDE subsystem to libata PATA drivers. This doesn't seem to be good thing in the long-term for Linux as while there is less and less PATA systems left in use:

* testing efforts are divided between two subsystems

* having duplicate drivers for same hardware confuses users

This patch converts omap1_defconfig to use libata PATA drivers.

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1872 arch\arm\configs\omap1_defconfig#0107 1873 arch\arm\configs\omap2plus_defconfig#0004 Repo: 9c106e4efab2 Tony Tue Nov 15 11:01:24 2016 -0800 Description: ARM: omap2plus_defconfig: Run make savedefconfig to save some space ------This shrinks down omap2plus_defconfig a bit and makes it easier for people to generate minimal patches against it.

ARM: omap2plus_defconfig: Enable LP873X support ------LP873X family of PMICs are used in dra71x-evm, So enable the same.

ARM: omap2plus_defconfig: Enable REGULATOR_GPIO ------GPIO regulator is used on dra71-evm platform to control MMCSD IO voltage

ARM: omap2plus_defconfig: Enable TOUCHSCREEN_TSC2004 ------The LogicPD DM3730 Torpedo and SOM-LV devices have the TI TSC2004 touchscreen controller. Enable the related driver as a module.

1874 arch\arm\configs\omap2plus_defconfig#0043 1875 arch\arm\configs\omap2plus_defconfig#0053 1876 arch\arm\configs\omap2plus_defconfig#0065 1877 arch\arm\configs\omap2plus_defconfig#0208 1878 arch\arm\configs\omap2plus_defconfig#0243 1879 arch\arm\configs\omap2plus_defconfig#0249 1880 arch\arm\configs\omap2plus_defconfig#0270 1881 arch\arm\configs\omap2plus_defconfig#0273 1882 arch\arm\configs\omap2plus_defconfig#0274 1883 arch\arm\configs\pxa_defconfig#0414 Repo: 40a3a0f2ba63 Linus Walleij Sat Nov 19 16:15:18 2016 +0100 Description: mfd: qcom-pm8xxx: Clean up PM8XXX namespace ------The Kconfig and file naming for the PM8xxx driver is totally confusing:

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- Kconfig options MFD_PM8XXX and MFD_PM8921_CORE, some in-kernel users depending on or selecting either at random. - A driver file named pm8921-core.c even if it is indeed used by the whole PM8xxx family of chips. - An irqchip named pm8xxx since it was (I guess) realized that the driver was generic for all pm8xxx PMICs.

As I may want to add support for PM8901 this is starting to get really messy. Fix this situation by:

- Remove the MFD_PM8921_CORE symbol and rely solely on MFD_PM8XXX and convert all users, including LEDs Kconfig and ARM defconfigs for qcom and multi_v7 to use that single symbol. - Renaming the driver to qcom-pm8xxx.c to fit along the two other qcom* prefixed drivers. - Rename functions withing the driver from 8921 to 8xxx to indicate it is generic. - Just drop the =m config from the pxa_defconfig, I have no clue why it is even there, it is not a Qualcomm platform. (Possibly older Kconfig noise from saveconfig.)

1884 arch\arm\configs\qcom_defconfig#0122 Repo: 775fadd09e7b Linus Thu Dec 15 15:41:04 2016 -0800 Description: Merge tag 'armsoc-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM SoC defconfig updates from Arnd Bergmann: "Defconfig additions, removals, etc. Most of these are small changes adding the options for newly upstreamed drivers, or drivers needed for new board support.

Bartlomiej Zolnierkiewicz has done a series of patches reducing the use of CONFIG_IDE from 19 to 3 in favor of CONFIG_ATA.

Overall more patches than usual, but nothing big"

* tag 'armsoc-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (54 commits) ARM: davinci_all_defconfig: Enable da8xx usb otg ARM: defconfig: drop GPIO_SYSFS on multiplatforms ARM: multi_v7_defconfig: enable STMicroelectronics HVA driver ARM: configs: Add new config fragment to change RAM start point ARM: davinci_all_defconfig: Enable OHCI as module ARM: defconfig: turn on the DT cpufreq for Integrator ARM: omap2plus_defconfig: Run make savedefconfig to save some space ARM: davinci_all_defconfig: add missing options for systemd ARM: davinci_all_defconfig: enable the mstpri and ddrctl drivers ARM: bcm2835: add thermal driver to default config

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ARM: omap2plus_defconfig: Enable LP873X support ARM: omap2plus_defconfig: Enable REGULATOR_GPIO ARM: omap2plus_defconfig: Enable TOUCHSCREEN_TSC2004 ARM: socfpga_defconfig: enable FS configs to support Angstrom filesystem ARM: config: Enable GPIO Key driver in stm32_defconfig ARM: tegra: Enable GMI driver in default configuration ARM: tegra: Enable SGTL5000 audio ARM: tegra: Update default configuration for v4.9-rc1 ARM: socfpga: updates for socfpga_defconfig ARM: davinci_all_defconfig: enable LED default-on trigger ...

mfd: qcom-pm8xxx: Clean up PM8XXX namespace ------The Kconfig and file naming for the PM8xxx driver is totally confusing:

- Kconfig options MFD_PM8XXX and MFD_PM8921_CORE, some in-kernel users depending on or selecting either at random. - A driver file named pm8921-core.c even if it is indeed used by the whole PM8xxx family of chips. - An irqchip named pm8xxx since it was (I guess) realized that the driver was generic for all pm8xxx PMICs.

As I may want to add support for PM8901 this is starting to get really messy. Fix this situation by:

- Remove the MFD_PM8921_CORE symbol and rely solely on MFD_PM8XXX and convert all users, including LEDs Kconfig and ARM defconfigs for qcom and multi_v7 to use that single symbol. - Renaming the driver to qcom-pm8xxx.c to fit along the two other qcom* prefixed drivers. - Rename functions withing the driver from 8921 to 8xxx to indicate it is generic. - Just drop the =m config from the pxa_defconfig, I have no clue why it is even there, it is not a Qualcomm platform. (Possibly older Kconfig noise from saveconfig.)

ARM: qcom_defconfig: Fix MDM9515 LCC and GCC config ------Correct prefix is MDM instead of MSM.

Fixes: 8aa788d3e59a ("ARM: configs: qualcomm: Add MDM9615 missing defconfigs")

ARM: configs: qualcomm: Add MDM9615 missing defconfigs ------

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1885 arch\arm\configs\qcom_defconfig#0165 1886 arch\arm\configs\s3c2410_defconfig#0089 Repo: 3ef01c968fbf Krzysztof Thu Dec 29 14:41:05 2016 +0200 Description: ARM: s3c2410_defconfig: Fix invalid values for NF_CT_PROTO_* ------NF_CT_PROTO_DCCP/SCTP/UDPLITE were switched from tristate to boolean so defconfig needs to be adjusted to silence warnings: warning: symbol value 'm' invalid for NF_CT_PROTO_DCCP warning: symbol value 'm' invalid for NF_CT_PROTO_SCTP warning: symbol value 'm' invalid for NF_CT_PROTO_UDPLITE

arm: s3c2410_defconfig: convert to use libata PATA drivers ------IDE subsystem has been deprecated since 2009 and the majority (if not all) of Linux distributions have switched to use libata for ATA support exclusively. However there are still some users (mostly old or/and embedded non-x86 systems) that have not converted from using IDE subsystem to libata PATA drivers. This doesn't seem to be good thing in the long-term for Linux as while there is less and less PATA systems left in use:

* testing efforts are divided between two subsystems

* having duplicate drivers for same hardware confuses users

This patch converts s3c2410_defconfig to use libata PATA drivers.

1887 arch\arm\configs\s3c2410_defconfig#0222 1888 arch\arm\configs\s3c2410_defconfig#0229 1889 arch\arm\configs\s3c2410_defconfig#0233 1890 arch\arm\configs\s3c2410_defconfig#0236 1891 arch\arm\configs\shannon_defconfig#0028 Repo: 1a2b32e580d4 Bartlomiej Wed Oct 26 18:43:32 2016 +0200 Description: arm: shannon_defconfig: disable IDE subsystem ------This patch disables deprecated IDE subsystem in shannon_defconfig (no IDE host drivers are selected in this config so there is no valid reason to enable IDE subsystem itself).

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1892 arch\arm\configs\shmobile_defconfig#0005 Repo: a604a37d46b8 Niklas Wed Aug 10 15:17:56 2016 +0200 Description: ARM: shmobile: defconfig: Enable CONFIG_CGROUPS ------Enable support for CONFIG_CGROUPS in shmobile_defconfig.

1893 arch\arm\configs\socfpga_defconfig#0028 Repo: cab004fa972f Dinh Nguyen Tue Nov 8 15:01:22 2016 -0600 Description: ARM: socfpga_defconfig: enable FS configs to support Angstrom filesystem ------systemd on the Angstrom root file system expects AUTOFS to be configured as a module and NFSD to be statically linked into the kernel. This patch adds the necessary configuration to get rid two "FAILED" error messages during systemd startup.

ARM: socfpga: updates for socfpga_defconfig ------This patch enables the following in the socfpga_defconfig:

+CONFIG_OF_OVERLAY=y Enable support for Device Tree Overlays

+CONFIG_FPGA_REGION=y Enable device tree overlay support for FPGA programming

+CONFIG_FPGA_MGR_SOCFPGA_A10=y Enable partial reconfiguration for Altera Arria 10 FPGA

+CONFIG_FPGA_BRIDGE=y Enable the FPGA Bridges framework

+CONFIG_SOCFPGA_FPGA_BRIDGE=y Enable support for SoCFPGA hardware bridges

+CONFIG_ALTERA_FREEZE_BRIDGE=y Enable support for the Altera Soft IP Freeze bridges

ARM: socfpga_defconfig: Enable HIGHMEM ------

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All of the SoCFPGA boards have at least 1GB of RAM, so enabling HIGHMEM is necessary to avoid the following warning:

[ 0.000000] Truncating RAM at 0x00000000-0x40000000 to -0x30000000 [ 0.000000] Consider using a HIGHMEM enabled kernel.

ARM: socfpga: defconfig: enable qspi ------

ARM: socfpga: enable PL330 DMA in socfpga_defconfig ------Enable the PL330 DMA and DMATEST on SoCFPGA.

make savedefconfig says CONFIG_FHANDLE is not needed in the defconfig, remove it.

1894 arch\arm\configs\socfpga_defconfig#0054 1895 arch\arm\configs\socfpga_defconfig#0109 1896 arch\arm\configs\socfpga_defconfig#0111 1897 arch\arm\configs\socfpga_defconfig#0119 1898 arch\arm\configs\socfpga_defconfig#0126 1899 arch\arm\configs\socfpga_defconfig#0128 1900 arch\arm\configs\spitz_defconfig#0099 Repo: bc9c6cc85784 Bartlomiej Wed Oct 26 18:43:33 2016 +0200 Description: arm: spitz_defconfig: convert to use libata PATA drivers ------IDE subsystem has been deprecated since 2009 and the majority (if not all) of Linux distributions have switched to use libata for ATA support exclusively. However there are still some users (mostly old or/and embedded non-x86 systems) that have not converted from using IDE subsystem to libata PATA drivers. This doesn't seem to be good thing in the long-term for Linux as while there is less and less PATA systems left in use:

* testing efforts are divided between two subsystems

* having duplicate drivers for same hardware confuses users

This patch converts spitz_defconfig to use libata PATA drivers.

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1901 arch\arm\configs\spitz_defconfig#0107 1902 arch\arm\configs\stm32_defconfig#0041 Repo: ca16c9c8a6e4 Maxime Fri Nov 4 15:02:20 2016 +0100 Description: ARM: config: Enable GPIO Key driver in stm32_defconfig ------

ARM: config: Enable GPIO Led driver in stm32_defconfig ------

1903 arch\arm\configs\sunxi_defconfig#0101 Repo: 305dbbdcd781 Maxime Wed May 11 22:35:09 2016 +0200 Description: ARM: sunxi: Enable VGA bridge ------Enable the VGA bridge used on the A13-Olinuxino in the sunxi defconfig

1904 arch\arm\configs\tegra_defconfig#0002 Repo: dafba3f6fb86 Thierry Tue Nov 8 11:49:41 2016 +0100 Description: ARM: tegra: Enable GMI driver in default configuration ------Enable the new Tegra GMI driver for the default configuration.

ARM: tegra: Enable SGTL5000 audio ------The NVIDIA Tegra 3 aka T30 based Apalis T30 and Colibri T30 as well as the new Tegra K1 aka TK1 based Apalis TK1 modules contain a Freescale SGTL5000 analogue audio codec.

ARM: tegra: Update default configuration for v4.9-rc1 ------Regenerate the default configuration on top of v4.9-rc1. This shuffles around a couple of symbols and drops some that have become defaults or which were dropped.

1905 arch\arm\configs\tegra_defconfig#0009 1906 arch\arm\configs\tegra_defconfig#0014 1907 arch\arm\configs\tegra_defconfig#0027

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1908 arch\arm\configs\tegra_defconfig#0032 1909 arch\arm\configs\tegra_defconfig#0034 1910 arch\arm\configs\tegra_defconfig#0044 1911 arch\arm\configs\tegra_defconfig#0062 1912 arch\arm\configs\tegra_defconfig#0089 1913 arch\arm\configs\tegra_defconfig#0134 1914 arch\arm\configs\tegra_defconfig#0136 1915 arch\arm\configs\tegra_defconfig#0154 1916 arch\arm\configs\tegra_defconfig#0159 1917 arch\arm\configs\tegra_defconfig#0219 1918 arch\arm\configs\tegra_defconfig#0265 1919 arch\arm\configs\u8500_defconfig#0007 Repo: 0a53ef4bea9b Linus Walleij Mon Oct 17 11:23:49 2016 +0200 Description: ARM: defconfig: update U8500 defconfig ------Some config options like perf events and PM are now implicit, we have an upstream driver for the AK8974, and we really want the HRTIMER software triggers from with some of the sensors.

1920 arch\arm\configs\u8500_defconfig#0029 1921 arch\arm\configs\u8500_defconfig#0111 1922 arch\arm\configs\u8500_defconfig#0115 1923 arch\arm\configs\u8500_defconfig#0116 1924 arch\arm\configs\u8500_defconfig#0122 1925 arch\arm\configs\dram_0xc0000000.config#newFile Repo: 292b44c3a3eb Alexandre Tue Nov 15 15:41:35 2016 +0100 Description: ARM: configs: Add new config fragment to change RAM start point ------arch\arm\crypto\ 1926 arch\arm\crypto\aes-ce-glue.c#0015 Repo: efad2b61ae25 Herbert Xu Thu Dec 1 13:45:05 2016 +0800 Description: crypto: aes-ce - Make aes_simd_algs static ------

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The variable aes_simd_algs should be static. In fact if it isn't it causes build errors when multiple copies of aes-ce-glue.c are built into the kernel.

Fixes: da40e7a4ba4d ("crypto: aes-ce - Convert to skcipher")

crypto: aes-ce - Convert to skcipher ------This patch converts aes-ce over to the skcipher interface.

crypto: arm/aes-ce - fix for big endian ------The AES key schedule generation is mostly endian agnostic, with the exception of the rotation and the incorporation of the round constant at the start of each round. So implement a big endian specific version of that part to make the whole routine big endian compatible.

Fixes: 86464859cc77 ("crypto: arm - AES in ECB/CBC/CTR/XTS modes using ARMv8 Crypto Extensions")

1927 arch\arm\crypto\aes-ce-glue.c#0091 1928 arch\arm\crypto\aes-ce-glue.c#0094 1929 arch\arm\crypto\aes-ce-glue.c#0136 1930 arch\arm\crypto\aes-ce-glue.c#0139 1931 arch\arm\crypto\aes-ce-glue.c#0146 1932 arch\arm\crypto\aes-ce-glue.c#0155 1933 arch\arm\crypto\aes-ce-glue.c#0158 1934 arch\arm\crypto\aes-ce-glue.c#0161 1935 arch\arm\crypto\aes-ce-glue.c#0172 1936 arch\arm\crypto\aes-ce-glue.c#0176 1937 arch\arm\crypto\aes-ce-glue.c#0178 1938 arch\arm\crypto\aes-ce-glue.c#0184 1939 arch\arm\crypto\aes-ce-glue.c#0190 1940 arch\arm\crypto\aes-ce-glue.c#0196 1941 arch\arm\crypto\aes-ce-glue.c#0198 1942 arch\arm\crypto\aes-ce-glue.c#0204

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1943 arch\arm\crypto\aes-ce-glue.c#0210 1944 arch\arm\crypto\aes-ce-glue.c#0217 1945 arch\arm\crypto\aes-ce-glue.c#0220 1946 arch\arm\crypto\aes-ce-glue.c#0225 1947 arch\arm\crypto\aes-ce-glue.c#0234 1948 arch\arm\crypto\aes-ce-glue.c#0241 1949 arch\arm\crypto\aes-ce-glue.c#0244 1950 arch\arm\crypto\aes-ce-glue.c#0249 1951 arch\arm\crypto\aes-ce-glue.c#0258 1952 arch\arm\crypto\aes-ce-glue.c#0265 1953 arch\arm\crypto\aes-ce-glue.c#0268 1954 arch\arm\crypto\aes-ce-glue.c#0272 1955 arch\arm\crypto\aes-ce-glue.c#0281 1956 arch\arm\crypto\aes-ce-glue.c#0287 1957 arch\arm\crypto\aes-ce-glue.c#0291 1958 arch\arm\crypto\aes-ce-glue.c#0301 1959 arch\arm\crypto\aes-ce-glue.c#0308 1960 arch\arm\crypto\aes-ce-glue.c#0311 1961 arch\arm\crypto\aes-ce-glue.c#0313 1962 arch\arm\crypto\aes-ce-glue.c#0316 1963 arch\arm\crypto\aes-ce-glue.c#0325 1964 arch\arm\crypto\aes-ce-glue.c#0333 1965 arch\arm\crypto\aes-ce-glue.c#0336 1966 arch\arm\crypto\aes-ce-glue.c#0338 1967 arch\arm\crypto\aes-ce-glue.c#0341 1968 arch\arm\crypto\aes-ce-glue.c#0350 1969 arch\arm\crypto\aes-ce-glue.c#0358 1970 arch\arm\crypto\aes-ce-glue.c#0377 1971 arch\arm\crypto\aes-ce-glue.c#0378

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1972 arch\arm\crypto\aes-ce-glue.c#0396 1973 arch\arm\crypto\aes-ce-glue.c#0397 1974 arch\arm\crypto\aes-ce-glue.c#0415 1975 arch\arm\crypto\aes-ce-glue.c#0416 1976 arch\arm\crypto\aes-ce-glue.c#0434 1977 arch\arm\crypto\aes-ce-glue.c#0516 1978 arch\arm\crypto\aes-ce-glue.c#0518 1979 arch\arm\crypto\aes-ce-glue.c#0520 1980 arch\arm\crypto\aes-ce-glue.c#0523 1981 arch\arm\crypto\aesbs-glue.c#0013 Repo: 81126d1a8bc2 Ard Tue Nov 29 17:23:36 2016 +0000 Description: crypto: arm/aesbs - fix brokenness after skcipher conversion ------The CBC encryption routine should use the encryption round keys, not the decryption round keys.

crypto: aesbs - Convert to skcipher ------This patch converts aesbs over to the skcipher interface.

1982 arch\arm\crypto\aesbs-glue.c#0059 1983 arch\arm\crypto\aesbs-glue.c#0062 1984 arch\arm\crypto\aesbs-glue.c#0066 1985 arch\arm\crypto\aesbs-glue.c#0075 1986 arch\arm\crypto\aesbs-glue.c#0078 1987 arch\arm\crypto\aesbs-glue.c#0082 1988 arch\arm\crypto\aesbs-glue.c#0089 1989 arch\arm\crypto\aesbs-glue.c#0092 1990 arch\arm\crypto\aesbs-glue.c#0096 1991 arch\arm\crypto\aesbs-glue.c#0101 1992 arch\arm\crypto\aesbs-glue.c#0111

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1993 arch\arm\crypto\aesbs-glue.c#0114 1994 arch\arm\crypto\aesbs-glue.c#0118 1995 arch\arm\crypto\aesbs-glue.c#0121 1996 arch\arm\crypto\aesbs-glue.c#0125 1997 arch\arm\crypto\aesbs-glue.c#0129 1998 arch\arm\crypto\aesbs-glue.c#0151 1999 arch\arm\crypto\aesbs-glue.c#0155 2000 arch\arm\crypto\aesbs-glue.c#0159 2001 arch\arm\crypto\aesbs-glue.c#0173 2002 arch\arm\crypto\aesbs-glue.c#0176 2003 arch\arm\crypto\aesbs-glue.c#0180 2004 arch\arm\crypto\aesbs-glue.c#0209 2005 arch\arm\crypto\aesbs-glue.c#0213 2006 arch\arm\crypto\aesbs-glue.c#0218 2007 arch\arm\crypto\aesbs-glue.c#0238 2008 arch\arm\crypto\aesbs-glue.c#0251 2009 arch\arm\crypto\aesbs-glue.c#0258 2010 arch\arm\crypto\aesbs-glue.c#0262 2011 arch\arm\crypto\aesbs-glue.c#0266 2012 arch\arm\crypto\aesbs-glue.c#0277 2013 arch\arm\crypto\aesbs-glue.c#0282 2014 arch\arm\crypto\aesbs-glue.c#0286 2015 arch\arm\crypto\aesbs-glue.c#0290 2016 arch\arm\crypto\aesbs-glue.c#0301 2017 arch\arm\crypto\aesbs-glue.c#0306 2018 arch\arm\crypto\aesbs-glue.c#0325 2019 arch\arm\crypto\aesbs-glue.c#0326 2020 arch\arm\crypto\aesbs-glue.c#0344 2021 arch\arm\crypto\aesbs-glue.c#0345

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2022 arch\arm\crypto\aesbs-glue.c#0363 2023 arch\arm\crypto\aesbs-glue.c#0425 2024 arch\arm\crypto\aesbs-glue.c#0427 2025 arch\arm\crypto\aesbs-glue.c#0430 2026 arch\arm\crypto\aesbs-glue.c#0433 2027 arch\arm\crypto\Kconfig#0091 Repo: d0a3431a7bbd Ard Mon Dec 5 18:42:28 2016 +0000 Description: crypto: arm/crc32 - accelerated support based on x86 SSE implementation ------This is a combination of the the Intel algorithm implemented using SSE and PCLMULQDQ instructions from arch/x86/crypto/crc32-pclmul_asm.S, and the new CRC32 extensions introduced for both 32-bit and 64-bit ARM in version 8 of the architecture. Two versions of the above combo are provided, one for CRC32 and one for CRC32C.

The PMULL/NEON algorithm is faster, but operates on blocks of at least 64 bytes, and on multiples of 16 bytes only. For the remaining input, or for all input on systems that lack the PMULL 64x64->128 instructions, the CRC32 instructions will be used.

crypto: arm/crct10dif - port x86 SSE implementation to ARM ------This is a transliteration of the Intel algorithm implemented using SSE and PCLMULQDQ instructions that resides in the file arch/x86/crypto/crct10dif-pcl-asm_64.S, but simplified to only operate on buffers that are 16 byte aligned (but of any size)

crypto: arm/aes - Add missing SIMD select for aesbs ------This patch adds one more missing SIMD select for AES_ARM_BS. It also changes selects on ALGAPI to BLKCIPHER.

Fixes: 211f41af534a ("crypto: aesbs - Convert to skcipher")

crypto: arm/aes - Select SIMD in Kconfig ------The skcipher conversion for ARM missed the select on CRYPTO_SIMD, causing build failures if SIMD was not otherwise enabled.

Fixes: da40e7a4ba4d ("crypto: aes-ce - Convert to skcipher") Fixes: 211f41af534a ("crypto: aesbs - Convert to skcipher")

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2028 arch\arm\crypto\Kconfig#0093 2029 arch\arm\crypto\Kconfig#0107 2030 arch\arm\crypto\Kconfig#0123 2031 arch\arm\crypto\Makefile#0016 Repo: d0a3431a7bbd Ard Mon Dec 5 18:42:28 2016 +0000 Description: crypto: arm/crc32 - accelerated support based on x86 SSE implementation ------This is a combination of the the Intel algorithm implemented using SSE and PCLMULQDQ instructions from arch/x86/crypto/crc32-pclmul_asm.S, and the new CRC32 extensions introduced for both 32-bit and 64-bit ARM in version 8 of the architecture. Two versions of the above combo are provided, one for CRC32 and one for CRC32C.

The PMULL/NEON algorithm is faster, but operates on blocks of at least 64 bytes, and on multiples of 16 bytes only. For the remaining input, or for all input on systems that lack the PMULL 64x64->128 instructions, the CRC32 instructions will be used.

crypto: arm/crct10dif - port x86 SSE implementation to ARM ------This is a transliteration of the Intel algorithm implemented using SSE and PCLMULQDQ instructions that resides in the file arch/x86/crypto/crct10dif-pcl-asm_64.S, but simplified to only operate on buffers that are 16 byte aligned (but of any size)

2032 arch\arm\crypto\Makefile#0041 2033 arch\arm\crypto\crc32-ce-core.S#newFile Repo: d0a3431a7bbd Ard Mon Dec 5 18:42:28 2016 +0000 Description: crypto: arm/crc32 - accelerated support based on x86 SSE implementation ------This is a combination of the the Intel algorithm implemented using SSE and PCLMULQDQ instructions from arch/x86/crypto/crc32-pclmul_asm.S, and the new CRC32 extensions introduced for both 32-bit and 64-bit ARM in version 8 of the architecture. Two versions of the above combo are provided, one for CRC32 and one for CRC32C.

The PMULL/NEON algorithm is faster, but operates on blocks of at least 64 bytes, and on multiples of 16 bytes only. For the remaining input, or for all input on systems that lack the PMULL 64x64->128 instructions, the CRC32 instructions will be used.

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2034 arch\arm\crypto\crc32-ce-glue.c#newFile Repo: d0a3431a7bbd Ard Mon Dec 5 18:42:28 2016 +0000 Description: crypto: arm/crc32 - accelerated support based on x86 SSE implementation ------This is a combination of the the Intel algorithm implemented using SSE and PCLMULQDQ instructions from arch/x86/crypto/crc32-pclmul_asm.S, and the new CRC32 extensions introduced for both 32-bit and 64-bit ARM in version 8 of the architecture. Two versions of the above combo are provided, one for CRC32 and one for CRC32C.

The PMULL/NEON algorithm is faster, but operates on blocks of at least 64 bytes, and on multiples of 16 bytes only. For the remaining input, or for all input on systems that lack the PMULL 64x64->128 instructions, the CRC32 instructions will be used.

2035 arch\arm\crypto\crct10dif-ce-core.S#newFile Repo: 1d481f1cd892 Ard Mon Dec 5 18:42:26 2016 +0000 Description: crypto: arm/crct10dif - port x86 SSE implementation to ARM ------This is a transliteration of the Intel algorithm implemented using SSE and PCLMULQDQ instructions that resides in the file arch/x86/crypto/crct10dif-pcl-asm_64.S, but simplified to only operate on buffers that are 16 byte aligned (but of any size)

2036 arch\arm\crypto\crct10dif-ce-glue.c#newFile Repo: 1d481f1cd892 Ard Mon Dec 5 18:42:26 2016 +0000 Description: crypto: arm/crct10dif - port x86 SSE implementation to ARM ------This is a transliteration of the Intel algorithm implemented using SSE and PCLMULQDQ instructions that resides in the file arch/x86/crypto/crct10dif-pcl-asm_64.S, but simplified to only operate on buffers that are 16 byte aligned (but of any size)

arch\arm\include\asm\ 2037 arch\arm\include\asm\arch_gicv3.h#0025 Repo: 92116b804a02 Vladimir Wed Nov 2 11:54:07 2016 +0000 Description: ARM: gic-v3-its: Add 32bit support to GICv3 ITS ------Wire-up flush_dcache, readq- and writeq-like gic-v3-its assessors, so GICv3 ITS gets all it needs to be built and run.

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2038 arch\arm\include\asm\arch_gicv3.h#0234 Review: COMMENT stecan Thu, 11 Jan 2018 07:26:34 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:34 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:26:34 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:34 +0100 Automatic commented! 2039 arch\arm\include\asm\arch_gicv3.h#0239 2040 arch\arm\include\asm\arch_gicv3.h#0245 2041 arch\arm\include\asm\arch_gicv3.h#0254 2042 arch\arm\include\asm\cputype.h#0097 Repo: ddc37832a134 Mark RutlandFri Jan 6 13:12:47 2017 +0100 Description: ARM: 8634/1: hw_breakpoint: blacklist Scorpion CPUs ------On APQ8060, the kernel crashes in arch_hw_breakpoint_init, taking an undefined instruction trap within write_wb_reg. This is because Scorpion CPUs erroneously appear to set DBGPRSR.SPD when WFI is issued, even if the core is not powered down. When DBGPRSR.SPD is set, breakpoint and watchpoint registers are treated as undefined.

It's possible to trigger similar crashes later on from userspace, by requesting the kernel to install a breakpoint or watchpoint, as we can go idle at any point between the reset of the debug registers and their later use. This has always been the case.

Given that this has always been broken, no-one has complained until now, and there is no clear workaround, disable hardware breakpoints and watchpoints on Scorpion to avoid these issues.

2043 arch\arm\include\asm\delay.h#0012 Repo: 207b1150c00d Nicolas Pitre Fri Oct 7 05:38:35 2016 +0100 Description: ARM: 8619/1: udelay: document the various constants ------Explain where the value for UDELAY_MULT and UDELAY_SHIFT come from. Also fix/clarify some comments pertaining to their usage in the assembly code.

Review: COMMENT stecan Thu, 11 Jan 2018 07:26:34 +0100

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Short Description: stecan Thu, 11 Jan 2018 07:26:34 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:26:34 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:34 +0100 Automatic commented! 2044 arch\arm\include\asm\efi.h#0060 Repo: 3552fdf29f01 Lukas Sat Nov 12 21:32:35 2016 +0000 Description: efi: Allow bitness-agnostic protocol calls ------We already have a macro to invoke boot services which on x86 adapts automatically to the bitness of the EFI firmware: efi_call_early().

The macro allows sharing of functions across arches and bitness variants as long as those functions only call boot services. However in practice functions in the EFI stub contain a mix of boot services calls and protocol calls.

Add an efi_call_proto() macro for bitness-agnostic protocol calls to allow sharing more code across arches as well as deduplicating 32 bit and 64 bit code paths.

On x86, implement it using a new efi_table_attr() macro for bitness- agnostic table lookups. Refactor efi_call_early() to make use of the same macro. (The resulting object code remains identical.)

2045 arch\arm\include\asm\ftrace.h#0057 Repo: 270c8cf1cacc Rabin Wed Nov 23 13:02:32 2016 +0100 Description: ARM: 8632/1: ftrace: fix syscall name matching ------ARM has a few system calls (most notably mmap) for which the names of the functions which are referenced in the syscall table do not match the names of the syscall tracepoints. As a consequence of this, these tracepoints are not made available. Implement arch_syscall_match_sym_name to fix this and allow tracing even these system calls.

2046 arch\arm\include\asm\io.h#0028 Repo: fe8ecc86fa83 Christoph Tue Nov 1 07:40:14 2016 -0600 Description: arm, arm64: don't include blk_types.h in ------No need for it - we only use struct bio_vec in prototypes and already have

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forward declarations for it.

2047 arch\arm\include\asm\Kbuild#0041 Repo: ed141f2890cd Russell King Wed Dec 14 11:14:00 2016 +0000 Description: Merge branch 'syscalls' into for-linus ------Conflicts: arch/arm/include/asm/unistd.h arch/arm/include/uapi/asm/unistd.h arch/arm/kernel/calls.S

2048 arch\arm\include\asm\mach-types.h#fileDeleted Repo: 4e2648db9c5f Russell King Tue Oct 18 20:11:23 2016 +0100 Description: ARM: remove indirection of asm/mach-types.h ------Arrange for mach-types.h to be directly generated in the relevant path, so we don't need a one-liner file in arch/arm/include/asm/.

2049 arch\arm\include\asm\mutex.h#fileDeleted Repo: 890658b7ab48 Peter Zijlstra Tue Aug 23 13:36:04 2016 +0200 Description: locking/mutex: Kill arch specific code ------Its all generic atomic_long_t stuff now.

2050 arch\arm\include\asm\processor.h#0085 Repo: 6d0d287891a0 Christian Wed Nov 16 13:23:05 2016 +0100 Description: locking/core: Provide common cpu_relax_yield() definition ------No need to duplicate the same define everywhere. Since the only user is stop-machine and the only provider is s390, we can use a default implementation of cpu_relax_yield() in sched.h.

locking/core, arch: Remove cpu_relax_lowlatency() ------As there are no users left, we can remove cpu_relax_lowlatency() implementations from every architecture.

locking/core: Introduce cpu_relax_yield()

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------For spinning loops people do often use barrier() or cpu_relax(). For most architectures cpu_relax and barrier are the same, but on some architectures cpu_relax can add some latency. For example on power,sparc64 and arc, cpu_relax can shift the CPU towards other hardware threads in an SMT environment. On s390 cpu_relax does even more, it uses an hypercall to the hypervisor to give up the timeslice. In contrast to the SMT yielding this can result in larger latencies. In some places this latency is unwanted, so another variant "cpu_relax_lowlatency" was introduced. Before this is used in more and more places, lets revert the logic and provide a cpu_relax_yield that can be called in places where yielding is more important than latency. By default this is the same as cpu_relax on all architectures.

2051 arch\arm\include\asm\tlb.h#0189 Repo: 692a68c1544d Aneesh Mon Dec 12 16:42:43 2016 -0800 Description: mm: remove the page size change check in tlb_remove_page ------Now that we check for page size change early in the loop, we can partially revert e9d55e157034a ("mm: change the interface for __tlb_remove_page").

This simplies the code much, by removing the need to track the last address with which we adjusted the range. We also go back to the older way of filling the mmu_gather array, ie, we add an entry and then check whether the gather batch is full.

Link: http://lkml.kernel.org/r/20161026084839.27299-6- [email protected]

mm: add tlb_remove_check_page_size_change to track page size change ------With commit e77b0852b551 ("mm/mmu_gather: track page size with mmu gather and force flush if page size change") we added the ability to force a tlb flush when the page size change in a mmu_gather loop. We did that by checking for a page size change every time we added a page to mmu_gather for lazy flush/remove. We can improve that by moving the page size change check early and not doing it every time we add a page.

This also helps us to do tlb flush when invalidating a range covering dax mapping. Wrt dax mapping we don't have a backing struct page and hence we don't call tlb_remove_page, which earlier forced the tlb flush on page size change. Moving the page size change check earlier means we will do the same even for dax mapping.

We also avoid doing this check on architecture other than powerpc.

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In a later patch we will remove page size check from tlb_remove_page().

Link: http://lkml.kernel.org/r/20161026084839.27299-5- [email protected]

mm/hugetlb: add tlb_remove_hugetlb_entry for handling hugetlb pages ------This add tlb_remove_hugetlb_entry similar to tlb_remove_pmd_tlb_entry.

Link: http://lkml.kernel.org/r/20161026084839.27299-4- [email protected]

mm/mmu_gather: track page size with mmu gather and force flush if page size change ------This allows an arch which needs to do special handing with respect to different page size when flushing tlb to implement the same in mmu gather.

Link: http://lkml.kernel.org/r/1465049193-22197-3-git-send-email- [email protected]

2052 arch\arm\include\asm\tlb.h#0216 2053 arch\arm\include\asm\tlb.h#0220 2054 arch\arm\include\asm\tlb.h#0225 2055 arch\arm\include\asm\tlb.h#0227 2056 arch\arm\include\asm\tlb.h#0235 2057 arch\arm\include\asm\tlb.h#0287 2058 arch\arm\include\asm\types.h#fileDeleted Repo: ed79c9d34f4f Nicolas Fri Jan 13 11:46:39 2017 +0100 Description: ARM: put types.h in uapi ------Due to the way kbuild works, this header was unintentionally exported back in 2013 when it was created, despite it not being in a uapi/ directory. This is very non-intuitive behaviour by Kbuild.

However, we've had this include exported to userland for almost four years, and searching google for "ARM types.h __UINTPTR_TYPE__" gives no hint that anyone has complained about it. So, let's make it officially exported in this state.

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2059 arch\arm\include\asm\uaccess.h#0481 Repo: 32b143637e81 Kees Cook Thu Feb 16 01:43:58 2017 +0100 Description: ARM: 8657/1: uaccess: consistently check object sizes ------In commit 76624175dcae ("arm64: uaccess: consistently check object sizes"), the object size checks are moved outside the access_ok() so that bad destinations are detected before hitting the "memset(dest, 0, size)" in the copy_from_user() failure path.

This makes the same change for arm, with attention given to possibly extracting the uaccess routines into a common header file for all architectures in the future.

2060 arch\arm\include\asm\uaccess.h#0485 2061 arch\arm\include\asm\uaccess.h#0498 2062 arch\arm\include\asm\uaccess.h#0502 2063 arch\arm\include\asm\uaccess.h#0509 2064 arch\arm\include\asm\uaccess.h#0529 2065 arch\arm\include\asm\uaccess.h#0534 2066 arch\arm\include\asm\uaccess.h#0536 2067 arch\arm\include\asm\uaccess.h#0543 2068 arch\arm\include\asm\uaccess.h#0547 2069 arch\arm\include\asm\uaccess.h#0553 2070 arch\arm\include\asm\uaccess.h#0556 2071 arch\arm\include\asm\uaccess.h#0567 2072 arch\arm\include\asm\unistd.h#0017 Repo: 96a8fae0fe09 Russell King Tue Oct 18 19:57:01 2016 +0100 Description: ARM: convert to generated system call tables ------Convert ARM to use a similar mechanism to x86 to generate the unistd.h system call numbers and the various kernel system call tables. This means that rather than having to edit three places (asm/unistd.h for the total number of system calls, uapi/asm/unistd.h for the system call numbers, and arch/arm/kernel/calls.S for the call table) we have only one place to edit, making the process much more simple.

The scripts have knowledge of the table padding requirements, so there's no need to worry about __NR_syscalls not fitting within the immediate constant field of ALU instructions anymore.

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ARM: wire up preadv2 and pwritev2 syscalls ------Wire up the preadv2 and pwritev2 syscalls for ARM.

Merge branches 'fixes' and 'misc' into for-next ------

ARM: remove user cmpxchg syscall ------Mark Brand reports that a NEEDS_SYSCALL_FOR_CMPXCHG enabled kernel would open a security hole in the ghost syscall used to implement cmpxchg, as it fails to validate the user pointer.

However, in order for this option to be enabled, you'd need to be building a pre-ARMv6 kernel with SMP support. There is only one system known which fits that, which is an early ARM SMP FPGA implementation based on the ARM926T.

In any case, the Kconfig does not allow SMP to be enabled for pre-ARMv6 systems.

Moreover, even if NEEDS_SYSCALL_FOR_CMPXCHG were to be enabled, the kernel would not build as __ARM_NR_cmpxchg64 is not defined.

The simple answer is to remove the buggy code.

ARM: wire up new syscalls ------Wire up the new userfaultfd and membarrier syscalls for ARM.

ARM: wire up getrandom syscall ------Add the new getrandom syscall for ARM.

ARM: 8097/1: unistd.h: relocate comments back to place ------Commit cb8db5d45 (UAPI: (Scripted) Disintegrate arch/arm/include/asm) moved these syscall comments out of their context into the UAPI headers. Fix this.

Fixes: cb8db5d4578a ("UAPI: (Scripted) Disintegrate arch/arm/include/asm")

ARM: 8007/1: Remove extraneous kcmp syscall ignore

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------The kcmp system call was ported to ARM in commit 3f7d1fe108dbaefd0c57a41753fc2c90b395f458 "ARM: 7665/1: Wire up kcmp syscall".

Fixes: 3f7d1fe108db ("ARM: 7665/1: Wire up kcmp syscall")

sched: Add new scheduler syscalls to support an extended scheduling parameters ABI ------Add the syscalls needed for supporting scheduling algorithms with extended scheduling parameters (e.g., SCHED_DEADLINE).

In general, it makes possible to specify a periodic/sporadic task, that executes for a given amount of runtime at each instance, and is scheduled according to the urgency of their own timing constraints, i.e.:

- a (maximum/typical) instance execution time, - a minimum interval between consecutive instances, - a time constraint by which each instance must be completed.

Thus, both the data structure that holds the scheduling parameters of the tasks and the system calls dealing with it must be extended. Unfortunately, modifying the existing struct sched_param would break the ABI and result in potentially serious compatibility issues with legacy binaries.

For these reasons, this patch:

- defines the new struct sched_attr, containing all the fields that are necessary for specifying a task in the computational model described above;

- defines and implements the new scheduling related syscalls that manipulate it, i.e., sched_setattr() and sched_getattr().

Syscalls are introduced for x86 (32 and 64 bits) and ARM only, as a proof of concept and for developing and testing purposes. Making them available on other architectures is straightforward.

Since no "user" for these new parameters is introduced in this patch, the implementation of the new system calls is just identical to their already existing counterpart. Future patches that implement scheduling policies able to exploit the new data structure must also take care of modifying the sched_*attr() calls accordingly with their own purposes.

consolidate cond_syscall and SYSCALL_ALIAS declarations ------take them to asm/linkage.h, with default in linux/linkage.h

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burying unused conditionals ------__ARCH_WANT_SYS_RT_SIGACTION, __ARCH_WANT_SYS_RT_SIGSUSPEND, __ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND, __ARCH_WANT_COMPAT_SYS_SCHED_RR_GET_INTERVAL - not used anymore CONFIG_GENERIC_{SIGALTSTACK,COMPAT_RT_SIG{ACTION,QUEUEINFO, PENDING,PROCMASK}} - can be assumed always set.

Bury the conditionals from kernel_thread/kernel_execve series ------All architectures have CONFIG_GENERIC_KERNEL_THREAD CONFIG_GENERIC_KERNEL_EXECVE __ARCH_WANT_SYS_EXECVE None of them have __ARCH_WANT_KERNEL_EXECVE and there are only two callers of kernel_execve() (which is a trivial wrapper for do_execve() now) left. Kill the conditionals and make both callers use do_execve().

arm: switch to generic fork/vfork/clone ------

Merge branch 'late-for-linus' of git://git..org/people/rmk/linux-arm ------Pull ARM update from Russell King: "This is the final round of stuff for ARM, left until the end of the merge window to reduce the number of conflicts. This set contains the ARM part of David Howells UAPI changes, and a fix to the ordering of 'select' statements in ARM Kconfig files (see the appropriate commit for why this happened - thanks to Andrew Morton for pointing out the problem.)

I've left this as long as I dare for this window to avoid conflicts, and I regenerated the config patch yesterday, posting it to our mailing list for review and testing. I have several acks which include successful test reports for it.

However, today I notice we've got new conflicts with previously unseen code... though that conflict should be trivial (it's my changes vs a one liner.)"

* 'late-for-linus' of git://git.linaro.org/people/rmk/linux-arm: ARM: config: make sure that platforms are ordered by option string ARM: config: sort select statements alphanumerically

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UAPI: (Scripted) Disintegrate arch/arm/include/asm

Fix up fairly conflict in arch/arm/Kconfig (the select re-organization vs recent addition of GENERIC_KERNEL_EXECVE)

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/signal ------Pull third pile of kernel_execve() patches from Al Viro: "The last bits of infrastructure for kernel_thread() et.al., with alpha/arm/x86 use of those. Plus sanitizing the asm glue and do_notify_resume() on alpha, fixing the "disabled irq while running task_work stuff" breakage there.

At that point the rest of kernel_thread/kernel_execve/sys_execve work can be done independently for different architectures. The only pending bits that do depend on having all architectures converted are restrictred to fs/* and kernel/* - that'll obviously have to wait for the next cycle.

I thought we'd have to wait for all of them done before we start eliminating the longjump-style insanity in kernel_execve(), but it turned out there's a very simple way to do that without flagday-style changes."

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/signal: alpha: switch to saner kernel_execve() semantics arm: switch to saner kernel_execve() semantics x86, um: convert to saner kernel_execve() semantics infrastructure for saner ret_from_kernel_thread semantics make sure that kernel_thread() callbacks call do_exit() themselves make sure that we always have a return path from kernel_execve() ppc: eeh_event should just use kthread_run() don't bother with kernel_thread/kernel_execve for launching linuxrc alpha: get rid of switch_stack argument of do_work_pending() alpha: don't bother passing switch_stack separately from regs alpha: take SIGPENDING/NOTIFY_RESUME loop into signal.c alpha: simplify TIF_NEED_RESCHED handling

arm: switch to saner kernel_execve() semantics ------

UAPI: (Scripted) Disintegrate arch/arm/include/asm ------

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/signal ------

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Pull generic execve() changes from Al Viro: "This introduces the generic kernel_thread() and kernel_execve() functions, and switches x86, arm, alpha, um and s390 over to them."

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/signal: (26 commits) s390: convert to generic kernel_execve() s390: switch to generic kernel_thread() s390: fold kernel_thread_helper() into ret_from_fork() s390: fold execve_tail() into start_thread(), convert to generic sys_execve() um: switch to generic kernel_thread() x86, um/x86: switch to generic sys_execve and kernel_execve x86: split ret_from_fork alpha: introduce ret_from_kernel_execve(), switch to generic kernel_execve() alpha: switch to generic kernel_thread() alpha: switch to generic sys_execve() arm: get rid of execve wrapper, switch to generic execve() implementation arm: optimized current_pt_regs() arm: introduce ret_from_kernel_execve(), switch to generic kernel_execve() arm: split ret_from_fork, simplify kernel_thread() [based on patch by rmk] generic sys_execve() generic kernel_execve() new helper: current_pt_regs() preparation for generic kernel_thread() um: kill thread->forking um: let signal_delivered() do SIGTRAP on singlestepping into handler ...

Merge branches 'atags', 'cache-l2x0', 'clkdev', 'fixes', 'integrator', 'misc', '' and 'syscall' into for-linus ------

arm: get rid of execve wrapper, switch to generic execve() implementation ------

arm: introduce ret_from_kernel_execve(), switch to generic kernel_execve() ------

ARM: reserve syscall 378 for kcmp ------kcmp has appeared on x86, but has not been noticed because checksyscalls.sh is broken at the moment. Reserve ARM syscall 378 for this should we ever need it, and add an __IGNORE entry for this unimplemented syscall.

ARM: 7524/1: support syscall tracing

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------As specified by ftrace-design.txt, TIF_SYSCALL_TRACEPOINT was added, as well as NR_syscalls in asm/unistd.h. Additionally, __sys_trace was modified to call trace_sys_enter and trace_sys_exit when appropriate.

Tests #2 - #4 of "perf test" now complete successfully.

ipc: use Kconfig options for __ARCH_WANT_[COMPAT_]IPC_PARSE_VERSION ------Rather than #define the options manually in the architecture code, add Kconfig options for them and select them there instead. This also allows us to select the compat IPC version parsing automatically for platforms using the old compat IPC interface.

UAPI: Split trivial #if defined(__KERNEL__) && X conditionals ------Split trivial #if defined(__KERNEL__) && X conditionals to make automated disintegration easier.

ARM: wire up process_vm_writev and process_vm_readv syscalls ------These two syscalls were introduced during the last merge window. Add the entries into the ARM call tables for them.

ARM: nommu: fix warning with checksyscalls.sh ------CALL scripts/checksyscalls.sh :46:1: warning: "__IGNORE_migrate_pages" redefined In file included from :2: arch/arm/include/asm/unistd.h:482:1: warning: this is the location of the previous definition

This is caused because we define __IGNORE_migrate_pages to be 1, but in the case of nommu, it's defined to be empty. Fix this by just defining the __IGNORE_ symbols to be empty.

Merge branch 'setns' ------* setns: ns: Wire up the setns system call

Done as a merge to make it easier to fix up conflicts in arm due to addition of sendmmsg system call

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ns: Wire up the setns system call ------32bit and 64bit on x86 are tested and working. The rest I have looked at closely and I can't find any problems.

setns is an easy system call to wire up. It just takes two ints so I don't expect any weird architecture porting problems.

While doing this I have noticed that we have some architectures that are very slow to get new system calls. cris seems to be the slowest where the last system calls wired up were preadv and pwritev. avr32 is weird in that recvmmsg was wired up but never declared in unistd.h. frv is behind with perf_event_open being the last syscall wired up. On h8300 the last system call wired up was epoll_wait. On m32r the last system call wired up was fallocate. mn10300 has recvmmsg as the last system call wired up. The rest seem to at least have syncfs wired up which was new in the 2.6.39.

v2: Most of the architecture support added by Daniel Lezcano v3: ported to v2.6.36-rc4 by: Eric W. Biederman v4: Moved wiring up of the system call to another patch v5: ported to v2.6.39-rc6 v6: rebased onto parisc-next and net-next to avoid syscall conflicts. v7: ported to Linus's latest post 2.6.39 tree.

> arch/blackfin/include/asm/unistd.h | 3 ++- > arch/blackfin/mach-common/entry.S | 1 +

ARM: add sendmmsg syscall ------Commit 228e548e (net: Add sendmmsg socket system call) added the new sendmmsg syscall. Add this to the syscall table for ARM.

ARM: Add new syscalls ------Add syscalls for name_to_handle_at, open_by_handle_at, clock_adjtime and syncfs.

ARM: 6343/1: wire up fanotify and prlimit64 syscalls on ARM ------The 2.6.36-rc kernel added three new system calls: fanotify_init, fanotify_mark, and prlimit64. This patch wires them up on ARM.

The only non-trivial issue here is the u64 argument to sys_fanotify_mark(), but it is the 3rd argument and thus passed in r2/r3 in both kernel and user space, so it causes

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no problems.

Tested with a 2.6.36-rc2 EABI kernel on an ixp4xx machine.

ARM: 6329/1: wire up sys_accept4() on ARM ------sys_accept4() was added in kernel 2.6.28, but ARM was not updated to include it. The number and types of parameters is such that no ARM-specific processing is needed, so wiring up sys_accept4() just requires defining __NR_accept4 and adding a direct call in the syscall entry table.

Tested with an EABI 2.6.35 kernel and Ulrich Drepper's original accept4() test program, modified to define __NR_accept4 for ARM.

Using the updated unistd.h also eliminates a warning then building glibc (2.10.2 and newer) about accept4() being unimplemented.

Add generic sys_ipc wrapper ------Add a generic implementation of the ipc demultiplexer syscall. Except for s390 and sparc64 all implementations of the sys_ipc are nearly identical.

There are slight differences in the types of the parameters, where mips and powerpc as the only 64-bit architectures with sys_ipc use unsigned long for the "third" argument as it gets casted to a pointer later, while it traditionally is an "int" like most other paramters. frv goes even further and uses unsigned long for all parameters execept for "ptr" which is a pointer type everywhere. The change from int to unsigned long for "third" and back to "int" for the others on frv should be fine due to the in-register calling conventions for syscalls (we already had a similar issue with the generic sys_ptrace), but I'd prefer to have the arch maintainers looks over this in details.

Except for that h8300, m68k and m68knommu lack an impplementation of the semtimedop sub call which this patch adds, and various architectures have gets used - at least on i386 it seems superflous as the compat code on x86-64 and ia64 doesn't even bother to implement it.

[[email protected]: add sys_ipc to sys_ni.c]

Add generic sys_old_mmap() ------Add a generic implementation of the old mmap() syscall, which expects its argument in a memory block and switch all architectures over to use it.

Add generic sys_old_select()

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------Add a generic implementation of the old select() syscall, which expects its argument in a memory block and switch all architectures over to use it.

ARM: add missing recvmmsg syscall number ------

ARM: Use a definition for the userspace cmpxchg emulation syscall ------Use a definition for the cmpxchg SWI instead of hard-coding the number.

ARM: Fix warning: #warning syscall migrate_pages not implemented ------We're not implementing this syscall (we're not NUMA) so we might as well silence this warning.

perf: Do the big rename: Performance Counters -> Performance Events ------Bye-bye Performance Counters, welcome Performance Events!

In the past few months the perfcounters subsystem has grown out its initial role of counting hardware events, and has become (and is becoming) a much broader generic event enumeration, reporting, logging, monitoring, analysis facility.

Naming its core object 'perf_counter' and naming the subsystem 'perfcounters' has become more and more of a misnomer. With pending code like hw-breakpoints support the 'counter' name is less and less appropriate.

All in one, we've decided to rename the subsystem to 'performance events' and to propagate this rename through all fields, variables and API names. (in an ABI compatible fashion)

The word 'event' is also a bit shorter than 'counter' - which makes it slightly more convenient to write/handle as well.

Thanks goes to Stephane Eranian who first observed this misnomer and suggested a rename.

User-space tooling and ABI compatibility is not affected - this patch should be function-invariant. (Also, defconfigs were not touched to keep the size down.)

This patch has been generated via the following script:

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FILES=$(find * -type f | grep -vE 'oprofile|[^K]config')

sed -i \ -e 's/PERF_EVENT_/PERF_RECORD_/g' \ -e 's/PERF_COUNTER/PERF_EVENT/g' \ -e 's/perf_counter/perf_event/g' \ -e 's/nb_counters/nb_events/g' \ -e 's/swcounter/swevent/g' \ -e 's/tpcounter_event/tp_event/g' \ $FILES

for N in $(find . -name perf_counter.[ch]); do M=$(echo $N | sed 's/perf_counter/perf_event/g') mv $N $M done

FILES=$(find . -name perf_event.*)

sed -i \ -e 's/COUNTER_MASK/REG_MASK/g' \ -e 's/COUNTER/EVENT/g' \ -e 's/\/event_id/g' \ -e 's/counter/event/g' \ -e 's/Counter/Event/g' \ $FILES

... to keep it as correct as possible. This script can also be used by anyone who has pending perfcounters patches - it converts a Linux kernel tree over to the new naming. We tried to time this change to the point in time where the amount of pending patches is the smallest: the end of the merge window.

Namespace clashes were fixed up in a preparatory patch - and some stylistic fallout will be fixed up in a subsequent patch.

( NOTE: 'counters' are still the proper terminology when we deal with hardware registers - and these sed scripts are a bit over-eager in renaming them. I've undone some of that, but in case there's something left where 'counter' would be better than 'event' we can undo that on an individual basis instead of touching an otherwise nicely automated patch. )

ARM: 5677/1: ARM support for TIF_RESTORE_SIGMASK/pselect6/ppoll/epoll_pwait ------This patch adds support for TIF_RESTORE_SIGMASK to ARM's signal handling, which allows to hook up the pselect6, ppoll, and epoll_pwait syscalls on ARM.

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Tested here with eabi userspace and a test program with a deliberate race between a child's exit and the parent's sigprocmask/select sequence. Using sys_pselect6() instead of sigprocmask/select reliably prevents the race.

The other arch's support for TIF_RESTORE_SIGMASK has evolved over time:

In 2.6.16: - add TIF_RESTORE_SIGMASK which parallels TIF_SIGPENDING - test both when checking for pending signal [changed later] - reimplement sys_sigsuspend() to use current->saved_sigmask, TIF_RESTORE_SIGMASK [changed later], and -ERESTARTNOHAND; ditto for sys_rt_sigsuspend(), but drop private code and use common code via __ARCH_WANT_SYS_RT_SIGSUSPEND; - there are now no "extra" calls to do_signal() so its oldset parameter is always ¤t->blocked so need not be passed, also its return value is changed to void - change handle_signal() to return 0/-errno - change do_signal() to honor TIF_RESTORE_SIGMASK: + get oldset from current->saved_sigmask if TIF_RESTORE_SIGMASK is set + if handle_signal() was successful then clear TIF_RESTORE_SIGMASK + if no signal was delivered and TIF_RESTORE_SIGMASK is set then clear it and restore the sigmask - hook up sys_pselect6() and sys_ppoll()

In 2.6.19: - hook up sys_epoll_pwait()

In 2.6.26: - allow archs to override how TIF_RESTORE_SIGMASK is implemented; default set_restore_sigmask() sets both TIF_RESTORE_SIGMASK and TIF_SIGPENDING; archs need now just test TIF_SIGPENDING again when checking for pending signal work; some archs now implement TIF_RESTORE_SIGMASK as a secondary/non-atomic thread flag bit - call set_restore_sigmask() in sys_sigsuspend() instead of setting TIF_RESTORE_SIGMASK

In 2.6.29-rc: - kill sys_pselect7() which no arch wanted

So for 2.6.31-rc6/ARM this patch does the following: - Add TIF_RESTORE_SIGMASK. Use the generic set_restore_sigmask() which sets both TIF_SIGPENDING and TIF_RESTORE_SIGMASK, so TIF_RESTORE_SIGMASK need not claim one of the scarce low thread flags, and existing TIF_SIGPENDING and _TIF_WORK_MASK tests need not be extended for TIF_RESTORE_SIGMASK. - sys_sigsuspend() is reimplemented to use current->saved_sigmask and set_restore_sigmask(), making it identical to most other archs

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- The private code for sys_rt_sigsuspend() is removed, instead generic code supplies it via __ARCH_WANT_SYS_RT_SIGSUSPEND. - sys_sigsuspend() and sys_rt_sigsuspend() no longer need a pt_regs parameter, so their assembly code wrappers are removed. - handle_signal() is changed to return 0 on success or -errno. - The oldset parameter to do_signal() is now redundant and removed, and the return value is now also redundant and changed to void. - do_signal() is changed to honor TIF_RESTORE_SIGMASK: + get oldset from current->saved_sigmask if TIF_RESTORE_SIGMASK is set + if handle_signal() was successful then clear TIF_RESTORE_SIGMASK + if no signal was delivered and TIF_RESTORE_SIGMASK is set then clear it and restore the sigmask - Hook up sys_pselect6, sys_ppoll, and sys_epoll_pwait.

[ARM] wire up rt_tgsigqueueinfo and perf_counter_open ------

[ARM] 5456/1: add sys_preadv and sys_pwritev ------Kernel 2.6.30-rc1 added sys_preadv and sys_pwritev to most archs but not ARM, resulting in

:1421:2: warning: #warning syscall preadv not implemented :1425:2: warning: #warning syscall pwritev not implemented

This patch adds sys_preadv and sys_pwritev to ARM.

These syscalls simply take five long-sized parameters, so they should have no calling-convention/ABI issues in the kernel.

Tested on armv5tel eabi using a preadv/pwritev test program posted on linuxppc-dev earlier this month.

It would be nice to get this into the kernel before 2.6.30 final, so that glibc's kernel version feature test for these syscalls doesn't have to special-case ARM.

[ARM] 5193/1: Wire up missing syscalls ------Setup some missing syscall pointed out by the checksyscalls.sh script. Fix two small whitespace issues while being there.

[ARM] move include/asm-arm to arch/arm/include/asm ------Move platform independent header files to arch/arm/include/asm, leaving

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those in asm/arch* and asm/plat* alone.

2073 arch\arm\include\asm\unistd.h#0019 2074 arch\arm\include\asm\unistd.h#0055 2075 arch\arm\include\asm\virt.h#0083 Repo: 488f94d7212b Jintack Lim Thu Dec 1 14:32:05 2016 -0500 Description: KVM: arm64: Access CNTHCTL_EL2 bit fields correctly on VHE systems ------Current KVM world switch code is unintentionally setting wrong bits to CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical timer. Bit positions of CNTHCTL_EL2 are changing depending on HCR_EL2.E2H bit. EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is not set, but they are 11th and 10th bits respectively when E2H is set.

In fact, on VHE we only need to set those bits once, not for every world switch. This is because the host kernel runs in EL2 with HCR_EL2.TGE == 1, which makes those bits have no effect for the host kernel execution. So we just set those bits once for guests, and that's it.

arch\arm\include\asm\xen\ 2076 arch\arm\include\asm\xen\hypercall.h#0001 Repo: 2fbadc3002c5 Marc Zyngier Fri Dec 2 14:19:35 2016 +0000 Description: arm/arm64: xen: Move shared architecture headers to include/xen/arm ------ARM and arm64 Xen ports share a number of headers, leading to packaging issues when these headers needs to be exported, as it breaks the reasonable requirement that an architecture port has self-contained headers.

Fix the issue by moving the 5 header files to include/xen/arm, and keep local placeholders to include the relevant files.

2077 arch\arm\include\asm\xen\hypervisor.h#0001 Repo: 2fbadc3002c5 Marc Zyngier Fri Dec 2 14:19:35 2016 +0000 Description: arm/arm64: xen: Move shared architecture headers to include/xen/arm ------ARM and arm64 Xen ports share a number of headers, leading to packaging issues when these headers needs to be exported, as it breaks the reasonable requirement that an architecture port has self-contained headers.

Fix the issue by moving the 5 header files to include/xen/arm,

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and keep local placeholders to include the relevant files.

2078 arch\arm\include\asm\xen\interface.h#0001 Repo: 2fbadc3002c5 Marc Zyngier Fri Dec 2 14:19:35 2016 +0000 Description: arm/arm64: xen: Move shared architecture headers to include/xen/arm ------ARM and arm64 Xen ports share a number of headers, leading to packaging issues when these headers needs to be exported, as it breaks the reasonable requirement that an architecture port has self-contained headers.

Fix the issue by moving the 5 header files to include/xen/arm, and keep local placeholders to include the relevant files.

arm: extend pvclock_wall_clock with sec_hi ------The hypervisor actually exposes an additional field to struct pvclock_wall_clock, with the high 32 bit seconds.

2079 arch\arm\include\asm\xen\page-coherent.h#0001 Repo: 2fbadc3002c5 Marc Zyngier Fri Dec 2 14:19:35 2016 +0000 Description: arm/arm64: xen: Move shared architecture headers to include/xen/arm ------ARM and arm64 Xen ports share a number of headers, leading to packaging issues when these headers needs to be exported, as it breaks the reasonable requirement that an architecture port has self-contained headers.

Fix the issue by moving the 5 header files to include/xen/arm, and keep local placeholders to include the relevant files.

2080 arch\arm\include\asm\xen\page.h#0001 Repo: 2fbadc3002c5 Marc Zyngier Fri Dec 2 14:19:35 2016 +0000 Description: arm/arm64: xen: Move shared architecture headers to include/xen/arm ------ARM and arm64 Xen ports share a number of headers, leading to packaging issues when these headers needs to be exported, as it breaks the reasonable requirement that an architecture port has self-contained headers.

Fix the issue by moving the 5 header files to include/xen/arm, and keep local placeholders to include the relevant files.

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xen/swiotlb: Pass addresses rather than frame numbers to xen_arch_need_swiotlb ------With 64KB page granularity support, the frame number will be different.

It will be easier to modify the behavior in a single place rather than in each caller.

arm/xen: Add support for 64KB page granularity ------The hypercall interface is always using 4KB page granularity. This is requiring to use xen page definition macro when we deal with hypercall.

Note that pfn_to_gfn is working with a Xen pfn (i.e 4KB). We may want to rename pfn_gfn to make this explicit.

We also allocate a 64KB page for the shared page even though only the first 4KB is used. I don't think this is really important for now as it helps to have the pointer 4KB aligned (XENMEM_add_to_physmap is taking a Xen PFN).

arch\arm\include\uapi\asm\ 2081 arch\arm\include\uapi\asm\Kbuild#0021 Repo: 96a8fae0fe09 Russell King Tue Oct 18 19:57:01 2016 +0100 Description: ARM: convert to generated system call tables ------Convert ARM to use a similar mechanism to x86 to generate the unistd.h system call numbers and the various kernel system call tables. This means that rather than having to edit three places (asm/unistd.h for the total number of system calls, uapi/asm/unistd.h for the system call numbers, and arch/arm/kernel/calls.S for the call table) we have only one place to edit, making the process much more simple.

The scripts have knowledge of the table padding requirements, so there's no need to worry about __NR_syscalls not fitting within the immediate constant field of ALU instructions anymore.

2082 arch\arm\include\uapi\asm\kvm.h#0090 Repo: 2988509dd8a0 Vladimir Wed Nov 2 11:55:34 2016 +0000 Description: ARM: KVM: Support vGICv3 ITS ------This patch allows to build and use vGICv3 ITS in 32-bit mode.

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2083 arch\arm\include\uapi\asm\kvm.h#0094 2084 arch\arm\include\uapi\asm\unistd.h#0020 Repo: 96a8fae0fe09 Russell King Tue Oct 18 19:57:01 2016 +0100 Description: ARM: convert to generated system call tables ------Convert ARM to use a similar mechanism to x86 to generate the unistd.h system call numbers and the various kernel system call tables. This means that rather than having to edit three places (asm/unistd.h for the total number of system calls, uapi/asm/unistd.h for the system call numbers, and arch/arm/kernel/calls.S for the call table) we have only one place to edit, making the process much more simple.

The scripts have knowledge of the table padding requirements, so there's no need to worry about __NR_syscalls not fitting within the immediate constant field of ALU instructions anymore.

ARM: wire up preadv2 and pwritev2 syscalls ------Wire up the preadv2 and pwritev2 syscalls for ARM.

ARM: wire up copy_file_range() syscall ------Add the copy_file_range() syscall to ARM.

ARM: wire up mlock2 syscall ------

ARM: wire up new syscalls ------Wire up the new userfaultfd and membarrier syscalls for ARM.

ARM: wire up execveat syscall ------

ARM: enable bpf syscall ------

ARM: wire up memfd_create syscall ------Add the memfd_create syscall to ARM.

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ARM: wire up getrandom syscall ------Add the new getrandom syscall for ARM.

Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/linux-security ------Pull security subsystem updates from James Morris: "In this release:

- PKCS#7 parser for the key management subsystem from David Howells - appoint Kees Cook as maintainer - bugfixes and general maintenance across the subsystem"

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/linux-security: (94 commits) X.509: Need to export x509_request_asymmetric_key() netlabel: shorter names for the NetLabel catmap funcs/structs netlabel: fix the catmap walking functions netlabel: fix the horribly broken catmap functions netlabel: fix a problem when setting bits below the previously lowest bit PKCS#7: X.509 certificate issuer and subject are mandatory fields in the ASN.1 tpm: simplify code by using %*phN specifier tpm: Provide a generic means to override the chip returned timeouts tpm: missing tpm_chip_put in tpm_get_random() tpm: Properly clean sysfs entries in error path tpm: Add missing tpm_do_selftest to ST33 I2C driver PKCS#7: Use x509_request_asymmetric_key() Revert "selinux: fix the default socket labeling in sock_graft()" X.509: x509_request_asymmetric_keys() doesn't need string length arguments PKCS#7: fix sparse non static symbol warning KEYS: revert encrypted key change ima: add support for measuring and appraising firmware firmware_class: perform new LSM checks security: introduce kernel_fw_from_file hook PKCS#7: Missing inclusion of linux/err.h ...

ARM: add seccomp syscall ------Wires up the new seccomp syscall.

ARM: 8097/1: unistd.h: relocate comments back to place ------Commit cb8db5d45 (UAPI: (Scripted) Disintegrate arch/arm/include/asm) moved these syscall comments out of their context into the UAPI headers. Fix this.

Fixes: cb8db5d4578a ("UAPI: (Scripted) Disintegrate arch/arm/include/asm")

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ARM: add renameat2 syscall ------

sched: Add new scheduler syscalls to support an extended scheduling parameters ABI ------Add the syscalls needed for supporting scheduling algorithms with extended scheduling parameters (e.g., SCHED_DEADLINE).

In general, it makes possible to specify a periodic/sporadic task, that executes for a given amount of runtime at each instance, and is scheduled according to the urgency of their own timing constraints, i.e.:

- a (maximum/typical) instance execution time, - a minimum interval between consecutive instances, - a time constraint by which each instance must be completed.

Thus, both the data structure that holds the scheduling parameters of the tasks and the system calls dealing with it must be extended. Unfortunately, modifying the existing struct sched_param would break the ABI and result in potentially serious compatibility issues with legacy binaries.

For these reasons, this patch:

- defines the new struct sched_attr, containing all the fields that are necessary for specifying a task in the computational model described above;

- defines and implements the new scheduling related syscalls that manipulate it, i.e., sched_setattr() and sched_getattr().

Syscalls are introduced for x86 (32 and 64 bits) and ARM only, as a proof of concept and for developing and testing purposes. Making them available on other architectures is straightforward.

Since no "user" for these new parameters is introduced in this patch, the implementation of the new system calls is just identical to their already existing counterpart. Future patches that implement scheduling policies able to exploit the new data structure must also take care of modifying the sched_*attr() calls accordingly with their own purposes.

ARM: 7665/1: Wire up kcmp syscall ------Wire up kcmp syscall for ability to proceed checkpoint/restore procedure on ARM platform.

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ARM: add finit_module syscall to ARM ------Add finit_module syscall to the ARM syscall list.

UAPI: (Scripted) Disintegrate arch/arm/include/asm ------

2085 arch\arm\include\uapi\asm\unistd.h#0023 2086 arch\arm\include\uapi\asm\unistd.h#0026 2087 arch\arm\include\uapi\asm\unistd.h#0371 2088 arch\arm\include\uapi\asm\unistd.h#0437 2089 arch\arm\include\uapi\asm\types.h#newFile Repo: ed79c9d34f4f Nicolas Fri Jan 13 11:46:39 2017 +0100 Description: ARM: put types.h in uapi ------Due to the way kbuild works, this header was unintentionally exported back in 2013 when it was created, despite it not being in a uapi/ directory. This is very non-intuitive behaviour by Kbuild.

However, we've had this include exported to userland for almost four years, and searching google for "ARM types.h __UINTPTR_TYPE__" gives no hint that anyone has complained about it. So, let's make it officially exported in this state.

arch\arm\kernel\ 2090 arch\arm\kernel\calls.S#fileDeleted Repo: 96a8fae0fe09 Russell King Tue Oct 18 19:57:01 2016 +0100 Description: ARM: convert to generated system call tables ------Convert ARM to use a similar mechanism to x86 to generate the unistd.h system call numbers and the various kernel system call tables. This means that rather than having to edit three places (asm/unistd.h for the total number of system calls, uapi/asm/unistd.h for the system call numbers, and arch/arm/kernel/calls.S for the call table) we have only one place to edit, making the process much more simple.

The scripts have knowledge of the table padding requirements, so there's no need to worry about __NR_syscalls not fitting within the immediate constant field of ALU instructions anymore.

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ARM: wire up preadv2 and pwritev2 syscalls ------Wire up the preadv2 and pwritev2 syscalls for ARM.

ARM: wire up copy_file_range() syscall ------Add the copy_file_range() syscall to ARM.

ARM: wire up mlock2 syscall ------

ARM: wire up new syscalls ------Wire up the new userfaultfd and membarrier syscalls for ARM.

ARM: wire up execveat syscall ------

ARM: enable bpf syscall ------

ARM: wire up memfd_create syscall ------Add the memfd_create syscall to ARM.

ARM: wire up getrandom syscall ------Add the new getrandom syscall for ARM.

ARM: add seccomp syscall ------Wires up the new seccomp syscall.

ARM: add renameat2 syscall ------

sched: Add new scheduler syscalls to support an extended scheduling parameters ABI ------Add the syscalls needed for supporting scheduling algorithms

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with extended scheduling parameters (e.g., SCHED_DEADLINE).

In general, it makes possible to specify a periodic/sporadic task, that executes for a given amount of runtime at each instance, and is scheduled according to the urgency of their own timing constraints, i.e.:

- a (maximum/typical) instance execution time, - a minimum interval between consecutive instances, - a time constraint by which each instance must be completed.

Thus, both the data structure that holds the scheduling parameters of the tasks and the system calls dealing with it must be extended. Unfortunately, modifying the existing struct sched_param would break the ABI and result in potentially serious compatibility issues with legacy binaries.

For these reasons, this patch:

- defines the new struct sched_attr, containing all the fields that are necessary for specifying a task in the computational model described above;

- defines and implements the new scheduling related syscalls that manipulate it, i.e., sched_setattr() and sched_getattr().

Syscalls are introduced for x86 (32 and 64 bits) and ARM only, as a proof of concept and for developing and testing purposes. Making them available on other architectures is straightforward.

Since no "user" for these new parameters is introduced in this patch, the implementation of the new system calls is just identical to their already existing counterpart. Future patches that implement scheduling policies able to exploit the new data structure must also take care of modifying the sched_*attr() calls accordingly with their own purposes.

ARM: 7665/1: Wire up kcmp syscall ------Wire up kcmp syscall for ability to proceed checkpoint/restore procedure on ARM platform.

arm: switch to generic sigaltstack ------

Merge tag 'modules-next-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rusty/linux ------

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Pull module update from : "Nothing all that exciting; a new module-from-fd syscall for those who want to verify the source of the module (ChromeOS) and/or use standard IMA on it or other security hooks."

* tag 'modules-next-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rusty/linux: MODSIGN: Fix kbuild output when using default extra_certificates MODSIGN: Avoid using .incbin in C source modules: don't hand 0 to vmalloc. module: Remove a extra null character at the top of module->strtab. ASN.1: Use the ASN1_LONG_TAG and ASN1_INDEFINITE_LENGTH constants ASN.1: Define indefinite length marker constant moduleparam: use __UNIQUE_ID() __UNIQUE_ID() MODSIGN: Add modules_sign make target powerpc: add finit_module syscall. ima: support new kernel module syscall add finit_module syscall to asm-generic ARM: add finit_module syscall to ARM security: introduce kernel_module_from_file hook module: add flags arg to sys_finit_module() module: add syscall to load module from fd

ARM: add finit_module syscall to ARM ------Add finit_module syscall to the ARM syscall list.

arm: switch to generic fork/vfork/clone ------

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/signal ------Pull generic execve() changes from Al Viro: "This introduces the generic kernel_thread() and kernel_execve() functions, and switches x86, arm, alpha, um and s390 over to them."

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/signal: (26 commits) s390: convert to generic kernel_execve() s390: switch to generic kernel_thread() s390: fold kernel_thread_helper() into ret_from_fork() s390: fold execve_tail() into start_thread(), convert to generic sys_execve() um: switch to generic kernel_thread() x86, um/x86: switch to generic sys_execve and kernel_execve x86: split ret_from_fork alpha: introduce ret_from_kernel_execve(), switch to generic kernel_execve() alpha: switch to generic kernel_thread() alpha: switch to generic sys_execve()

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arm: get rid of execve wrapper, switch to generic execve() implementation arm: optimized current_pt_regs() arm: introduce ret_from_kernel_execve(), switch to generic kernel_execve() arm: split ret_from_fork, simplify kernel_thread() [based on patch by rmk] generic sys_execve() generic kernel_execve() new helper: current_pt_regs() preparation for generic kernel_thread() um: kill thread->forking um: let signal_delivered() do SIGTRAP on singlestepping into handler ...

arm: get rid of execve wrapper, switch to generic execve() implementation ------

ARM: reserve syscall 378 for kcmp ------kcmp has appeared on x86, but has not been noticed because checksyscalls.sh is broken at the moment. Reserve ARM syscall 378 for this should we ever need it, and add an __IGNORE entry for this unimplemented syscall.

ARM: wire up process_vm_writev and process_vm_readv syscalls ------These two syscalls were introduced during the last merge window. Add the entries into the ARM call tables for them.

All Arch: remove linkage for sys_nfsservctl system call ------The nfsservctl system call is now gone, so we should remove all linkage for it.

Merge branch 'setns' ------* setns: ns: Wire up the setns system call

Done as a merge to make it easier to fix up conflicts in arm due to addition of sendmmsg system call

ns: Wire up the setns system call ------32bit and 64bit on x86 are tested and working. The rest I have looked at closely and I can't find any problems.

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setns is an easy system call to wire up. It just takes two ints so I don't expect any weird architecture porting problems.

While doing this I have noticed that we have some architectures that are very slow to get new system calls. cris seems to be the slowest where the last system calls wired up were preadv and pwritev. avr32 is weird in that recvmmsg was wired up but never declared in unistd.h. frv is behind with perf_event_open being the last syscall wired up. On h8300 the last system call wired up was epoll_wait. On m32r the last system call wired up was fallocate. mn10300 has recvmmsg as the last system call wired up. The rest seem to at least have syncfs wired up which was new in the 2.6.39.

v2: Most of the architecture support added by Daniel Lezcano v3: ported to v2.6.36-rc4 by: Eric W. Biederman v4: Moved wiring up of the system call to another patch v5: ported to v2.6.39-rc6 v6: rebased onto parisc-next and net-next to avoid syscall conflicts. v7: ported to Linus's latest post 2.6.39 tree.

> arch/blackfin/include/asm/unistd.h | 3 ++- > arch/blackfin/mach-common/entry.S | 1 +

ARM: add sendmmsg syscall ------Commit 228e548e (net: Add sendmmsg socket system call) added the new sendmmsg syscall. Add this to the syscall table for ARM.

ARM: Add new syscalls ------Add syscalls for name_to_handle_at, open_by_handle_at, clock_adjtime and syncfs.

ARM: 6343/1: wire up fanotify and prlimit64 syscalls on ARM ------The 2.6.36-rc kernel added three new system calls: fanotify_init, fanotify_mark, and prlimit64. This patch wires them up on ARM.

The only non-trivial issue here is the u64 argument to sys_fanotify_mark(), but it is the 3rd argument and thus passed in r2/r3 in both kernel and user space, so it causes no problems.

Tested with a 2.6.36-rc2 EABI kernel on an ixp4xx machine.

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ARM: 6329/1: wire up sys_accept4() on ARM ------sys_accept4() was added in kernel 2.6.28, but ARM was not updated to include it. The number and types of parameters is such that no ARM-specific processing is needed, so wiring up sys_accept4() just requires defining __NR_accept4 and adding a direct call in the syscall entry table.

Tested with an EABI 2.6.35 kernel and Ulrich Drepper's original accept4() test program, modified to define __NR_accept4 for ARM.

Using the updated unistd.h also eliminates a warning then building glibc (2.10.2 and newer) about accept4() being unimplemented.

Add generic sys_old_mmap() ------Add a generic implementation of the old mmap() syscall, which expects its argument in a memory block and switch all architectures over to use it.

Add generic sys_old_select() ------Add a generic implementation of the old select() syscall, which expects its argument in a memory block and switch all architectures over to use it.

arm: add arch_mmap_check(), get rid of sys_arm_mremap() ------

net: Introduce recvmmsg socket syscall ------Meaning receive multiple messages, reducing the number of syscalls and net stack entry/exit operations.

Next patches will introduce mechanisms where protocols that want to optimize this operation will provide an unlocked_recvmsg operation.

This takes into account comments made by:

. Paul Moore: sock_recvmsg is called only for the first datagram, sock_recvmsg_nosec is used for the rest.

. Caitlin Bestler: recvmmsg now has a struct timespec timeout, that works in the same fashion as the ppoll one.

If the underlying protocol returns a datagram with MSG_OOB set, this will make recvmmsg return right away with as many datagrams (+ the OOB

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one) it has received so far.

. Rémi Denis-Courmont & Steven Whitehouse: If we receive N < vlen datagrams and then recvmsg returns an error, recvmmsg will return the successfully received datagrams, store the error and return it in the next call.

This paves the way for a subsequent optimization, sk_prot->unlocked_recvmsg, where we will be able to acquire the lock only at batch start and end, not at every underlying recvmsg call.

perf: Do the big rename: Performance Counters -> Performance Events ------Bye-bye Performance Counters, welcome Performance Events!

In the past few months the perfcounters subsystem has grown out its initial role of counting hardware events, and has become (and is becoming) a much broader generic event enumeration, reporting, logging, monitoring, analysis facility.

Naming its core object 'perf_counter' and naming the subsystem 'perfcounters' has become more and more of a misnomer. With pending code like hw-breakpoints support the 'counter' name is less and less appropriate.

All in one, we've decided to rename the subsystem to 'performance events' and to propagate this rename through all fields, variables and API names. (in an ABI compatible fashion)

The word 'event' is also a bit shorter than 'counter' - which makes it slightly more convenient to write/handle as well.

Thanks goes to Stephane Eranian who first observed this misnomer and suggested a rename.

User-space tooling and ABI compatibility is not affected - this patch should be function-invariant. (Also, defconfigs were not touched to keep the size down.)

This patch has been generated via the following script:

FILES=$(find * -type f | grep -vE 'oprofile|[^K]config')

sed -i \ -e 's/PERF_EVENT_/PERF_RECORD_/g' \ -e 's/PERF_COUNTER/PERF_EVENT/g' \ -e 's/perf_counter/perf_event/g' \ -e 's/nb_counters/nb_events/g' \ -e 's/swcounter/swevent/g' \

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-e 's/tpcounter_event/tp_event/g' \ $FILES

for N in $(find . -name perf_counter.[ch]); do M=$(echo $N | sed 's/perf_counter/perf_event/g') mv $N $M done

FILES=$(find . -name perf_event.*)

sed -i \ -e 's/COUNTER_MASK/REG_MASK/g' \ -e 's/COUNTER/EVENT/g' \ -e 's/\/event_id/g' \ -e 's/counter/event/g' \ -e 's/Counter/Event/g' \ $FILES

... to keep it as correct as possible. This script can also be used by anyone who has pending perfcounters patches - it converts a Linux kernel tree over to the new naming. We tried to time this change to the point in time where the amount of pending patches is the smallest: the end of the merge window.

Namespace clashes were fixed up in a preparatory patch - and some stylistic fallout will be fixed up in a subsequent patch.

( NOTE: 'counters' are still the proper terminology when we deal with hardware registers - and these sed scripts are a bit over-eager in renaming them. I've undone some of that, but in case there's something left where 'counter' would be better than 'event' we can undo that on an individual basis instead of touching an otherwise nicely automated patch. )

ARM: 5677/1: ARM support for TIF_RESTORE_SIGMASK/pselect6/ppoll/epoll_pwait ------This patch adds support for TIF_RESTORE_SIGMASK to ARM's signal handling, which allows to hook up the pselect6, ppoll, and epoll_pwait syscalls on ARM.

Tested here with eabi userspace and a test program with a deliberate race between a child's exit and the parent's sigprocmask/select sequence. Using sys_pselect6() instead of sigprocmask/select reliably prevents the race.

The other arch's support for TIF_RESTORE_SIGMASK has evolved over time:

In 2.6.16:

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- add TIF_RESTORE_SIGMASK which parallels TIF_SIGPENDING - test both when checking for pending signal [changed later] - reimplement sys_sigsuspend() to use current->saved_sigmask, TIF_RESTORE_SIGMASK [changed later], and -ERESTARTNOHAND; ditto for sys_rt_sigsuspend(), but drop private code and use common code via __ARCH_WANT_SYS_RT_SIGSUSPEND; - there are now no "extra" calls to do_signal() so its oldset parameter is always ¤t->blocked so need not be passed, also its return value is changed to void - change handle_signal() to return 0/-errno - change do_signal() to honor TIF_RESTORE_SIGMASK: + get oldset from current->saved_sigmask if TIF_RESTORE_SIGMASK is set + if handle_signal() was successful then clear TIF_RESTORE_SIGMASK + if no signal was delivered and TIF_RESTORE_SIGMASK is set then clear it and restore the sigmask - hook up sys_pselect6() and sys_ppoll()

In 2.6.19: - hook up sys_epoll_pwait()

In 2.6.26: - allow archs to override how TIF_RESTORE_SIGMASK is implemented; default set_restore_sigmask() sets both TIF_RESTORE_SIGMASK and TIF_SIGPENDING; archs need now just test TIF_SIGPENDING again when checking for pending signal work; some archs now implement TIF_RESTORE_SIGMASK as a secondary/non-atomic thread flag bit - call set_restore_sigmask() in sys_sigsuspend() instead of setting TIF_RESTORE_SIGMASK

In 2.6.29-rc: - kill sys_pselect7() which no arch wanted

So for 2.6.31-rc6/ARM this patch does the following: - Add TIF_RESTORE_SIGMASK. Use the generic set_restore_sigmask() which sets both TIF_SIGPENDING and TIF_RESTORE_SIGMASK, so TIF_RESTORE_SIGMASK need not claim one of the scarce low thread flags, and existing TIF_SIGPENDING and _TIF_WORK_MASK tests need not be extended for TIF_RESTORE_SIGMASK. - sys_sigsuspend() is reimplemented to use current->saved_sigmask and set_restore_sigmask(), making it identical to most other archs - The private code for sys_rt_sigsuspend() is removed, instead generic code supplies it via __ARCH_WANT_SYS_RT_SIGSUSPEND. - sys_sigsuspend() and sys_rt_sigsuspend() no longer need a pt_regs parameter, so their assembly code wrappers are removed. - handle_signal() is changed to return 0 on success or -errno. - The oldset parameter to do_signal() is now redundant and removed, and the return value is now also redundant and changed to void. - do_signal() is changed to honor TIF_RESTORE_SIGMASK: + get oldset from current->saved_sigmask if TIF_RESTORE_SIGMASK

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is set + if handle_signal() was successful then clear TIF_RESTORE_SIGMASK + if no signal was delivered and TIF_RESTORE_SIGMASK is set then clear it and restore the sigmask - Hook up sys_pselect6, sys_ppoll, and sys_epoll_pwait.

[ARM] wire up rt_tgsigqueueinfo and perf_counter_open ------

[ARM] 5456/1: add sys_preadv and sys_pwritev ------Kernel 2.6.30-rc1 added sys_preadv and sys_pwritev to most archs but not ARM, resulting in

:1421:2: warning: #warning syscall preadv not implemented :1425:2: warning: #warning syscall pwritev not implemented

This patch adds sys_preadv and sys_pwritev to ARM.

These syscalls simply take five long-sized parameters, so they should have no calling-convention/ABI issues in the kernel.

Tested on armv5tel eabi using a preadv/pwritev test program posted on linuxppc-dev earlier this month.

It would be nice to get this into the kernel before 2.6.30 final, so that glibc's kernel version feature test for these syscalls doesn't have to special-case ARM.

[CVE-2009-0029] Rename old_readdir to sys_old_readdir ------This way it matches the generic system call name convention.

[ARM] 5193/1: Wire up missing syscalls ------Setup some missing syscall pointed out by the checksyscalls.sh script. Fix two small whitespace issues while being there.

Merge branch 'omap2-upstream' into devel ------

[ARM] 4852/1: Add timerfd_create, timerfd_settime and timerfd_gettime syscall entries ------

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[ARM] 4878/1: Add oabi shim for fstatat64 ------Ccoreutils and other have started using fstatat64. Thus, we need a shim for it if we want to support modern oldabi userlands (such as Debian/arm/lenny) with EABI kernels.

See http://bugs.debian.org/462677

timerfd: new timerfd API ------This is the new timerfd API as it is implemented by the following patch:

int timerfd_create(int clockid, int flags); int timerfd_settime(int ufd, int flags, const struct itimerspec *utmr, struct itimerspec *otmr); int timerfd_gettime(int ufd, struct itimerspec *otmr);

The timerfd_create() API creates an un-programmed timerfd fd. The "clockid" parameter can be either CLOCK_MONOTONIC or CLOCK_REALTIME.

The timerfd_settime() API give new settings by the timerfd fd, by optionally retrieving the previous expiration time (in case the "otmr" parameter is not NULL).

The time value specified in "utmr" is absolute, if the TFD_TIMER_ABSTIME bit is set in the "flags" parameter. Otherwise it's a relative time.

The timerfd_gettime() API returns the next expiration time of the timer, or {0, 0} if the timerfd has not been set yet.

Like the previous timerfd API implementation, read(2) and poll(2) are supported (with the same interface). Here's a simple test program I used to exercise the new timerfd APIs:

http://www.xmailserver.org/timerfd-test2.c

[[email protected]: coding-style cleanups] [[email protected]: fix ia64 build] [[email protected]: fix m68k build] [[email protected]: fix mips build] [[email protected]: fix alpha, arm, blackfin, cris, m68k, s390, sparc and sparc64 builds] [[email protected]: fix s390] [[email protected]: fix powerpc build] [[email protected]: fix sparc64 more]

[ARM] Add fallocate syscall entry

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------

Introduce fixed sys_sync_file_range2() syscall, implement on PowerPC and ARM ------Not all the world is an i386. Many architectures need 64-bit arguments to be aligned in suitable pairs of registers, and the original sys_sync_file_range(int, loff_t, loff_t, int) was therefore wasting an argument register for padding after the first integer. Since we don't normally have more than 6 arguments for system calls, that left no room for the final argument on some architectures.

Fix this by introducing sys_sync_file_range2(int, int, loff_t, loff_t) which all fits nicely. In fact, ARM already had that, but called it sys_arm_sync_file_range. Move it to fs/sync.c and rename it, then implement the needed compatibility routine. And stop the missing syscall check from bitching about the absence of sys_sync_file_range() if we've implemented sys_sync_file_range2() instead.

Tested on PPC32 and with 32-bit and 64-bit userspace on PPC64.

[ARM] Update ARM syscalls ------Add utimensat, signalfd, timerfd, eventfd syscalls. Add ignore defines for sync_file_range and fadvise64_64 which we implement differently.

[ARM] 4137/1: Add kexec support ------Add kexec support to ARM.

Improvements like commandline handling could be made but this patch gives basic functional support. It uses the next available syscall number, 347.

Once the syscall number is known, userspace support will be finalised/submitted to kexec-tools, various patches already exist.

Originally based on a patch by Maxim Syrchin but updated and forward ported by various people.

[ARM] Add more syscalls ------Add: sys_unshare sys_set_robust_list sys_get_robust_list sys_splice

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sys_arm_sync_file_range sys_tee sys_vmsplice sys_move_pages sys_getcpu

Special note about sys_arm_sync_file_range(), which is implemented as:

asmlinkage long sys_arm_sync_file_range(int fd, unsigned int flags, loff_t offset, loff_t nbytes) { return sys_sync_file_range(fd, offset, nbytes, flags); }

We can't export sys_sync_file_range() directly on ARM because the argument list someone picked does not fit in the available registers. Would be nice if... there was an arch maintainer review mechanism for new syscalls before they hit the kernel.

[ARM] Add sys_*at syscalls ------Later glibc requires the *at syscalls. Add them.

[ARM] 3338/1: old ABI compat: sys_socketcall ------Patch from Nicolas Pitre

Commit 99595d0237926b5aba1fe4c844a011a1ba1ee1f8 forgot to intercept sys_socketcall as well.

[ARM] 3308/1: old ABI compat: struct sockaddr_un ------Patch from Nicolas Pitre

struct sockaddr_un loses its padding with EABI. Since the size of the structure is used as a validation test in unix_mkname(), we need to change the length argument to 110 whenever it is 112.

[ARM] safer handling of syscall table padding ------ARM entry-common.S needs to know syscall table size; in itself that would not be a problem, but there's an additional constraint - some of the instructions using it want a constant that would be a multiple of 4. So we have to pad syscall table with sys_ni_syscall and that's where the trouble begins. .rept pseudo-op wants a constant expression for number of repetitions and subtraction of two labels (before and after

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syscall table) doesn't always get simplified to constant early enough for .rept. If labels end up in different frags, we lose. And while the frag size is large enough (slightly below 4Kb), the syscall table is about 1/3 of that. We used to get away with that, but the recent changes had been enough to trigger the breakage.

Proper fix is simple: have a macro (CALL(x)) to populate the table instead of using explicit .long x and the first time we include calls.S have it defined to .equ NR_syscalls,NR_syscalls+1. Then we can find the proper amount of padding on the first inclusion simply by looking at NR_syscalls at that time. And that will be constant, no matter what.

Moreover, the same trick kills the need of having an estimate of padded NR_syscalls - it will be calculated for free at the same time.

[ARM] 3110/5: old ABI compat: multi-ABI syscall entry support ------Patch from Nicolas Pitre

This patch adds the required code to support both user space ABIs at the same time. A second syscall table is created to include legacy ABI syscalls that need an ABI compat wrapper.

[ARM] 3108/2: old ABI compat: statfs64 and fstatfs64 ------Patch from Nicolas Pitre

struct statfs64 has extra padding with EABI growing its size from 84 to 88. This struct is now __attribute__((packed,aligned(4))) with a small assembly wrapper to force the sz argument to 84 if it is 88 to avoid copying the extra padding over user space memory unexpecting it.

[ARM] Fix sys_sendto and sys_recvfrom 6-arg syscalls ------Rather than providing more wrappers for 6-arg syscalls, arrange for them to be supported as standard. This just means that we always store the 6th argument on the stack, rather than in the wrappers.

This means we eliminate the wrappers for: * sys_futex * sys_arm_fadvise64_64 * sys_mbind * sys_ipc

[ARM] 2896/1: Add sys_ipc_wrapper to pass 'fifth' argument on stack ------

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Patch from George G. Davis

As pointed out be Matthew Klahn , some sys_ipc() call options require six args, e.g. SEMTIMEDOP. This patch adds an ARM sys_ipc_wrapper to save the sys_ipc() 'fifth' arg on the stack.

[ARM] sys_mbind needs wrapping ------sys_mbind is a 6-arg syscall, hence needs wrapping to save the sixth argument.

[ARM] Add memory type based allocation syscalls ------Add syscall numbers and syscall table entries for mbind, set_mempolicy and get_mempolicy.

[ARM] 2865/2: fix fadvise64_64 syscall argument passing ------Patch from Nicolas Pitre

The prototype for sys_fadvise64_64() is: long sys_fadvise64_64(int fd, loff_t offset, loff_t len, int advice) The argument list is therefore as follows on legacy ABI: fd: type int (r0) offset: type long long (r1-r2) len: type long long (r3-sp[0]) advice: type int (sp[4]) With EABI this becomes: fd: type int (r0) offset: type long long (r2-r3) len: type long long (sp[0]-sp[4]) advice: type int (sp[8]) Not only do we have ABI differences here, but the EABI version requires one additional word on the syscall stack. To avoid the ABI mismatch and the extra stack space required with EABI this syscall is now defined with a different argument ordering on ARM as follows: long sys_arm_fadvise64_64(int fd, int advice, loff_t offset, loff_t len) This gives us the following ABI independent argument distribution: fd: type int (r0) advice: type int (r1) offset: type long long (r2-r3) len: type long long (sp[0]-sp[4]) Now, since the syscall entry code takes care of 5 registers only by default including the store of r4 to the stack, we need a wrapper to store r5 to the stack as well. Because that wrapper was missing and was always required this means that sys_fadvise64_64 never worked on ARM and

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therefore we can safely reuse its syscall number for our new sys_arm_fadvise64_64 interface.

[ARM] Add syscall stubs for and ioprio system calls ------

Linux-2.6.12-rc2 ------Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it.

Let it rip!

2091 arch\arm\kernel\entry-common.S#0015 Repo: 96a8fae0fe09 Russell King Tue Oct 18 19:57:01 2016 +0100 Description: ARM: convert to generated system call tables ------Convert ARM to use a similar mechanism to x86 to generate the unistd.h system call numbers and the various kernel system call tables. This means that rather than having to edit three places (asm/unistd.h for the total number of system calls, uapi/asm/unistd.h for the system call numbers, and arch/arm/kernel/calls.S for the call table) we have only one place to edit, making the process much more simple.

The scripts have knowledge of the table padding requirements, so there's no need to worry about __NR_syscalls not fitting within the immediate constant field of ALU instructions anymore.

2092 arch\arm\kernel\entry-common.S#0019 2093 arch\arm\kernel\entry-common.S#0128 2094 arch\arm\kernel\entry-common.S#0294 2095 arch\arm\kernel\entry-common.S#0317 2096 arch\arm\kernel\entry-common.S#0320 2097 arch\arm\kernel\entry-common.S#0322

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2098 arch\arm\kernel\entry-common.S#0324 2099 arch\arm\kernel\entry-common.S#0327 2100 arch\arm\kernel\entry-common.S#0426 2101 arch\arm\kernel\entry-common.S#0431 2102 arch\arm\kernel\hw_breakpoint.c#0928 Repo: ddc37832a134 Mark RutlandFri Jan 6 13:12:47 2017 +0100 Description: ARM: 8634/1: hw_breakpoint: blacklist Scorpion CPUs ------On APQ8060, the kernel crashes in arch_hw_breakpoint_init, taking an undefined instruction trap within write_wb_reg. This is because Scorpion CPUs erroneously appear to set DBGPRSR.SPD when WFI is issued, even if the core is not powered down. When DBGPRSR.SPD is set, breakpoint and watchpoint registers are treated as undefined.

It's possible to trigger similar crashes later on from userspace, by requesting the kernel to install a breakpoint or watchpoint, as we can go idle at any point between the reset of the debug registers and their later use. This has always been the case.

Given that this has always been broken, no-one has complained until now, and there is no clear workaround, disable hardware breakpoints and watchpoints on Scorpion to avoid these issues.

ARM/hw_breakpoint: Convert to hotplug state machine ------Install the callbacks via the state machine and let the core invoke the callbacks on the already online CPUs.

smp_call_function_single() has been removed because the function is already invoked on the target CPU.

[ tglx: Added protection agaist hotplug back according to discussion with Will ]

2103 arch\arm\kernel\hw_breakpoint.c#0930 2104 arch\arm\kernel\hw_breakpoint.c#1023 2105 arch\arm\kernel\hw_breakpoint.c#1026 2106 arch\arm\kernel\hw_breakpoint.c#1032 2107 arch\arm\kernel\hw_breakpoint.c#1041

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2108 arch\arm\kernel\hw_breakpoint.c#1062 2109 arch\arm\kernel\hw_breakpoint.c#1069 2110 arch\arm\kernel\hw_breakpoint.c#1088 2111 arch\arm\kernel\hw_breakpoint.c#1093 2112 arch\arm\kernel\hw_breakpoint.c#1097 Review: COMMENT stecan Thu, 11 Jan 2018 07:26:36 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:36 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:26:36 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:36 +0100 Automatic commented! 2113 arch\arm\kernel\hw_breakpoint.c#1101 2114 arch\arm\kernel\hw_breakpoint.c#1104 2115 arch\arm\kernel\hw_breakpoint.c#1107 2116 arch\arm\kernel\hw_breakpoint.c#1127 2117 arch\arm\kernel\hw_breakpoint.c#1129 2118 arch\arm\kernel\ptrace.c#0603 Repo: 228dbbfb5d77 Dave Martin Wed Jan 18 17:11:56 2017 +0100 Description: ARM: 8643/3: arm/ptrace: Preserve previous registers for short regset write ------Ensure that if userspace supplies insufficient data to PTRACE_SETREGSET to fill all the registers, the thread's old registers are preserved.

arm/ptrace: run seccomp after ptrace ------Close the hole where ptrace can change a syscall out from under seccomp.

2119 arch\arm\kernel\smp_tlb.c#0012 Repo: 90f92c631b21 Linus Walleij Tue Sep 13 12:31:17 2016 +0100 Description: ARM: 8613/1: Fix the uaccess crash on PB11MPCore ------The following patch was sketched by Russell in response to my crashes on the PB11MPCore after the patch for software-based priviledged no access support for ARMv8.1. See this thread: http://marc.info/?l=linux-arm-kernel&m=144051749807214&w=2

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I am unsure what is going on, I suspect everyone involved in the discussion is. I just want to repost this to get the discussion restarted, as I still have to apply this patch with every kernel iteration to get my PB11MPCore Realview running.

Testing by Neil Armstrong on the Oxnas NAS has revealed that this bug exist also on that widely deployed hardware, so we are probably currently regressing all ARM11MPCore systems.

2120 arch\arm\kernel\smp_tlb.c#0044 2121 arch\arm\kernel\smp_tlb.c#0047 2122 arch\arm\kernel\smp_tlb.c#0061 2123 arch\arm\kernel\smp_tlb.c#0064 2124 arch\arm\kernel\smp_twd.c#0342 Repo: 73c1b41e63f0 Thomas Wed Dec 21 20:19:54 2016 +0100 Description: cpu/hotplug: Cleanup state names ------When the state names got added a script was used to add the extra argument to the calls. The script basically converted the state constant to a string, but the cleanup to convert these strings into meaningful ones did not happen.

Replace all the useless strings with 'subsys/xxx/yyy:state' strings which are used in all the other places already.

2125 arch\arm\kernel\swp_emulate.c#0032 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

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2126 arch\arm\kernel\topology.c#0015 Repo: 7e5930aaef5d Juri Lelli Sun Nov 6 01:34:31 2016 +0100 Description: ARM: 8622/3: add sysfs cpu_capacity attribute ------Add a sysfs cpu_capacity attribute with which it is possible to read and write (thus over-writing default values) CPUs capacity. This might be useful in situations where values needs changing after boot.

The new attribute shows up as:

/sys/devices/system/cpu/cpu*/cpu_capacity

ARM: 8621/3: parse cpu capacity-dmips-mhz from DT ------With the introduction of cpu capacity-dmips-mhz bindings, CPU capacities can now be calculated from values extracted from DT and information coming from cpufreq. Add parsing of DT information at boot time, and complement it with cpufreq information. We keep code that can produce same information, based on different DT properties and hard-coded values, as fall-back for backward compatibility.

Caveat: the information provided by this patch will start to be used in the future. We need to #define arch_scale_cpu_capacity to something provided in arch, so that scheduler's default implementation (which gets used if arch_scale_cpu_capacity is not defined) is overwritten.

2127 arch\arm\kernel\topology.c#0025 2128 arch\arm\kernel\topology.c#0027 2129 arch\arm\kernel\topology.c#0047 2130 arch\arm\kernel\topology.c#0059 2131 arch\arm\kernel\topology.c#0144 2132 arch\arm\kernel\topology.c#0149 2133 arch\arm\kernel\topology.c#0305 2134 arch\arm\kernel\topology.c#0322 2135 arch\arm\kernel\topology.c#0370 2136 arch\arm\kernel\topology.c#0381 arch\arm\kvm\ 2137 arch\arm\kvm\arm.c#0036 Repo: 488f94d7212b Jintack Lim Thu Dec 1 14:32:05 2016 -0500

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Description: KVM: arm64: Access CNTHCTL_EL2 bit fields correctly on VHE systems ------Current KVM world switch code is unintentionally setting wrong bits to CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical timer. Bit positions of CNTHCTL_EL2 are changing depending on HCR_EL2.E2H bit. EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is not set, but they are 11th and 10th bits respectively when E2H is set.

In fact, on VHE we only need to set those bits once, not for every world switch. This is because the host kernel runs in EL2 with HCR_EL2.TGE == 1, which makes those bits have no effect for the host kernel execution. So we just set those bits once for guests, and that's it.

Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

ARM: KVM: Support vGICv3 ITS ------This patch allows to build and use vGICv3 ITS in 32-bit mode.

arm/arm64: KVM: Perform local TLB invalidation when multiplexing vcpus on a single CPU ------Architecturally, TLBs are private to the (physical) CPU they're associated with. But when multiple vcpus from the same VM are being multiplexed on the same CPU, the TLBs are not private to the vcpus (and are actually shared across the VMID).

Let's consider the following scenario:

- vcpu-0 maps PA to VA - vcpu-1 maps PA' to VA

If run on the same physical CPU, vcpu-1 can hit TLB entries generated by vcpu-0 accesses, and access the wrong physical page.

The solution to this is to keep a per-VM map of which vcpu ran last on each given physical CPU, and invalidate local TLBs when switching to a different vcpu from the same VM.

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2138 arch\arm\kvm\arm.c#0224 2139 arch\arm\kvm\arm.c#1102 2140 arch\arm\kvm\guest.c#0026 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

2141 arch\arm\kvm\Kconfig#0037 Repo: 2988509dd8a0 Vladimir Wed Nov 2 11:55:34 2016 +0000 Description: ARM: KVM: Support vGICv3 ITS ------This patch allows to build and use vGICv3 ITS in 32-bit mode.

2142 arch\arm\kvm\Makefile#0035 Repo: 2988509dd8a0 Vladimir Wed Nov 2 11:55:34 2016 +0000 Description: ARM: KVM: Support vGICv3 ITS ------This patch allows to build and use vGICv3 ITS in 32-bit mode.

arch\arm\mach-artpec\ 2143 arch\arm\mach-artpec\Kconfig#0017 Repo: 048f789b9531 Niklas Fri Oct 14 15:08:08 2016 +0200 Description: ARM: ARTPEC-6: add select MFD_SYSCON to MACH_ARTPEC6 ------Since the ARTPEC-6 machine port already uses syscon, MACH_ARTPEC6 should select MFD_SYSCON.

arch\arm\mach-bcm\ 2144 arch\arm\mach-bcm\bcm_5301x.c#0012 Repo: 09f3510fb70a Rafa Miecki Sat Oct 29 13:12:29 2016 +0200

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Description: ARM: BCM5301X: Add back handler ignoring external imprecise aborts ------Since early BCM5301X days we got abort handler that was removed by commit 937b12306ea79 ("ARM: BCM5301X: remove workaround imprecise abort fault handler"). It assumed we need to deal only with pending aborts left by the bootloader. Unfortunately this isn't true for BCM5301X.

When probing PCI config space (device enumeration) it is expected to have master aborts on the PCI bus. Most bridges don't forward (or they allow disabling it) these errors onto the AXI/AMBA bus but not the Northstar (BCM5301X) one.

iProc PCIe controller on Northstar seems to be some older one, without a control register for errors forwarding. It means we need to workaround this at platform level. All newer platforms are not affected by this issue.

2145 arch\arm\mach-bcm\bcm_5301x.c#0015 2146 arch\arm\mach-bcm\bcm_5301x.c#0024 2147 arch\arm\mach-bcm\bcm_5301x.c#0049 arch\arm\mach-davinci\ 2148 arch\arm\mach-davinci\board-da830-evm.c#0017 Repo: b5e1438cf98a Axel Haslam Thu Nov 24 16:04:54 2016 +0100 Description: ARM: davinci: da830-evm: use gpio descriptor for mmc pins ------Currently the mmc driver is polling the gpio to know if the card was removed.

By using a gpio descriptor instead of the platform callbacks, the driver will be able to register the gpio using the mmc core APIs designed for this purpose.

This has the advantage that an irq will be registered, and polling is no longer needed. Also, a dependency on platform callbacks is removed for this board.

ARM: davinci: da8xx: add usb phy clocks ------Up to this point, the USB phy clock configuration was handled manually in the board files and in the usb drivers. This adds proper clocks so that the usb drivers can use clk_get and clk_enable and not have to worry about the details. Also, the related code is removed from the board files and replaced with the new clock registration functions.

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This also removes the #if IS_ENABLED(CONFIG_USB_MUSB_HDRC) around the musb declaration and renames the musb platform device so that we can reference it from the usb20 clock even if the musb device is not used.

ARM: davinci: da8xx: Add USB PHY platform device ------There is now a proper phy driver for the DA8xx SoC USB PHY. This adds the platform device declarations needed to use it.

ARM: davinci: da8xx: Add full regulator constraints for non-DT boot ------The phy framework requests an optional "phy" regulator. If it does not find one, it returns -EPROBE_DEFER. In the case of non-DT boot for the omap138-lcdk board, this would prevent the usb11 phy to probe correctly and ohci would not enumerate.

By calling regulator_has_full_constraints(), An error would be returned instead of -EPROBE_DEFER for the regulator, and the probe of the phy driver can continue normally without a regulator.

ARM: davinci: da8xx: Add CFGCHIP syscon platform device ------The CFGCHIP registers are used by a number of devices, so use a syscon device to share them. The first consumer of this will be the phy-da8xx-usb driver.

Add the syscon device and register it.

ARM: davinci: da8xx: Remove duplicated defines ------Some macro for DA8xx CFGCHIP are defined in usb-davinci.h, but da8xx-cfgchip.h intend to replace them. Remove duplicated defines between da8xx-cfgchip.h and usb-davinci.h

2149 arch\arm\mach-davinci\board-da830-evm.c#0031 2150 arch\arm\mach-davinci\board-da830-evm.c#0111 2151 arch\arm\mach-davinci\board-da830-evm.c#0113 2152 arch\arm\mach-davinci\board-da830-evm.c#0119

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2153 arch\arm\mach-davinci\board-da830-evm.c#0124 2154 arch\arm\mach-davinci\board-da830-evm.c#0130 2155 arch\arm\mach-davinci\board-da830-evm.c#0225 2156 arch\arm\mach-davinci\board-da830-evm.c#0228 2157 arch\arm\mach-davinci\board-da830-evm.c#0239 2158 arch\arm\mach-davinci\board-da830-evm.c#0256 2159 arch\arm\mach-davinci\board-da830-evm.c#0264 2160 arch\arm\mach-davinci\board-da830-evm.c#0275 2161 arch\arm\mach-davinci\board-da830-evm.c#0591 2162 arch\arm\mach-davinci\board-da830-evm.c#0650 2163 arch\arm\mach-davinci\board-da850-evm.c#0018 Repo: 196249beabe3 Arnd Wed Nov 30 14:48:30 2016 +0100 Description: Merge tag 'davinci-for-v4.10/soc-3' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc ------Pull "DaVinci SoC updates for v4.10 (part 3)" from Sekhar Nori:

mach-davinci SoC support updates to adjust USB ohci device name to that used by drivers and update of various board files to use gpio descriptor API used by MMC subsystem for card detect and write-protect detection.

* tag 'davinci-for-v4.10/soc-3' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux- davinci: ARM: davinci: da830-evm: use gpio descriptor for mmc pins ARM: davinci: da850-evm: use gpio descriptor for mmc pins ARM: davinci: hawk: use gpio descriptor for mmc pins ARM: davinci: da8xx: Fix ohci device name

Merge tag 'davinci-for-v4.10/cleanup-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc ------Pull DaVinci cleanup for v4.10 from Sekhar Nori:

mach-davinci cleanup to make it easy to add PM support for DT-boot.

* tag 'davinci-for-v4.10/cleanup-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: ARM: davinci: PM: fix build when da850 not compiled in ARM: davinci: PM: cleanup: remove references to pdata

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ARM: davinci: PM: rework init, remove platform device

ARM: davinci: da850-evm: use gpio descriptor for mmc pins ------Currently the mmc driver is polling the gpio to know if the card was removed.

By using a gpio descriptor instead of the platform callbacks, the driver will be able to register the gpio using the mmc core APIs designed for this purpose.

This has the advantage that an irq will be registered, and polling is no longer needed. Also, a dependency on platform callbacks is removed for this board.

ARM: davinci: PM: rework init, remove platform device ------Remove fake platform device used for PM init. Move pdata values which are common across all current platforms into pm.c.

Also, since PM is only used on da8xx, remove davinci_pm_init() from common init code, and only use in da850/omapl138 board files that are currently creating the fake platform_device.

ARM: davinci: da8xx: Add CFGCHIP syscon platform device ------The CFGCHIP registers are used by a number of devices, so use a syscon device to share them. The first consumer of this will be the phy-da8xx-usb driver.

Add the syscon device and register it.

2164 arch\arm\mach-davinci\board-da850-evm.c#0060 2165 arch\arm\mach-davinci\board-da850-evm.c#0199 2166 arch\arm\mach-davinci\board-da850-evm.c#0779 2167 arch\arm\mach-davinci\board-da850-evm.c#0784 2168 arch\arm\mach-davinci\board-da850-evm.c#0790 2169 arch\arm\mach-davinci\board-da850-evm.c#1348 2170 arch\arm\mach-davinci\board-da850-evm.c#1382

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2171 arch\arm\mach-davinci\board-da850-evm.c#1388 2172 arch\arm\mach-davinci\board-da850-evm.c#1456 2173 arch\arm\mach-davinci\board-mityomapl138.c#0501 Repo: e264ae280ce1 Arnd Wed Nov 30 14:45:31 2016 +0100 Description: Merge tag 'davinci-for-v4.10/cleanup-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc ------Pull DaVinci cleanup for v4.10 from Sekhar Nori:

mach-davinci cleanup to make it easy to add PM support for DT-boot.

* tag 'davinci-for-v4.10/cleanup-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: ARM: davinci: PM: fix build when da850 not compiled in ARM: davinci: PM: cleanup: remove references to pdata ARM: davinci: PM: rework init, remove platform device

ARM: davinci: PM: rework init, remove platform device ------Remove fake platform device used for PM init. Move pdata values which are common across all current platforms into pm.c.

Also, since PM is only used on da8xx, remove davinci_pm_init() from common init code, and only use in da850/omapl138 board files that are currently creating the fake platform_device.

ARM: davinci: da8xx: Add CFGCHIP syscon platform device ------The CFGCHIP registers are used by a number of devices, so use a syscon device to share them. The first consumer of this will be the phy-da8xx-usb driver.

Add the syscon device and register it.

ARM: davinci: only use NVMEM when available ------The davinci platform contains code that calls into the nvmem subsystem, but that might be a loadable module, causing a link error:

arch/arm/mach-davinci/built-in.o: In function `davinci_get_mac_addr': :(.text+0x1088): undefined reference to `nvmem_device_read' arch/arm/mach-davinci/built-in.o: In function `read_factory_config':

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:(.text+0x214c): undefined reference to `nvmem_device_read'

Also, when NVMEM is completely disabled, the functions fail with nonobvious error messages.

This ensures we only call the API functions when the code is actually reachable from the board file, and otherwise prints a unique log message.

2174 arch\arm\mach-davinci\board-mityomapl138.c#0517 2175 arch\arm\mach-davinci\board-mityomapl138.c#0558 2176 arch\arm\mach-davinci\board-omapl138-hawk.c#0016 Repo: c69f43fb4f26 Axel Haslam Thu Nov 24 16:04:52 2016 +0100 Description: ARM: davinci: hawk: use gpio descriptor for mmc pins ------Currently the mmc driver is polling the gpio to know if the card was removed.

By using a gpio descriptor instead of the platform callbacks, the driver will be able to register the gpio using the mmc core APIs designed for this purpose.

This has the advantage that an irq will be registered, and polling is no longer needed. Also, a dependency on platform callbacks is removed for this board.

ARM: davinci: da8xx: add usb phy clocks ------Up to this point, the USB phy clock configuration was handled manually in the board files and in the usb drivers. This adds proper clocks so that the usb drivers can use clk_get and clk_enable and not have to worry about the details. Also, the related code is removed from the board files and replaced with the new clock registration functions.

This also removes the #if IS_ENABLED(CONFIG_USB_MUSB_HDRC) around the musb declaration and renames the musb platform device so that we can reference it from the usb20 clock even if the musb device is not used.

ARM: davinci: da8xx: Add USB PHY platform device ------There is now a proper phy driver for the DA8xx SoC USB PHY. This adds the platform device declarations needed to use it.

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ARM: davinci: da8xx: Add full regulator constraints for non-DT boot ------The phy framework requests an optional "phy" regulator. If it does not find one, it returns -EPROBE_DEFER. In the case of non-DT boot for the omap138-lcdk board, this would prevent the usb11 phy to probe correctly and ohci would not enumerate.

By calling regulator_has_full_constraints(), An error would be returned instead of -EPROBE_DEFER for the regulator, and the probe of the phy driver can continue normally without a regulator.

ARM: davinci: da8xx: Add CFGCHIP syscon platform device ------The CFGCHIP registers are used by a number of devices, so use a syscon device to share them. The first consumer of this will be the phy-da8xx-usb driver.

Add the syscon device and register it.

ARM: davinci: da8xx: Remove duplicated defines ------Some macro for DA8xx CFGCHIP are defined in usb-davinci.h, but da8xx-cfgchip.h intend to replace them. Remove duplicated defines between da8xx-cfgchip.h and usb-davinci.h

2177 arch\arm\mach-davinci\board-omapl138-hawk.c#0018 2178 arch\arm\mach-davinci\board-omapl138-hawk.c#0029 2179 arch\arm\mach-davinci\board-omapl138-hawk.c#0125 2180 arch\arm\mach-davinci\board-omapl138-hawk.c#0134 2181 arch\arm\mach-davinci\board-omapl138-hawk.c#0136 2182 arch\arm\mach-davinci\board-omapl138-hawk.c#0153 2183 arch\arm\mach-davinci\board-omapl138-hawk.c#0161 2184 arch\arm\mach-davinci\board-omapl138-hawk.c#0178 2185 arch\arm\mach-davinci\board-omapl138-hawk.c#0246 2186 arch\arm\mach-davinci\board-omapl138-hawk.c#0254 2187 arch\arm\mach-davinci\board-omapl138-hawk.c#0256

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2188 arch\arm\mach-davinci\board-omapl138-hawk.c#0261 2189 arch\arm\mach-davinci\board-omapl138-hawk.c#0295 2190 arch\arm\mach-davinci\board-omapl138-hawk.c#0320 2191 arch\arm\mach-davinci\clock.c#0034 Repo: 48cd30b49527 Alexandre Fri Dec 9 17:59:32 2016 +0100 Description: ARM: davinci: Make __clk_{enable,disable} functions public ------In some cases, there is a need to enable a clock as part of clock enable callback of a different clock. For example, USB 2.0 PHY clock enable requires USB 2.0 clock to be enabled. In this case, it is safe to instead call __clk_enable() since the clock framework lock is already taken. Calling clk_enable() causes recursive locking error.

A similar case arises in the clock disable path.

To enable such usage, make __clk_{enable,disable} functions publicly available outside of clock.c. Also, call them davinci_clk_{enable|disable} now to be consistent with how other davinci-specific clock functions are named.

Note that these functions are not exported to drivers. They are meant for usage in platform specific clock management code.

2192 arch\arm\mach-davinci\clock.c#0037 2193 arch\arm\mach-davinci\clock.c#0047 2194 arch\arm\mach-davinci\clock.c#0059 2195 arch\arm\mach-davinci\clock.c#0106 2196 arch\arm\mach-davinci\clock.c#0121 2197 arch\arm\mach-davinci\clock.h#0135 Repo: 48cd30b49527 Alexandre Fri Dec 9 17:59:32 2016 +0100 Description: ARM: davinci: Make __clk_{enable,disable} functions public ------In some cases, there is a need to enable a clock as part of clock enable callback of a different clock. For example, USB 2.0 PHY clock enable requires USB 2.0 clock to be enabled. In this case, it is safe to instead call __clk_enable() since the clock framework lock is already taken. Calling clk_enable() causes recursive locking error.

A similar case arises in the clock disable path.

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To enable such usage, make __clk_{enable,disable} functions publicly available outside of clock.c. Also, call them davinci_clk_{enable|disable} now to be consistent with how other davinci-specific clock functions are named.

Note that these functions are not exported to drivers. They are meant for usage in platform specific clock management code.

2198 arch\arm\mach-davinci\common.c#0121 Repo: aa9aa1ec2df6 Kevin HilmanTue Nov 15 11:54:19 2016 -0800 Description: ARM: davinci: PM: rework init, remove platform device ------Remove fake platform device used for PM init. Move pdata values which are common across all current platforms into pm.c.

Also, since PM is only used on da8xx, remove davinci_pm_init() from common init code, and only use in da850/omapl138 board files that are currently creating the fake platform_device.

2199 arch\arm\mach-davinci\da830.c#0415 Repo: 8439a1d77d07 Axel Haslam Thu Nov 3 17:03:06 2016 +0100 Description: ARM: davinci: da8xx: Fix ohci device name ------While the clk lookup table is making reference to "ohci" other subsystems (such as phy) are trying to match "ohci.0"

Since there is a single ohci instance, instead of changing the clk name, change the dev id to -1, and add the "-da8xx" postfix to match the driver name that will also be changed in a subsequent patch.

ARM: davinci: da8xx: Add USB device names to clock lookup tables ------This adds device names for the SoC USB devices to the clock lookup tables in da830.c and da850.c.

Also add the USB device names to the da850_auxdata_lookup[] table.

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2200 arch\arm\mach-davinci\da830.c#0423 2201 arch\arm\mach-davinci\da850.c#0322 Repo: ef37427ac567 Bartosz Wed Dec 7 16:22:16 2016 +0100 Description: ARM: davinci: da850: don't add emac clock to lookup table twice ------Similarly to the aemif clock - this screws up the linked list of clock children. Create a separate clock for mdio inheriting the rate from emac_clk.

ARM: davinci: da850: fix infinite loop in clk_set_rate() ------The aemif clock is added twice to the lookup table in da850.c. This breaks the children list of pll0_sysclk3 as we're using the same list links in struct clk. When calling clk_set_rate(), we get stuck in propagate_rate().

Create a separate clock for nand, inheriting the rate of the aemif clock and retrieve it in the davinci_nand module.

Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM SoC platform updates from Arnd Bergmann: "These are updates for platform specific code on 32-bit ARM machines, essentially anything that can not (yet) be expressed using DT files.

Noteworthy changes include:

- Added support for the TI DRA71x family of SoCs in mach-omap2, this is an new variant of the the DRA72x/DRA74x automotive infotainment chips we already supported for a while.

- Added support for the ST STM32F746 SoC, the first Cortex-M7 based microcontroller we support, related to the smaller STM32F4 family.

- Renesas adds support for r8a7743 and r8a7745 in mach-shmobile, see http://elinux.org/RZ-G

- SMP is now supported on the OX820 platform

- A lot of code in mach-omap2 gets removed as a follow-up to removing support for board files in the previous release

- Davinci has some new work to improve USB support

- For i.MX, the performance monitor now supports profiling the memory controller using 'perf'"

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* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (95 commits) ARM: davinci: da830-evm: use gpio descriptor for mmc pins ARM: davinci: da850-evm: use gpio descriptor for mmc pins ARM: davinci: hawk: use gpio descriptor for mmc pins ARM: ARTPEC-6: add select MFD_SYSCON to MACH_ARTPEC6 ARM: davinci: da8xx: Fix ohci device name ARM: oxnas: Add OX820 config and makefile entry ARM: oxnas: Add OX820 SMP support ARM: davinci: PM: fix build when da850 not compiled in ARM: orion5x: remove legacy support of ls-chl ARM: integrator: drop EBI access use syscon ARM: BCM5301X: Add back handler ignoring external imprecise aborts ARM: davinci: PM: support da8xx DT platforms ARM: davinci: PM: cleanup: remove references to pdata ARM: davinci: PM: rework init, remove platform device ARM: Kconfig: Introduce MACH_STM32F746 flag ARM: mach-stm32: Add a new SOC - STM32F746 ARM: shmobile: document SK-RZG1E board ARM: shmobile: r8a7745: basic SoC support ARM: imx: mach-imx6ul: add imx6ull support ARM: zynq: Reserve correct amount of non-DMA RAM ...

Merge tag 'davinci-for-v4.10/soc-3' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc ------Pull "DaVinci SoC updates for v4.10 (part 3)" from Sekhar Nori:

mach-davinci SoC support updates to adjust USB ohci device name to that used by drivers and update of various board files to use gpio descriptor API used by MMC subsystem for card detect and write-protect detection.

* tag 'davinci-for-v4.10/soc-3' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux- davinci: ARM: davinci: da830-evm: use gpio descriptor for mmc pins ARM: davinci: da850-evm: use gpio descriptor for mmc pins ARM: davinci: hawk: use gpio descriptor for mmc pins ARM: davinci: da8xx: Fix ohci device name

Merge tag 'davinci-for-v4.10/cleanup-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc ------Pull DaVinci cleanup for v4.10 from Sekhar Nori:

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mach-davinci cleanup to make it easy to add PM support for DT-boot.

* tag 'davinci-for-v4.10/cleanup-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: ARM: davinci: PM: fix build when da850 not compiled in ARM: davinci: PM: cleanup: remove references to pdata ARM: davinci: PM: rework init, remove platform device

ARM: davinci: da8xx: Fix ohci device name ------While the clk lookup table is making reference to "ohci" other subsystems (such as phy) are trying to match "ohci.0"

Since there is a single ohci instance, instead of changing the clk name, change the dev id to -1, and add the "-da8xx" postfix to match the driver name that will also be changed in a subsequent patch.

ARM: davinci: PM: rework init, remove platform device ------Remove fake platform device used for PM init. Move pdata values which are common across all current platforms into pm.c.

Also, since PM is only used on da8xx, remove davinci_pm_init() from common init code, and only use in da850/omapl138 board files that are currently creating the fake platform_device.

ARM: davinci: da850: Fix pwm name matching ------This fixes pwm name matching for DA850 familiy devices. When using device tree, the da850_auxdata_lookup[] table caused pwm devices to have the exact same name, which caused errors when trying to register the devices.

We cannot have multiple entries for the same clock in in da850_clks[], so we have added child clocks to the EHRPWM and ECAP LPSC clocks so that each PWM device will have its own clock for proper name matching.

ARM: davinci: da8xx: Add USB device names to clock lookup tables ------This adds device names for the SoC USB devices to the clock lookup tables in da830.c and da850.c.

Also add the USB device names to the da850_auxdata_lookup[] table.

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2202 arch\arm\mach-davinci\da850.c#0380 2203 arch\arm\mach-davinci\da850.c#0447 2204 arch\arm\mach-davinci\da850.c#0484 2205 arch\arm\mach-davinci\da850.c#0501 2206 arch\arm\mach-davinci\da850.c#0552 2207 arch\arm\mach-davinci\da850.c#0560 2208 arch\arm\mach-davinci\da850.c#0576 2209 arch\arm\mach-davinci\da850.c#1245 2210 arch\arm\mach-davinci\da8xx-dt.c#0026 Repo: e79ab194d15e Linus Thu Dec 15 15:39:02 2016 -0800 Description: Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM SoC platform updates from Arnd Bergmann: "These are updates for platform specific code on 32-bit ARM machines, essentially anything that can not (yet) be expressed using DT files.

Noteworthy changes include:

- Added support for the TI DRA71x family of SoCs in mach-omap2, this is an new variant of the the DRA72x/DRA74x automotive infotainment chips we already supported for a while.

- Added support for the ST STM32F746 SoC, the first Cortex-M7 based microcontroller we support, related to the smaller STM32F4 family.

- Renesas adds support for r8a7743 and r8a7745 in mach-shmobile, see http://elinux.org/RZ-G

- SMP is now supported on the OX820 platform

- A lot of code in mach-omap2 gets removed as a follow-up to removing support for board files in the previous release

- Davinci has some new work to improve USB support

- For i.MX, the performance monitor now supports profiling the memory controller using 'perf'"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (95 commits) ARM: davinci: da830-evm: use gpio descriptor for mmc pins ARM: davinci: da850-evm: use gpio descriptor for mmc pins ARM: davinci: hawk: use gpio descriptor for mmc pins ARM: ARTPEC-6: add select MFD_SYSCON to MACH_ARTPEC6

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ARM: davinci: da8xx: Fix ohci device name ARM: oxnas: Add OX820 config and makefile entry ARM: oxnas: Add OX820 SMP support ARM: davinci: PM: fix build when da850 not compiled in ARM: orion5x: remove legacy support of ls-chl ARM: integrator: drop EBI access use syscon ARM: BCM5301X: Add back handler ignoring external imprecise aborts ARM: davinci: PM: support da8xx DT platforms ARM: davinci: PM: cleanup: remove references to pdata ARM: davinci: PM: rework init, remove platform device ARM: Kconfig: Introduce MACH_STM32F746 flag ARM: mach-stm32: Add a new SOC - STM32F746 ARM: shmobile: document SK-RZG1E board ARM: shmobile: r8a7745: basic SoC support ARM: imx: mach-imx6ul: add imx6ull support ARM: zynq: Reserve correct amount of non-DMA RAM ...

ARM: davinci: da8xx: Fix ohci device name ------While the clk lookup table is making reference to "ohci" other subsystems (such as phy) are trying to match "ohci.0"

Since there is a single ohci instance, instead of changing the clk name, change the dev id to -1, and add the "-da8xx" postfix to match the driver name that will also be changed in a subsequent patch.

ARM: davinci: PM: support da8xx DT platforms ------Add PM support for DA850 device-tree boot.

ARM: davinci: da850: Fix pwm name matching ------This fixes pwm name matching for DA850 familiy devices. When using device tree, the da850_auxdata_lookup[] table caused pwm devices to have the exact same name, which caused errors when trying to register the devices.

We cannot have multiple entries for the same clock in in da850_clks[], so we have added child clocks to the EHRPWM and ECAP LPSC clocks so that each PWM device will have its own clock for proper name matching.

ARM: davinci: da8xx: register USB PHY clocks in the DT file ------The usb20_phy clock needs to be registered for the driver to be able to get and enable a clock. Currently the usb phy clocks are registered

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from board files, which will not be called during a device tree based boot.

To be able to probe correctly usb form a device tree boot, register the usb phy clocks from the DT specific init.

Unfortunately, davinci does not have proper clock support on device tree yet, so by registering the clock from the DT specific file we are forced to hardcode the parent clock, and cannot select refclkin as parent for any of the phy clocks of the da850 family.

As none of the current da850 based boards currently in mainline use refclkin as source. I guess we can live with this limitation until clocks are correctly represented through CCF/device tree.

ARM: davinci: da8xx-dt: add OF_DEV_AUXDATA entry for USB phy ------Add OF_DEV_AUXDATA() entry for USB phy. This is required for so that clock lookup will work for the USB PHY driver.

ARM: davinci: da8xx: Add USB device names to clock lookup tables ------This adds device names for the SoC USB devices to the clock lookup tables in da830.c and da850.c.

Also add the USB device names to the da850_auxdata_lookup[] table.

ARM: davinci: da8xx-dt: add OF_DEV_AUXDATA entry for lcdc ------This is required for tilcdc to be able to acquire a functional clock on da850 SoCs.

2211 arch\arm\mach-davinci\da8xx-dt.c#0041 2212 arch\arm\mach-davinci\da8xx-dt.c#0052 2213 arch\arm\mach-davinci\da8xx-dt.c#0064 2214 arch\arm\mach-davinci\devices-da8xx.c#0014 Repo: 0fcd54112a9f David Tue Oct 25 22:06:48 2016 -0500 Description: ARM: davinci: da8xx: Add CFGCHIP syscon platform device ------The CFGCHIP registers are used by a number of devices, so use a syscon device to share them. The first consumer of this will be the phy-da8xx-usb driver.

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Add the syscon device and register it.

ARM: davinci: devices-da8xx: Remove DMA resources for MMC and SPI ------The drivers are now converted to not use the DMA resource.

2215 arch\arm\mach-davinci\devices-da8xx.c#0061 2216 arch\arm\mach-davinci\devices-da8xx.c#0967 2217 arch\arm\mach-davinci\devices-da8xx.c#0990 2218 arch\arm\mach-davinci\devices-da8xx.c#1091 2219 arch\arm\mach-davinci\devices.c#0039 Repo: 638671053c66 Peter UjfalusiWed Sep 28 13:35:28 2016 +0300 Description: ARM: davinci: devices: Remove DMA resources for MMC ------The driver is converted to not use the DMA resource.

2220 arch\arm\mach-davinci\dm355.c#0400 Repo: 0dc68bc0840e Peter UjfalusiWed Sep 28 13:35:29 2016 +0300 Description: ARM: davinci: dm355: Remove DMA resources for SPI ------The driver is converted to not use the DMA resource.

2221 arch\arm\mach-davinci\dm365.c#0663 Repo: fc89017c83b7 Peter UjfalusiWed Sep 28 13:35:30 2016 +0300 Description: ARM: davinci: dm365: Remove DMA resources for SPI ------The driver is converted to not use the DMA resource.

2222 arch\arm\mach-davinci\Makefile#0039 Repo: f7715b299954 Kevin HilmanWed Nov 16 08:44:38 2016 -0800 Description: ARM: davinci: PM: fix build when da850 not compiled in ------Currently, suspend/resume support is only available on da850 platforms, and the platform PM code has dependencies on da850 functions. However, CONFIG_SUSPEND might be enabled even when da850 support is not, causing build failure:

arch/arm/mach-davinci/built-in.o: In function `davinci_pm_init':

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pm_domain.c:(.init.text+0x1fb8): undefined reference to `da8xx_get_mem_ctlr' pm_domain.c:(.init.text+0x20b0): undefined reference to `da8xx_syscfg1_base'

Fix this by only building the PM core when da850 is enabled.

2223 arch\arm\mach-davinci\Makefile#0040 2224 arch\arm\mach-davinci\pm.c#0024 Repo: 1428ed1ad3e8 Kevin HilmanTue Nov 15 11:54:20 2016 -0800 Description: ARM: davinci: PM: cleanup: remove references to pdata ------Since the PM core code is no longer using a fake platform_device or platform_data, remove references to 'pdata'.

No functional changes.

ARM: davinci: PM: rework init, remove platform device ------Remove fake platform device used for PM init. Move pdata values which are common across all current platforms into pm.c.

Also, since PM is only used on da8xx, remove davinci_pm_init() from common init code, and only use in da850/omapl138 board files that are currently creating the fake platform_device.

2225 arch\arm\mach-davinci\pm.c#0028 2226 arch\arm\mach-davinci\pm.c#0031 2227 arch\arm\mach-davinci\pm.c#0033 2228 arch\arm\mach-davinci\pm.c#0036 2229 arch\arm\mach-davinci\pm.c#0051 2230 arch\arm\mach-davinci\pm.c#0054 2231 arch\arm\mach-davinci\pm.c#0056 2232 arch\arm\mach-davinci\pm.c#0061 2233 arch\arm\mach-davinci\pm.c#0063 2234 arch\arm\mach-davinci\pm.c#0067 2235 arch\arm\mach-davinci\pm.c#0069

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2236 arch\arm\mach-davinci\pm.c#0073 2237 arch\arm\mach-davinci\pm.c#0075 2238 arch\arm\mach-davinci\pm.c#0078 2239 arch\arm\mach-davinci\pm.c#0080 2240 arch\arm\mach-davinci\pm.c#0083 2241 arch\arm\mach-davinci\pm.c#0085 2242 arch\arm\mach-davinci\pm.c#0091 2243 arch\arm\mach-davinci\pm.c#0093 2244 arch\arm\mach-davinci\pm.c#0099 2245 arch\arm\mach-davinci\pm.c#0102 2246 arch\arm\mach-davinci\pm.c#0127 2247 arch\arm\mach-davinci\pm.c#0129 2248 arch\arm\mach-davinci\pm.c#0148 2249 arch\arm\mach-davinci\pm.c#0156 2250 arch\arm\mach-davinci\pm.c#0165 2251 arch\arm\mach-davinci\pm.c#0170 2252 arch\arm\mach-davinci\time.c#0271 Repo: a5a1d1c2914b Thomas Wed Dec 21 20:32:01 2016 +0100 Description: clocksource: Use a plain u64 instead of cycle_t ------There is no point in having an extra type for extra confusion. u64 is unambiguous.

Conversion was done with the following coccinelle script:

@rem@ @@ -typedef u64 cycle_t;

@fix@ typedef cycle_t; @@ -cycle_t +u64

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2253 arch\arm\mach-davinci\usb-da8xx.c#0004 Repo: d1df1e01af1d Alexandre Fri Dec 9 17:59:33 2016 +0100 Description: ARM: davinci: da8xx: Fix sleeping function called from invalid context ------Everytime the usb20 phy is enabled, there is a "sleeping function called from invalid context" BUG. In addition, there is a recursive locking happening because of the recurse call to clk_enable().

clk_enable() from arch/arm/mach-davinci/clock.c uses spin_lock_irqsave() before to invoke the callback usb20_phy_clk_enable(). usb20_phy_clk_enable() uses clk_get() and clk_enable_prepapre() which may sleep.

Replace clk_prepare_enable() by davinci_clk_enable().

ARM: davinci: da8xx: Fix ohci device name ------While the clk lookup table is making reference to "ohci" other subsystems (such as phy) are trying to match "ohci.0"

Since there is a single ohci instance, instead of changing the clk name, change the dev id to -1, and add the "-da8xx" postfix to match the driver name that will also be changed in a subsequent patch.

ARM: davinci: da8xx: add usb phy clocks ------Up to this point, the USB phy clock configuration was handled manually in the board files and in the usb drivers. This adds proper clocks so that the usb drivers can use clk_get and clk_enable and not have to worry about the details. Also, the related code is removed from the board files and replaced with the new clock registration functions.

This also removes the #if IS_ENABLED(CONFIG_USB_MUSB_HDRC) around the musb declaration and renames the musb platform device so that we can reference it from the usb20 clock even if the musb device is not used.

ARM: davinci: da8xx: Add USB PHY platform device ------There is now a proper phy driver for the DA8xx SoC USB PHY. This adds the platform device declarations needed to use it.

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2254 arch\arm\mach-davinci\usb-da8xx.c#0008 2255 arch\arm\mach-davinci\usb-da8xx.c#0014 2256 arch\arm\mach-davinci\usb-da8xx.c#0020 2257 arch\arm\mach-davinci\usb-da8xx.c#0025 2258 arch\arm\mach-davinci\usb-da8xx.c#0027 2259 arch\arm\mach-davinci\usb-da8xx.c#0073 2260 arch\arm\mach-davinci\usb-da8xx.c#0077 2261 arch\arm\mach-davinci\usb-da8xx.c#0095 2262 arch\arm\mach-davinci\usb-da8xx.c#0098 2263 arch\arm\mach-davinci\usb-da8xx.c#0114 2264 arch\arm\mach-davinci\usb-da8xx.c#0129 arch\arm\mach-davinci\include\mach\ 2265 arch\arm\mach-davinci\include\mach\da8xx.h#0064 Repo: e264ae280ce1 Arnd Wed Nov 30 14:45:31 2016 +0100 Description: Merge tag 'davinci-for-v4.10/cleanup-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc ------Pull DaVinci cleanup for v4.10 from Sekhar Nori:

mach-davinci cleanup to make it easy to add PM support for DT-boot.

* tag 'davinci-for-v4.10/cleanup-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: ARM: davinci: PM: fix build when da850 not compiled in ARM: davinci: PM: cleanup: remove references to pdata ARM: davinci: PM: rework init, remove platform device

ARM: davinci: PM: rework init, remove platform device ------Remove fake platform device used for PM init. Move pdata values which are common across all current platforms into pm.c.

Also, since PM is only used on da8xx, remove davinci_pm_init() from common init code, and only use in da850/omapl138 board files that are currently creating the fake platform_device.

ARM: davinci: da8xx: add usb phy clocks ------

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Up to this point, the USB phy clock configuration was handled manually in the board files and in the usb drivers. This adds proper clocks so that the usb drivers can use clk_get and clk_enable and not have to worry about the details. Also, the related code is removed from the board files and replaced with the new clock registration functions.

This also removes the #if IS_ENABLED(CONFIG_USB_MUSB_HDRC) around the musb declaration and renames the musb platform device so that we can reference it from the usb20 clock even if the musb device is not used.

ARM: davinci: da8xx: Add USB PHY platform device ------There is now a proper phy driver for the DA8xx SoC USB PHY. This adds the platform device declarations needed to use it.

ARM: davinci: da8xx: Add CFGCHIP syscon platform device ------The CFGCHIP registers are used by a number of devices, so use a syscon device to share them. The first consumer of this will be the phy-da8xx-usb driver.

Add the syscon device and register it.

2266 arch\arm\mach-davinci\include\mach\da8xx.h#0092 2267 arch\arm\mach-davinci\include\mach\da8xx.h#0095 2268 arch\arm\mach-davinci\include\mach\da8xx.h#0109 2269 arch\arm\mach-davinci\include\mach\da8xx.h#0120 arch\arm\mach-ep93xx\ 2270 arch\arm\mach-ep93xx\timer-ep93xx.c#0062 Repo: a5a1d1c2914b Thomas Wed Dec 21 20:32:01 2016 +0100 Description: clocksource: Use a plain u64 instead of cycle_t ------There is no point in having an extra type for extra confusion. u64 is unambiguous.

Conversion was done with the following coccinelle script:

@rem@ @@ -typedef u64 cycle_t;

@fix@

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typedef cycle_t; @@ -cycle_t +u64

2271 arch\arm\mach-ep93xx\timer-ep93xx.c#0068 arch\arm\mach-exynos\ 2272 arch\arm\mach-exynos\platsmp.c#0388 Repo: 379f10910c96 Pankaj Fri Nov 4 09:09:21 2016 +0530 Description: ARM: EXYNOS: Remove smp_init_cpus hook from platsmp.c ------We can safely remove exynos_smp_init_cpus() hook from mach-exynos/platsmp.c, as all SMP platforms in mach-exynos can rely on DT for CPU core description instead of determining number of cores from the SCU.

2273 arch\arm\mach-exynos\platsmp.c#0482 arch\arm\mach-footbridge\ 2274 arch\arm\mach-footbridge\dc21285-timer.c#0022 Repo: a5a1d1c2914b Thomas Wed Dec 21 20:32:01 2016 +0100 Description: clocksource: Use a plain u64 instead of cycle_t ------There is no point in having an extra type for extra confusion. u64 is unambiguous.

Conversion was done with the following coccinelle script:

@rem@ @@ -typedef u64 cycle_t;

@fix@ typedef cycle_t; @@ -cycle_t +u64

arch\arm\mach-imx\ 2275 arch\arm\mach-imx\common.h#0046 Repo: 6fe5aeb5e7e9 Vladimir Mon Sep 26 03:03:43 2016 +0300 Description: ARM: clk: imx31: properly init clocks for machines with DT

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------Clock initialization for i.MX31 powered machines with DT support should be done by a call of an init function registered with CLK_OF_DECLARE() in common clock framework.

The change converts exported mx31_clocks_init_dt() into a static initialization function registered by CLK_OF_DECLARE().

2276 arch\arm\mach-imx\gpc.c#0383 Repo: cc773e75a0e2 Rafael J. Mon Dec 12 20:43:19 2016 +0100 Description: Merge branch 'pm-domains' ------* pm-domains: PM / Domains: Fix compatible for domain idle state PM / Domains: Do not print PM domain add error message if EPROBE_DEFER PM / Domains: Fix a warning message PM / Domains: check for negative return from of_count_phandle_with_args() PM / doc: Update device documentation for devices in IRQ-safe PM domains PM / Domains: Support IRQ safe PM domains PM / Domains: Abstract genpd locking dt/bindings / PM/Domains: Update binding for PM domain idle states PM / Domains: Save the fwnode in genpd_power_state PM / Domains: Allow domain power states to be read from DT PM / Domains: Add residency property to genpd states PM / Domains: Make genpd state allocation dynamic

Conflicts: arch/arm/mach-imx/gpc.c

ARM: imx: gpc: Fix the imx_gpc_genpd_init() error path ------If of_genpd_add_provider_onecell() fails the following kernel crash is observed on a kernel built with multi_v7_defconfig:

[ 1.739301] [00000040] *pgd=00000000 [ 1.739310] Internal error: Oops: 5 [#1] SMP ARM [ 1.739319] Modules linked in: [ 1.739328] CPU: 1 PID: 95 Comm: kworker/1:4 Not tainted 4.8.0-11897-g6b5e09a #1 [ 1.739331] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree) [ 1.739352] Workqueue: pm genpd_power_off_work_fn [ 1.739356] task: ee63d400 task.stack: ee70a000 [ 1.739365] PC is at mutex_lock+0xc/0x4c [ 1.739374] LR is at regulator_disable+0x2c/0x60 [ 1.739379] pc : [] lr : [] psr: 60000013 [ 1.739379] sp : ee70beb0 ip : 10624dd3 fp : ee6e6280 [ 1.739382] r10: eefb0900 r9 : 00000000 r8 : c1309918 [ 1.739385] r7 : 00000000 r6 : 00000040 r5 : 00000000 r4 : 00000040

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[ 1.739390] r3 : 0000004c r2 : 7fffd540 r1 : 000001e4 r0 : 00000040

Instead of returning of_genpd_add_provider_onecell() directly, we should check its return value and in the case of error we should unwind the previously taken actions, which in these case are: - Call imx6q_pm_pu_power_off() - Set imx6q_pu_domain.reg back to NULL

Setting imx6q_pu_domain.reg to NULL in the error case is important as it will prevent further operations in the pu_reg regulator.

This kernel crash is not observed with imx_v6_v7_defconfig because it selects GPU and VPU drivers, which are consumers of the GPC block and thus change the refcount of the pu_reg regulator.

2277 arch\arm\mach-imx\gpc.c#0433 2278 arch\arm\mach-imx\imx31-dt.c#0026 Repo: 6fe5aeb5e7e9 Vladimir Mon Sep 26 03:03:43 2016 +0300 Description: ARM: clk: imx31: properly init clocks for machines with DT ------Clock initialization for i.MX31 powered machines with DT support should be done by a call of an init function registered with CLK_OF_DECLARE() in common clock framework.

The change converts exported mx31_clocks_init_dt() into a static initialization function registered by CLK_OF_DECLARE().

2279 arch\arm\mach-imx\imx31-dt.c#0046 2280 arch\arm\mach-imx\Kconfig#0560 Repo: 0d74a9c2eb59 Andrey Wed Nov 9 08:44:10 2016 -0800 Description: ARM: imx: Drop errata 769419 for Vybrid ------According to the datasheet, VF610 uses revision r3p2 of the L2C-310 block, same as i.MX6Q+, which does not require a software workaround for ARM errata 769419.

2281 arch\arm\mach-imx\mach-imx1.c#0040 Repo: d7da1ccfa2c2 Vladimir Fri Dec 2 15:05:38 2016 +0000 Description: ARM: i.MX: remove map_io callback ------There is no need to define map_io only for debug_ll_io_init() since it is already called in devicemaps_init() if map_io is NULL.

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Apart from that, for NOMMU build debug_ll_io_init() is a nop which leads to following error:

CC arch/arm/mach-imx/mach-imx1.o arch/arm/mach-imx/mach-imx1.c:40:13: error: 'debug_ll_io_init' undeclared here (not in a function) .map_io = debug_ll_io_init, ^ make[1]: *** [arch/arm/mach-imx/mach-imx1.o] Error 1

2282 arch\arm\mach-imx\mach-imx6ul.c#0092 Repo: 75b832fea256 Peter Chen Mon Nov 14 15:04:21 2016 +0800 Description: ARM: imx: mach-imx6ul: add imx6ull support ------imx6ull is derived SoC from imx6ul.

2283 arch\arm\mach-imx\mmdc.c#0002 Repo: 7f1931b35f09 Arnd Tue Jan 10 13:19:05 2017 +0100 Description: ARM: imx: hide unused variable in #ifdef ------A bugfix added a new local variable that is only used inside of an #ifdef section, and unused if CONFIG_PERF_EVENTS is disabled:

arch/arm/mach-imx/mmdc.c:63:25: warning: 'cpuhp_mmdc_state' defined but not used [- Wunused-variable]

This moves the variable down inside that same ifdef.

Fixes: a051f220d6b9 ("ARM/imx/mmcd: Fix broken cpu hotplug handling")

ARM/imx/mmcd: Fix broken cpu hotplug handling ------The cpu hotplug support of this perf driver is broken in several ways:

1) It adds a instance before setting up the state.

2) The state for the instance is different from the state of the callback. It's just a randomly chosen state.

3) The instance registration is not error checked so nobody noticed that the call can never succeed.

4) The state for the multi install callbacks is chosen randomly and overwrites existing state. This is now prevented by the core code so the call is guaranteed to fail.

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5) The error exit path in the init function leaves the instance registered and then frees the memory which contains the enqueued hlist node.

6) The remove function is removing the state and not the instance.

Fix it by:

- Setting up the state before adding instances. Use a dynamically allocated state for it.

- Installing instances after the state has been set up

- Removing the instance in the error path before freeing memory

- Removing the instance not the state in the driver remove callback

While at is use raw_cpu_processor_id(), because cpu_processor_id() cannot be used in preemptible context, and set the driver data after successful registration of the pmu.

ARM: imx: mmdc perf function support i.MX6QP ------i.MX6QP added new register bit PROFILE_SEL in MADPCR0. need set it at perf start.

ARM: imx: Added perf functionality to mmdc driver ------MMDC is a multi-mode DDR controller that supports DDR3/DDR3L x16/x32/x64 and LPDDR2 two channel x16/x32 memory types. MMDC is configurable, high performance, and optimized. MMDC is present on i.MX6 Quad and i.MX6 QuadPlus devices, but this driver only supports i.MX6 Quad at the moment. MMDC provides registers for performance counters which read via this driver to help debug memory throughput and similar issues.

$ perf stat -a -e mmdc/busy-cycles/,mmdc/read-accesses/,mmdc/read-bytes/,mmdc/total- cycles/,mmdc/write-accesses/,mmdc/write-bytes/ dd if=/dev/zero of=/dev/null bs=1M count=5000 Performance counter stats for 'dd if=/dev/zero of=/dev/null bs=1M count=5000':

898021787 mmdc/busy-cycles/ 14819600 mmdc/read-accesses/ 471.30 MB mmdc/read-bytes/ 2815419216 mmdc/total-cycles/ 13367354 mmdc/write-accesses/ 427.76 MB mmdc/write-bytes/

5.334757334 seconds time elapsed

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Review: COMMENT stecan Thu, 11 Jan 2018 07:26:40 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:40 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:26:40 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:40 +0100 Automatic commented! 2284 arch\arm\mach-imx\mmdc.c#0013 2285 arch\arm\mach-imx\mmdc.c#0015 2286 arch\arm\mach-imx\mmdc.c#0021 2287 arch\arm\mach-imx\mmdc.c#0034 2288 arch\arm\mach-imx\mmdc.c#0065 2289 arch\arm\mach-imx\mmdc.c#0560 2290 arch\arm\mach-imx\mmdc.c#0568 2291 arch\arm\mach-imx\mmdc.c#0574 arch\arm\mach-integrator\ 2292 arch\arm\mach-integrator\impd1.c#0024 Repo: 562b488443f6 Linus Walleij Fri Nov 25 10:53:39 2016 +0100 Description: gpio: pl061: move platform data into driver ------No boardfile defines any PL061 platform data anymore: the Integrator IM/PD-1 includes the file but is not making use of the struct. Let's delete the include and all references, then move the platform data into the driver for later consolidation into the driver state container.

The only resource defined by the IM/PD-1 is the IRQ which is passed through the AMBA PrimeCell bus abstraction struct amba_device.

2293 arch\arm\mach-integrator\integrator_ap.c#0030 Repo: 94a07de1902e Linus Walleij Wed Nov 9 09:12:06 2016 +0100 Description: ARM: integrator: drop EBI access use syscon ------The EBI lookup is not longer in use: this has been moved to the NAND chip driver. The syscon node is better accessed indirectly using the regmap like the NAND chip driver does, so let's use the syscon to set the modem control signals RTS/CTS through the dedicated syscon register.

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We also migrate the decoder status "SC_DEC" register that enumerate the logic modules using syscon.

ARM: integrator: cut down on static maps ------This removes all the unused static maps on the Integrator/AP and Integrator/CP and also take this opportunity to strip down a big list of unused #includes from each boardfile.

2294 arch\arm\mach-integrator\integrator_ap.c#0042 2295 arch\arm\mach-integrator\integrator_ap.c#0045 2296 arch\arm\mach-integrator\integrator_ap.c#0128 2297 arch\arm\mach-integrator\integrator_ap.c#0149 2298 arch\arm\mach-integrator\integrator_ap.c#0190 2299 arch\arm\mach-integrator\integrator_ap.c#0192 2300 arch\arm\mach-integrator\integrator_ap.c#0194 2301 arch\arm\mach-integrator\integrator_ap.c#0197 2302 arch\arm\mach-integrator\integrator_ap.c#0202 2303 arch\arm\mach-integrator\integrator_ap.c#0206 2304 arch\arm\mach-integrator\integrator_ap.c#0208 2305 arch\arm\mach-integrator\integrator_ap.c#0214 2306 arch\arm\mach-integrator\integrator_ap.c#0216 arch\arm\mach-iop13xx\ 2307 arch\arm\mach-iop13xx\irq.c#0023 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

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ARM: iop13xx: make headers more local ------Some header files are never included outside of a mach-iop13xx directory and do not need to be made visible in include/mach, so let's just move them all down one level.

arch\arm\mach-ixp4xx\ 2308 arch\arm\mach-ixp4xx\common.c#0037 Repo: a5a1d1c2914b Thomas Wed Dec 21 20:32:01 2016 +0100 Description: clocksource: Use a plain u64 instead of cycle_t ------There is no point in having an extra type for extra confusion. u64 is unambiguous.

Conversion was done with the following coccinelle script:

@rem@ @@ -typedef u64 cycle_t;

@fix@ typedef cycle_t; @@ -cycle_t +u64

Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

2309 arch\arm\mach-ixp4xx\common.c#0496 2310 arch\arm\mach-ixp4xx\dsmg600-setup.c#0029 Repo: 7548dd7e47c8 Geliang Fri Nov 18 22:21:10 2016 +0800 Description: ARM: ixp4xx: drop duplicate header gpio.h ------Drop duplicate header gpio.h from dsmg600-setup.c.

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Line Link NR. Descriptions arch\arm\mach-lpc32xx\ 2311 arch\arm\mach-lpc32xx\clock.h#fileDeleted Repo: d1193df9c3cb Vladimir Thu Sep 8 06:00:09 2016 +0300 Description: ARM: lpc32xx: remove unused header file clock.h ------The removed clock.h file is a leftover after moving the platform to a common clock framework driver, it contains unused "struct clk" definition, which under circumstances may coalesce with a generic "struct clk" declaration for clock consumers. Also remove useless include of the removed local file from a single source file mach-lpc32xx/pm.c.

2312 arch\arm\mach-lpc32xx\common.h#0027 Repo: ee1df783d15b Vladimir Thu Sep 8 06:00:08 2016 +0300 Description: ARM: lpc32xx: remove unused header file mach/irqs.h ------The removed LPC32xx mach/irqs.h file is not included in any source code, function declaration lpc32xx_init_irq() is also unused, remove them as leftovers after switching to a new interrupt controller driver.

ARM: lpc32xx: remove leftovers of legacy clock source and provider drivers ------After switching the platform to common clock framework there is no more need to keep dead code in arch/arm/mach-lpc32xx, which glued legacy clock source and clock provider drivers, remove the leftovers.

2313 arch\arm\mach-lpc32xx\phy3250.c#0026 Repo: 4362321817f3 Geliang Fri Nov 18 22:21:11 2016 +0800 Description: ARM: lpc32xx: drop duplicate header device.h ------Drop duplicate header device.h from phy3250.c.

2314 arch\arm\mach-lpc32xx\pm.c#0076 Repo: d1193df9c3cb Vladimir Thu Sep 8 06:00:09 2016 +0300 Description: ARM: lpc32xx: remove unused header file clock.h ------The removed clock.h file is a leftover after moving the platform to a common clock framework driver, it contains unused "struct clk" definition, which under circumstances may coalesce with a generic "struct clk" declaration for clock consumers. Also remove useless

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include of the removed local file from a single source file mach-lpc32xx/pm.c.

arch\arm\mach-lpc32xx\include\mach\ 2315 arch\arm\mach-lpc32xx\include\mach\irqs.h#fileDeleted Repo: ee1df783d15b Vladimir Thu Sep 8 06:00:08 2016 +0300 Description: ARM: lpc32xx: remove unused header file mach/irqs.h ------The removed LPC32xx mach/irqs.h file is not included in any source code, function declaration lpc32xx_init_irq() is also unused, remove them as leftovers after switching to a new interrupt controller driver.

arch\arm\mach-mediatek\ 2316 arch\arm\mach-mediatek\Makefile#0001 Repo: 494975c9cc00 Masahiro Mon Sep 19 03:11:13 2016 +0900 Description: ARM: mediatek: clean up mach-mediatek/Makefile ------Kbuild descends into arch/arm/mach-mediatek/Makefile only when CONFIG_ARCH_MEDIATEK is enabled. So, obj-$(CONFIG_ARCH_MEDIATEK) is always equivalent to obj-y in this Makefile.

arch\arm\mach-mmp\ 2317 arch\arm\mach-mmp\time.c#0147 Repo: a5a1d1c2914b Thomas Wed Dec 21 20:32:01 2016 +0100 Description: clocksource: Use a plain u64 instead of cycle_t ------There is no point in having an extra type for extra confusion. u64 is unambiguous.

Conversion was done with the following coccinelle script:

@rem@ @@ -typedef u64 cycle_t;

@fix@ typedef cycle_t; @@ -cycle_t +u64

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ARM: mmp: make all header files local ------The mach/*.h headers are now inaccessible to any external code, so we can move them all into the mach-mmp directory itself and remove the subdirectories.

A few headers are not used at all, so we remove them here.

ARM/mmp/time: Migrate to new 'set-state' interface ------Migrate mmp driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now.

This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED.

We weren't doing anything in set_mode(RESUME) except of local_irq_{save|restore}(), which isn't required and so ->tick_resume isn't implemented.

arch\arm\mach-mvebu\ 2318 arch\arm\mach-mvebu\coherency.c#0151 Repo: 73c1b41e63f0 Thomas Wed Dec 21 20:19:54 2016 +0100 Description: cpu/hotplug: Cleanup state names ------When the state names got added a script was used to add the extra argument to the calls. The script basically converted the state constant to a string, but the cleanup to convert these strings into meaningful ones did not happen.

Replace all the useless strings with 'subsys/xxx/yyy:state' strings which are used in all the other places already.

arch\arm\mach-omap1\ 2319 arch\arm\mach-omap1\dma.c#0035 Repo: 657279778af5 Peter UjfalusiTue Jan 3 13:22:34 2017 +0200 Description: ARM: OMAP1: DMA: Correct the number of logical channels ------OMAP1510, OMAP5910 and OMAP310 have only 9 logical channels. OMAP1610, OMAP5912, OMAP1710, OMAP730, and OMAP850 have 16 logical channels

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available.

The wired 17 for the lch_count must have been used to cover the 16 + 1 dedicated LCD channel, in reality we can only use 9 or 16 channels.

The d->chan_count is not used by the omap-dma stack, so we can skip the setup. chan_count was configured to the number of logical channels and not the actual number of physical channels anyways.

2320 arch\arm\mach-omap1\dma.c#0351 2321 arch\arm\mach-omap1\dma.c#0369 2322 arch\arm\mach-omap1\dma.c#0375 2323 arch\arm\mach-omap1\i2c.c#0022 Repo: 65fa3e719f36 Tony Mon Oct 17 00:06:54 2016 -0700 Description: ARM: OMAP2+: Remove legacy i2c.c platform init code ------We can now initialize I2C for mach-omap2 using device tree. And we can move the remaining code in plat-omap/i2c.c into mach-omap1/i2c.c.

Note that we cannot remove some of the I2C bus reset functions as they are being used by hwmod code.

2324 arch\arm\mach-omap1\i2c.c#0095 2325 arch\arm\mach-omap1\Kconfig#0034 Repo: e9f5f1e45608 Tony Thu Oct 20 06:42:19 2016 -0700 Description: ARM: OMAP2+: Remove legacy mux code ------All the boards booting with device tree use drivers/pinctrl-single.c instead.

Note that mach-omap1 is still using the legacy mux, so let's move the related Kconfig options from plat-omap to mach-omap1.

arch\arm\mach-omap2\ 2326 arch\arm\mach-omap2\board-flash.c#fileDeleted Repo: 6a6e640bc191 Javier Fri Oct 21 03:43:35 2016 -0700 Description: ARM: OMAP2+: Remove legacy board-flash.c ------Legacy board files in mach-omap2 used the helper functions

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board_{nor,nand,onenand}_init() to initialize the flash devices attached to the GPMC.

With Device Tree booting the initialization is handled by the GPMC driver gpmc_probe_*_child() functions so this code is not needed anymore now that OMAP2+ is DT-only.

2327 arch\arm\mach-omap2\board-flash.h#fileDeleted Repo: 6a6e640bc191 Javier Fri Oct 21 03:43:35 2016 -0700 Description: ARM: OMAP2+: Remove legacy board-flash.c ------Legacy board files in mach-omap2 used the helper functions board_{nor,nand,onenand}_init() to initialize the flash devices attached to the GPMC.

With Device Tree booting the initialization is handled by the GPMC driver gpmc_probe_*_child() functions so this code is not needed anymore now that OMAP2+ is DT-only.

2328 arch\arm\mach-omap2\board-generic.c#0033 Repo: f86a2c875fd1 Grygorii Mon Dec 5 09:27:44 2016 +0530 Description: ARM: omap2+: am437x: rollback to use omap3_gptimer_timer_init() ------The commit 55ee7017ee31 ("arm: omap2: board-generic: use omap4_local_timer_init for AM437x") unintentionally changes the clocksource devices for AM437x from OMAP GP Timer to SyncTimer32K.

Unfortunately, the SyncTimer32K is starving from frequency deviation as mentioned in commit 5b5c01359152 ("ARM: OMAP2+: AM43x: Use gptimer as clocksource") and, as reported by Franklin [1], even its monotonic nature is under question (most probably there is a HW issue, but it's still under investigation).

Taking into account above facts It's reasonable to rollback to the use of omap3_gptimer_timer_init().

[1] http://www.spinics.net/lists/linux-omap/msg127425.html

Fixes: 55ee7017ee31 ("arm: omap2: board-generic: use omap4_local_timer_init for AM437x")

Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM SoC platform updates from Arnd Bergmann: "These are updates for platform specific code on 32-bit ARM machines,

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essentially anything that can not (yet) be expressed using DT files.

Noteworthy changes include:

- Added support for the TI DRA71x family of SoCs in mach-omap2, this is an new variant of the the DRA72x/DRA74x automotive infotainment chips we already supported for a while.

- Added support for the ST STM32F746 SoC, the first Cortex-M7 based microcontroller we support, related to the smaller STM32F4 family.

- Renesas adds support for r8a7743 and r8a7745 in mach-shmobile, see http://elinux.org/RZ-G

- SMP is now supported on the OX820 platform

- A lot of code in mach-omap2 gets removed as a follow-up to removing support for board files in the previous release

- Davinci has some new work to improve USB support

- For i.MX, the performance monitor now supports profiling the memory controller using 'perf'"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (95 commits) ARM: davinci: da830-evm: use gpio descriptor for mmc pins ARM: davinci: da850-evm: use gpio descriptor for mmc pins ARM: davinci: hawk: use gpio descriptor for mmc pins ARM: ARTPEC-6: add select MFD_SYSCON to MACH_ARTPEC6 ARM: davinci: da8xx: Fix ohci device name ARM: oxnas: Add OX820 config and makefile entry ARM: oxnas: Add OX820 SMP support ARM: davinci: PM: fix build when da850 not compiled in ARM: orion5x: remove legacy support of ls-chl ARM: integrator: drop EBI access use syscon ARM: BCM5301X: Add back handler ignoring external imprecise aborts ARM: davinci: PM: support da8xx DT platforms ARM: davinci: PM: cleanup: remove references to pdata ARM: davinci: PM: rework init, remove platform device ARM: Kconfig: Introduce MACH_STM32F746 flag ARM: mach-stm32: Add a new SOC - STM32F746 ARM: shmobile: document SK-RZG1E board ARM: shmobile: r8a7745: basic SoC support ARM: imx: mach-imx6ul: add imx6ull support ARM: zynq: Reserve correct amount of non-DMA RAM ...

ARM: OMAP2+: board-generic: add support for DRA71x family

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------DRA71x processor family is a derivative of DRA722 ES2.0 targetted for infotainment systems.

ARM: OMAP2+: Remove the omapdss_early_init_of() function ------The function is empty, remove it.

2329 arch\arm\mach-omap2\board-generic.c#0309 2330 arch\arm\mach-omap2\board-generic.c#0344 2331 arch\arm\mach-omap2\clockdomains7xx_data.c#0412 Repo: c2ce5fb3f3f5 Joel Tue Oct 18 10:55:25 2016 +0300 Description: ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP only ------Using HWSUP for l4sec clock domain is causing warnings in HWMOD code for DRA7. Based on some observations, once the clock domain goes into an IDLE state (because of no activity etc), the IDLEST for the module goes to '0x2' value which means Interface IDLE condition. So far so go, however once the MODULEMODE is set to disabled for the particular IP, the IDLEST for the module should go to '0x3', per the HW AUTO IDLE protocol. However this is not observed and there is no reason per the protocl for the transition to not happen. This could potentially be a bug in the HW AUTO state-machine.

Work around for this is to use SWSUP only for the particular clockdomain. With this all the transitions of IDLEST happen correctly and warnings don't occur.

2332 arch\arm\mach-omap2\common-board-devices.c#fileDeleted Repo: dbf828ec4c76 Tony Thu Nov 10 15:46:13 2016 -0700 Description: ARM: OMAP2+: Drop legacy ads7846 init ------

2333 arch\arm\mach-omap2\common-board-devices.h#0006 Repo: dbf828ec4c76 Tony Thu Nov 10 15:46:13 2016 -0700 Description: ARM: OMAP2+: Drop legacy ads7846 init ------This code is no longer used and can be removed as we are using device tree.

ARM: OMAP2+: Remove legacy twl4030 platform init code ------

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2334 arch\arm\mach-omap2\common-board-devices.h#0008 2335 arch\arm\mach-omap2\common.h#0080 Repo: e79ab194d15e Linus Thu Dec 15 15:39:02 2016 -0800 Description: Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM SoC platform updates from Arnd Bergmann: "These are updates for platform specific code on 32-bit ARM machines, essentially anything that can not (yet) be expressed using DT files.

Noteworthy changes include:

- Added support for the TI DRA71x family of SoCs in mach-omap2, this is an new variant of the the DRA72x/DRA74x automotive infotainment chips we already supported for a while.

- Added support for the ST STM32F746 SoC, the first Cortex-M7 based microcontroller we support, related to the smaller STM32F4 family.

- Renesas adds support for r8a7743 and r8a7745 in mach-shmobile, see http://elinux.org/RZ-G

- SMP is now supported on the OX820 platform

- A lot of code in mach-omap2 gets removed as a follow-up to removing support for board files in the previous release

- Davinci has some new work to improve USB support

- For i.MX, the performance monitor now supports profiling the memory controller using 'perf'"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (95 commits) ARM: davinci: da830-evm: use gpio descriptor for mmc pins ARM: davinci: da850-evm: use gpio descriptor for mmc pins ARM: davinci: hawk: use gpio descriptor for mmc pins ARM: ARTPEC-6: add select MFD_SYSCON to MACH_ARTPEC6 ARM: davinci: da8xx: Fix ohci device name ARM: oxnas: Add OX820 config and makefile entry ARM: oxnas: Add OX820 SMP support ARM: davinci: PM: fix build when da850 not compiled in ARM: orion5x: remove legacy support of ls-chl ARM: integrator: drop EBI access use syscon ARM: BCM5301X: Add back handler ignoring external imprecise aborts ARM: davinci: PM: support da8xx DT platforms ARM: davinci: PM: cleanup: remove references to pdata ARM: davinci: PM: rework init, remove platform device ARM: Kconfig: Introduce MACH_STM32F746 flag

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ARM: mach-stm32: Add a new SOC - STM32F746 ARM: shmobile: document SK-RZG1E board ARM: shmobile: r8a7745: basic SoC support ARM: imx: mach-imx6ul: add imx6ull support ARM: zynq: Reserve correct amount of non-DMA RAM ...

Merge tag 'omap-for-v4.10/legacy-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc ------Legacy platform_data removal for omaps for v4.10 merge window. We've dropped the last legacy boot board-*.c files for mach-omap2 for v4.9 so now we can start removing the unused platform_data.

All of the below has been unused since v4.9 merge window:

- Drop legacy pmic init code - Apply seq_puts() fixes for legacy mux code, then drop it - Drop legacy serial init - Drop legacy i2c init - Drop legacy PM init - Drop legacy twl4030 platform init - Drop legacy USB host init - Drop legacy muxing for tusb6010, n8x0 is still using it's platform init via pdata-quirks.c - Drop legacy musb init - Drop hwmod related legacy mux code - Drop legacy hwmod data for omap3 - Drop legacy smsc911x and smc91x init - Drop legacy board flash init - Drop legacy ads7846 init - Drop legacy sdram timings

* tag 'omap-for-v4.10/legacy-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits) ARM: OMAP2+: Drop legacy sdram timings ARM: OMAP2+: Drop legacy ads7846 init ARM: OMAP2+: Remove legacy board-flash.c ARM: OMAP2+: Remove legacy smsc911x and smc91x GPMC support ARM: OMAP2+: Remove legacy data from hwmod for omap3 ARM: OMAP2+: Remove legacy mux code ARM: OMAP2+: Remove legacy hwmod mux code ARM: OMAP2+: Remove legacy usb-musb.c platform init code ARM: OMAP2+: Remove legacy muxing for usb-tusb6010.c ARM: OMAP2+: Remove legacy usb-host.c platform init code ARM: OMAP2+: Remove legacy twl4030 platform init code ARM: OMAP2+: Remove legacy PM init ARM: OMAP2+: Remove legacy i2c.c platform init code ARM: OMAP2+: Remove legacy serial.c

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ARM: OMAP2+: mux: Use seq_putc() in omap_mux_dbg_signal_show() ARM: OMAP2+: mux: Replace three seq_printf() calls by seq_puts() ARM: OMAP: kill omap_pmic_init ARM: OMAP2: kill omap2_pmic_init ARM: OMAP3: kill omap3_pmic_init ARM: OMAP3: kill omap3_pmic_get_config and twl_{get,set}_voltage ...

ARM: OMAP2+: Remove legacy mux code ------All the boards booting with device tree use drivers/pinctrl-single.c instead.

Note that mach-omap1 is still using the legacy mux, so let's move the related Kconfig options from plat-omap to mach-omap1.

ARM: OMAP2+: Remove the omapdss_early_init_of() function ------The function is empty, remove it.

ARM: OMAP5: Fix mpuss_early_init ------We need to properly initialize mpuss also on omap5 like we do on omap4. Otherwise we run into similar kexec problems like we had on omap4 when trying to kexec from a kernel with PM initialized.

Fixes: 0573b957fc21 ("ARM: OMAP4+: Prevent CPU1 related hang with kexec")

ARM: OMAP4+: Allow kexec on SMP variants ------Kexec needs omap4_cpu_kill, otherwise kexec will produce on SMP:

kexec_load failed: Invalid argument

ARM: OMAP4+: Prevent CPU1 related hang with kexec ------Kexec booted kernels on omap4 will hang early during the boot if the booted kernel is different version from the previous kernel.

This is because the previous kernel may have configured low-power mode using CPU1_WAKEUP_NS_PA_ADDR. In that case it points to the previous kernel's omap4_secondary_startup(), and CPU1 can be in low power mode from the previous kernel. When the new kernel configures the CPU1 clockdomain, CPU1 can wake from low power state prematurely during omap44xx_clockdomains_init() running random code.

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Let's fix the issue by configuring CPU1_WAKEUP_NS_PA_ADDR before we call omap44xx_clockdomains_init(). Note that this is very early during the init, and we will do proper CPU1 reset during SMP init a bit later on in omap4_smp_prepare_cpus(). And we need to do this when SMP is not enabled as the previous kernel may have had it enabled.

2336 arch\arm\mach-omap2\common.h#0265 2337 arch\arm\mach-omap2\common.h#0278 2338 arch\arm\mach-omap2\common.h#0286 2339 arch\arm\mach-omap2\common.h#0308 2340 arch\arm\mach-omap2\common.h#0312 2341 arch\arm\mach-omap2\common.h#0314 2342 arch\arm\mach-omap2\common.h#0316 2343 arch\arm\mach-omap2\common.h#0346 2344 arch\arm\mach-omap2\cpuidle44xx.c#0024 Repo: 7abdb0e23e7b Santosh Mon Nov 7 16:50:11 2016 -0700 Description: ARM: OMAP5: Add basic cpuidle MPU CSWR support ------Add OMAP5 CPUIDLE support.

This patch adds MPUSS low power states in cpuidle.

C1 - CPU0 WFI + CPU1 WFI + MPU ON C2 - CPU0 RET + CPU1 RET + MPU CSWR

Modified from TI kernel tree commit 605967fd2205 ("ARM: DRA7: PM: cpuidle MPU CSWR support") except enable cpuidle for omap5 instead of dra7.

According to Nishanth Menon , cpuidle on dra7 is not supported properly in the hardware so we don't want to enable it. However, for omap5 this adds some nice power savings. Note that the TI 3.8 based tree has other cpuidle states that we may be able to enable later on.

On omap5-uevm, the power consumption eventually settles down to about 920mW with ehci-omap and ohci-omap3 unloaded compared to about 1.7W without these patches. Note that it seems to take few minutes after booting for the idle power to go down to 920mW from 1.3W, no idea so far what might be causing that.

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2345 arch\arm\mach-omap2\cpuidle44xx.c#0034 2346 arch\arm\mach-omap2\cpuidle44xx.c#0055 2347 arch\arm\mach-omap2\cpuidle44xx.c#0074 2348 arch\arm\mach-omap2\cpuidle44xx.c#0096 2349 arch\arm\mach-omap2\cpuidle44xx.c#0265 2350 arch\arm\mach-omap2\cpuidle44xx.c#0301 2351 arch\arm\mach-omap2\cpuidle44xx.c#0325 2352 arch\arm\mach-omap2\devices.c#0033 Repo: b42814557fd5 Tony Thu Oct 20 06:35:21 2016 -0700 Description: ARM: OMAP2+: Remove legacy hwmod mux code ------This is no longer needed when booted with device tree.

2353 arch\arm\mach-omap2\display.c#0568 Repo: 71b2e2e3b31d Laurent Sun Sep 18 14:52:13 2016 +0300 Description: ARM: OMAP2+: Remove the omapdss_early_init_of() function ------The function is empty, remove it.

2354 arch\arm\mach-omap2\dss-common.c#fileDeleted Repo: dbf828ec4c76 Tony Thu Nov 10 15:46:13 2016 -0700 Description: ARM: OMAP2+: Drop legacy ads7846 init ------All the boards booting with device tree use drivers/pinctrl-single.c instead.

Note that mach-omap1 is still using the legacy mux, so let's move the related Kconfig options from plat-omap to mach-omap1.

ARM: OMAP2+: Remove legacy mux code ------

2355 arch\arm\mach-omap2\dss-common.h#fileDeleted Repo: dbf828ec4c76 Tony Thu Nov 10 15:46:13 2016 -0700 Description: ARM: OMAP2+: Drop legacy ads7846 init ------

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2356 arch\arm\mach-omap2\gpio.c#fileDeleted Repo: 14944934f8ac Grygorii Mon Nov 21 11:26:27 2016 -0600 Description: ARM: OMAP2+: Remove legacy gpio code ------OMAP2+ GPOs are initialized now using device tree, so legacy gpio initialization code can be removed.

2357 arch\arm\mach-omap2\gpmc-smsc911x.c#fileDeleted Repo: b7b23ffcf7d8 Javier Fri Nov 29 20:18:15 2013 +0100 Description: ARM: OMAP2+: Remove legacy smsc911x and smc91x GPMC support ------When connecting an ethernet chip to the GPMC, such as smc91x or smsc911x, a GPIO has to be requested to be used as an IRQ and also the IO memory for a GPMC chip-select.

When booting with DT the chip-select allocation is handled in a generic manner in the GPMC driver and the GPIO to IRQ mapping is made by the DT core so this code is not needed anymore now that mach-omap2 related boards are DT-only.

2358 arch\arm\mach-omap2\gpmc-smsc911x.h#fileDeleted Repo: b7b23ffcf7d8 Javier Fri Nov 29 20:18:15 2013 +0100 Description: ARM: OMAP2+: Remove legacy smsc911x and smc91x GPMC support ------When connecting an ethernet chip to the GPMC, such as smc91x or smsc911x, a GPIO has to be requested to be used as an IRQ and also the IO memory for a GPMC chip-select.

When booting with DT the chip-select allocation is handled in a generic manner in the GPMC driver and the GPIO to IRQ mapping is made by the DT core so this code is not needed anymore now that mach-omap2 related boards are DT-only.

2359 arch\arm\mach-omap2\hsmmc.c#0025 Repo: e9f5f1e45608 Tony Thu Oct 20 06:42:19 2016 -0700 Description: ARM: OMAP2+: Remove legacy mux code ------All the boards booting with device tree use drivers/pinctrl-single.c instead.

Note that mach-omap1 is still using the legacy mux, so let's move the related Kconfig options from plat-omap

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to mach-omap1.

2360 arch\arm\mach-omap2\hsmmc.c#0150 2361 arch\arm\mach-omap2\hsmmc.c#0413 2362 arch\arm\mach-omap2\i2c.c#0029 Repo: 65fa3e719f36 Tony Mon Oct 17 00:06:54 2016 -0700 Description: ARM: OMAP2+: Remove legacy i2c.c platform init code ------We can now initialize I2C for mach-omap2 using device tree. And we can move the remaining code in plat-omap/i2c.c into mach-omap1/i2c.c.

Note that we cannot remove some of the I2C bus reset functions as they are being used by hwmod code.

2363 arch\arm\mach-omap2\i2c.c#0039 2364 arch\arm\mach-omap2\i2c.c#0110 2365 arch\arm\mach-omap2\io.c#0430 Repo: 6d1e66bb4e41 Olof Fri Nov 18 16:49:09 2016 -0800 Description: Merge tag 'omap-for-v4.10/legacy-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc ------Legacy platform_data removal for omaps for v4.10 merge window. We've dropped the last legacy boot board-*.c files for mach-omap2 for v4.9 so now we can start removing the unused platform_data.

All of the below has been unused since v4.9 merge window:

- Drop legacy pmic init code - Apply seq_puts() fixes for legacy mux code, then drop it - Drop legacy serial init - Drop legacy i2c init - Drop legacy PM init - Drop legacy twl4030 platform init - Drop legacy USB host init - Drop legacy muxing for tusb6010, n8x0 is still using it's platform init via pdata-quirks.c - Drop legacy musb init - Drop hwmod related legacy mux code - Drop legacy hwmod data for omap3 - Drop legacy smsc911x and smc91x init - Drop legacy board flash init - Drop legacy ads7846 init - Drop legacy sdram timings

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* tag 'omap-for-v4.10/legacy-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits) ARM: OMAP2+: Drop legacy sdram timings ARM: OMAP2+: Drop legacy ads7846 init ARM: OMAP2+: Remove legacy board-flash.c ARM: OMAP2+: Remove legacy smsc911x and smc91x GPMC support ARM: OMAP2+: Remove legacy data from hwmod for omap3 ARM: OMAP2+: Remove legacy mux code ARM: OMAP2+: Remove legacy hwmod mux code ARM: OMAP2+: Remove legacy usb-musb.c platform init code ARM: OMAP2+: Remove legacy muxing for usb-tusb6010.c ARM: OMAP2+: Remove legacy usb-host.c platform init code ARM: OMAP2+: Remove legacy twl4030 platform init code ARM: OMAP2+: Remove legacy PM init ARM: OMAP2+: Remove legacy i2c.c platform init code ARM: OMAP2+: Remove legacy serial.c ARM: OMAP2+: mux: Use seq_putc() in omap_mux_dbg_signal_show() ARM: OMAP2+: mux: Replace three seq_printf() calls by seq_puts() ARM: OMAP: kill omap_pmic_init ARM: OMAP2: kill omap2_pmic_init ARM: OMAP3: kill omap3_pmic_init ARM: OMAP3: kill omap3_pmic_get_config and twl_{get,set}_voltage ...

ARM: OMAP2+: Remove legacy mux code ------All the boards booting with device tree use drivers/pinctrl-single.c instead.

Note that mach-omap1 is still using the legacy mux, so let's move the related Kconfig options from plat-omap to mach-omap1.

ARM: OMAP5: Fix mpuss_early_init ------We need to properly initialize mpuss also on omap5 like we do on omap4. Otherwise we run into similar kexec problems like we had on omap4 when trying to kexec from a kernel with PM initialized.

Fixes: 0573b957fc21 ("ARM: OMAP4+: Prevent CPU1 related hang with kexec")

ARM: OMAP4+: Prevent CPU1 related hang with kexec ------Kexec booted kernels on omap4 will hang early during the boot if the booted kernel is different version from the previous kernel.

This is because the previous kernel may have configured low-power mode

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using CPU1_WAKEUP_NS_PA_ADDR. In that case it points to the previous kernel's omap4_secondary_startup(), and CPU1 can be in low power mode from the previous kernel. When the new kernel configures the CPU1 clockdomain, CPU1 can wake from low power state prematurely during omap44xx_clockdomains_init() running random code.

Let's fix the issue by configuring CPU1_WAKEUP_NS_PA_ADDR before we call omap44xx_clockdomains_init(). Note that this is very early during the init, and we will do proper CPU1 reset during SMP init a bit later on in omap4_smp_prepare_cpus(). And we need to do this when SMP is not enabled as the previous kernel may have had it enabled.

2366 arch\arm\mach-omap2\io.c#0720 2367 arch\arm\mach-omap2\io.c#0724 2368 arch\arm\mach-omap2\Makefile#0009 Repo: 74de7126fc53 Tony Tue Dec 27 10:29:24 2016 -0800 Description: Merge branch 'omap-for-v4.10/legacy' into omap-for-v4.10/fixes ------OMAP2+ GPOs are initialized now using device tree, so legacy gpio initialization code can be removed.

ARM: OMAP2+: Remove legacy gpio code ------Legacy platform_data removal for omaps for v4.10 merge window. We've dropped the last legacy boot board-*.c files for mach-omap2 for v4.9 so now we can start removing the unused platform_data.

All of the below has been unused since v4.9 merge window:

- Drop legacy pmic init code - Apply seq_puts() fixes for legacy mux code, then drop it - Drop legacy serial init - Drop legacy i2c init - Drop legacy PM init - Drop legacy twl4030 platform init - Drop legacy USB host init - Drop legacy muxing for tusb6010, n8x0 is still using it's platform init via pdata-quirks.c - Drop legacy musb init - Drop hwmod related legacy mux code - Drop legacy hwmod data for omap3 - Drop legacy smsc911x and smc91x init - Drop legacy board flash init - Drop legacy ads7846 init - Drop legacy sdram timings

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* tag 'omap-for-v4.10/legacy-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits) ARM: OMAP2+: Drop legacy sdram timings ARM: OMAP2+: Drop legacy ads7846 init ARM: OMAP2+: Remove legacy board-flash.c ARM: OMAP2+: Remove legacy smsc911x and smc91x GPMC support ARM: OMAP2+: Remove legacy data from hwmod for omap3 ARM: OMAP2+: Remove legacy mux code ARM: OMAP2+: Remove legacy hwmod mux code ARM: OMAP2+: Remove legacy usb-musb.c platform init code ARM: OMAP2+: Remove legacy muxing for usb-tusb6010.c ARM: OMAP2+: Remove legacy usb-host.c platform init code ARM: OMAP2+: Remove legacy twl4030 platform init code ARM: OMAP2+: Remove legacy PM init ARM: OMAP2+: Remove legacy i2c.c platform init code ARM: OMAP2+: Remove legacy serial.c ARM: OMAP2+: mux: Use seq_putc() in omap_mux_dbg_signal_show() ARM: OMAP2+: mux: Replace three seq_printf() calls by seq_puts() ARM: OMAP: kill omap_pmic_init ARM: OMAP2: kill omap2_pmic_init ARM: OMAP3: kill omap3_pmic_init ARM: OMAP3: kill omap3_pmic_get_config and twl_{get,set}_voltage ...

Merge tag 'omap-for-v4.10/legacy-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc ------

ARM: OMAP2+: Drop legacy ads7846 init ------Legacy board files in mach-omap2 used the helper functions board_{nor,nand,onenand}_init() to initialize the flash devices attached to the GPMC.

With Device Tree booting the initialization is handled by the GPMC driver gpmc_probe_*_child() functions so this code is not needed anymore now that OMAP2+ is DT-only.

ARM: OMAP2+: Remove legacy board-flash.c ------When connecting an ethernet chip to the GPMC, such as smc91x or smsc911x, a GPIO has to be requested to be used as an IRQ and also the IO memory for a GPMC chip-select.

When booting with DT the chip-select allocation is handled in a generic manner in the GPMC driver and the GPIO to IRQ

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mapping is made by the DT core so this code is not needed anymore now that mach-omap2 related boards are DT-only.

ARM: OMAP2+: Remove legacy smsc911x and smc91x GPMC support ------All the boards booting with device tree use drivers/pinctrl-single.c instead.

Note that mach-omap1 is still using the legacy mux, so let's move the related Kconfig options from plat-omap to mach-omap1.

ARM: OMAP2+: Remove legacy mux code ------This is no longer needed when booted with device tree.

ARM: OMAP2+: Remove legacy usb-musb.c platform init code ------This is no longer needed when booted with device tree.

ARM: OMAP2+: Remove legacy usb-host.c platform init code ------This code is no longer used and can be removed as we are using device tree.

ARM: OMAP2+: Remove legacy twl4030 platform init code ------We can now initialize the UARTs using device tree.

ARM: OMAP2+: Remove legacy serial.c ------It's CONFIG_SOC_OMAP5, not CONFIG_ARCH_OMAP5. Looks like make randconfig builds have not hit this one yet.

Fixes: b3bf289c1c45 ("ARM: OMAP2+: Fix build with CONFIG_SMP and CONFIG_PM is not set")

ARM: OMAP5: Fix build for PM code ------

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2369 arch\arm\mach-omap2\Makefile#0066 2370 arch\arm\mach-omap2\Makefile#0083 2371 arch\arm\mach-omap2\Makefile#0238 2372 arch\arm\mach-omap2\Makefile#0245 2373 arch\arm\mach-omap2\Makefile#0249 2374 arch\arm\mach-omap2\Makefile#0256 2375 arch\arm\mach-omap2\msdi.c#0033 Repo: e9f5f1e45608 Tony Thu Oct 20 06:42:19 2016 -0700 Description: ARM: OMAP2+: Remove legacy mux code ------All the boards booting with device tree use drivers/pinctrl-single.c instead.

Note that mach-omap1 is still using the legacy mux, so let's move the related Kconfig options from plat-omap to mach-omap1.

2376 arch\arm\mach-omap2\mux.c#fileDeleted Repo: e9f5f1e45608 Tony Thu Oct 20 06:42:19 2016 -0700 Description: ARM: OMAP2+: Remove legacy mux code ------All the boards booting with device tree use drivers/pinctrl-single.c instead.

Note that mach-omap1 is still using the legacy mux, so let's move the related Kconfig options from plat-omap to mach-omap1.

ARM: OMAP2+: mux: Use seq_putc() in omap_mux_dbg_signal_show() ------A single character (line break) should be put into a sequence. Thus use the corresponding function "seq_putc".

This issue was detected by using the Coccinelle software.

ARM: OMAP2+: mux: Replace three seq_printf() calls by seq_puts() ------Strings which did not contain data format specification should be put into a sequence. Thus use the corresponding function "seq_puts".

This issue was detected by using the Coccinelle software.

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2377 arch\arm\mach-omap2\mux.h#fileDeleted Repo: e9f5f1e45608 Tony Thu Oct 20 06:42:19 2016 -0700 Description: ARM: OMAP2+: Remove legacy mux code ------All the boards booting with device tree use drivers/pinctrl-single.c instead.

Note that mach-omap1 is still using the legacy mux, so let's move the related Kconfig options from plat-omap to mach-omap1.

2378 arch\arm\mach-omap2\mux34xx.c#fileDeleted Repo: e9f5f1e45608 Tony Thu Oct 20 06:42:19 2016 -0700 Description: ARM: OMAP2+: Remove legacy mux code ------All the boards booting with device tree use drivers/pinctrl-single.c instead.

Note that mach-omap1 is still using the legacy mux, so let's move the related Kconfig options from plat-omap to mach-omap1.

2379 arch\arm\mach-omap2\mux34xx.h#fileDeleted Repo: e9f5f1e45608 Tony Thu Oct 20 06:42:19 2016 -0700 Description: ARM: OMAP2+: Remove legacy mux code ------All the boards booting with device tree use drivers/pinctrl-single.c instead.

Note that mach-omap1 is still using the legacy mux, so let's move the related Kconfig options from plat-omap to mach-omap1.

2380 arch\arm\mach-omap2\omap-mpuss-lowpower.c#0051 Repo: cbf264287233 Tony Mon Nov 7 16:50:11 2016 -0700 Description: ARM: OMAP4+: Fix bad fallthrough for cpuidle ------We don't want to fall through to a bunch of errors for retention if PM_OMAP4_CPU_OSWR_DISABLE is not configured for a SoC.

Fixes: 6099dd37c669 ("ARM: OMAP5 / DRA7: Enable CPU RET on suspend")

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ARM: OMAP5: Fix mpuss_early_init ------We need to properly initialize mpuss also on omap5 like we do on omap4. Otherwise we run into similar kexec problems like we had on omap4 when trying to kexec from a kernel with PM initialized.

Fixes: 0573b957fc21 ("ARM: OMAP4+: Prevent CPU1 related hang with kexec")

2381 arch\arm\mach-omap2\omap-mpuss-lowpower.c#0248 2382 arch\arm\mach-omap2\omap-mpuss-lowpower.c#0250 2383 arch\arm\mach-omap2\omap-mpuss-lowpower.c#0374 2384 arch\arm\mach-omap2\omap-mpuss-lowpower.c#0398 2385 arch\arm\mach-omap2\omap-mpuss-lowpower.c#0464 2386 arch\arm\mach-omap2\omap-mpuss-lowpower.c#0471 2387 arch\arm\mach-omap2\omap-mpuss-lowpower.c#0473 2388 arch\arm\mach-omap2\omap-mpuss-lowpower.c#0478 2389 arch\arm\mach-omap2\omap4-sar-layout.h#0034 Repo: 8a8be46afeaa Tony Mon Nov 7 16:50:11 2016 -0700 Description: ARM: OMAP5: Fix mpuss_early_init ------We need to properly initialize mpuss also on omap5 like we do on omap4. Otherwise we run into similar kexec problems like we had on omap4 when trying to kexec from a kernel with PM initialized.

Fixes: 0573b957fc21 ("ARM: OMAP4+: Prevent CPU1 related hang with kexec")

2390 arch\arm\mach-omap2\omap_hwmod.c#0163 Repo: 5066d5296ff2 Maninder Thu Dec 8 09:40:30 2016 +0530 Description: ARM: omap2+: fixing wrong strcat for Non-NULL terminated string ------Issue caught with static analysis tool: "Dangerous usage of 'name' (strncpy doesn't always 0-terminate it)"

Use strlcpy _includes_ the NUL terminator, and strlcat() which ensures that it won't overflow the buffer.

ARM: OMAP2+: Remove legacy hwmod mux code ------This is no longer needed when booted with device tree.

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2391 arch\arm\mach-omap2\omap_hwmod.c#0220 2392 arch\arm\mach-omap2\omap_hwmod.c#0597 2393 arch\arm\mach-omap2\omap_hwmod.c#0793 2394 arch\arm\mach-omap2\omap_hwmod.c#0794 2395 arch\arm\mach-omap2\omap_hwmod.c#0799 2396 arch\arm\mach-omap2\omap_hwmod.c#2021 2397 arch\arm\mach-omap2\omap_hwmod.c#2112 Review: COMMENT stecan Thu, 11 Jan 2018 07:26:45 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:45 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:26:45 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:45 +0100 Automatic commented! 2398 arch\arm\mach-omap2\omap_hwmod.c#2116 2399 arch\arm\mach-omap2\omap_hwmod.c#2148 2400 arch\arm\mach-omap2\omap_hwmod.c#2263 2401 arch\arm\mach-omap2\omap_hwmod.c#2337 2402 arch\arm\mach-omap2\omap_hwmod.c#3732 2403 arch\arm\mach-omap2\omap_hwmod.c#3765 2404 arch\arm\mach-omap2\omap_hwmod_2xxx_3xxx_interconnect_data.c#0020 Repo: d9d9cec02835 Tony Fri Oct 21 03:02:12 2016 -0700 Description: ARM: OMAP2+: Remove legacy data from hwmod for omap3 ------This data is now coming from device tree so we can remove the duplicate data. Let's keep the DSS and DMA related things for now until those have been converted to device tree completely.

While at it, let's also add the trailing commas to data structures so further processing with scripts will be a bit easier.

2405 arch\arm\mach-omap2\omap_hwmod_2xxx_3xxx_interconnect_data.c#0150 2406 arch\arm\mach-omap2\omap_hwmod_2xxx_3xxx_interconnect_data.c#0152

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2407 arch\arm\mach-omap2\omap_hwmod_2xxx_3xxx_interconnect_data.c#0154 2408 arch\arm\mach-omap2\omap_hwmod_2xxx_3xxx_ipblock_data.c#0048 Repo: d9d9cec02835 Tony Fri Oct 21 03:02:12 2016 -0700 Description: ARM: OMAP2+: Remove legacy data from hwmod for omap3 ------This data is now coming from device tree so we can remove the duplicate data. Let's keep the DSS and DMA related things for now until those have been converted to device tree completely.

While at it, let's also add the trailing commas to data structures so further processing with scripts will be a bit easier.

2409 arch\arm\mach-omap2\omap_hwmod_2xxx_3xxx_ipblock_data.c#0126 2410 arch\arm\mach-omap2\omap_hwmod_2xxx_3xxx_ipblock_data.c#0130 2411 arch\arm\mach-omap2\omap_hwmod_2xxx_3xxx_ipblock_data.c#0134 2412 arch\arm\mach-omap2\omap_hwmod_2xxx_3xxx_ipblock_data.c#0138 2413 arch\arm\mach-omap2\omap_hwmod_2xxx_3xxx_ipblock_data.c#0143 2414 arch\arm\mach-omap2\omap_hwmod_2xxx_3xxx_ipblock_data.c#0215 2415 arch\arm\mach-omap2\omap_hwmod_2xxx_3xxx_ipblock_data.c#0218 2416 arch\arm\mach-omap2\omap_hwmod_2xxx_3xxx_ipblock_data.c#0253 2417 arch\arm\mach-omap2\omap_hwmod_2xxx_3xxx_ipblock_data.c#0256 2418 arch\arm\mach-omap2\omap_hwmod_2xxx_3xxx_ipblock_data.c#0280 2419 arch\arm\mach-omap2\omap_hwmod_2xxx_interconnect_data.c#0194 Repo: d9d9cec02835 Tony Fri Oct 21 03:02:12 2016 -0700 Description: ARM: OMAP2+: Remove legacy data from hwmod for omap3 ------This data is now coming from device tree so we can remove the duplicate data. Let's keep the DSS and DMA related things for now until those have been converted to device tree completely.

While at it, let's also add the trailing commas to data structures so further processing with scripts will be a bit easier.

2420 arch\arm\mach-omap2\omap_hwmod_2xxx_interconnect_data.c#0209 2421 arch\arm\mach-omap2\omap_hwmod_2xxx_interconnect_data.c#0224

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2422 arch\arm\mach-omap2\omap_hwmod_2xxx_interconnect_data.c#0239 2423 arch\arm\mach-omap2\omap_hwmod_2xxx_ipblock_data.c#0572 Repo: d9d9cec02835 Tony Fri Oct 21 03:02:12 2016 -0700 Description: ARM: OMAP2+: Remove legacy data from hwmod for omap3 ------This data is now coming from device tree so we can remove the duplicate data. Let's keep the DSS and DMA related things for now until those have been converted to device tree completely.

While at it, let's also add the trailing commas to data structures so further processing with scripts will be a bit easier.

2424 arch\arm\mach-omap2\omap_hwmod_33xx_43xx_common_data.h#0071 Repo: d88d30e7b55d Lokesh Vutla Tue Oct 18 10:55:27 2016 +0300 Description: ARM: AMx3xx: hwmod: Add data for RNG ------Hardware random number generator is present in both AM33xx and AM43xx SoC's. So moving the hwmod data to common data.

2425 arch\arm\mach-omap2\omap_hwmod_33xx_43xx_common_data.h#0084 2426 arch\arm\mach-omap2\omap_hwmod_33xx_43xx_interconnect_data.c#0550 Repo: d88d30e7b55d Lokesh Vutla Tue Oct 18 10:55:27 2016 +0300 Description: ARM: AMx3xx: hwmod: Add data for RNG ------Hardware random number generator is present in both AM33xx and AM43xx SoC's. So moving the hwmod data to common data.

2427 arch\arm\mach-omap2\omap_hwmod_33xx_43xx_ipblock_data.c#0271 Repo: d88d30e7b55d Lokesh Vutla Tue Oct 18 10:55:27 2016 +0300 Description: ARM: AMx3xx: hwmod: Add data for RNG ------Hardware random number generator is present in both AM33xx and AM43xx SoC's. So moving the hwmod data to common data.

2428 arch\arm\mach-omap2\omap_hwmod_33xx_43xx_ipblock_data.c#1345 2429 arch\arm\mach-omap2\omap_hwmod_33xx_43xx_ipblock_data.c#1419

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2430 arch\arm\mach-omap2\omap_hwmod_33xx_data.c#0506 Repo: d88d30e7b55d Lokesh Vutla Tue Oct 18 10:55:27 2016 +0300 Description: ARM: AMx3xx: hwmod: Add data for RNG ------Hardware random number generator is present in both AM33xx and AM43xx SoC's. So moving the hwmod data to common data.

2431 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0056 Repo: d9d9cec02835 Tony Fri Oct 21 03:02:12 2016 -0700 Description: ARM: OMAP2+: Remove legacy data from hwmod for omap3 ------This data is now coming from device tree so we can remove the duplicate data. Let's keep the DSS and DMA related things for now until those have been converted to device tree completely.

While at it, let's also add the trailing commas to data structures so further processing with scripts will be a bit easier.

2432 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0065 2433 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0098 2434 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0105 2435 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0131 2436 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0200 2437 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0219 2438 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0237 2439 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0255 2440 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0273 2441 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0292 2442 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0311 2443 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0330 2444 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0349 2445 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0368 2446 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0387

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2447 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0404 2448 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0411 2449 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0488 2450 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0507 2451 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0526 2452 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0544 2453 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0549 2454 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0557 2455 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0573 2456 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0578 2457 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0600 2458 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0628 2459 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0717 2460 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0741 2461 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0754 2462 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0818 2463 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0843 2464 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0865 2465 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0870 2466 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0879 2467 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0931 2468 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0956 2469 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#0981 2470 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1006 2471 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1024 2472 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1036 2473 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1054 2474 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1066 2475 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1159

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2476 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1169 2477 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1186 2478 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1200 2479 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1218 2480 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1232 2481 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1250 2482 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1257 2483 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1266 2484 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1283 2485 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1290 2486 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1299 2487 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1328 2488 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1336 2489 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1342 2490 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1350 2491 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1397 2492 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1416 2493 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1434 2494 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1442 2495 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1461 2496 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1479 2497 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1548 2498 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1571 2499 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1588 2500 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1593 2501 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1607 2502 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1624 2503 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1629 2504 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1641

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2505 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1676 2506 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1678 2507 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1685 2508 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1694 2509 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1714 2510 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1725 2511 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1750 2512 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1755 2513 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1777 2514 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1797 2515 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1817 2516 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1822 2517 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1839 2518 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1859 2519 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1878 2520 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1883 2521 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1895 2522 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1934 2523 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#1944 2524 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2018 2525 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2027 2526 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2042 2527 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2137 2528 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2146 2529 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2170 2530 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2183 2531 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2187 2532 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2200 2533 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2218

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2534 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2259 2535 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2261 2536 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2268 2537 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2270 2538 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2278 2539 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2280 2540 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2287 2541 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2289 2542 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2293 2543 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2306 2544 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2308 2545 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2312 2546 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2325 2547 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2330 2548 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2343 2549 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2348 2550 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2361 2551 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2366 2552 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2379 2553 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2384 2554 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2397 2555 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2406 2556 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2412 2557 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2422 2558 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2428 2559 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2434 2560 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2447 2561 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2453 2562 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2459

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2563 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2472 2564 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2480 2565 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2485 2566 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2498 2567 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2506 2568 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2510 2569 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2524 2570 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2528 2571 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2542 2572 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2561 2573 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2575 2574 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2579 2575 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2593 2576 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2597 2577 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2611 2578 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2615 2579 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2629 2580 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2633 2581 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2647 2582 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2651 2583 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2665 2584 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2669 2585 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2683 2586 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2687 2587 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2701 2588 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2705 2589 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2719 2590 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2728 2591 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2737

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2592 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2741 2593 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2755 2594 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2760 2595 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2773 2596 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2782 2597 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2788 2598 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2797 2599 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2803 2600 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2813 2601 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2819 2602 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2824 2603 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2838 2604 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2844 2605 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2854 2606 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2860 2607 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2870 2608 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2876 2609 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2883 2610 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2895 2611 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2900 2612 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2912 2613 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2917 2614 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#2929 2615 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3005 2616 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3017 2617 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3022 2618 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3034 2619 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3039 2620 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3051

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2621 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3067 2622 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3069 2623 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3081 2624 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3096 2625 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3100 2626 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3115 2627 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3119 2628 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3134 2629 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3138 2630 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3153 2631 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3157 2632 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3172 2633 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3176 2634 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3191 2635 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3195 2636 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3210 2637 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3226 2638 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3235 2639 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3244 2640 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3249 2641 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3262 2642 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3273 2643 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3297 2644 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3301 2645 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3315 2646 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3324 2647 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3330 2648 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3339 2649 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3352

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2650 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3437 2651 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3462 2652 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3467 2653 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3474 2654 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3489 2655 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3502 2656 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3528 2657 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3536 2658 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3550 2659 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3563 2660 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3664 2661 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3669 2662 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3674 2663 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3680 2664 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3685 2665 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3713 2666 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3720 2667 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3732 2668 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3739 2669 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3746 2670 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3760 2671 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3784 2672 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3803 2673 arch\arm\mach-omap2\omap_hwmod_3xxx_data.c#3811 2674 arch\arm\mach-omap2\omap_hwmod_43xx_data.c#0445 Repo: d88d30e7b55d Lokesh Vutla Tue Oct 18 10:55:27 2016 +0300 Description: ARM: AMx3xx: hwmod: Add data for RNG ------Hardware random number generator is present in both AM33xx and AM43xx SoC's. So moving the hwmod data to common data.

ARM: AM43xx: hwmod: Add data for DES ------

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AM43xx SoC contains DES crypto hardware accelerator. Add hwmod data for this IP so that it can be utilized by crypto frameworks.

2675 arch\arm\mach-omap2\omap_hwmod_43xx_data.c#0898 2676 arch\arm\mach-omap2\omap_hwmod_43xx_data.c#0952 2677 arch\arm\mach-omap2\omap_hwmod_43xx_data.c#0986 2678 arch\arm\mach-omap2\omap_hwmod_7xx_data.c#0693 Repo: 6cd9699c6b21 Nishanth Fri Oct 21 16:08:38 2016 +0530 Description: ARM: DRA7: hwmod: Do not register RTC on DRA71 ------RTC is not available on DRA71x, so accessing any of the RTC register or clkctrl register will lead to a crash. So, do not register RTC hwmod for DRA71x.

ARM: DRA7: hwmod: Add data for RNG IP ------DRA7 SoC contains hardware random number generator. Add hwmod data for this IP so that it can be utilized.

ARM: DRA7: hwmod: Add data for SHA IP ------DRA7 SoC contains SHA crypto hardware accelerator. Add hwmod data for this IP so that it can be utilized by crypto frameworks.

ARM: DRA7: hwmod: Add data for AES IP ------DRA7 SoC contains AES crypto hardware accelerator. Add hwmod data for this IP so that it can be utilized by crypto frameworks.

ARM: DRA7: hwmod: Add data for DES IP ------DRA7 SoC contains DES crypto hardware accelerator. Add hwmod data for this IP so that it can be utilized by crypto frameworks.

ARM: DRA7: hwmod: remove DSS addresses from hwmod ------The addresses for DSS are provided in the DT data, so they can be removed from the hwmod.

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2679 arch\arm\mach-omap2\omap_hwmod_7xx_data.c#2616 2680 arch\arm\mach-omap2\omap_hwmod_7xx_data.c#3060 2681 arch\arm\mach-omap2\omap_hwmod_7xx_data.c#3797 2682 arch\arm\mach-omap2\omap_hwmod_7xx_data.c#3829 2683 arch\arm\mach-omap2\omap_hwmod_7xx_data.c#3970 2684 arch\arm\mach-omap2\omap_hwmod_7xx_data.c#4018 2685 arch\arm\mach-omap2\omap_hwmod_7xx_data.c#4047 2686 arch\arm\mach-omap2\omap_hwmod_7xx_data.c#4065 2687 arch\arm\mach-omap2\omap_hwmod_7xx_data.c#4079 2688 arch\arm\mach-omap2\omap_hwmod_7xx_data.c#4099 2689 arch\arm\mach-omap2\omap_hwmod_common_data.h#0022 Repo: 14944934f8ac Grygorii Mon Nov 21 11:26:27 2016 -0600 Description: ARM: OMAP2+: Remove legacy gpio code ------OMAP2+ GPOs are initialized now using device tree, so legacy gpio initialization code can be removed.

ARM: OMAP2+: Remove legacy data from hwmod for omap3 ------This data is now coming from device tree so we can remove the duplicate data. Let's keep the DSS and DMA related things for now until those have been converted to device tree completely.

While at it, let's also add the trailing commas to data structures so further processing with scripts will be a bit easier.

2690 arch\arm\mach-omap2\omap_hwmod_common_data.h#0036 2691 arch\arm\mach-omap2\omap_hwmod_common_data.h#0139 2692 arch\arm\mach-omap2\pdata-quirks.c#0034 Repo: a3ac350793d9 Adam Ford Tue Jan 3 11:37:48 2017 -0600 Description: ARM: OMAP2+: Fix WL1283 Bluetooth Baud Rate ------Commit 485fa1261f78 ("ARM: OMAP2+: LogicPD Torpedo + Wireless: Add Bluetooth") set the wrong baud rate for the UART. The Baud rate was 300,000 and it should be 3,000,000 for WL1283.

ARM: OMAP2+: Drop legacy ads7846 init

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------

2693 arch\arm\mach-omap2\pdata-quirks.c#0165 2694 arch\arm\mach-omap2\pm-debug.c#0117 Repo: 5c02b01d234f Markus Sat Oct 15 22:30:44 2016 +0200 Description: ARM: OMAP2+: pm-debug: Use seq_putc() in two functions ------A single character (line break) should be put into a sequence at the end. Thus use the corresponding function "seq_putc".

This issue was detected by using the Coccinelle software.

2695 arch\arm\mach-omap2\pm-debug.c#0141 2696 arch\arm\mach-omap2\pm.c#0033 Repo: cb6675d6a868 Tony Mon Oct 17 00:08:40 2016 -0700 Description: ARM: OMAP2+: Remove legacy PM init ------This is no longer needed when booted with device tree. And let's replace cpu_is with soc_is for the PM code to avoid confusion, they do the same thing.

Note that omap_pmic_late_init() now just calls omap3_twl_init() and omap4_twl_init() to initialize the voltage layer so we can remove the remaining references to twl-common code and remove it in the following patch.

2697 arch\arm\mach-omap2\pm.c#0075 2698 arch\arm\mach-omap2\pm.c#0218 2699 arch\arm\mach-omap2\pm.c#0230 2700 arch\arm\mach-omap2\pm.c#0255 2701 arch\arm\mach-omap2\pm.c#0264 2702 arch\arm\mach-omap2\pm.c#0272 2703 arch\arm\mach-omap2\pm.c#0282 2704 arch\arm\mach-omap2\pm.c#0292 2705 arch\arm\mach-omap2\pm.c#0298

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2706 arch\arm\mach-omap2\pm.c#0308 2707 arch\arm\mach-omap2\pm44xx.c#0290 Repo: 7abdb0e23e7b Santosh Mon Nov 7 16:50:11 2016 -0700 Description: ARM: OMAP5: Add basic cpuidle MPU CSWR support ------Add OMAP5 CPUIDLE support.

This patch adds MPUSS low power states in cpuidle.

C1 - CPU0 WFI + CPU1 WFI + MPU ON C2 - CPU0 RET + CPU1 RET + MPU CSWR

Modified from TI kernel tree commit 605967fd2205 ("ARM: DRA7: PM: cpuidle MPU CSWR support") except enable cpuidle for omap5 instead of dra7.

According to Nishanth Menon , cpuidle on dra7 is not supported properly in the hardware so we don't want to enable it. However, for omap5 this adds some nice power savings. Note that the TI 3.8 based tree has other cpuidle states that we may be able to enable later on.

On omap5-uevm, the power consumption eventually settles down to about 920mW with ehci-omap and ohci-omap3 unloaded compared to about 1.7W without these patches. Note that it seems to take few minutes after booting for the idle power to go down to 920mW from 1.3W, no idea so far what might be causing that.

2708 arch\arm\mach-omap2\prcm43xx.h#0095 Repo: d88d30e7b55d Lokesh Vutla Tue Oct 18 10:55:27 2016 +0300 Description: ARM: AMx3xx: hwmod: Add data for RNG ------Hardware random number generator is present in both AM33xx and AM43xx SoC's. So moving the hwmod data to common data.

ARM: AM43xx: hwmod: Add data for DES ------AM43xx SoC contains DES crypto hardware accelerator. Add hwmod data for this IP so that it can be utilized by crypto frameworks.

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2709 arch\arm\mach-omap2\prcm43xx.h#0137 2710 arch\arm\mach-omap2\prm_common.c#0298 Repo: 9a6b6f75d9da Markus Sat Dec 3 21:46:02 2016 +0100 Description: ARM: OMAP2+: PRM: Delete an error message for a failed memory allocation ------Omit an extra message for a memory allocation failure in this function.

Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings- WSang_0.pdf

2711 arch\arm\mach-omap2\prm_common.c#0301 2712 arch\arm\mach-omap2\sdram-hynix-h8mbx00u0mer-0em.h#fileDeleted Repo: 19944b3a4a30 Tony Thu Nov 10 16:07:32 2016 -0700 Description: ARM: OMAP2+: Drop legacy sdram timings ------These are no longer used. If somebody needs to configure memory timings for various idle modes, they should be implemented as a device driver callbacks from the PM code.

2713 arch\arm\mach-omap2\sdram-micron-mt46h32m32lf-6.h#fileDeleted Repo: 19944b3a4a30 Tony Thu Nov 10 16:07:32 2016 -0700 Description: ARM: OMAP2+: Drop legacy sdram timings ------These are no longer used. If somebody needs to configure memory timings for various idle modes, they should be implemented as a device driver callbacks from the PM code.

2714 arch\arm\mach-omap2\sdram-nokia.c#fileDeleted Repo: 19944b3a4a30 Tony Thu Nov 10 16:07:32 2016 -0700 Description: ARM: OMAP2+: Drop legacy sdram timings ------These are no longer used. If somebody needs to configure memory timings for various idle modes, they should be implemented as a device driver callbacks from the PM code.

ARM: OMAP: remove plat/clock.h ------Remove arch/arm/plat-omap/include/plat/clock.h by merging it into

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arch/arm/mach-omap1/clock.h and arch/arm/mach-omap2/clock.h. The goal here is to facilitate ARM single image kernels by removing includes via the "plat/" symlink.

2715 arch\arm\mach-omap2\sdram-nokia.h#fileDeleted Repo: 19944b3a4a30 Tony Thu Nov 10 16:07:32 2016 -0700 Description: ARM: OMAP2+: Drop legacy sdram timings ------These are no longer used. If somebody needs to configure memory timings for various idle modes, they should be implemented as a device driver callbacks from the PM code.

2716 arch\arm\mach-omap2\sdram-numonyx-m65kxxxxam.h#fileDeleted Repo: 19944b3a4a30 Tony Thu Nov 10 16:07:32 2016 -0700 Description: ARM: OMAP2+: Drop legacy sdram timings ------These are no longer used. If somebody needs to configure memory timings for various idle modes, they should be implemented as a device driver callbacks from the PM code.

2717 arch\arm\mach-omap2\sdram-qimonda-hyb18m512160af-6.h#fileDeleted Repo: 19944b3a4a30 Tony Thu Nov 10 16:07:32 2016 -0700 Description: ARM: OMAP2+: Drop legacy sdram timings ------These are no longer used. If somebody needs to configure memory timings for various idle modes, they should be implemented as a device driver callbacks from the PM code.

2718 arch\arm\mach-omap2\serial.c#fileDeleted Repo: f3b78f728955 Tony Mon Oct 17 00:02:23 2016 -0700 Description: ARM: OMAP2+: Remove legacy serial.c ------We can now initialize the UARTs using device tree.

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2719 arch\arm\mach-omap2\timer.c#0372 Repo: f86a2c875fd1 Grygorii Mon Dec 5 09:27:44 2016 +0530 Description: ARM: omap2+: am437x: rollback to use omap3_gptimer_timer_init() ------The commit 55ee7017ee31 ("arm: omap2: board-generic: use omap4_local_timer_init for AM437x") unintentionally changes the clocksource devices for AM437x from OMAP GP Timer to SyncTimer32K.

Unfortunately, the SyncTimer32K is starving from frequency deviation as mentioned in commit 5b5c01359152 ("ARM: OMAP2+: AM43x: Use gptimer as clocksource") and, as reported by Franklin [1], even its monotonic nature is under question (most probably there is a HW issue, but it's still under investigation).

Taking into account above facts It's reasonable to rollback to the use of omap3_gptimer_timer_init().

[1] http://www.spinics.net/lists/linux-omap/msg127425.html

Fixes: 55ee7017ee31 ("arm: omap2: board-generic: use omap4_local_timer_init for AM437x")

clocksource: Use a plain u64 instead of cycle_t ------There is no point in having an extra type for extra confusion. u64 is unambiguous.

Conversion was done with the following coccinelle script:

@rem@ @@ -typedef u64 cycle_t;

@fix@ typedef cycle_t; @@ -cycle_t +u64

2720 arch\arm\mach-omap2\timer.c#0374 2721 arch\arm\mach-omap2\timer.c#0513 2722 arch\arm\mach-omap2\timer.c#0519

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2723 arch\arm\mach-omap2\timer.c#0525 2724 arch\arm\mach-omap2\twl-common.c#fileDeleted Repo: 0d07c1cba36e Tony Mon Oct 17 00:30:02 2016 -0700 Description: ARM: OMAP2+: Remove legacy twl4030 platform init code ------This code is no longer used and can be removed as we are using device tree.

ARM: OMAP: kill omap_pmic_init ------Last user of this function was removed in commit 9b714 ("ARM: OMAP2+: Drop legacy board file for n900") during legacy board file removal.

ARM: OMAP3: kill omap3_pmic_get_config and twl_{get,set}_voltage ------Last user of these functions was removed in commit e92fc4 ("ARM: OMAP2+: Drop legacy board file for LDP") during legacy board file removal.

ARM: OMAP4: kill omap4_pmic_init and omap4_pmic_get_config ------Last user of these functions was deleted in commit b42b91 ("ARM: OMAP2+: Remove board-omap4panda.c") during DT transition.

2725 arch\arm\mach-omap2\twl-common.h#fileDeleted Repo: 0d07c1cba36e Tony Mon Oct 17 00:30:02 2016 -0700 Description: ARM: OMAP2+: Remove legacy twl4030 platform init code ------This code is no longer used and can be removed as we are using device tree.

ARM: OMAP: kill omap_pmic_init ------Last user of this function was removed in commit 9b714 ("ARM: OMAP2+: Drop legacy board file for n900") during legacy board file removal.

ARM: OMAP2: kill omap2_pmic_init ------Last call of function was removed with commit

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bfd46a ("ARM: OMAP: Fix i2c init for twl4030")

ARM: OMAP3: kill omap3_pmic_init ------Last user of this function was removed in commit e92fc4 ("ARM: OMAP2+: Drop legacy board file for LDP") during legacy board file removal.

ARM: OMAP3: kill omap3_pmic_get_config and twl_{get,set}_voltage ------Last user of these functions was removed in commit e92fc4 ("ARM: OMAP2+: Drop legacy board file for LDP") during legacy board file removal.

ARM: OMAP4: kill omap4_pmic_init and omap4_pmic_get_config ------Last user of these functions was deleted in commit b42b91 ("ARM: OMAP2+: Remove board-omap4panda.c") during DT transition.

2726 arch\arm\mach-omap2\usb-host.c#fileDeleted Repo: 9080b8dc761a Tony Mon Oct 17 00:44:45 2016 -0700 Description: ARM: OMAP2+: Remove legacy usb-host.c platform init code ------This is no longer needed when booted with device tree.

usb: phy: rename to ------now that all functions match the driver name, the only missing piece is to rename the header file itself.

2727 arch\arm\mach-omap2\usb-musb.c#fileDeleted Repo: 4e37d32fef08 Tony Mon Oct 17 00:48:32 2016 -0700 Description: ARM: OMAP2+: Remove legacy usb-musb.c platform init code ------This is no longer needed when booted with device tree.

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2728 arch\arm\mach-omap2\usb-tusb6010.c#0025 Repo: 602105ed740d Tony Mon Oct 17 00:47:34 2016 -0700 Description: ARM: OMAP2+: Remove legacy muxing for usb-tusb6010.c ------We are moving to device tree based booting, and this should be done using pinctrl-single instead.

2729 arch\arm\mach-omap2\usb-tusb6010.c#0229 arch\arm\mach-orion5x\ 2730 arch\arm\mach-orion5x\Kconfig#0087 Repo: ecfe69639157 Ashley Sat Nov 19 08:16:39 2016 +0100 Description: ARM: orion5x: remove legacy support of ls-chl ------This patch removes the legacy support of ls-chl which is converted to the device tree.

[[email protected]: removal extracted from a wider patch]

2731 arch\arm\mach-orion5x\ls-chl-setup.c#fileDeleted Repo: ecfe69639157 Ashley Sat Nov 19 08:16:39 2016 +0100 Description: ARM: orion5x: remove legacy support of ls-chl ------This patch removes the legacy support of ls-chl which is converted to the device tree.

[[email protected]: removal extracted from a wider patch]

ARM: orion5x: clean up mach/*.h headers ------This is a simple move of all header files that are no longer included by anything else from the include/mach directory to the platform directory itself as preparation for multiplatform support.

The mach/uncompress.h headers are left in place for now, and are mildly modified to be independent of the other headers. They will be removed entirely when ARCH_MULTIPLATFORM gets enabled and they become obsolete.

Rather than updating the path names inside of the comments of each header, I delete those comments to avoid having to update them again, should they get moved or copied another time.

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2732 arch\arm\mach-orion5x\Makefile#0021 Repo: ecfe69639157 Ashley Sat Nov 19 08:16:39 2016 +0100 Description: ARM: orion5x: remove legacy support of ls-chl ------This patch removes the legacy support of ls-chl which is converted to the device tree.

[[email protected]: removal extracted from a wider patch] arch\arm\mach-oxnas\ 2733 arch\arm\mach-oxnas\Kconfig#0004 Repo: e330ea5e8cea Neil Fri Sep 9 12:23:45 2016 +0200 Description: ARM: oxnas: Add OX820 config and makefile entry ------Refactor the oxnas Kconfig entries among the OX810SE and OX820 configs, and add the files to support the OX820 SMP feature.

ARM: oxnas: select reset controller framework ------For unknown reasons, we have to enable three symbols for a platform to use a reset controller driver, otherwise we get a Kconfig warning:

warning: (MACH_OX810SE) selects RESET_OXNAS which has unmet direct dependencies (RESET_CONTROLLER)

This selects the other two symbols for oxnas.

2734 arch\arm\mach-oxnas\Kconfig#0006 2735 arch\arm\mach-oxnas\Kconfig#0013 2736 arch\arm\mach-oxnas\Kconfig#0021 2737 arch\arm\mach-oxnas\Kconfig#0023 2738 arch\arm\mach-oxnas\Kconfig#0026 2739 arch\arm\mach-oxnas\headsmp.S#newFile Repo: af76e806b5b7 Neil Fri Sep 9 12:23:11 2016 +0200 Description: ARM: oxnas: Add OX820 SMP support ------The Oxford Semiconductor OX820 is a ARM11MPcore based SoC sharing some features with the OX810 earlier SoC. This patch adds the core to wake up the second core.

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Clarifications about Copyrights dates : - hotplug.c was taken from an old versatile code by Ma Haijun and left verbatim - headsmp.S was taken from an old versatile code and adapted by Ma Haijun - platsmp.c is a mix from versatile code, Ma Haijun code and my code for DT Hence the 2002/2003 ARM Coryrights and 2013 Ma Haijun Copyrights.

2740 arch\arm\mach-oxnas\hotplug.c#newFile Repo: af76e806b5b7 Neil Fri Sep 9 12:23:11 2016 +0200 Description: ARM: oxnas: Add OX820 SMP support ------The Oxford Semiconductor OX820 is a ARM11MPcore based SoC sharing some features with the OX810 earlier SoC. This patch adds the core to wake up the second core.

Clarifications about Copyrights dates : - hotplug.c was taken from an old versatile code by Ma Haijun and left verbatim - headsmp.S was taken from an old versatile code and adapted by Ma Haijun - platsmp.c is a mix from versatile code, Ma Haijun code and my code for DT Hence the 2002/2003 ARM Coryrights and 2013 Ma Haijun Copyrights.

2741 arch\arm\mach-oxnas\Makefile#newFile Repo: af76e806b5b7 Neil Fri Sep 9 12:23:11 2016 +0200 Description: ARM: oxnas: Add OX820 SMP support ------The Oxford Semiconductor OX820 is a ARM11MPcore based SoC sharing some features with the OX810 earlier SoC. This patch adds the core to wake up the second core.

Clarifications about Copyrights dates : - hotplug.c was taken from an old versatile code by Ma Haijun and left verbatim - headsmp.S was taken from an old versatile code and adapted by Ma Haijun - platsmp.c is a mix from versatile code, Ma Haijun code and my code for DT Hence the 2002/2003 ARM Coryrights and 2013 Ma Haijun Copyrights.

2742 arch\arm\mach-oxnas\platsmp.c#newFile Repo: af76e806b5b7 Neil Fri Sep 9 12:23:11 2016 +0200 Description: ARM: oxnas: Add OX820 SMP support ------The Oxford Semiconductor OX820 is a ARM11MPcore based SoC sharing some features with the OX810 earlier SoC. This patch adds the core to wake up the second core.

Clarifications about Copyrights dates :

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- hotplug.c was taken from an old versatile code by Ma Haijun and left verbatim - headsmp.S was taken from an old versatile code and adapted by Ma Haijun - platsmp.c is a mix from versatile code, Ma Haijun code and my code for DT Hence the 2002/2003 ARM Coryrights and 2013 Ma Haijun Copyrights.

arch\arm\mach-pxa\ 2743 arch\arm\mach-pxa\corgi.c#0038 Repo: f2131c543649 Wei Yongjun Sat Oct 29 13:56:30 2016 +0200 Description: ARM: pxa: remove duplicated include from spitz.c ------This partially reverts commit 12beb346710b ("Merge tag 'pxa-fixes-v4.8' of https://github.com/rjarzmik/linux into randconfig-4.8").

This former patch introduced accidentally a double include of module.h.

2744 arch\arm\mach-pxa\em-x270.c#0026 Repo: d9fa04725f27 Robert Fri Sep 23 22:30:54 2016 +0200 Description: ARM: pxa: em-x270: use the new pxa_camera platform_data ------pxa_camera has transitioned from a soc_camera driver to a standalone v4l2 driver. Amend the device declaration accordingly.

2745 arch\arm\mach-pxa\em-x270.c#0038 2746 arch\arm\mach-pxa\em-x270.c#0961 2747 arch\arm\mach-pxa\em-x270.c#0972 2748 arch\arm\mach-pxa\em-x270.c#0991 2749 arch\arm\mach-pxa\em-x270.c#0997 2750 arch\arm\mach-pxa\em-x270.c#1026 2751 arch\arm\mach-pxa\em-x270.c#1033 2752 arch\arm\mach-pxa\em-x270.c#1037 2753 arch\arm\mach-pxa\em-x270.c#1041 2754 arch\arm\mach-pxa\em-x270.c#1043 2755 arch\arm\mach-pxa\em-x270.c#1045 2756 arch\arm\mach-pxa\ezx.c#0020 Repo: 6c1b417adc8f Robert Fri Sep 23 22:30:53 2016 +0200 Description: ARM: pxa: ezx: use the new pxa_camera platform_data

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------pxa_camera has transitioned from a soc_camera driver to a standalone v4l2 driver. Amend the device declaration accordingly.

2757 arch\arm\mach-pxa\ezx.c#0028 2758 arch\arm\mach-pxa\ezx.c#0726 2759 arch\arm\mach-pxa\ezx.c#0770 2760 arch\arm\mach-pxa\ezx.c#0773 2761 arch\arm\mach-pxa\ezx.c#0776 2762 arch\arm\mach-pxa\ezx.c#0777 2763 arch\arm\mach-pxa\ezx.c#0780 2764 arch\arm\mach-pxa\ezx.c#0782 2765 arch\arm\mach-pxa\ezx.c#0784 2766 arch\arm\mach-pxa\ezx.c#0787 2767 arch\arm\mach-pxa\ezx.c#0791 2768 arch\arm\mach-pxa\ezx.c#0801 2769 arch\arm\mach-pxa\ezx.c#0814 2770 arch\arm\mach-pxa\ezx.c#0819 2771 arch\arm\mach-pxa\ezx.c#0821 2772 arch\arm\mach-pxa\ezx.c#0827 2773 arch\arm\mach-pxa\ezx.c#1004 2774 arch\arm\mach-pxa\ezx.c#1020 2775 arch\arm\mach-pxa\ezx.c#1023 2776 arch\arm\mach-pxa\ezx.c#1026 2777 arch\arm\mach-pxa\ezx.c#1027 2778 arch\arm\mach-pxa\ezx.c#1030 2779 arch\arm\mach-pxa\ezx.c#1035 2780 arch\arm\mach-pxa\ezx.c#1052 2781 arch\arm\mach-pxa\ezx.c#1054 2782 arch\arm\mach-pxa\ezx.c#1056

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2783 arch\arm\mach-pxa\ezx.c#1125 2784 arch\arm\mach-pxa\ezx.c#1129 2785 arch\arm\mach-pxa\ezx.c#1148 2786 arch\arm\mach-pxa\ezx.c#1150 2787 arch\arm\mach-pxa\ezx.c#1156 2788 arch\arm\mach-pxa\generic.c#0046 Repo: d3570e3c5002 Robert Mon Sep 19 21:12:15 2016 +0200 Description: ARM: sa11x0/pxa: get rid of get_clock_tick_rate ------The last user of this function is gone, so remove it. The clock API should now be used to get clock rates.

ARM: sa11x0/pxa: acquire timer rate from the clock rate ------As both pxa and sa1100 provide a clock to the timer, the rate can be inferred from the clock rather than hard encoded in a functional call.

This patch changes the pxa timer to have a mandatory clock which is used as the timer rate.

ARM: pxa: Transition pxa25x, pxa27x, pxa3xx to clk framework ------Transition the PXA25x, PXA27x and PXA3xx CPUs to the clock framework. This transition still enables legacy platforms to run without device tree as before, ie relying on platform data encoded in board specific files.

This is the last step of clock framework transition for pxa platforms. It was tested on lubbock (pxa25x), mioa701 (pxa27x) and zylonite (pxa3xx).

2789 arch\arm\mach-pxa\generic.c#0072 2790 arch\arm\mach-pxa\idp.c#0088 Repo: 9a9743421581 Robert Mon Oct 17 21:45:29 2016 +0200 Description: ARM: pxa: enhance smc91x platform data ------Instead of having the smc91x driver relying on machine_is_*() calls, provide this data through platform data, ie. idp, mainstone and stargate.

This way, the driver doesn't need anymore machine_is_*() calls, which

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wouldn't work anymore with a device-tree build.

2791 arch\arm\mach-pxa\mainstone.c#0143 Repo: 9a9743421581 Robert Mon Oct 17 21:45:29 2016 +0200 Description: ARM: pxa: enhance smc91x platform data ------Instead of having the smc91x driver relying on machine_is_*() calls, provide this data through platform data, ie. idp, mainstone and stargate.

This way, the driver doesn't need anymore machine_is_*() calls, which wouldn't work anymore with a device-tree build.

ARM: pxa: make more mach/*.h files local ------Lots of header files are never included outside of a mach-pxa directory and do not need to be made visible in include/mach, so let's just move them all down one level.

ARM: pxa: mainstone: Use PWM lookup table ------Use a PWM lookup table to provide the PWM to the pwm-backlight device. The driver has a legacy code path that is required only because boards still use the legacy method of requesting PWMs by global ID. Replacing these usages allows that legacy fallback to be removed.

2792 arch\arm\mach-pxa\mioa701.c#0060 Repo: 4ebfcdee815a Robert Fri Sep 23 22:30:52 2016 +0200 Description: ARM: pxa: mioa701: use the new pxa_camera platform_data ------pxa_camera has transitioned from a soc_camera driver to a standalone v4l2 driver. Amend the device declaration accordingly.

2793 arch\arm\mach-pxa\mioa701.c#0630 2794 arch\arm\mach-pxa\mioa701.c#0647 2795 arch\arm\mach-pxa\mioa701.c#0687 2796 arch\arm\mach-pxa\mioa701.c#0699

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2797 arch\arm\mach-pxa\mioa701.c#0764 2798 arch\arm\mach-pxa\mioa701.c#0772 2799 arch\arm\mach-pxa\pxa25x.c#0159 Repo: e413bd33ac44 Robert Mon Sep 26 09:21:51 2016 +0200 Description: ARM: pxa: fix pxa25x interrupt init ------In the device-tree case, the root interrupt controller cannot be accessed through the 6th coprocessor, contrary to pxa27x and pxa3xx architectures.

Fix it to behave as in non-devicetree builds.

Fixes: 32f17997c130 ("ARM: pxa: remove irq init from dt machines")

2800 arch\arm\mach-pxa\pxa_cplds_irqs.c#0123 Repo: 3738ca1b2a7b Robert Mon Sep 26 09:21:28 2016 +0200 Description: ARM: pxa: pxa_cplds: honor probe deferral ------The method to acquire the input interrupt was working in a platform data based board, but was failing in a device-tree one when the gpio controller was probed after pxa_cplds.

Use platform_get_irq() to benefit from the probe deferral mechanism. Moreover, as seen in dm9000.c development, platform_get_irq() doesn't honor the irq type IO resource (ie. edge rising for example), and it must be passed again at irq request in a not device-tree build, hence the irq_get_trigger_type() call.

2801 arch\arm\mach-pxa\pxa_cplds_irqs.c#0145 2802 arch\arm\mach-pxa\spitz.c#0034 Repo: f2131c543649 Wei Yongjun Sat Oct 29 13:56:30 2016 +0200 Description: ARM: pxa: remove duplicated include from spitz.c ------This partially reverts commit 12beb346710b ("Merge tag 'pxa-fixes-v4.8' of https://github.com/rjarzmik/linux into randconfig-4.8").

This former patch introduced accidentally a double include of module.h.

2803 arch\arm\mach-pxa\stargate2.c#0676 Repo: 9a9743421581 Robert Mon Oct 17 21:45:29 2016 +0200 Description: ARM: pxa: enhance smc91x platform data

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------Instead of having the smc91x driver relying on machine_is_*() calls, provide this data through platform data, ie. idp, mainstone and stargate.

This way, the driver doesn't need anymore machine_is_*() calls, which wouldn't work anymore with a device-tree build.

arch\arm\mach-pxa\include\mach\ 2804 arch\arm\mach-pxa\include\mach\hardware.h#0306 Repo: d3570e3c5002 Robert Mon Sep 19 21:12:15 2016 +0200 Description: ARM: sa11x0/pxa: get rid of get_clock_tick_rate ------The last user of this function is gone, so remove it. The clock API should now be used to get clock rates.

ARM: pxa: Move iotable mapping inside vmalloc region ------In order to remove the following ugly message:

BUG: mapping for 0x00000000 at 0xff000000 out of vmalloc space

the iotable mappings should be re-located inside the vmalloc region. Such move was introduced at commit:

commit 0536bdf33faff4d940ac094c77998cfac368cfff Author: Nicolas Pitre Date: Thu Aug 25 00:35:59 2011 -0400

ARM: move iotable mappings within the vmalloc region

arch\arm\mach-rpc\ 2805 arch\arm\mach-rpc\dma.c#0023 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

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Requested-by: Al Viro arch\arm\mach-s3c24xx\ 2806 arch\arm\mach-s3c24xx\common-smdk.c#0174 Repo: e9f66ae23c20 Sergio Prado Thu Oct 20 19:42:44 2016 -0200 Description: mtd: s3c2410: make ecc mode configurable via platform data ------Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode field in the drivers's platform data structure so it can be selectable via platform data.

Also setting this field to NAND_ECC_SOFT in all boards using this driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.

2807 arch\arm\mach-s3c24xx\common.c#0348 Repo: 9d56d6cb4e93 Sylwester Fri Nov 4 10:45:53 2016 +0100 Description: ARM: S3C24XX: Add DMA slave maps for remaining s3c24xx SoCs ------This patch adds DMA slave map tables for the remaining s3c24xx SoC types so the whole platform can be switched to the new API. A few devices for which there was no DMA support with current code are omitted from the tables.

2808 arch\arm\mach-s3c24xx\common.c#0380 2809 arch\arm\mach-s3c24xx\common.c#0421 2810 arch\arm\mach-s3c24xx\common.c#0449 2811 arch\arm\mach-s3c24xx\common.c#0593 2812 arch\arm\mach-s3c24xx\common.c#0615 2813 arch\arm\mach-s3c24xx\mach-anubis.c#0226 Repo: e9f66ae23c20 Sergio Prado Thu Oct 20 19:42:44 2016 -0200 Description: mtd: s3c2410: make ecc mode configurable via platform data ------Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode field in the drivers's platform data structure so it can be selectable via platform data.

Also setting this field to NAND_ECC_SOFT in all boards using this driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.

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2814 arch\arm\mach-s3c24xx\mach-at2440evb.c#0117 Repo: e9f66ae23c20 Sergio Prado Thu Oct 20 19:42:44 2016 -0200 Description: mtd: s3c2410: make ecc mode configurable via platform data ------Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode field in the drivers's platform data structure so it can be selectable via platform data.

Also setting this field to NAND_ECC_SOFT in all boards using this driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.

2815 arch\arm\mach-s3c24xx\mach-bast.c#0302 Repo: e9f66ae23c20 Sergio Prado Thu Oct 20 19:42:44 2016 -0200 Description: mtd: s3c2410: make ecc mode configurable via platform data ------Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode field in the drivers's platform data structure so it can be selectable via platform data.

Also setting this field to NAND_ECC_SOFT in all boards using this driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.

2816 arch\arm\mach-s3c24xx\mach-gta02.c#0446 Repo: e9f66ae23c20 Sergio Prado Thu Oct 20 19:42:44 2016 -0200 Description: mtd: s3c2410: make ecc mode configurable via platform data ------Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode field in the drivers's platform data structure so it can be selectable via platform data.

Also setting this field to NAND_ECC_SOFT in all boards using this driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.

2817 arch\arm\mach-s3c24xx\mach-jive.c#0235 Repo: e9f66ae23c20 Sergio Prado Thu Oct 20 19:42:44 2016 -0200 Description: mtd: s3c2410: make ecc mode configurable via platform data ------Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode field in the drivers's platform data structure so it can be selectable via platform data.

Also setting this field to NAND_ECC_SOFT in all boards using this

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driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.

2818 arch\arm\mach-s3c24xx\mach-mini2440.c#0290 Repo: e9f66ae23c20 Sergio Prado Thu Oct 20 19:42:44 2016 -0200 Description: mtd: s3c2410: make ecc mode configurable via platform data ------Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode field in the drivers's platform data structure so it can be selectable via platform data.

Also setting this field to NAND_ECC_SOFT in all boards using this driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.

2819 arch\arm\mach-s3c24xx\mach-osiris.c#0241 Repo: e9f66ae23c20 Sergio Prado Thu Oct 20 19:42:44 2016 -0200 Description: mtd: s3c2410: make ecc mode configurable via platform data ------Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode field in the drivers's platform data structure so it can be selectable via platform data.

Also setting this field to NAND_ECC_SOFT in all boards using this driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.

2820 arch\arm\mach-s3c24xx\mach-qt2410.c#0287 Repo: e9f66ae23c20 Sergio Prado Thu Oct 20 19:42:44 2016 -0200 Description: mtd: s3c2410: make ecc mode configurable via platform data ------Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode field in the drivers's platform data structure so it can be selectable via platform data.

Also setting this field to NAND_ECC_SOFT in all boards using this driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.

2821 arch\arm\mach-s3c24xx\mach-rx1950.c#0614 Repo: e9f66ae23c20 Sergio Prado Thu Oct 20 19:42:44 2016 -0200 Description: mtd: s3c2410: make ecc mode configurable via platform data ------Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode field in the drivers's platform data structure so it can be selectable

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via platform data.

Also setting this field to NAND_ECC_SOFT in all boards using this driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.

2822 arch\arm\mach-s3c24xx\mach-rx3715.c#0167 Repo: e9f66ae23c20 Sergio Prado Thu Oct 20 19:42:44 2016 -0200 Description: mtd: s3c2410: make ecc mode configurable via platform data ------Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode field in the drivers's platform data structure so it can be selectable via platform data.

Also setting this field to NAND_ECC_SOFT in all boards using this driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.

2823 arch\arm\mach-s3c24xx\mach-vstms.c#0120 Repo: e9f66ae23c20 Sergio Prado Thu Oct 20 19:42:44 2016 -0200 Description: mtd: s3c2410: make ecc mode configurable via platform data ------Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode field in the drivers's platform data structure so it can be selectable via platform data.

Also setting this field to NAND_ECC_SOFT in all boards using this driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.

arch\arm\mach-s3c64xx\ 2824 arch\arm\mach-s3c64xx\mach-hmt.c#0207 Repo: e9f66ae23c20 Sergio Prado Thu Oct 20 19:42:44 2016 -0200 Description: mtd: s3c2410: make ecc mode configurable via platform data ------Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode field in the drivers's platform data structure so it can be selectable via platform data.

Also setting this field to NAND_ECC_SOFT in all boards using this driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.

ARM: s3c64xx: enable sparse IRQ support ------This is another prerequisite for enabling multiplatform

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support, and it is the part I am least certain about.

I assume it will cause the extra boot message "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated" to be printed, but otherwise work ok. This definitely needs to be tested on real hardware to see if it works.

2825 arch\arm\mach-s3c64xx\mach-mini6410.c#0145 Repo: e9f66ae23c20 Sergio Prado Thu Oct 20 19:42:44 2016 -0200 Description: mtd: s3c2410: make ecc mode configurable via platform data ------Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode field in the drivers's platform data structure so it can be selectable via platform data.

Also setting this field to NAND_ECC_SOFT in all boards using this driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.

ARM: s3c64xx: use new adc/touchscreen driver ------The old ADC and touchscreen drivers are not compatible with multiplatform support, but we can use the exynos-adc driver as a replacement.

This changes the common device creation functions for s3c64xx (but not s3c24xx for now) to use the new driver. To do this, we have to pass the interrupt resources in the opposite order and pass the platform data in the adc device node.

2826 arch\arm\mach-s3c64xx\mach-real6410.c#0197 Repo: e9f66ae23c20 Sergio Prado Thu Oct 20 19:42:44 2016 -0200 Description: mtd: s3c2410: make ecc mode configurable via platform data ------Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode field in the drivers's platform data structure so it can be selectable via platform data.

Also setting this field to NAND_ECC_SOFT in all boards using this driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.

ARM: s3c64xx: use new adc/touchscreen driver ------The old ADC and touchscreen drivers are not compatible with

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multiplatform support, but we can use the exynos-adc driver as a replacement.

This changes the common device creation functions for s3c64xx (but not s3c24xx for now) to use the new driver. To do this, we have to pass the interrupt resources in the opposite order and pass the platform data in the adc device node.

2827 arch\arm\mach-s3c64xx\pl080.c#0120 Repo: 5d13982a246c Sylwester Thu Nov 10 16:17:50 2016 +0100 Description: ARM: s3c64xx: Add DMA slave maps for PL080 devices ------This patch adds DMA slave map tables to the pl080 devices's platform_data in order to support the new channel request API. A few devices for which there was no DMA support with current code are omitted in the tables.

2828 arch\arm\mach-s3c64xx\pl080.c#0156 2829 arch\arm\mach-s3c64xx\pl080.c#0231 2830 arch\arm\mach-s3c64xx\pl080.c#0257 arch\arm\mach-sa1100\ 2831 arch\arm\mach-sa1100\generic.c#0381 Repo: f4e14edf2566 Robert Mon Sep 19 21:12:13 2016 +0200 Description: ARM: sa11x0/pxa: acquire timer rate from the clock rate ------As both pxa and sa1100 provide a clock to the timer, the rate can be inferred from the clock rather than hard encoded in a functional call.

This patch changes the pxa timer to have a mandatory clock which is used as the timer rate.

ARM: sa1100: clear reset status prior to reboot ------Clear the current reset status prior to rebooting the platform. This adds the bit missing from 04fef228fb00 ("[ARM] pxa: introduce reset_status and clear_reset_status for driver's usage").

Fixes: 04fef228fb00 ("[ARM] pxa: introduce reset_status and clear_reset_status for driver's usage")

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Line Link NR. Descriptions arch\arm\mach-sa1100\include\mach\ 2832 arch\arm\mach-sa1100\include\mach\hardware.h#0046 Repo: 66d466722c39 Linus Thu Dec 15 16:06:15 2016 -0800 Description: Merge branch 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm ------Pull ARM updates from Russell King:

- an update for clkdev registration error detection to simplify users

- add cpu capacity parsing from DT

- support for larger cachelines found on UniPhier caches

- documentation for udelay constants

- properly tag assembly function declarations

- remove unnecessary indirection of asm/mach-types.h

- switch to syscall table based generation to simplify future additions of system calls, along with correpsonding commit for pkey syscalls

- remove redundant sa1101 header file

- RONX protect modules when they're in the vmalloc region

* 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: ARM: mm: allow set_memory_*() to be used on the vmalloc region ARM: mm: fix set_memory_*() bounds checks ARM: 8631/1: clkdev: Detect errors in clk_hw_register_clkdev() for mass registration ARM: 8629/1: vfp: properly tag assembly function declarations in C code ARM: 8622/3: add sysfs cpu_capacity attribute ARM: 8621/3: parse cpu capacity-dmips-mhz from DT ARM: 8623/1: mm: add ARM_L1_CACHE_SHIFT_7 for UniPhier outer cache ARM: Update mach-types ARM: sa1100: remove SA-1101 header file ARM: 8619/1: udelay: document the various constants ARM: wire up new pkey syscalls ARM: convert to generated system call tables ARM: remove indirection of asm/mach-types.h

ARM: sa1100: remove SA-1101 header file ------Remove the completely unused SA-1101 header file.

ARM: sa11x0/pxa: get rid of get_clock_tick_rate

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------The last user of this function is gone, so remove it. The clock API should now be used to get clock rates.

ARM: document and update UNCACHEABLE_ADDR definitions ------Document the UNCACHEABLE_ADDR definitions for footbridge and SA1100 so that we know where they're located and/or what they're accessing. Change RiscPC to calculate the UNCACHEABLE_ADDR value from FLUSH_BASE as that's where we locate that.

UNCACHEABLE_ADDR is used to perform an uncached access (ARMv4 terminology) necessary to force a CPU clock-switch to the memory- speed clock, as required for entering WFI.

2833 arch\arm\mach-sa1100\include\mach\hardware.h#0059 2834 arch\arm\mach-sa1100\include\mach\SA-1101.h#fileDeleted Repo: e642873dcce4 Russell King Wed Aug 31 08:49:55 2016 +0100 Description: ARM: sa1100: remove SA-1101 header file ------Remove the completely unused SA-1101 header file.

arch\arm\mach-shmobile\ 2835 arch\arm\mach-shmobile\Kconfig#0035 Repo: 991688bfc635 Linus Thu Dec 15 16:03:25 2016 -0800 Description: Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM SoC driver updates from Arnd Bergmann: "Driver updates for ARM SoCs, including a couple of newly added drivers:

- A new driver for the power management controller on TI Keystone

- Support for the prerelease "SCPI" firmware protocol that ended up being shipped by Amlogic in their GXBB SoC.

- A soc_device can now be matched using a glob from inside the kernel, when another driver wants to know the specific chip it is running on and cannot find out from DT, firmware or hardware.

- Renesas SoCs now support identification through the soc_device interface, both in user space and kernel.

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- Renesas r8a7743 and r8a7745 gain support for their system controller

- A new checking module for the ARM "PSCI" (not to be confused with "SCPI" mentioned above) firmware interface.

- A new driver for the Tegra GMI memory interface

- Support for the Tegra firmware interfaces with their power management controllers

As usual, the updates for the reset controller framework are merged here, as they tend to touch multiple SoCs as well, including a new driver for the Oxford (now Broadcom) OX820 chip and the Tegra bpmp interface.

The existing drivers for Atmel, Qualcomm, NVIDIA, TI Davinci, and Rockchips SoCs see some further updates"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (76 commits) misc: sram: remove useless #ifdef drivers: psci: Allow PSCI node to be disabled drivers: psci: PSCI checker module soc: renesas: Identify SoC and register with the SoC bus firmware: qcom: scm: Return PTR_ERR when devm_clk_get fails firmware: qcom: scm: Remove core, iface and bus clocks dependency dt-bindings: firmware: scm: Add MSM8996 DT bindings memory: da8xx-ddrctl: drop the call to of_flat_dt_get_machine_name() bus: da8xx-mstpri: drop the call to of_flat_dt_get_machine_name() ARM: shmobile: Document DT bindings for Product Register soc: renesas: rcar-sysc: add R8A7745 support reset: Add Tegra BPMP reset driver dt-bindings: firmware: Allow child nodes inside the Tegra BPMP dt-bindings: Add power domains to Tegra BPMP firmware firmware: tegra: Add BPMP support firmware: tegra: Add IVC library dt-bindings: firmware: Add bindings for Tegra BPMP mailbox: tegra-hsp: Use after free in tegra_hsp_remove_doorbells() mailbox: Add Tegra HSP driver firmware: arm_scpi: add support for pre-v1.0 SCPI compatible ...

soc: renesas: Identify SoC and register with the SoC bus ------Identify the SoC type and revision, and register this information with the SoC bus, so it is available under /sys/devices/soc0/, and can be checked where needed using soc_device_match().

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Identification is done using the Product Register or Common Chip Code Register, as declared in DT (PRR only for now), or using a hardcoded fallback if missing.

Example:

Detected Renesas R-Car Gen2 r8a7791 ES1.0 ... # cat /sys/devices/soc0/{machine,family,soc_id,revision} Koelsch R-Car Gen2 r8a7791 ES1.0

ARM: shmobile: r8a7745: basic SoC support ------Add minimal support for the RZ/G1E (R8A7745) SoC.

ARM: shmobile: select errata 798181 for SoCs with CA15 cores ------Select ARM errata 798181 on SoCs cores affected CA15 cores.

ARM: shmobile: r8a7743: basic SoC support ------Add minimal support for the RZ/G1M (R8A7743) SoC.

Based on the original (and large) patch by Dmitry Shifrin .

ARM: shmobile: Sort Kconfig selections ------Sort alphabetically all symbols selected by ARCH_RENESAS

2836 arch\arm\mach-shmobile\Kconfig#0038 2837 arch\arm\mach-shmobile\Kconfig#0042 2838 arch\arm\mach-shmobile\Kconfig#0044 2839 arch\arm\mach-shmobile\Kconfig#0064 2840 arch\arm\mach-shmobile\Kconfig#0072

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2841 arch\arm\mach-shmobile\Kconfig#0092 2842 arch\arm\mach-shmobile\Kconfig#0098 2843 arch\arm\mach-shmobile\Kconfig#0104 2844 arch\arm\mach-shmobile\Kconfig#0109 2845 arch\arm\mach-shmobile\Makefile#0016 Repo: a0c4e2ccb315 Laurent Mon Oct 17 16:59:04 2016 +0300 Description: ARM: shmobile: Consolidate R8A7743 and R8A779[234] machine definitions ------The four SoCs use identical machine operations, consolidate them into two machine definitions in a single file.

ARM: shmobile: r8a7743: basic SoC support ------Add minimal support for the RZ/G1M (R8A7743) SoC.

Based on the original (and large) patch by Dmitry Shifrin .

2846 arch\arm\mach-shmobile\setup-r8a7778.c#0018 Repo: f3519926babe Geert Wed Jun 1 15:16:57 2016 +0200 Description: ARM: shmobile: r8a7778: Stop passing mode pins state to clock driver ------Now the R-Car M1A CPG clock driver obtains the state of the mode pins from the R-Car RST driver, there's no longer a need to pass this state explicitly. Hence we can just remove the .init_time() callback, the generic ARM code will take care of calling of_clk_init().

2847 arch\arm\mach-shmobile\setup-r8a7778.c#0026 2848 arch\arm\mach-shmobile\setup-r8a7778.c#0073 2849 arch\arm\mach-shmobile\setup-r8a7779.c#0017 Repo: eae339264fd4 Geert Wed Jun 1 15:21:14 2016 +0200 Description: ARM: shmobile: r8a7779: Stop passing mode pins state to clock driver ------Now the R-Car H1 CPG clock driver obtains the state of the mode pins from the R-Car RST driver, there's no longer a need to pass this state explicitly. Hence we can just remove the .init_time() callback, the generic ARM code will take care of calling of_clk_init() and clocksource_probe().

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2850 arch\arm\mach-shmobile\setup-r8a7779.c#0079 2851 arch\arm\mach-shmobile\setup-r8a7779.c#0112 2852 arch\arm\mach-shmobile\setup-r8a7792.c#fileDeleted Repo: a0c4e2ccb315 Laurent Mon Oct 17 16:59:04 2016 +0300 Description: ARM: shmobile: Consolidate R8A7743 and R8A779[234] machine definitions ------The four SoCs use identical machine operations, consolidate them into two machine definitions in a single file.

2853 arch\arm\mach-shmobile\setup-r8a7793.c#fileDeleted Repo: a0c4e2ccb315 Laurent Mon Oct 17 16:59:04 2016 +0300 Description: ARM: shmobile: Consolidate R8A7743 and R8A779[234] machine definitions ------The four SoCs use identical machine operations, consolidate them into two machine definitions in a single file.

2854 arch\arm\mach-shmobile\setup-r8a7794.c#fileDeleted Repo: a0c4e2ccb315 Laurent Mon Oct 17 16:59:04 2016 +0300 Description: ARM: shmobile: Consolidate R8A7743 and R8A779[234] machine definitions ------The four SoCs use identical machine operations, consolidate them into two machine definitions in a single file.

2855 arch\arm\mach-shmobile\setup-rcar-gen2.c#0018 Repo: e79ab194d15e Linus Thu Dec 15 15:39:02 2016 -0800 Description: Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM SoC platform updates from Arnd Bergmann: "These are updates for platform specific code on 32-bit ARM machines, essentially anything that can not (yet) be expressed using DT files.

Noteworthy changes include:

- Added support for the TI DRA71x family of SoCs in mach-omap2, this is an new variant of the the DRA72x/DRA74x automotive infotainment chips we already supported for a while.

- Added support for the ST STM32F746 SoC, the first Cortex-M7 based microcontroller we support, related to the smaller STM32F4 family.

- Renesas adds support for r8a7743 and r8a7745 in mach-shmobile, see

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http://elinux.org/RZ-G

- SMP is now supported on the OX820 platform

- A lot of code in mach-omap2 gets removed as a follow-up to removing support for board files in the previous release

- Davinci has some new work to improve USB support

- For i.MX, the performance monitor now supports profiling the memory controller using 'perf'"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (95 commits) ARM: davinci: da830-evm: use gpio descriptor for mmc pins ARM: davinci: da850-evm: use gpio descriptor for mmc pins ARM: davinci: hawk: use gpio descriptor for mmc pins ARM: ARTPEC-6: add select MFD_SYSCON to MACH_ARTPEC6 ARM: davinci: da8xx: Fix ohci device name ARM: oxnas: Add OX820 config and makefile entry ARM: oxnas: Add OX820 SMP support ARM: davinci: PM: fix build when da850 not compiled in ARM: orion5x: remove legacy support of ls-chl ARM: integrator: drop EBI access use syscon ARM: BCM5301X: Add back handler ignoring external imprecise aborts ARM: davinci: PM: support da8xx DT platforms ARM: davinci: PM: cleanup: remove references to pdata ARM: davinci: PM: rework init, remove platform device ARM: Kconfig: Introduce MACH_STM32F746 flag ARM: mach-stm32: Add a new SOC - STM32F746 ARM: shmobile: document SK-RZG1E board ARM: shmobile: r8a7745: basic SoC support ARM: imx: mach-imx6ul: add imx6ull support ARM: zynq: Reserve correct amount of non-DMA RAM ...

ARM: shmobile: r8a7745: basic SoC support ------Add minimal support for the RZ/G1E (R8A7745) SoC.

ARM: shmobile: rcar-gen2: Stop passing mode pins state to clock driver ------Now the R-Car Gen2 CPG clock driver obtains the state of the mode pins from the R-Car RST driver, there's no longer a need to pass this state explicitly. Hence we can just call of_clk_init() instead.

ARM: shmobile: Consolidate R8A7743 and R8A779[234] machine definitions

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------The four SoCs use identical machine operations, consolidate them into two machine definitions in a single file.

ARM: shmobile: only call rcar_gen2_clocks_init() if present ------The RZ/G1M (r8a7743) uses the R-Car Gen2 core, but not the R-Car Gen2 clock driver. This is a harbinger of a transition for R-Car Gen2 SoCs. As the process to get all the required pieces in place is somewhat complex it seems useful to try to disentangle dependencies where possible.

The approach here is to temporarily disable calling rcar_gen2_clocks_init() if no R-Car Gen2 SoC are configured and thus the symbol will not be present.

ARM: shmobile: rcar-gen2: Correct arch timer frequency on R-Car V2H ------According to the datasheet, the frequency of the ARM architecture timer on R-Car V2H depends on the frequency of the ZS clock, just like on R-Car E2.

2856 arch\arm\mach-shmobile\setup-rcar-gen2.c#0027 2857 arch\arm\mach-shmobile\setup-rcar-gen2.c#0075 2858 arch\arm\mach-shmobile\setup-rcar-gen2.c#0133 2859 arch\arm\mach-shmobile\setup-rcar-gen2.c#0206 arch\arm\mach-socfpga\ 2860 arch\arm\mach-socfpga\l2_cache.c#0077 Repo: ed72af3a8ccf Colin King Tue Nov 15 08:52:17 2016 -0600 Description: ARM: socfpga: fix spelling mistake in error message ------Trivial fix to spelling mistake "Mananger" to "Manager" in error message

arch\arm\mach-spear\ 2861 arch\arm\mach-spear\time.c#0236 Repo: ce3409615244 Christophe Sat Oct 29 15:58:39 2016 +0200 Description: ARM: spear: Fix error handling ------'clk_get_sys()' returns an error pointer in case of error, not NULL. So test it with IS_ERR.

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Line Link NR. Descriptions arch\arm\mach-sti\ 2862 arch\arm\mach-sti\Kconfig#0031 Repo: 64933513e461 Peter Griffin Wed Sep 14 14:27:53 2016 +0100 Description: reset: sti: Remove STiH415/6 reset support ------Support for STiH415/6 SoCs is being removed from the kernel because the platforms are obsolete. This patch removes the reset drivers for these SoC's.

2863 arch\arm\mach-sti\Kconfig#0041 arch\arm\mach-stm32\ 2864 arch\arm\mach-stm32\board-dt.c#0014 Repo: a77e393c321f Alexandre Tue Nov 15 12:02:33 2016 +0100 Description: ARM: mach-stm32: Add a new SOC - STM32F746 ------arch\arm\mach-ux500\ 2865 arch\arm\mach-ux500\pm.c#0137 Repo: f0e8faa7a5e8 Arnd Wed Nov 16 16:20:37 2016 +0100 Description: ARM: ux500: fix prcmu_is_cpu_in_wfi() calculation ------This function clearly never worked and always returns true, as pointed out by gcc-7:

arch/arm/mach-ux500/pm.c: In function 'prcmu_is_cpu_in_wfi': arch/arm/mach-ux500/pm.c:137:212: error: ?: using integer constants in boolean context, the expression will always evaluate to 'true' [-Werror=int-in-bool-context]

With the added braces, the condition actually makes sense.

Fixes: 34fe6f107eab ("mfd : Check if the other db8500 core is in WFI") arch\arm\mach-vexpress\ 2866 arch\arm\mach-vexpress\platsmp.c#0029 Repo: 525d4015e633 Lorenzo Fri Sep 23 14:09:06 2016 +0100 Description: ARM: vexpress: refine MCPM smp operations override criteria ------Current vexpress smp init code detects whether to override the default smp ops with MCPM smp ops by matching the "cci-400" compatible string, in that MCPM requires control over CCI ports

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to manage low-power states entry/exit.

The "cci-400" compatible string check is a necessary but not sufficient condition for MCPM to work, because the cci-400 can be made visible to the kernel, but firmware can nonetheless disable non-secure CCI ports control, while still allowing PMU access; if booted in non-secure world, the kernel would still blindly override smp operations with MCPM operations, resulting in kernel faults when the CCI ports programming interface is accessed from non-secure world.

This means that the "cci-400" compatible string check would result in a false positive in systems that eg boot in HYP mode, where CCI ports non-secure access is explicitly not allowed, and it is reported in the respective device tree nodes with CCI ports marked as disabled.

Refactor the smp operations initialization to make sure that the kernel is actually allowed to take control over CCI ports (by enabling MCPM smp operations) before overriding default vexpress smp operations.

2867 arch\arm\mach-vexpress\platsmp.c#0033 Review: COMMENT stecan Thu, 11 Jan 2018 07:26:51 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:51 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:26:51 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:51 +0100 Automatic commented! 2868 arch\arm\mach-vexpress\platsmp.c#0039 2869 arch\arm\mach-vexpress\platsmp.c#0054 2870 arch\arm\mach-vexpress\platsmp.c#0059 arch\arm\mach-zx\ 2871 arch\arm\mach-zx\zx296702-pm-domain.c#0172 Repo: 9cfc93b2f881 Christophe Sun Oct 30 09:10:10 2016 +0100 Description: ARM: zx: Fix error handling ------'devm_ioremap_resource()' returns an error pointer in case of error, not NULL. So test it with IS_ERR.

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Line Link NR. Descriptions arch\arm\mach-zynq\ 2872 arch\arm\mach-zynq\common.c#0062 Repo: 7a3cc2a7b2c7 Kyle Mon Oct 31 11:26:17 2016 -0500 Description: ARM: zynq: Reserve correct amount of non-DMA RAM ------On Zynq, we haven't been reserving the correct amount of DMA-incapable RAM to keep DMA away from it (per the Zynq TRM Section 4.1, it should be the first 512k). In older kernels, this was masked by the memblock_reserve call in arm_memblock_init(). Now, reserve the correct amount excplicitly rather than relying on swapper_pg_dir, which is an address and not a size anyway.

Fixes: 46f5b96 ("ARM: zynq: Reserve not DMAable space in front of the kernel")

arch\arm\mm\ 2873 arch\arm\mm\cache-l2x0-pmu.c#0566 Repo: 73c1b41e63f0 Thomas Wed Dec 21 20:19:54 2016 +0100 Description: cpu/hotplug: Cleanup state names ------When the state names got added a script was used to add the extra argument to the calls. The script basically converted the state constant to a string, but the cleanup to convert these strings into meaningful ones did not happen.

Replace all the useless strings with 'subsys/xxx/yyy:state' strings which are used in all the other places already.

2874 arch\arm\mm\cache-l2x0.c#0686 Repo: 73c1b41e63f0 Thomas Wed Dec 21 20:19:54 2016 +0100 Description: cpu/hotplug: Cleanup state names ------When the state names got added a script was used to add the extra argument to the calls. The script basically converted the state constant to a string, but the cleanup to convert these strings into meaningful ones did not happen.

Replace all the useless strings with 'subsys/xxx/yyy:state' strings which are used in all the other places already.

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2875 arch\arm\mm\fault.c#0613 Repo: 97a98ae5b8ac Alexander Tue Jan 17 21:10:11 2017 +0100 Description: ARM: 8642/1: LPAE: catch pending imprecise abort on unmask ------Asynchronous external abort is coded differently in DFSR with LPAE enabled.

Fixes: 9254970c "ARM: 8447/1: catch pending imprecise abort on unmask".

2876 arch\arm\mm\fault.c#0615 2877 arch\arm\mm\fault.h#0014 Repo: 97a98ae5b8ac Alexander Tue Jan 17 21:10:11 2017 +0100 Description: ARM: 8642/1: LPAE: catch pending imprecise abort on unmask ------Asynchronous external abort is coded differently in DFSR with LPAE enabled.

Fixes: 9254970c "ARM: 8447/1: catch pending imprecise abort on unmask".

2878 arch\arm\mm\fault.h#0021 2879 arch\arm\mm\Kconfig#0994 Repo: 01bf92788ee7 Masahiro Mon Oct 31 14:37:13 2016 +0100 Description: ARM: 8623/1: mm: add ARM_L1_CACHE_SHIFT_7 for UniPhier outer cache ------The UniPhier outer cache (arch/arm/mm/cache-uniphier.c) has 128 byte line length and its tags are also managed per 128 byte line. This is very unfortunate, but the current 64 byte alignment for kmalloc() causes sharing problems on DMA if used with this outer cache.

This commit adds ARM_L1_CACHE_SHIFT_7 to increase the DMA minimum alignment to 128 byte if CACHE_UNIPHIER is enabled. There are several drivers that assume aligning to L1_CACHE_BYTES will be DMA safe, so this commit also changes the L1_CACHE_BYTES for safety.

Having said that, I hesitate to align all the other SoCs in Multi platform to the UniPhier's requirement. So, I am disabling the CONFIG_CACHE_UNIPHIER by default, so that multi_v7_defconfig will still stay with CONFIG_ARM_L1_CACHE_SHIFT=6. With this commit, UniPhier SoCs will become slower, but it is much better than system crash. If desired, the outer-cache can be enabled by merge_config or something.

Note: The UniPhier PH1-Pro5 SoC is equipped also with L3 cache with 256 byte line size but its tags are managed per 128 byte sub-line. So, ARM_L1_CACHE_SHIFT_7 should be fine for all the UniPhier SoCs.

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ARM: 8611/1: l2x0: add PMU support ------The L2C-220 (AKA L220) and L2C-310 (AKA PL310) cache controllers feature a Performance Monitoring Unit (PMU), which can be useful for tuning and/or debugging. This hardware is always present and the relevant registers are accessible to non-secure accesses. Thus, no special firmware interface is necessary.

This patch adds support for the PMU, plugging into the usual perf infrastructure. The overflow interrupt is not always available (e.g. on RealView PBX A9 it is not wired up at all), and the hardware counters saturate, so the driver does not make use of this. Instead, the driver periodically polls and reset counters as required to avoid losing events due to saturation.

2880 arch\arm\mm\Kconfig#1015 2881 arch\arm\mm\Kconfig#1022 2882 arch\arm\mm\pageattr.c#0037 Repo: 76fb051d4294 Russell King Mon Nov 21 16:07:05 2016 +0000 Description: ARM: mm: allow set_memory_*() to be used on the vmalloc region ------We can allow modules to be loaded into the vmalloc region, where they should also benefit from the same protections as those loaded into the more efficient module region. Allow these functions to operate there as well.

ARM: mm: fix set_memory_*() bounds checks ------The set_memory_*() bounds checks are buggy on several fronts:

1. They fail to round the region size up if the passed address is not page aligned. 2. The region check was incomplete, and didn't correspond with what was being asked of apply_to_page_range()

So, rework change_memory_common() to fix these problems, adding an "in_region()" helper to determine whether the start & size fit within the provided region start and stop addresses.

2883 arch\arm\mm\pageattr.c#0047

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2884 arch\arm\mm\pageattr.c#0053 2885 arch\arm\mm\pageattr.c#0055 2886 arch\arm\mm\pageattr.c#0058 2887 arch\arm\mm\pageattr.c#0062 arch\arm\plat-iop\ 2888 arch\arm\plat-iop\time.c#0028 Repo: a5a1d1c2914b Thomas Wed Dec 21 20:32:01 2016 +0100 Description: clocksource: Use a plain u64 instead of cycle_t ------There is no point in having an extra type for extra confusion. u64 is unambiguous.

Conversion was done with the following coccinelle script:

@rem@ @@ -typedef u64 cycle_t;

@fix@ typedef cycle_t; @@ -cycle_t +u64

Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

2889 arch\arm\plat-iop\time.c#0041 arch\arm\plat-omap\ 2890 arch\arm\plat-omap\i2c.c#fileDeleted Repo: 65fa3e719f36 Tony Mon Oct 17 00:06:54 2016 -0700 Description: ARM: OMAP2+: Remove legacy i2c.c platform init code ------

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We can now initialize I2C for mach-omap2 using device tree. And we can move the remaining code in plat-omap/i2c.c into mach-omap1/i2c.c.

Note that we cannot remove some of the I2C bus reset functions as they are being used by hwmod code.

2891 arch\arm\plat-omap\Kconfig#0066 Repo: e9f5f1e45608 Tony Thu Oct 20 06:42:19 2016 -0700 Description: ARM: OMAP2+: Remove legacy mux code ------All the boards booting with device tree use drivers/pinctrl-single.c instead.

Note that mach-omap1 is still using the legacy mux, so let's move the related Kconfig options from plat-omap to mach-omap1.

2892 arch\arm\plat-omap\Makefile#0014 Repo: 65fa3e719f36 Tony Mon Oct 17 00:06:54 2016 -0700 Description: ARM: OMAP2+: Remove legacy i2c.c platform init code ------We can now initialize I2C for mach-omap2 using device tree. And we can move the remaining code in plat-omap/i2c.c into mach-omap1/i2c.c.

Note that we cannot remove some of the I2C bus reset functions as they are being used by hwmod code.

arch\arm\plat-orion\ 2893 arch\arm\plat-orion\gpio.c#0481 Repo: d6ea689345ec Markus Sun Oct 16 12:30:48 2016 +0200 Description: ARM/orion/gpio: Replace three seq_printf() calls by seq_puts() in orion_gpio_dbg_show() ------Strings which did not contain data format specifications should be put into a sequence. Thus use the corresponding function "seq_puts".

This issue was detected by using the Coccinelle software.

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2894 arch\arm\plat-orion\gpio.c#0485 2895 arch\arm\plat-orion\gpio.c#0487 arch\arm\plat-samsung\ 2896 arch\arm\plat-samsung\devs.c#1127 Repo: c41668ad5de9 Sylwester Thu Nov 10 16:17:52 2016 +0100 Description: ARM: s3c64xx: Drop unused DMA fields from struct s3c64xx_spi_csinfo ------There is no drivers using those fields so remove them and the remaining initializations.

2897 arch\arm\plat-samsung\devs.c#1172 2898 arch\arm\plat-samsung\devs.c#1180 2899 arch\arm\plat-samsung\devs.c#1216 arch\arm\plat-samsung\include\plat\ 2900 arch\arm\plat-samsung\include\plat\gpio-cfg.h#0029 Repo: 9efeccacd3a4 Michael S. Sun Dec 11 06:34:53 2016 +0200 Description: linux: drop __bitwise__ everywhere ------__bitwise__ used to mean "yes, please enable sparse checks unconditionally", but now that we dropped __CHECK_ENDIAN__ __bitwise is exactly the same. There aren't many users, replace it by __bitwise everywhere.

arch\arm\tools\ 2901 arch\arm\tools\mach-types#0019 Repo: ffa5d3eec7b1 Russell King Sun Oct 30 20:21:01 2016 +0000 Description: ARM: Update mach-types ------It's been a while since the mach-types file was updated, as we have moved away to DT for platform stuff. Updating it has the advantage of retiring lots of entries which have not been made use of, resulting in rougly halving the size of the file.

2902 arch\arm\tools\mach-types#0155

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2903 arch\arm\tools\mach-types#0396 2904 arch\arm\tools\mach-types#0415 2905 arch\arm\tools\mach-types#0438 2906 arch\arm\tools\mach-types#0440 2907 arch\arm\tools\mach-types#0475 2908 arch\arm\tools\mach-types#0493 2909 arch\arm\tools\mach-types#0526 2910 arch\arm\tools\mach-types#0529 2911 arch\arm\tools\mach-types#0543 2912 arch\arm\tools\mach-types#0545 2913 arch\arm\tools\mach-types#0550 2914 arch\arm\tools\mach-types#0555 2915 arch\arm\tools\mach-types#0560 2916 arch\arm\tools\mach-types#0799 2917 arch\arm\tools\mach-types#0840 2918 arch\arm\tools\Makefile#0007 Repo: 96a8fae0fe09 Russell King Tue Oct 18 19:57:01 2016 +0100 Description: ARM: convert to generated system call tables ------Convert ARM to use a similar mechanism to x86 to generate the unistd.h system call numbers and the various kernel system call tables. This means that rather than having to edit three places (asm/unistd.h for the total number of system calls, uapi/asm/unistd.h for the system call numbers, and arch/arm/kernel/calls.S for the call table) we have only one place to edit, making the process much more simple.

The scripts have knowledge of the table padding requirements, so there's no need to worry about __NR_syscalls not fitting within the immediate constant field of ALU instructions anymore.

ARM: remove indirection of asm/mach-types.h ------Arrange for mach-types.h to be directly generated in the relevant path, so we don't need a one-liner file in arch/arm/include/asm/.

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2919 arch\arm\tools\Makefile#0040 2920 arch\arm\tools\Makefile#0042 2921 arch\arm\tools\syscall.tbl#newFile Repo: 219622b7b3dc Russell King Tue Oct 18 20:26:10 2016 +0100 Description: ARM: wire up new pkey syscalls ------Wire up the new pkey syscalls for ARM. This illustrates the ease that the generated/tabular approach gives us: adding new system calls becomes much easier, and all the dependencies are automatically handled for the update.

2922 arch\arm\tools\syscallhdr.sh#newFile Repo: 96a8fae0fe09 Russell King Tue Oct 18 19:57:01 2016 +0100 Description: ARM: convert to generated system call tables ------Convert ARM to use a similar mechanism to x86 to generate the unistd.h system call numbers and the various kernel system call tables. This means that rather than having to edit three places (asm/unistd.h for the total number of system calls, uapi/asm/unistd.h for the system call numbers, and arch/arm/kernel/calls.S for the call table) we have only one place to edit, making the process much more simple.

The scripts have knowledge of the table padding requirements, so there's no need to worry about __NR_syscalls not fitting within the immediate constant field of ALU instructions anymore.

2923 arch\arm\tools\syscallnr.sh#newFile Repo: 96a8fae0fe09 Russell King Tue Oct 18 19:57:01 2016 +0100 Description: ARM: convert to generated system call tables ------Convert ARM to use a similar mechanism to x86 to generate the unistd.h system call numbers and the various kernel system call tables. This means that rather than having to edit three places (asm/unistd.h for the total number of system calls, uapi/asm/unistd.h for the system call numbers, and arch/arm/kernel/calls.S for the call table) we have only one place to edit, making the process much more simple.

The scripts have knowledge of the table padding requirements, so there's no need to worry about __NR_syscalls not fitting within the immediate constant field of ALU instructions anymore.

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2924 arch\arm\tools\syscalltbl.sh#newFile Repo: 96a8fae0fe09 Russell King Tue Oct 18 19:57:01 2016 +0100 Description: ARM: convert to generated system call tables ------Convert ARM to use a similar mechanism to x86 to generate the unistd.h system call numbers and the various kernel system call tables. This means that rather than having to edit three places (asm/unistd.h for the total number of system calls, uapi/asm/unistd.h for the system call numbers, and arch/arm/kernel/calls.S for the call table) we have only one place to edit, making the process much more simple.

The scripts have knowledge of the table padding requirements, so there's no need to worry about __NR_syscalls not fitting within the immediate constant field of ALU instructions anymore.

arch\arm\vfp\ 2925 arch\arm\vfp\vfp.h#0158 Repo: a85b2257a57d Nicolas Pitre Wed Nov 16 22:20:14 2016 +0100 Description: ARM: 8629/1: vfp: properly tag assembly function declarations in C code ------This is good for consistency even if there is no difference in compiled code. LTO might rely on this eventually. No need to preserve the extern attribute as it is the default with function prototypes.

2926 arch\arm\vfp\vfp.h#0273 2927 arch\arm\vfp\vfp.h#0380 2928 arch\arm\vfp\vfpmodule.c#0037 Repo: 73c1b41e63f0 Thomas Wed Dec 21 20:19:54 2016 +0100 Description: cpu/hotplug: Cleanup state names ------When the state names got added a script was used to add the extra argument to the calls. The script basically converted the state constant to a string, but the cleanup to convert these strings into meaningful ones did not happen.

Replace all the useless strings with 'subsys/xxx/yyy:state' strings which are used in all the other places already.

ARM: 8629/1: vfp: properly tag assembly function declarations in C code ------This is good for consistency even if there is no difference in compiled

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code. LTO might rely on this eventually. No need to preserve the extern attribute as it is the default with function prototypes.

2929 arch\arm\vfp\vfpmodule.c#0041 2930 arch\arm\vfp\vfpmodule.c#0802 arch\arm\xen\ 2931 arch\arm\xen\enlighten.c#0375 Repo: 73c1b41e63f0 Thomas Wed Dec 21 20:19:54 2016 +0100 Description: cpu/hotplug: Cleanup state names ------When the state names got added a script was used to add the extra argument to the calls. The script basically converted the state constant to a string, but the cleanup to convert these strings into meaningful ones did not happen.

Replace all the useless strings with 'subsys/xxx/yyy:state' strings which are used in all the other places already.

arm/xen: Use alloc_percpu rather than __alloc_percpu ------The function xen_guest_init is using __alloc_percpu with an alignment which are not power of two.

However, the percpu allocator never supported alignments which are not power of two and has always behaved incorectly in thise case.

Commit 3ca45a4 "percpu: ensure requested alignment is power of two" introduced a check which trigger a warning [1] when booting linux-next on Xen. But in reality this bug was always present.

This can be fixed by replacing the call to __alloc_percpu with alloc_percpu. The latter will use an alignment which are a power of two.

[1]

[ 0.023921] illegal size (48) or align (48) for percpu allocation [ 0.024167] ------[ cut here ]------[ 0.024344] WARNING: CPU: 0 PID: 1 at linux/mm/percpu.c:892 pcpu_alloc+0x88/0x6c0 [ 0.024584] Modules linked in: [ 0.024708] [ 0.024804] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.9.0-rc7-next-20161128 #473 [ 0.025012] Hardware name: Foundation-v8A (DT) [ 0.025162] task: ffff80003d870000 task.stack: ffff80003d844000

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[ 0.025351] PC is at pcpu_alloc+0x88/0x6c0 [ 0.025490] LR is at pcpu_alloc+0x88/0x6c0 [ 0.025624] pc : [] lr : [] pstate: 60000045 [ 0.025830] sp : ffff80003d847cd0 [ 0.025946] x29: ffff80003d847cd0 x28: 0000000000000000 [ 0.026147] x27: 0000000000000000 x26: 0000000000000000 [ 0.026348] x25: 0000000000000000 x24: 0000000000000000 [ 0.026549] x23: 0000000000000000 x22: 00000000024000c0 [ 0.026752] x21: ffff000008e97000 x20: 0000000000000000 [ 0.026953] x19: 0000000000000030 x18: 0000000000000010 [ 0.027155] x17: 0000000000000a3f x16: 00000000deadbeef [ 0.027357] x15: 0000000000000006 x14: ffff000088f79c3f [ 0.027573] x13: ffff000008f79c4d x12: 0000000000000041 [ 0.027782] x11: 0000000000000006 x10: 0000000000000042 [ 0.027995] x9 : ffff80003d847a40 x8 : 6f697461636f6c6c [ 0.028208] x7 : 6120757063726570 x6 : ffff000008f79c84 [ 0.028419] x5 : 0000000000000005 x4 : 0000000000000000 [ 0.028628] x3 : 0000000000000000 x2 : 000000000000017f [ 0.028840] x1 : ffff80003d870000 x0 : 0000000000000035 [ 0.029056] [ 0.029152] ---[ end trace 0000000000000000 ]--- [ 0.029297] Call trace: [ 0.029403] Exception stack(0xffff80003d847b00 to 0xffff80003d847c30) [ 0.029621] 7b00: 0000000000000030 0001000000000000 ffff80003d847cd0 ffff00000818e678 [ 0.029901] 7b20: 0000000000000002 0000000000000004 ffff000008f7c060 0000000000000035 [ 0.030153] 7b40: ffff000008f79000 ffff000008c4cd88 ffff80003d847bf0 ffff000008101778 [ 0.030402] 7b60: 0000000000000030 0000000000000000 ffff000008e97000 00000000024000c0 [ 0.030647] 7b80: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 [ 0.030895] 7ba0: 0000000000000035 ffff80003d870000 000000000000017f 0000000000000000 [ 0.031144] 7bc0: 0000000000000000 0000000000000005 ffff000008f79c84 6120757063726570 [ 0.031394] 7be0: 6f697461636f6c6c ffff80003d847a40 0000000000000042 0000000000000006 [ 0.031643] 7c00: 0000000000000041 ffff000008f79c4d ffff000088f79c3f 0000000000000006 [ 0.031877] 7c20: 00000000deadbeef 0000000000000a3f [ 0.032051] [] pcpu_alloc+0x88/0x6c0 [ 0.032229] [] __alloc_percpu+0x18/0x20 [ 0.032409] [] xen_guest_init+0x174/0x2f4 [ 0.032591] [] do_one_initcall+0x38/0x130 [ 0.032783] [] kernel_init_freeable+0xe0/0x248 [ 0.032995] [] kernel_init+0x10/0x100

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[ 0.033172] [] ret_from_fork+0x10/0x50

2932 arch\arm\xen\enlighten.c#0416 2933 arch\arm\xen\mm.c#0189 Repo: 7641842164c3 Alexander Wed Nov 2 07:12:47 2016 -0400 Description: swiotlb-xen: Enforce return of DMA_ERROR_CODE in mapping function ------The mapping function should always return DMA_ERROR_CODE when a mapping has failed as this is what the DMA API expects when a DMA error has occurred. The current function for mapping a page in Xen was returning either DMA_ERROR_CODE or 0 depending on where it failed.

On x86 DMA_ERROR_CODE is 0, but on other architectures such as ARM it is ~0. We need to make sure we return the same error value if either the mapping failed or the device is not capable of accessing the mapping.

If we are returning DMA_ERROR_CODE as our error value we can drop the function for checking the error code as the default is to compare the return value against DMA_ERROR_CODE if no function is defined.

arch\arm64\ 2934 arch\arm64\Kconfig#0055 Repo: f4000cd99750 Linus Tue Dec 13 16:39:21 2016 -0800 Description: Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux ------Pull arm64 updates from Catalin Marinas:

- struct thread_info moved off-stack (also touching include/linux/thread_info.h and include/linux/restart_block.h)

- cpus_have_cap() reworked to avoid __builtin_constant_p() for static key use (also touching drivers/irqchip/irq-gic-v3.c)

- uprobes support (currently only for native 64-bit tasks)

- Emulation of kernel Privileged Access Never (PAN) using TTBR0_EL1 switching to a reserved

- CPU capacity information passing via DT or sysfs (used by the scheduler)

- support for systems without FP/SIMD (IOW, kernel avoids touching these registers; there is no soft-float ABI, nor kernel emulation for AArch64 FP/SIMD)

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- handling of hardware watchpoint with unaligned addresses, varied lengths and offsets from base

- use of the page table contiguous hint for kernel mappings

- hugetlb fixes for sizes involving the contiguous hint

- remove unnecessary I-cache invalidation in flush_cache_range()

- CNTHCTL_EL2 access fix for CPUs with VHE support (ARMv8.1)

- boot-time checks for writable+executable kernel mappings

- simplify asm/opcodes.h and avoid including the 32-bit ARM counterpart and make the arm64 kernel headers self-consistent (Xen headers patch merged separately)

- Workaround for broken .inst support in certain binutils versions

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (60 commits) arm64: Disable PAN on uaccess_enable() arm64: Work around broken .inst when defective gas is detected arm64: Add detection code for broken .inst support in binutils arm64: Remove reference to asm/opcodes.h arm64: Get rid of asm/opcodes.h arm64: smp: Prevent raw_smp_processor_id() recursion arm64: head.S: Fix CNTHCTL_EL2 access on VHE system arm64: Remove I-cache invalidation from flush_cache_range() arm64: Enable HIBERNATION in defconfig arm64: Enable CONFIG_ARM64_SW_TTBR0_PAN arm64: xen: Enable user access before a privcmd hvc call arm64: Handle faults caused by inadvertent user access with PAN enabled arm64: Disable TTBR0_EL1 during normal kernel execution arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1 arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro arm64: Factor out PAN enabling/disabling into separate uaccess_* macros arm64: Update the synchronous external abort fault description selftests: arm64: add test for unaligned/inexact watchpoint handling arm64: Allow hw watchpoint of length 3,5,6 and 7 arm64: hw_breakpoint: Handle inexact watchpoint addresses ...

ACPI / APEI / ARM64: APEI initial support for ARM64 ------This patch provides APEI arch-specific bits for ARM64

Meanwhile,

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(1) Move HEST type (ACPI_HEST_TYPE_IA32_CORRECTED_CHECK) checking to a generic place. (2) Select HAVE_ACPI_APEI when EFI and ACPI is set on ARM64, because arch_apei_get_mem_attribute is using efi_mem_attributes() on ARM64.

arm64: Enable CONFIG_ARM64_SW_TTBR0_PAN ------This patch adds the Kconfig option to enable support for TTBR0 PAN emulation. The option is default off because of a slight performance hit when enabled, caused by the additional TTBR0_EL1 switching during user access operations or exception entry/exit code.

arm64: split thread_info from task stack ------This patch moves arm64's struct thread_info from the task stack into task_struct. This protects thread_info from corruption in the case of stack overflows, and makes its address harder to determine if stack addresses are leaked, making a number of attacks more difficult. Precise detection and handling of overflow is left for subsequent patches.

Largely, this involves changing code to store the task_struct in sp_el0, and acquire the thread_info from the task struct. Core code now implements current_thread_info(), and as noted in this relies on offsetof(task_struct, thread_info) == 0, enforced by core code.

This change means that the 'tsk' register used in entry.S now points to a task_struct, rather than a thread_info as it used to. To make this clear, the TI_* field offsets are renamed to TSK_TI_*, with asm-offsets appropriately updated to account for the structural change.

Userspace clobbers sp_el0, and we can no longer restore this from the stack. Instead, the current task is cached in a per-cpu variable that we can safely access from early assembly as interrupts are disabled (and we are thus not preemptible).

Both secondary entry and idle are updated to stash the sp and task pointer separately.

arm64: Add uprobe support ------This patch adds support for uprobe on ARM64 architecture.

Unit tests for following have been done so far and they have been found working 1. Step-able instructions, like sub, ldr, add etc.

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2. Simulation-able like ret, cbnz, cbz etc. 3. uretprobe 4. Reject-able instructions like sev, wfe etc. 5. trapped and abort xol path 6. probe at unaligned user address. 7. longjump test cases

Currently it does not support aarch32 instruction probing.

2935 arch\arm64\Kconfig#0113 2936 arch\arm64\Kconfig#0243 2937 arch\arm64\Kconfig#0798 2938 arch\arm64\Kconfig.debug#0005 Repo: 1404d6f13e47 Laura Abbott Thu Oct 27 09:27:34 2016 -0700 Description: arm64: dump: Add checking for writable and exectuable pages ------Page mappings with full RWX permissions are a security risk. x86 has an option to walk the page tables and dump any bad pages. (See e1a58320a38d ("x86/mm: Warn on W^X mappings")). Add a similar implementation for arm64.

arm64: dump: Make ptdump debugfs a separate option ------ptdump_register currently initializes a set of page table information and registers debugfs. There are uses for the ptdump option without wanting the debugfs options. Split this out to make it a separate option.

2939 arch\arm64\Kconfig.debug#0011 2940 arch\arm64\Kconfig.debug#0045 2941 arch\arm64\Kconfig.platforms#0116 Repo: 991688bfc635 Linus Thu Dec 15 16:03:25 2016 -0800 Description: Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM SoC driver updates from Arnd Bergmann: "Driver updates for ARM SoCs, including a couple of newly added drivers:

- A new driver for the power management controller on TI Keystone

- Support for the prerelease "SCPI" firmware protocol that ended up being shipped by Amlogic in their GXBB SoC.

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- A soc_device can now be matched using a glob from inside the kernel, when another driver wants to know the specific chip it is running on and cannot find out from DT, firmware or hardware.

- Renesas SoCs now support identification through the soc_device interface, both in user space and kernel.

- Renesas r8a7743 and r8a7745 gain support for their system controller

- A new checking module for the ARM "PSCI" (not to be confused with "SCPI" mentioned above) firmware interface.

- A new driver for the Tegra GMI memory interface

- Support for the Tegra firmware interfaces with their power management controllers

As usual, the updates for the reset controller framework are merged here, as they tend to touch multiple SoCs as well, including a new driver for the Oxford (now Broadcom) OX820 chip and the Tegra bpmp interface.

The existing drivers for Atmel, Qualcomm, NVIDIA, TI Davinci, and Rockchips SoCs see some further updates"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (76 commits) misc: sram: remove useless #ifdef drivers: psci: Allow PSCI node to be disabled drivers: psci: PSCI checker module soc: renesas: Identify SoC and register with the SoC bus firmware: qcom: scm: Return PTR_ERR when devm_clk_get fails firmware: qcom: scm: Remove core, iface and bus clocks dependency dt-bindings: firmware: scm: Add MSM8996 DT bindings memory: da8xx-ddrctl: drop the call to of_flat_dt_get_machine_name() bus: da8xx-mstpri: drop the call to of_flat_dt_get_machine_name() ARM: shmobile: Document DT bindings for Product Register soc: renesas: rcar-sysc: add R8A7745 support reset: Add Tegra BPMP reset driver dt-bindings: firmware: Allow child nodes inside the Tegra BPMP dt-bindings: Add power domains to Tegra BPMP firmware firmware: tegra: Add BPMP support firmware: tegra: Add IVC library dt-bindings: firmware: Add bindings for Tegra BPMP mailbox: tegra-hsp: Use after free in tegra_hsp_remove_doorbells() mailbox: Add Tegra HSP driver firmware: arm_scpi: add support for pre-v1.0 SCPI compatible ...

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Merge tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM SoC 64-bit updates from Arnd Bergmann: "Changes to platform code for 64-bit ARM platforms. We are not adding any new platforms that require code or Kconfig changes this time, so it's basically just defconfig changes to enable support for more drivers used on the existing platforms.

This is mainly interesting for the Raspberry Pi 3, which should now work much better with the default build"

* tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: arm64: defconfig: drop GPIO_SYSFS on multiplatforms arm64: defconfig: Do not lower CONFIG_LOG_BUF_SHIFT arm64: defconfig: allow rk3399-based boards to boot from mmc and usb arm64: defconfig: enable RK808 components arm64: defconfig: enable I2C and DW MMC controller on rockchip platform arm64: defconfig: Enable Tegra186 SoC ARM64: configs: Activate Internal PHY for Meson GXL arm64: qcom: enable GPIOLIB in Kconfig arm64: configs: enable configs for msm899(2/4) basic support ARM64: bcm2835: add thermal driver to default config ARM64: configs: Add Platform MHU in defconfig MAINTAINERS: Update Broadcom Vulcan maintainer email arm64: defconfig: enable EEPROM_AT25 config option arm64: Enable HIBERNATION in defconfig arm64: defconfig: Enable DRM DU and V4L2 FCP + VSP modules ARM64: defconfig: Enable MMC related configs arm64: Add BCM2835 (Raspberry Pi 3) support to the defconfig

soc: renesas: Identify SoC and register with the SoC bus ------Identify the SoC type and revision, and register this information with the SoC bus, so it is available under /sys/devices/soc0/, and can be checked where needed using soc_device_match().

Identification is done using the Product Register or Common Chip Code Register, as declared in DT (PRR only for now), or using a hardcoded fallback if missing.

Example:

Detected Renesas R-Car Gen2 r8a7791 ES1.0 ... # cat /sys/devices/soc0/{machine,family,soc_id,revision} Koelsch R-Car Gen2 r8a7791

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ES1.0

arm64: qcom: enable GPIOLIB in Kconfig ------While debugging a kernel image size issue, I discovered that if all non ARCH_QCOM configs in the ARM64 defconfig are disabled, the QCOM pinctrl drivers will not be built.

The QCOM pinctrl drivers have a dependency on GPIOLIB which was being selected when other ARCH configs were enabled, but ARCH_QCOM doesn't select GPIOLIB directly. Let's select GPIOLIB here to ensure the pinctrl drivers are built for QCOM platforms.

arm64: uniphier: select ARCH_HAS_RESET_CONTROLLER ------The UniPhier reset driver (drivers/reset/reset-uniphier.c) has been merged. Select ARCH_HAS_RESET_CONTROLLER from the SoC Kconfig.

Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM 64-bit DT updates from Arnd Bergmann: "The 64-bit DT changes are surprisingly small this time, we only add two SoC platforms: the ZTE ZX296718 Set-top-box SoC and the SocioNext UniPhier LD11 TV SoC, each with their reference boards.

There are three new machines added for existing SoC platforms:

- The Marvell Armada 8040 development board is an impressive quad-core Cortex-A72 machine with three 10gbit ethernet interfaces

- Qualcomms DragonBoard 820c single-board computer is their current high-end phone platform in the 96boards form factor

- Rockchip: Tronsmart Orion r86 set-top-box is a popular mid-range Android box based on the 8-core rk3368 SoC"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (91 commits) arm64: dts: berlin4ct: Add L2 cache topology arm64: dts: berlin4ct: enable all wdt nodes unconditionally arm64: dts: berlin4ct: switch to Cortex-A53 specific pmu nodes arm64: dts: Add ZTE ZX296718 SoC dts and Makefile arm64: dts: apm: Add DT node for APM X-Gene 2 CPU clocks arm64: dts: apm: Add X-Gene SoC hwmon to device tree arm64: dts: apm: Fix interrupt polarity for X-Gene PCIe legacy interrupts arm64: dts: apm: Add APM X-Gene v2 SoC PMU DTS entries arm64: dts: apm: Add APM X-Gene SoC PMU DTS entries

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arm64: dts: marvell: enable MSI for PCIe on Armada 7K/8K arm64: dts: ls2080a: Add 'dma-coherent' for ls2080a PCI nodes arm64: dts: rockchip: add Type-C phy for RK3399 arm64: dts: rockchip: enable the gmac for rk3399 evb board arm64: dts: rockchip: add the gmac needed node for rk3399 arm64: dts: rockchip: support the pmu node for rk3399 arm64: dts: rockchip: change all interrupts cells to 4 on rk3399 SoCs arm64: dts: rockchip: add the tcpc for rk3399 power domain arm64: dts: rockchip: add efuse0 device node for rk3399 arm64: dts: rockchip: configure PCIe support for rk3399-evb arm64: dts: rockchip: add the PCIe controller support for RK3399 ...

2942 arch\arm64\Kconfig.platforms#0147 2943 arch\arm64\Makefile#0040 Repo: bbb56c27228d Marc Zyngier Tue Dec 6 15:27:43 2016 +0000 Description: arm64: Add detection code for broken .inst support in binutils ------Binutils version up to (and including) 2.25 have a pathological behaviour when it comes to mixing .inst directive and arithmetic involving labels. The assembler complains about non-constant expressions and compilation stops pretty quickly.

In order to detect this and work around it, let's add a bit of detection code that will set the CONFIG_BROKEN_GAS_INST option should a broken gas be detected.

2944 arch\arm64\Makefile#0049 arch\arm64\boot\dts\ 2945 arch\arm64\boot\dts\Makefile#0002 Repo: 4e3886081848 Andre Tue Jan 19 10:36:39 2016 +0000 Description: arm64: dts: add Pine64 support ------The Pine64 is a cost-efficient development board based on the Allwinner A64 SoC. There are three models: the basic version with Fast Ethernet and 512 MB of DRAM (Pine64) and two Pine64+ versions, which both feature Gigabit Ethernet and additional connectors for touchscreens and a camera. Or as my son put it: "Those are smaller and these are missing." ;-) The two Pine64+ models just differ in the amount of DRAM (1GB vs. 2GB). Since U-Boot will figure out the right size for us and patches the DT accordingly we just need to provide one DT for the Pine64+.

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Line Link NR. Descriptions arch\arm64\boot\dts\amlogic\ 2946 arch\arm64\boot\dts\amlogic\Makefile#0001 Repo: 8441add12b9e Neil Tue Nov 22 12:41:54 2016 +0100 Description: ARM64: dts: meson-gxl: Add support for Nexbox A95X ------The Nexbox A95X exists with a Meson GXBB (S905) Soc or a Meson GXL SoC (S905X). Add the S905X variant which uses the internal PHY instead of an external PHY.

ARM64: dts: meson-gxm: Add support for the Nexbox A1 ------Add support for the Nexbox A1 board based on the Amlogic S912 SoC.

ARM64: dts: Add support for Meson GXM ------Following the Amlogic Linux kernel, it seem the only differences between the GXL and GXM SoCs are the CPU Clusters.

This commit renames the gxl-s905d-p23x DTSI in a common file for S905D p23x and S912 q20x boards.

Then adds a meson-gxm dtsi and reproduce the P23x to Q20x boards dts files since the S905D and S912 SoCs shares the same pinout and the P23x and Q20x boards are identical.

ARM64: dts: meson-gxbb: Add support for the Nexbox A95X Board ------Add support for the S905 (GXBB) version of the Nexbox A95X.

ARM64: dts: amlogic: Add basic support for Amlogic S905D ------This patch introduces the basic support for the Amlogic S905D (MesonGXL) and for the Amlogic evaluation boards P230 and P231. No documentation has been released yet for this SoC, so for now only the bare minimum has been added in the DT.

ARM64: dts: amlogic: Add basic support for Amlogic S905X ------This patch introduces the basic support for the Amlogic S905X (Meson GXL) and for the Amlogic evaluation board P212. No documentation has been released yet for this SoC, so for now only the bare minimum has been added in the DT.

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ARM64: dts: amlogic: Add P200/P201 boards ------Add minimal DT files for the Amlogic P20x development boards, based on the Amlogic S905/GXBB SoC.

2947 arch\arm64\boot\dts\amlogic\Makefile#0008 2948 arch\arm64\boot\dts\amlogic\meson-gxbb-odroidc2.dts#0067 Repo: feb3cbea0946 Jerome Fri Jan 20 08:20:24 2017 -0800 Description: ARM64: dts: meson-gxbb-odroidc2: fix GbE tx link breakage ------OdroidC2 GbE link breaks under heavy tx transfer. This happens even if the MAC does not enable Energy Efficient Ethernet (No Low Power state Idle on the Tx path). The problem seems to come from the phy Rx path, entering the LPI state.

Disabling EEE advertisement on the phy prevent this feature to be negociated with the link partner and solve the issue.

ARM64: dts: meson-gxbb-odroidc2: Disable SCPI DVFS ------The current hardware is not able to run with all cores enabled at a cluster frequency superior at 1536MHz. But the currently shipped u-boot for the platform still reports an OPP table with possible DVFS frequency up to 2GHz, and will not change since the off-tree linux tree supports limiting the OPPs with a kernel parameter. A recent u-boot change reports the boot-time DVFS around 100MHz and the default performance cpufreq governor sets the maximum frequency. Previous version of u-boot reported to be already at the max OPP and left the OPP as is. Nevertheless, other governors like ondemand could setup the max frequency and make the system crash.

This patch disables the DVFS clock and disables cpufreq.

Fixes: 70db166a2baa ("ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes")

ARM64: dts: meson-gxbb: add MMC support ------Add binding and basic support for the SD/eMMC controller on Amlogic S905/GXBB devices.

ARM64: dts: meson-gxbb-odroidc2: Enable USB Nodes ------

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Enable both gxbb USB controller and add a 5V regulator for the OTG port VBUS

ARM64: dts: meson-gxbb: Add rmii pinctrl node and rename rgmii node ------For boards only supporting 10/100 ethernet over a RMII PHY link, add a separate pinctrl node. By the way, rename the existing node to rgmii specific naming in all boards dts.

2949 arch\arm64\boot\dts\amlogic\meson-gxbb-odroidc2.dts#0088 2950 arch\arm64\boot\dts\amlogic\meson-gxbb-odroidc2.dts#0140 2951 arch\arm64\boot\dts\amlogic\meson-gxbb-odroidc2.dts#0152 2952 arch\arm64\boot\dts\amlogic\meson-gxbb-odroidc2.dts#0154 2953 arch\arm64\boot\dts\amlogic\meson-gxbb-odroidc2.dts#0179 2954 arch\arm64\boot\dts\amlogic\meson-gxbb-p20x.dtsi#0073 Repo: fafdbdf76789 Neil Thu Dec 1 10:05:58 2016 +0100 Description: ARM64: dts: meson-gx: Add Graphic Controller nodes ------Add Video Processing Unit and CVBS Output nodes, and enable CVBS on selected boards.

ARM64: dts: meson-gxbb: Add P20x Wifi SDIO support ------Add Wifi module support on the Amlogic P20x boards on the SDIO port. The Wifi module also needs a 32768Hz clock provided by the PWM E port through a pwm-clock node in it's power sequence.

ARM64: dts: meson-gxbb: Add Wifi 32K clock for p20x boards ------Add a 32768Hz clock generated by the PWM E port used by the WiFi module.

ARM64: dts: meson-gxbb: add MMC support ------Add binding and basic support for the SD/eMMC controller on Amlogic S905/GXBB devices.

ARM64: dts: meson-gxbb: Add rmii pinctrl node and rename rgmii node ------For boards only supporting 10/100 ethernet over a RMII PHY link, add a separate pinctrl node. By the way, rename the existing node to rgmii

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specific naming in all boards dts.

2955 arch\arm64\boot\dts\amlogic\meson-gxbb-p20x.dtsi#0149 2956 arch\arm64\boot\dts\amlogic\meson-gxbb-p20x.dtsi#0175 2957 arch\arm64\boot\dts\amlogic\meson-gxbb-vega-s95.dtsi#0068 Repo: ab5b24fdd2d5 Martin Sat Nov 12 14:07:19 2016 +0100 Description: ARM64: dts: meson-gxbb-vega-s95: Add SD/SDIO/MMC and PWM nodes ------All boards from the Tronsmart Vega S95 series are sharing similar MMC based hardware. sd_emmc_a is used to connect a Broadcom based SDIO wifi card (supported by the brcmfmac driver). The 32.768KHz LPO clock for the wifi chip is generated by PWM_E. sd_emmc_b is routed to the SD-card. Unlike p20x there is no GPIO regulator, meaning it only supports 3.3V (which seems to be hard-wired). The eMMC chip is connected to sd_emmc_c and is implemented similar to the meson-gxbb-p20x boards (meaning that hard-wired fixed regulators are used).

ARM64: dts: meson-gxbb: Add rmii pinctrl node and rename rgmii node ------For boards only supporting 10/100 ethernet over a RMII PHY link, add a separate pinctrl node. By the way, rename the existing node to rgmii specific naming in all boards dts.

ARM64: dts: meson-gxbb-vega-s95: Enable USB Nodes ------Enable both gxbb USB controller and add a 5V regulator for the OTG port VBUS

2958 arch\arm64\boot\dts\amlogic\meson-gxbb-vega-s95.dtsi#0118 2959 arch\arm64\boot\dts\amlogic\meson-gxbb-vega-s95.dtsi#0138 2960 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0043 Repo: f7bcd4b6f698 Neil Fri Jan 6 09:04:32 2017 +0100 Description: ARM64: dts: meson-gxbb-odroidc2: Disable SCPI DVFS ------The current hardware is not able to run with all cores enabled at a cluster frequency superior at 1536MHz. But the currently shipped u-boot for the platform still reports an OPP table with possible DVFS frequency up to 2GHz, and will not change since the off-tree linux tree supports limiting the OPPs with a kernel parameter.

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A recent u-boot change reports the boot-time DVFS around 100MHz and the default performance cpufreq governor sets the maximum frequency. Previous version of u-boot reported to be already at the max OPP and left the OPP as is. Nevertheless, other governors like ondemand could setup the max frequency and make the system crash.

This patch disables the DVFS clock and disables cpufreq.

Fixes: 70db166a2baa ("ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes")

ARM64: dts: meson-gx: Add Graphic Controller nodes ------Add Video Processing Unit and CVBS Output nodes, and enable CVBS on selected boards.

ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ------The SCPI driver has an updated compatible to indicate the pre-released (pre v1.0) status of the driver. Since Amlogic used a pre-1.0 version, add that compatible as well.

ARM64: dts: meson-gxbb: add the USB reset also to the second USB PHY ------When the USB PHY driver was introduced the reset framework did not have support for triggering a reset pulse for shared resets. On GXBB however there is only one reset line for both PHYs (meaning we have a shared reset line). With the latest changes to the reset framework and the corresponding updates to the phy-meson8b-usb2 driver we can now pass the reset to the second PHY as well.

ARM64: dts: meson-gxbb: Move common nodes to meson-gx ------Move common nodes between GXBB and GXL in to the common GX dtsi. Leave the clock attributes in the GXBB dtsi for now.

ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes ------

ARM64: dts: meson-gxbb: Add SRAM node ------

ARM64: dts: meson-gxbb: add MMC support

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------Add binding and basic support for the SD/eMMC controller on Amlogic S905/GXBB devices.

ARM64: dts: meson-gxbb: Add rmii pinctrl node and rename rgmii node ------For boards only supporting 10/100 ethernet over a RMII PHY link, add a separate pinctrl node. By the way, rename the existing node to rgmii specific naming in all boards dts.

ARM64: dts: amlogic: Add Meson GX dtsi from GXBB ------Move all non-gxbb specific nodes to a common GX dtsi.

2961 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0054 2962 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0058 2963 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0062 2964 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0069 2965 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0076 2966 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0082 2967 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0091 2968 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0149 2969 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0168 2970 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0173 2971 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0180 2972 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0186 2973 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0194 2974 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0201 2975 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0202 2976 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0277 2977 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0289 2978 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0290

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2979 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0297 2980 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0303 2981 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0312 2982 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0319 2983 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0326 2984 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0334 2985 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0341 2986 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0348 2987 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0362 2988 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0363 2989 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0369 2990 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0370 2991 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0377 2992 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0378 2993 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0384 2994 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0385 2995 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0391 2996 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0392 2997 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0403 2998 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0414 2999 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0415 3000 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0421 3001 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0431 3002 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0440 3003 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0450 3004 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0462 3005 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0474 3006 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0481 3007 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0489

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3008 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0497 3009 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0505 3010 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0513 3011 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0521 3012 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0529 3013 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0549 3014 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0556 3015 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0563 3016 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0570 3017 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0577 3018 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0600 3019 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0612 3020 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0613 3021 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0623 3022 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0631 3023 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0643 3024 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0655 3025 arch\arm64\boot\dts\amlogic\meson-gxbb.dtsi#0669 3026 arch\arm64\boot\dts\amlogic\meson-gx-p23x-q20x.dtsi#newFile Repo: bb51b5350d2f Neil Tue Nov 22 11:00:45 2016 +0100 Description: ARM64: dts: Add support for Meson GXM ------Following the Amlogic Linux kernel, it seem the only differences between the GXL and GXM SoCs are the CPU Clusters.

This commit renames the gxl-s905d-p23x DTSI in a common file for S905D p23x and S912 q20x boards.

Then adds a meson-gxm dtsi and reproduce the P23x to Q20x boards dts files since the S905D and S912 SoCs shares the same pinout and the P23x and Q20x boards are identical.

3027 arch\arm64\boot\dts\amlogic\meson-gx.dtsi#newFile Repo: bba8e3f42736 Neil Fri Jan 20 08:20:25 2017 -0800 Description: ARM64: dts: meson-gx: Add firmware reserved memory zones ------

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The Amlogic Meson GXBB/GXL/GXM secure monitor uses part of the memory space, this patch adds these reserved zones.

Without such reserved memory zones, running the following stress command : $ stress-ng --vm 16 --vm-bytes 128M --timeout 10s multiple times:

Could lead to the following kernel crashes : [ 46.937975] Bad mode in Error handler detected on CPU1, code 0xbf000000 -- SError ... [ 47.058536] Internal error: Attempting to execute userspace memory: 8600000f [#3] PREEMPT SMP ... Instead of the OOM killer.

Fixes: 4f24eda8401f ("ARM64: dts: Prepare configs for Amlogic Meson GXBaby")

3028 arch\arm64\boot\dts\amlogic\meson-gxbb-nexbox-a95x.dts#newFile Repo: fafdbdf76789 Neil Thu Dec 1 10:05:58 2016 +0100 Description: ARM64: dts: meson-gx: Add Graphic Controller nodes ------Add Video Processing Unit and CVBS Output nodes, and enable CVBS on selected boards.

3029 arch\arm64\boot\dts\amlogic\meson-gxl-nexbox-a95x.dts#newFile Repo: fafdbdf76789 Neil Thu Dec 1 10:05:58 2016 +0100 Description: ARM64: dts: meson-gx: Add Graphic Controller nodes ------Add Video Processing Unit and CVBS Output nodes, and enable CVBS on selected boards.

3030 arch\arm64\boot\dts\amlogic\meson-gxl-s905d-p230.dts#newFile Repo: bb51b5350d2f Neil Tue Nov 22 11:00:45 2016 +0100 Description: ARM64: dts: Add support for Meson GXM ------Following the Amlogic Linux kernel, it seem the only differences between the GXL and GXM SoCs are the CPU Clusters.

This commit renames the gxl-s905d-p23x DTSI in a common file for S905D p23x and S912 q20x boards.

Then adds a meson-gxm dtsi and reproduce the P23x to Q20x boards dts files since the S905D and S912 SoCs shares the same pinout and the P23x and Q20x boards are identical.

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3031 arch\arm64\boot\dts\amlogic\meson-gxl-s905d-p231.dts#newFile Repo: bb51b5350d2f Neil Tue Nov 22 11:00:45 2016 +0100 Description: ARM64: dts: Add support for Meson GXM ------Following the Amlogic Linux kernel, it seem the only differences between the GXL and GXM SoCs are the CPU Clusters.

This commit renames the gxl-s905d-p23x DTSI in a common file for S905D p23x and S912 q20x boards.

Then adds a meson-gxm dtsi and reproduce the P23x to Q20x boards dts files since the S905D and S912 SoCs shares the same pinout and the P23x and Q20x boards are identical.

3032 arch\arm64\boot\dts\amlogic\meson-gxl-s905d.dtsi#newFile Repo: da47515ee63f Neil Tue Oct 4 17:37:10 2016 +0200 Description: ARM64: dts: amlogic: Add basic support for Amlogic S905D ------This patch introduces the basic support for the Amlogic S905D (MesonGXL) and for the Amlogic evaluation boards P230 and P231. No documentation has been released yet for this SoC, so for now only the bare minimum has been added in the DT.

3033 arch\arm64\boot\dts\amlogic\meson-gxl-s905x-p212.dts#newFile Repo: 15abee8ab055 Carlo Caione Tue Oct 4 17:37:09 2016 +0200 Description: ARM64: dts: amlogic: Add basic support for Amlogic S905X ------This patch introduces the basic support for the Amlogic S905X (Meson GXL) and for the Amlogic evaluation board P212. No documentation has been released yet for this SoC, so for now only the bare minimum has been added in the DT.

3034 arch\arm64\boot\dts\amlogic\meson-gxl-s905x.dtsi#newFile Repo: 0fbab1516b35 Neil Mon Nov 7 11:43:57 2016 +0100 Description: ARM64: dts: meson-gxl-s905x: Enable internal ethernet PHY ------

3035 arch\arm64\boot\dts\amlogic\meson-gxl.dtsi#newFile Repo: fafdbdf76789 Neil Thu Dec 1 10:05:58 2016 +0100 Description: ARM64: dts: meson-gx: Add Graphic Controller nodes ------

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Add Video Processing Unit and CVBS Output nodes, and enable CVBS on selected boards.

3036 arch\arm64\boot\dts\amlogic\meson-gxm-nexbox-a1.dts#newFile Repo: fafdbdf76789 Neil Thu Dec 1 10:05:58 2016 +0100 Description: ARM64: dts: meson-gx: Add Graphic Controller nodes ------Add Video Processing Unit and CVBS Output nodes, and enable CVBS on selected boards.

3037 arch\arm64\boot\dts\amlogic\meson-gxm-s912-q200.dts#newFile Repo: bb51b5350d2f Neil Tue Nov 22 11:00:45 2016 +0100 Description: ARM64: dts: Add support for Meson GXM ------Following the Amlogic Linux kernel, it seem the only differences between the GXL and GXM SoCs are the CPU Clusters.

This commit renames the gxl-s905d-p23x DTSI in a common file for S905D p23x and S912 q20x boards.

Then adds a meson-gxm dtsi and reproduce the P23x to Q20x boards dts files since the S905D and S912 SoCs shares the same pinout and the P23x and Q20x boards are identical.

3038 arch\arm64\boot\dts\amlogic\meson-gxm-s912-q201.dts#newFile Repo: bb51b5350d2f Neil Tue Nov 22 11:00:45 2016 +0100 Description: ARM64: dts: Add support for Meson GXM ------Following the Amlogic Linux kernel, it seem the only differences between the GXL and GXM SoCs are the CPU Clusters.

This commit renames the gxl-s905d-p23x DTSI in a common file for S905D p23x and S912 q20x boards.

Then adds a meson-gxm dtsi and reproduce the P23x to Q20x boards dts files since the S905D and S912 SoCs shares the same pinout and the P23x and Q20x boards are identical.

3039 arch\arm64\boot\dts\amlogic\meson-gxm.dtsi#newFile Repo: fafdbdf76789 Neil Thu Dec 1 10:05:58 2016 +0100 Description: ARM64: dts: meson-gx: Add Graphic Controller nodes

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------Add Video Processing Unit and CVBS Output nodes, and enable CVBS on selected boards.

arch\arm64\boot\dts\arm\ 3040 arch\arm64\boot\dts\arm\juno-base.dtsi#0032 Repo: 482c3e8835e9 Linus Thu Dec 15 15:58:28 2016 -0800 Description: Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources:

- Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line - Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips

Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time:

- Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board

For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits) arm64: dts: fix build errors from missing dependencies

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ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...

3041 arch\arm64\boot\dts\arm\juno-base.dtsi#0171 3042 arch\arm64\boot\dts\arm\juno-base.dtsi#0430 3043 arch\arm64\boot\dts\arm\juno-base.dtsi#0512 3044 arch\arm64\boot\dts\arm\juno-base.dtsi#0569 3045 arch\arm64\boot\dts\arm\juno-base.dtsi#0586 3046 arch\arm64\boot\dts\arm\juno-base.dtsi#0601 3047 arch\arm64\boot\dts\arm\juno-base.dtsi#0655 3048 arch\arm64\boot\dts\arm\juno-base.dtsi#0663 3049 arch\arm64\boot\dts\arm\juno-r1.dts#0093 Repo: 482c3e8835e9 Linus Thu Dec 15 15:58:28 2016 -0800 Description: Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources:

- Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product

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line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line - Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips

Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time:

- Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board

For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits) arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...

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3050 arch\arm64\boot\dts\arm\juno-r1.dts#0104 3051 arch\arm64\boot\dts\arm\juno-r1.dts#0115 3052 arch\arm64\boot\dts\arm\juno-r1.dts#0126 3053 arch\arm64\boot\dts\arm\juno-r1.dts#0137 3054 arch\arm64\boot\dts\arm\juno-r1.dts#0148 3055 arch\arm64\boot\dts\arm\juno-r2.dts#0093 Repo: 482c3e8835e9 Linus Thu Dec 15 15:58:28 2016 -0800 Description: Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources:

- Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line - Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips

Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time:

- Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board

For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits)

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arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...

3056 arch\arm64\boot\dts\arm\juno-r2.dts#0104 3057 arch\arm64\boot\dts\arm\juno-r2.dts#0115 3058 arch\arm64\boot\dts\arm\juno-r2.dts#0126 3059 arch\arm64\boot\dts\arm\juno-r2.dts#0137 3060 arch\arm64\boot\dts\arm\juno-r2.dts#0148 3061 arch\arm64\boot\dts\arm\juno.dts#0093 Repo: 482c3e8835e9 Linus Thu Dec 15 15:58:28 2016 -0800 Description: Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources:

- Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810)

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mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line - Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips

Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time:

- Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board

For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits) arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...

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3062 arch\arm64\boot\dts\arm\juno.dts#0104 3063 arch\arm64\boot\dts\arm\juno.dts#0115 3064 arch\arm64\boot\dts\arm\juno.dts#0126 3065 arch\arm64\boot\dts\arm\juno.dts#0137 3066 arch\arm64\boot\dts\arm\juno.dts#0148 3067 arch\arm64\boot\dts\arm\rtsm_ve-aemv8a.dts#0084 Repo: 1dff32d7df7f Sudeep Tue Dec 13 14:24:53 2016 +0000 Description: arm64: dts: vexpress: Support GICC_DIR operations ------The GICv2 CPU interface registers span across 8K, not 4K as indicated in the DT. Only the GICC_DIR register is located after the initial 4K boundary, leaving a functional system but without support for separately EOI'ing and deactivating interrupts.

After this change the system supports split priority drop and interrupt deactivation. This patch is based on similar one from Christoffer Dall: commit 368400e242dc ("ARM: dts: vexpress: Support GICC_DIR operations")

arch\arm64\boot\dts\broadcom\ 3068 arch\arm64\boot\dts\broadcom\bcm2837-rpi-3-b.dts#0005 Repo: a44e87b47148 Andrea Fri Nov 11 09:38:21 2016 -0800 Description: ARM64: dts: bcm2837-rpi-3-b: remove incorrect pwr LED ------We are incorrectly defining the pwr LED, attaching it to a gpio line that is wired to the Wi-Fi SDIO module (which fails due to this).

The actual power LED is connected to the GPIO expander, which we don't expose currently.

Fixes: 9d56c22a7861 ("ARM: bcm2835: Add devicetree for the Raspberry Pi 3.") Thanks-to: Eric Anholt [for clarifying we can't control the LED]

ARM64: dts: bcm283x: Use dtsi for USB host mode ------In case dr_mode isn't passed via DT, the dwc2 driver defaults to OTG mode. But the Raspberry Pi 3 is designed only for host mode. So fix this issue by linking to the dtsi file which set the dr_mode to host.

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3069 arch\arm64\boot\dts\broadcom\bcm2837-rpi-3-b.dts#0019 3070 arch\arm64\boot\dts\broadcom\bcm2837.dtsi#0004 Repo: ce2a6ca5c6ec Martin Sperl Wed Nov 2 10:18:24 2016 +0000 Description: ARM64: bcm2835: dts: add thermal node to device-tree of bcm2837 ------Add the node for the thermal sensor of the bcm2837-soc to the device tree.

ARM64: dts: bcm2835: Fix bcm2837 compatible string ------bcm2837-rpi-3-b.dts, its only in-tree user, was overriding it as "brcm,bcm2837" already.

Fixes: 9d56c22a7861 ("ARM: bcm2835: Add devicetree for the Raspberry Pi 3.")

3071 arch\arm64\boot\dts\broadcom\bcm2837.dtsi#0077 3072 arch\arm64\boot\dts\broadcom\ns2-svk.dts#0059 Repo: 482c3e8835e9 Linus Thu Dec 15 15:58:28 2016 -0800 Description: Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources:

- Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line - Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips

Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time:

- Huawei Nexus 6P (Angler) mobile phone

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- LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board

For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits) arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...

arm64: dts: NS2: enable sdio1 ------Enable sdio1 in the Northstar2 SVK device tree file

arm64: dts: NS2: add AMAC ethernet support ------Add support for the AMAC ethernet to the Broadcom Northstar2 SoC device tree

arm64: dts: Updated NAND DT properties for NS2 SVK ------This patch adds NAND DT properties for NS2 SVK to configure the bus width width and OOB sector size

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arm64: dts: Updated NAND DT properties for NS2 SVK ------This patch adds NAND DT properties for NS2 SVK to configure the bus width width and OOB sector size

ARM64: dts: Add QSPI Device Tree node for NS2 ------Adding QSPI node compatible with the new spi-bcm-qspi driver for the Broadcom's Northstar2 SoC.

3073 arch\arm64\boot\dts\broadcom\ns2-svk.dts#0164 3074 arch\arm64\boot\dts\broadcom\ns2-svk.dts#0185 3075 arch\arm64\boot\dts\broadcom\ns2-svk.dts#0199 3076 arch\arm64\boot\dts\broadcom\ns2.dtsi#0136 Repo: 482c3e8835e9 Linus Thu Dec 15 15:58:28 2016 -0800 Description: Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources:

- Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line - Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips

Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time:

- Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone

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- Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board

For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits) arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...

arm64: dts: NS2: Add PCI PHYs ------PCI PHYs are missing from the Northstar2 DT entries for the 2 PCI buses. Add them so that PCI devices can be discovered.

arm64: dts: NS2: add AMAC ethernet support ------Add support for the AMAC ethernet to the Broadcom Northstar2 SoC device tree

arm64: dts: Add Broadcom Northstar2 device tree entries for PDC driver. ------Add Broadcom Northstar2 SoC device tree entries for PDC driver.

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arm64: dts: Update Broadcom NS2 to generic IOMMU binding ------With the "mmu-masters" property now deprecated and optional, the generic binding offers a more efficient way to specify no masters.

CC: Ray Jui CC: Scott Branden CC: Jon Mason

ARM64: dts: Add QSPI Device Tree node for NS2 ------Adding QSPI node compatible with the new spi-bcm-qspi driver for the Broadcom's Northstar2 SoC.

3077 arch\arm64\boot\dts\broadcom\ns2.dtsi#0177 3078 arch\arm64\boot\dts\broadcom\ns2.dtsi#0200 3079 arch\arm64\boot\dts\broadcom\ns2.dtsi#0305 3080 arch\arm64\boot\dts\broadcom\ns2.dtsi#0622 arch\arm64\boot\dts\exynos\ 3081 arch\arm64\boot\dts\exynos\exynos7-pinctrl.dtsi#0023 Repo: 86bb573d0b2a Krzysztof Fri Sep 16 23:41:56 2016 +0200 Description: arm64: dts: exynos: Use human-friendly symbols for interrupt properties in exynos7 ------Replace hard-coded values of type of GIC interrupt and its flags with respective macros from header to increase code readability

arm64: dts: exynos: Fix invalid GIC interrupt flags in exynos7 ------Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and generates an error: genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)

The GIC requires shared interrupts to be edge rising or level high. Platform declares support for both. Arbitrarily choose level high everywhere hoping it will work on each platform.

3082 arch\arm64\boot\dts\exynos\exynos7-pinctrl.dtsi#0040

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3083 arch\arm64\boot\dts\exynos\exynos7.dtsi#0038 Repo: b2c3b216d996 Arnd Wed Nov 30 22:40:08 2016 +0100 Description: Merge tag 'samsung-dt64-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64 ------Pull "Samsung DeviceTree arm64 second update for v4.10" from Krzysztof Kozowski:

1. Add Performance Monitor Unit to Exynos7. 2. Add MFC, JPEG and Gscaler to Exynos5433 based TM2 board. 3. Cleanups and fixes for recently added TM2 and TM2E boards.

* tag 'samsung-dt64-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: dts: exynos: TM2 - add support for MFC video codec device arm64: dts: exynos: TM2 - add support for JPEG codec device arm64: dts: exynos: TM2 - add support for GScaler devices arm64: dts: exynos: TM2 - remove unused UART3 and set clocks directly on CMU arm64: dts: exynos: Assign parent clock of the clkout clock for TM2 board arm64: dts: exynos: Move FSYS CMU configuration from Exynos5433 dtsi to TM2 dts arm64: dts: exynos: Add missing parent clocks to audio block in Exynos5433 SoC arm64: dts: exynos: Fix FSYS CMU parent clocks in Exynos5433 SoC arm64: dts: exynos: Fix IRQ type flags for Exynos5433 SoC arm64: dts: Add ARM PMU node for exynos7

arm64: dts: Add ARM PMU node for exynos7 ------This patch adds ARM Performance Monitor Unit dt node for exynos7. PMU provides various statistics on the operation of the CPU and memory system at runtime, which are very useful when debugging or profiling code. This enables the same.

arm64: dts: exynos: Use human-friendly symbols for interrupt properties in exynos7 ------Replace hard-coded values of type of GIC interrupt and its flags with respective macros from header to increase code readability

arm64: dts: exynos: Fix invalid GIC interrupt flags in exynos7 ------Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and generates an error: genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)

The GIC requires shared interrupts to be edge rising or level high. Platform declares support for both. Arbitrarily choose level high everywhere hoping it will work on each platform.

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3084 arch\arm64\boot\dts\exynos\exynos7.dtsi#0045 3085 arch\arm64\boot\dts\exynos\exynos7.dtsi#0052 3086 arch\arm64\boot\dts\exynos\exynos7.dtsi#0059 3087 arch\arm64\boot\dts\exynos\exynos7.dtsi#0109 3088 arch\arm64\boot\dts\exynos\exynos7.dtsi#0120 3089 arch\arm64\boot\dts\exynos\exynos7.dtsi#0223 3090 arch\arm64\boot\dts\exynos\exynos7.dtsi#0233 3091 arch\arm64\boot\dts\exynos\exynos7.dtsi#0243 3092 arch\arm64\boot\dts\exynos\exynos7.dtsi#0253 3093 arch\arm64\boot\dts\exynos\exynos7.dtsi#0267 3094 arch\arm64\boot\dts\exynos\exynos7.dtsi#0274 3095 arch\arm64\boot\dts\exynos\exynos7.dtsi#0280 3096 arch\arm64\boot\dts\exynos\exynos7.dtsi#0286 3097 arch\arm64\boot\dts\exynos\exynos7.dtsi#0292 3098 arch\arm64\boot\dts\exynos\exynos7.dtsi#0298 3099 arch\arm64\boot\dts\exynos\exynos7.dtsi#0304 3100 arch\arm64\boot\dts\exynos\exynos7.dtsi#0310 3101 arch\arm64\boot\dts\exynos\exynos7.dtsi#0316 3102 arch\arm64\boot\dts\exynos\exynos7.dtsi#0322 3103 arch\arm64\boot\dts\exynos\exynos7.dtsi#0335 3104 arch\arm64\boot\dts\exynos\exynos7.dtsi#0348 3105 arch\arm64\boot\dts\exynos\exynos7.dtsi#0361 3106 arch\arm64\boot\dts\exynos\exynos7.dtsi#0374 3107 arch\arm64\boot\dts\exynos\exynos7.dtsi#0387 3108 arch\arm64\boot\dts\exynos\exynos7.dtsi#0400 3109 arch\arm64\boot\dts\exynos\exynos7.dtsi#0413 3110 arch\arm64\boot\dts\exynos\exynos7.dtsi#0426 3111 arch\arm64\boot\dts\exynos\exynos7.dtsi#0439 3112 arch\arm64\boot\dts\exynos\exynos7.dtsi#0452

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3113 arch\arm64\boot\dts\exynos\exynos7.dtsi#0465 3114 arch\arm64\boot\dts\exynos\exynos7.dtsi#0475 3115 arch\arm64\boot\dts\exynos\exynos7.dtsi#0512 3116 arch\arm64\boot\dts\exynos\exynos7.dtsi#0522 3117 arch\arm64\boot\dts\exynos\exynos7.dtsi#0531 3118 arch\arm64\boot\dts\exynos\exynos7.dtsi#0544 3119 arch\arm64\boot\dts\exynos\exynos7.dtsi#0557 3120 arch\arm64\boot\dts\exynos\exynos7.dtsi#0571 3121 arch\arm64\boot\dts\exynos\exynos7.dtsi#0591 3122 arch\arm64\boot\dts\exynos\Makefile#0001 Repo: 8ac46fc57df8 Chanwoo Thu Nov 3 15:39:09 2016 +0900 Description: arm64: dts: exynos: Add dts file for Exynos5433-based TM2E board ------This patch adds the Device Tree source for Exynos5433-based Samsung TM2E board. TM2E board is very similar to the TM2 board so the exynos5433-tm2e.dts includes the TM2 DTS and overrides the differences.

arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board ------This patch adds the Device Tree source for Exynos5433-based Samsung TM2 board.

This patch adds support for following devices: 1. basic SoC - Initial booting for Samsung Exynos5433 SoC - DRAM LPDDR3 (3GB) - eMMC (32GB) - ARM architecture timer

2. power management devices - Sasmung S2MPS13 PMIC for the power supply - CPUFREQ for big.LITTLE cores - TMU for big.LITTLE cores and GPU - ADC with thermistor to measure the temperature of AP/Battery/Charger - Maxim MAX77843 Interface PMIC (MUIC/Haptic/Regulator)

3. sound devices - I2S for sound bus - LPASS for sound power control - Wolfson WM5110 for sound codec - Maxim MAX98504 for speaker amplifier - TM2 ASoC Machine device driver node

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3. display devices - DECON, DSI and MIC for the panel output

4. USB devices - USB 3.0 DRD (Dual Role Device) - USB 3.0 Host controller

5. storage devices - MSHC (Mobile Storage Host Controller) for eMMC device

6. misc devices - gpio-keys (power, volume up/down, home key) - PWM (Pulse Width Modulation Timer)

3123 arch\arm64\boot\dts\exynos\exynos5433-pinctrl.dtsi#newFile Repo: cebef6be66f1 Marek Thu Nov 17 15:27:29 2016 +0100 Description: arm64: dts: exynos: Fix IRQ type flags for Exynos5433 SoC ------Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts. The GIC requires shared interrupts to be edge rising or level high. Platform declares support for both. Set all interrupts type to level high, as this works fine - tested on Exynos5433-based TM2 board.

3124 arch\arm64\boot\dts\exynos\exynos5433-tm2.dts#newFile Repo: 2a4c744fcb15 Jaehoon Wed Nov 23 16:43:34 2016 +0900 Description: arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ------TM2 can support the HS400 mode, but eMMC is working in the lowest mode. This patch adds the properties for HS400 and other modes.

3125 arch\arm64\boot\dts\exynos\exynos5433-tm2e.dts#newFile Repo: 8ac46fc57df8 Chanwoo Thu Nov 3 15:39:09 2016 +0900 Description: arm64: dts: exynos: Add dts file for Exynos5433-based TM2E board ------This patch adds the Device Tree source for Exynos5433-based Samsung TM2E board. TM2E board is very similar to the TM2 board so the exynos5433-tm2e.dts includes the TM2 DTS and overrides the differences.

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3126 arch\arm64\boot\dts\exynos\exynos5433-tmu-g3d-sensor-conf.dtsi#newFile Repo: 5f04c4cfcc92 Chanwoo Thu Nov 3 15:39:07 2016 +0900 Description: arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC ------This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). Exynos5433 supports PSCI (Power State Coordination Interface) v0.1.

This patch includes following Device Tree nodes to support Exynos5433 SoC: 1. Octa cores for big.LITTLE architecture - Cortex-A53 LITTLE Quad-core - Cortex-A57 big Quad-core - Supporting PSCI v0.1

2. Clock controller nodes - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - CMU_CPIF : clocks for LLI (Low Latency Interface) - CMU_MIF : clocks for DRAM Memory Controller - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA - CMU_G2D : clocks for G2D/MDMA - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses - CMU_G3D : clocks for 3D Graphics Engine - CMU_GSCL : clocks for GSCALER - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor. - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and L2 cache controller. - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs. - CMU_MFC : clocks for MFC (Multi-Format Codec) IP. - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP. - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs.

3. Pinctrl nodes for GPIO - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad

4. Timers - ARM architecture timer (armv8-timer) - MCT (Multi Core Timer) timer

5. Interrupt controller (GIC-400)

6. BUS devices - HS-I2C (High-Speed I2C) device

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- SPI (Serial Peripheral Interface) device

7. Sound devices - I2S bus - LPASS (Low Power Audio Subsystem)

8. Power management devices - CPUFREQ for for Cortex-A53/A57 - TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP

9. Display controller devices - DECON (Display and enhancement controller) for panel output - DSI (Display Serial Interface) - MIC (Mobile Image Compressor)

10. USB - USB 3.0 DRD (Dual Role Device) controller - USB 3.0 Host controller

11. Storage devices - MSHC (Mobile Storage Host Controller)

12. Misc devices - UART devices - ADC (Analog Digital Converter) - PWM (Pulse Width Modulation) - ADMA (Advanced DMA) and PDMA (Peripheral DMA)

3127 arch\arm64\boot\dts\exynos\exynos5433-tmu-sensor-conf.dtsi#newFile Repo: 5f04c4cfcc92 Chanwoo Thu Nov 3 15:39:07 2016 +0900 Description: arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC ------This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). Exynos5433 supports PSCI (Power State Coordination Interface) v0.1.

This patch includes following Device Tree nodes to support Exynos5433 SoC: 1. Octa cores for big.LITTLE architecture - Cortex-A53 LITTLE Quad-core - Cortex-A57 big Quad-core - Supporting PSCI v0.1

2. Clock controller nodes - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - CMU_CPIF : clocks for LLI (Low Latency Interface) - CMU_MIF : clocks for DRAM Memory Controller - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS

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- CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA - CMU_G2D : clocks for G2D/MDMA - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses - CMU_G3D : clocks for 3D Graphics Engine - CMU_GSCL : clocks for GSCALER - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor. - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and L2 cache controller. - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs. - CMU_MFC : clocks for MFC (Multi-Format Codec) IP. - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP. - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs.

3. Pinctrl nodes for GPIO - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad

4. Timers - ARM architecture timer (armv8-timer) - MCT (Multi Core Timer) timer

5. Interrupt controller (GIC-400)

6. BUS devices - HS-I2C (High-Speed I2C) device - SPI (Serial Peripheral Interface) device

7. Sound devices - I2S bus - LPASS (Low Power Audio Subsystem)

8. Power management devices - CPUFREQ for for Cortex-A53/A57 - TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP

9. Display controller devices - DECON (Display and enhancement controller) for panel output - DSI (Display Serial Interface) - MIC (Mobile Image Compressor)

10. USB - USB 3.0 DRD (Dual Role Device) controller - USB 3.0 Host controller

11. Storage devices - MSHC (Mobile Storage Host Controller)

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12. Misc devices - UART devices - ADC (Analog Digital Converter) - PWM (Pulse Width Modulation) - ADMA (Advanced DMA) and PDMA (Peripheral DMA)

3128 arch\arm64\boot\dts\exynos\exynos5433-tmu.dtsi#newFile Repo: 5f04c4cfcc92 Chanwoo Thu Nov 3 15:39:07 2016 +0900 Description: arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC ------This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). Exynos5433 supports PSCI (Power State Coordination Interface) v0.1.

This patch includes following Device Tree nodes to support Exynos5433 SoC: 1. Octa cores for big.LITTLE architecture - Cortex-A53 LITTLE Quad-core - Cortex-A57 big Quad-core - Supporting PSCI v0.1

2. Clock controller nodes - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - CMU_CPIF : clocks for LLI (Low Latency Interface) - CMU_MIF : clocks for DRAM Memory Controller - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA - CMU_G2D : clocks for G2D/MDMA - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses - CMU_G3D : clocks for 3D Graphics Engine - CMU_GSCL : clocks for GSCALER - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor. - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and L2 cache controller. - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs. - CMU_MFC : clocks for MFC (Multi-Format Codec) IP. - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP. - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs.

3. Pinctrl nodes for GPIO - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad

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4. Timers - ARM architecture timer (armv8-timer) - MCT (Multi Core Timer) timer

5. Interrupt controller (GIC-400)

6. BUS devices - HS-I2C (High-Speed I2C) device - SPI (Serial Peripheral Interface) device

7. Sound devices - I2S bus - LPASS (Low Power Audio Subsystem)

8. Power management devices - CPUFREQ for for Cortex-A53/A57 - TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP

9. Display controller devices - DECON (Display and enhancement controller) for panel output - DSI (Display Serial Interface) - MIC (Mobile Image Compressor)

10. USB - USB 3.0 DRD (Dual Role Device) controller - USB 3.0 Host controller

11. Storage devices - MSHC (Mobile Storage Host Controller)

12. Misc devices - UART devices - ADC (Analog Digital Converter) - PWM (Pulse Width Modulation) - ADMA (Advanced DMA) and PDMA (Peripheral DMA)

3129 arch\arm64\boot\dts\exynos\exynos5433.dtsi#newFile Repo: 64cbff449a8a Masahiro Wed Dec 28 00:51:26 2016 +0900 Description: ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus" part 3 ------Tree-wide replacement was done by commit 2ef7d5f342c1 ("ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"), then the 2nd round by commit 15b7cc78f095 ("arm64: dts: drop "arm,amba-bus" in favor of "simple-bus" part 2").

Here, some new users have appeared for Linux v4.10-rc1. Eliminate them now.

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Line Link NR. Descriptions arch\arm64\boot\dts\freescale\ 3130 arch\arm64\boot\dts\freescale\fsl-ls1043a-qds.dts#0048 Repo: 18486552b752 Hongtao Jia Sun Oct 9 14:47:05 2016 +0800 Description: arm64: dts: ls1043a: Add TMU device tree support for LS1043A ------Also add nodes and properties for thermal management support.

arm64: dts: add stdout-path to chosen node for ls2080a/ls1043a boards ------Add a default stdout-path to chosen node for ls2080a/ls1043a boards to allow booting kernels without specifying console info in bootargs.

3131 arch\arm64\boot\dts\freescale\fsl-ls1043a-rdb.dts#0048 Repo: 18486552b752 Hongtao Jia Sun Oct 9 14:47:05 2016 +0800 Description: arm64: dts: ls1043a: Add TMU device tree support for LS1043A ------Also add nodes and properties for thermal management support.

arm64: dts: add stdout-path to chosen node for ls2080a/ls1043a boards ------Add a default stdout-path to chosen node for ls2080a/ls1043a boards to allow booting kernels without specifying console info in bootargs.

3132 arch\arm64\boot\dts\freescale\fsl-ls1043a.dtsi#0047 Repo: 22381d08c7eb Olof Fri Nov 18 10:32:14 2016 -0800 Description: Merge tag 'imx-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64 ------Freescale arm64 device tree updates for 4.10: - Enable Thermal Monitoring Unit (TMU) for thermal management on LS1043A and LS2080A. - Add support for LS1046A SoC, which has similar peripherals as LS1043A but integrates 4 A72 cores. - Add two LS1046A based board support: LS1046A-QDS and LS1046A-RDB.

* tag 'imx-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: ls2080a: Add TMU device tree support for LS2080A arm64: dts: ls1043a: Add TMU device tree support for LS1043A arm64: dts: add LS1046A-QDS board support Documentation: DT: Add entry for QorIQ LS1046A-QDS board arm64: dts: add LS1046A-RDB board support Documentation: DT: Add entry for QorIQ LS1046A-RDB board

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arm64: dts: add QorIQ LS1046A SoC support dt-bindings: ahci-fsl-qoriq: updated for SoC ls1046a dt-bindings: qoriq-clock: add LS1043A/LS1046A/LS2080A compatible for clockgen dt-bindings: i2c: adds two more nxp devices dt-bindings: fsl: add LS1043A/LS1046A/LS2080A compatible for SCFG and DCFG dt-bindings: fsl: Add LS1043A/LS1046A/LS2080A SoC compatible strings

arm64: dts: ls1043a: Add TMU device tree support for LS1043A ------Also add nodes and properties for thermal management support.

arm64: dts: Add timer erratum property for LS2080A and LS1043A ------Both the LS1043A and LS2080A platforms are affected by the Freescale A008585 erratum. Advertise it in their respective device trees.

3133 arch\arm64\boot\dts\freescale\fsl-ls1043a.dtsi#0071 3134 arch\arm64\boot\dts\freescale\fsl-ls1043a.dtsi#0261 3135 arch\arm64\boot\dts\freescale\fsl-ls2080a-qds.dts#0049 Repo: 236f794e4463 Hongtao Jia Sun Oct 9 14:47:06 2016 +0800 Description: arm64: dts: ls2080a: Add TMU device tree support for LS2080A ------Also add nodes and properties for thermal management support.

3136 arch\arm64\boot\dts\freescale\fsl-ls2080a-rdb.dts#0049 Repo: 236f794e4463 Hongtao Jia Sun Oct 9 14:47:06 2016 +0800 Description: arm64: dts: ls2080a: Add TMU device tree support for LS2080A ------Also add nodes and properties for thermal management support.

3137 arch\arm64\boot\dts\freescale\fsl-ls2080a-simu.dts#0049 Repo: 236f794e4463 Hongtao Jia Sun Oct 9 14:47:06 2016 +0800 Description: arm64: dts: ls2080a: Add TMU device tree support for LS2080A ------Also add nodes and properties for thermal management support.

dts/ls2080a: Update Simulator DTS to add support of various peripherals ------This patch updates the LS2080a simulator DTS to add support of various

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peripherals which are supported on the simulator platform and explicitly disables those which are yet not supported on the platform.

dts/ls2080a: Remove text about writing to Free Software Foundation ------Checkpatch complains about the text suggesting writing to Free Software Foundation for GPLv2 license copy.

This patch removes the same from the .dtsi and .dts

3138 arch\arm64\boot\dts\freescale\fsl-ls2080a.dtsi#0047 Repo: 482c3e8835e9 Linus Thu Dec 15 15:58:28 2016 -0800 Description: Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources:

- Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line - Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips

Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time:

- Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board

For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom,

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Rockchip, Berlin, and ZTE"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits) arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...

ARM64: dts: ls2080a: add device configuration node ------Add the dts node for device configuration unit that provides general purpose configuration and status for the device.

Merge tag 'imx-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64 ------Freescale arm64 device tree updates for 4.10: - Enable Thermal Monitoring Unit (TMU) for thermal management on LS1043A and LS2080A. - Add support for LS1046A SoC, which has similar peripherals as LS1043A but integrates 4 A72 cores. - Add two LS1046A based board support: LS1046A-QDS and LS1046A-RDB.

* tag 'imx-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: ls2080a: Add TMU device tree support for LS2080A arm64: dts: ls1043a: Add TMU device tree support for LS1043A arm64: dts: add LS1046A-QDS board support Documentation: DT: Add entry for QorIQ LS1046A-QDS board arm64: dts: add LS1046A-RDB board support Documentation: DT: Add entry for QorIQ LS1046A-RDB board

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arm64: dts: add QorIQ LS1046A SoC support dt-bindings: ahci-fsl-qoriq: updated for SoC ls1046a dt-bindings: qoriq-clock: add LS1043A/LS1046A/LS2080A compatible for clockgen dt-bindings: i2c: adds two more nxp devices dt-bindings: fsl: add LS1043A/LS1046A/LS2080A compatible for SCFG and DCFG dt-bindings: fsl: Add LS1043A/LS1046A/LS2080A SoC compatible strings

arm64: dts: ls2080a: Add TMU device tree support for LS2080A ------Also add nodes and properties for thermal management support.

arm64: dts: Add timer erratum property for LS2080A and LS1043A ------Both the LS1043A and LS2080A platforms are affected by the Freescale A008585 erratum. Advertise it in their respective device trees.

3139 arch\arm64\boot\dts\freescale\fsl-ls2080a.dtsi#0067 3140 arch\arm64\boot\dts\freescale\fsl-ls2080a.dtsi#0073 3141 arch\arm64\boot\dts\freescale\fsl-ls2080a.dtsi#0076 3142 arch\arm64\boot\dts\freescale\fsl-ls2080a.dtsi#0084 3143 arch\arm64\boot\dts\freescale\fsl-ls2080a.dtsi#0090 3144 arch\arm64\boot\dts\freescale\fsl-ls2080a.dtsi#0093 3145 arch\arm64\boot\dts\freescale\fsl-ls2080a.dtsi#0101 3146 arch\arm64\boot\dts\freescale\fsl-ls2080a.dtsi#0107 3147 arch\arm64\boot\dts\freescale\fsl-ls2080a.dtsi#0110 3148 arch\arm64\boot\dts\freescale\fsl-ls2080a.dtsi#0118 3149 arch\arm64\boot\dts\freescale\fsl-ls2080a.dtsi#0124 3150 arch\arm64\boot\dts\freescale\fsl-ls2080a.dtsi#0127 3151 arch\arm64\boot\dts\freescale\fsl-ls2080a.dtsi#0225 3152 arch\arm64\boot\dts\freescale\Makefile#0003 Repo: b20ca2af125a Shaohui Xie Tue Sep 13 16:10:03 2016 +0800 Description: arm64: dts: add LS1046A-QDS board support ------The LS1046A QorIQ development system (QDS) board is a high-performance computing, evaluation, development, and test platform supporting the LS1046A SoC.

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arm64: dts: add LS1046A-RDB board support ------The LS1046A reference design board (RDB) is a high-performance computing, evaluation, and development platform that supports the LS1046A SoC.

3153 arch\arm64\boot\dts\freescale\fsl-ls1046a-qds.dts#newFile Repo: b20ca2af125a Shaohui Xie Tue Sep 13 16:10:03 2016 +0800 Description: arm64: dts: add LS1046A-QDS board support ------The LS1046A QorIQ development system (QDS) board is a high-performance computing, evaluation, development, and test platform supporting the LS1046A SoC.

3154 arch\arm64\boot\dts\freescale\fsl-ls1046a-rdb.dts#newFile Repo: 796b436034fb Mingkai Hu Tue Sep 13 16:10:01 2016 +0800 Description: arm64: dts: add LS1046A-RDB board support ------The LS1046A reference design board (RDB) is a high-performance computing, evaluation, and development platform that supports the LS1046A SoC.

3155 arch\arm64\boot\dts\freescale\fsl-ls1046a.dtsi#newFile Repo: 8126d88162a5 Mingkai Hu Tue Sep 13 16:09:59 2016 +0800 Description: arm64: dts: add QorIQ LS1046A SoC support ------LS1046A is an SoC with 4 ARMv8 A72 cores and most other IP blocks are similar to LS1043A which also complies to Freescale Chassis 2.1 spec.

Created LS1046A SoC DTSI file to be included by board level DTS files.

arch\arm64\boot\dts\hisilicon\ 3156 arch\arm64\boot\dts\hisilicon\hi6220.dtsi#0367 Repo: 786a72d79140 Linus Thu Dec 15 15:50:24 2016 -0800 Description: Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

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We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

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- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

usb: dwc2: Deprecate g-use-dma binding ------This is not needed as the gadget now fully supports DMA and it can autodetect it. This was initially added because gadget DMA mode was only partially implemented so could not be automatically enabled.

ARM: dts: Add #pinctrl-cells for pinctrl-single instances ------Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the driver changes as the driver supports also the legacy binding without #pinctrl-cells.

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3157 arch\arm64\boot\dts\hisilicon\hi6220.dtsi#0406 3158 arch\arm64\boot\dts\hisilicon\hi6220.dtsi#0415 3159 arch\arm64\boot\dts\hisilicon\hi6220.dtsi#0753 3160 arch\arm64\boot\dts\hisilicon\hip06-d03.dts#0044 Repo: 84ad1f54095b John Garry Tue Nov 8 00:44:24 2016 +0800 Description: arm64: dts: hisi: disable sas0 and sas2 for d03 ------The SAS nodes sas0 and sas2 are not available on d03, so disable them.

arm64: dts: hip06: Append sas node ------This patch adds sas and relevant nodes for Hip06 D03 board.

3161 arch\arm64\boot\dts\hisilicon\hip06-d03.dts#0052 3162 arch\arm64\boot\dts\hisilicon\hip06.dtsi#0321 Repo: 85f5bd9e7713 John Garry Tue Nov 8 00:44:25 2016 +0800 Description: arm64: dts: hisi: add refclk node to hip06 dts files for SAS ------We will only maintain 1 dts for D03 and there are 50MHz and 66MHz versions of D03: so we expect UEFI to update refclk rate in the fdt at boot time.

arm64: dts: hisi: fix hip06 sas am-max-trans quirk ------The string for the am max transmissions quirk property is not correct -> fix it.

arm64: dts: hip06: Fix no reg property warning ------Warning (unit_address_vs_reg): Node /soc/ethernet@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/ethernet@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/ethernet@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/ethernet@1 has a unit name, but no reg property

Fix warning when build with W=1.

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arm64: dts: hip06: Correct hardware pin number of usb node ------The ohci/ehci hardware pin number should be 640/641, correct them.

Fixes: commit aa8d3e74f54d ("arm64: dts: Add initial dts for Hisilicon Hip06 D03 board")

arm64: dts: hip06: Append sas node ------This patch adds sas and relevant nodes for Hip06 D03 board.

3163 arch\arm64\boot\dts\hisilicon\hip06.dtsi#0331 3164 arch\arm64\boot\dts\hisilicon\hip06.dtsi#0340 3165 arch\arm64\boot\dts\hisilicon\hip06.dtsi#0517 3166 arch\arm64\boot\dts\hisilicon\hip06.dtsi#0526 3167 arch\arm64\boot\dts\hisilicon\hip06.dtsi#0535 3168 arch\arm64\boot\dts\hisilicon\hip06.dtsi#0544 3169 arch\arm64\boot\dts\hisilicon\hip06.dtsi#0561 3170 arch\arm64\boot\dts\hisilicon\hip06.dtsi#0600 3171 arch\arm64\boot\dts\hisilicon\hip06.dtsi#0604 3172 arch\arm64\boot\dts\hisilicon\hip06.dtsi#0646 3173 arch\arm64\boot\dts\hisilicon\Makefile#0004 Repo: 4f357f94e13d Kefeng Sat Sep 24 17:14:23 2016 +0800 Description: arm64: dts: hisilicon: Add initial dts for Hip07 D05 board ------Adding initial dt file for Hip07 D05 board, it is with dual socket and each socket has two SCCLs(supper cpu cluster), one SCCL contains four clusters and each cluster has quard Cortex-A72.

Since each SCCL has their own DDR controller, it could be treated as a separate numa node. Thus, there are four numa nodes(one node with sixteen core) on Hip07 SoC.

3174 arch\arm64\boot\dts\hisilicon\hip07-d05.dts#newFile Repo: 4f357f94e13d Kefeng Sat Sep 24 17:14:23 2016 +0800 Description: arm64: dts: hisilicon: Add initial dts for Hip07 D05 board ------Adding initial dt file for Hip07 D05 board, it is with dual socket and each socket has two SCCLs(supper cpu cluster), one SCCL contains four clusters and each cluster has quard Cortex-A72.

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Since each SCCL has their own DDR controller, it could be treated as a separate numa node. Thus, there are four numa nodes(one node with sixteen core) on Hip07 SoC.

3175 arch\arm64\boot\dts\hisilicon\hip07.dtsi#newFile Repo: 4f357f94e13d Kefeng Sat Sep 24 17:14:23 2016 +0800 Description: arm64: dts: hisilicon: Add initial dts for Hip07 D05 board ------Adding initial dt file for Hip07 D05 board, it is with dual socket and each socket has two SCCLs(supper cpu cluster), one SCCL contains four clusters and each cluster has quard Cortex-A72.

Since each SCCL has their own DDR controller, it could be treated as a separate numa node. Thus, there are four numa nodes(one node with sixteen core) on Hip07 SoC.

arch\arm64\boot\dts\marvell\ 3176 arch\arm64\boot\dts\marvell\armada-3720-db.dts#0059 Repo: 482c3e8835e9 Linus Thu Dec 15 15:58:28 2016 -0800 Description: Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources:

- Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line - Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips

Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time:

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- Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board

For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits) arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...

ARM64: dts: marvell: Add network support for Armada 3700 ------Add neta nodes for network support both in device tree for the SoC and the board.

ARM64: dts: marvell: Fixup memory DT warning for Armada 37xx ------memory has a reg property so the unit name should contain an address.

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3177 arch\arm64\boot\dts\marvell\armada-3720-db.dts#0084 3178 arch\arm64\boot\dts\marvell\armada-37xx.dtsi#0094 Repo: 482c3e8835e9 Linus Thu Dec 15 15:58:28 2016 -0800 Description: Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources:

- Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line - Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips

Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time:

- Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board

For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits) arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node

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arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...

ARM64: dts: marvell: Add network support for Armada 3700 ------Add neta nodes for network support both in device tree for the SoC and the board.

arm64: dts: marvell: Fixup internal-regs DT warning for Armada 37xx ------internal-regs has a ranges property so the unit name should contain an address.

3179 arch\arm64\boot\dts\marvell\armada-37xx.dtsi#0143 3180 arch\arm64\boot\dts\marvell\armada-ap806.dtsi#0074 Repo: 70347888dca1 Gregory Mon Nov 7 15:02:06 2016 +0100 Description: arm64: dts: marvell: Fixup config-space DT warning For Armada 7K/8K ------config-space has a ranges property so the unit name should contain an address.

3181 arch\arm64\boot\dts\marvell\armada-cp110-master.dtsi#0055 Repo: 482c3e8835e9 Linus Thu Dec 15 15:58:28 2016 -0800 Description: Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources:

- Samsung Exynos5433 mobile phone platform, including an (almost)

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fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line - Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips

Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time:

- Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board

For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits) arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310

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arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...

Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 ------Pull crypto updates from Herbert Xu: "Here is the crypto update for 4.10:

API: - add skcipher walk interface - add asynchronous compression (acomp) interface - fix algif_aed AIO handling of zero buffer

Algorithms: - fix unaligned access in poly1305 - fix DRBG output to large buffers

Drivers: - add support for iMX6UL to caam - fix givenc descriptors (used by IPsec) in caam - accelerated SHA256/SHA512 for ARM64 from OpenSSL - add SSE CRCT10DIF and CRC32 to ARM/ARM64 - add AEAD support to Chelsio chcr - add Armada 8K support to omap-rng"

* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (148 commits) crypto: testmgr - fix overlap in chunked tests again crypto: arm/crc32 - accelerated support based on x86 SSE implementation crypto: arm64/crc32 - accelerated support based on x86 SSE implementation crypto: arm/crct10dif - port x86 SSE implementation to ARM crypto: arm64/crct10dif - port x86 SSE implementation to arm64 crypto: testmgr - add/enhance test cases for CRC-T10DIF crypto: testmgr - avoid overlap in chunked tests crypto: chcr - checking for IS_ERR() instead of NULL crypto: caam - check caam_emi_slow instead of re-lookup platform crypto: algif_aead - fix AIO handling of zero buffer crypto: aes-ce - Make aes_simd_algs static crypto: algif_skcipher - set error code when kcalloc fails crypto: caam - make aamalg_desc a proper module crypto: caam - pass key buffers with typesafe pointers crypto: arm64/aes-ce-ccm - Fix AEAD decryption length MAINTAINERS: add crypto headers to crypto entry crypt: doc - remove misleading mention of async API crypto: doc - fix header file name crypto: api - fix comment typo crypto: skcipher - Add separate walker for AEAD decryption ..

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Merge tag 'mvebu-dt64-4.10-2' of git://git.infradead.org/linux-mvebu into next/dt64 ------Pull "mvebu dt64 for 4.10 (part 2)" from Gregory CLEMENT:

Fix DTC warning on Armada 37xx and 7K/8K

* tag 'mvebu-dt64-4.10-2' of git://git.infradead.org/linux-mvebu: ARM64: dts: marvell: Fixup memory DT warning for Armada 37xx arm64: dts: marvell: Fixup config-space DT warning For Armada 7K/8K arm64: dts: marvell: Fixup internal-regs DT warning for Armada 37xx

arm64: dts: marvell: Fixup config-space DT warning For Armada 7K/8K ------config-space has a ranges property so the unit name should contain an address.

arm64: dts: marvell: add TRNG description for Armada 8K CP ------This commits adds the devicetree description of the SafeXcel IP-76 TRNG found in the two Armada CP110.

3182 arch\arm64\boot\dts\marvell\armada-cp110-master.dtsi#0167 3183 arch\arm64\boot\dts\marvell\armada-cp110-slave.dtsi#0055 Repo: 482c3e8835e9 Linus Thu Dec 15 15:58:28 2016 -0800 Description: Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources:

- Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line

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- Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips

Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time:

- Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board

For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits) arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...

Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 ------Pull crypto updates from Herbert Xu: "Here is the crypto update for 4.10:

API: - add skcipher walk interface - add asynchronous compression (acomp) interface

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- fix algif_aed AIO handling of zero buffer

Algorithms: - fix unaligned access in poly1305 - fix DRBG output to large buffers

Drivers: - add support for iMX6UL to caam - fix givenc descriptors (used by IPsec) in caam - accelerated SHA256/SHA512 for ARM64 from OpenSSL - add SSE CRCT10DIF and CRC32 to ARM/ARM64 - add AEAD support to Chelsio chcr - add Armada 8K support to omap-rng"

* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (148 commits) crypto: testmgr - fix overlap in chunked tests again crypto: arm/crc32 - accelerated support based on x86 SSE implementation crypto: arm64/crc32 - accelerated support based on x86 SSE implementation crypto: arm/crct10dif - port x86 SSE implementation to ARM crypto: arm64/crct10dif - port x86 SSE implementation to arm64 crypto: testmgr - add/enhance test cases for CRC-T10DIF crypto: testmgr - avoid overlap in chunked tests crypto: chcr - checking for IS_ERR() instead of NULL crypto: caam - check caam_emi_slow instead of re-lookup platform crypto: algif_aead - fix AIO handling of zero buffer crypto: aes-ce - Make aes_simd_algs static crypto: algif_skcipher - set error code when kcalloc fails crypto: caam - make aamalg_desc a proper module crypto: caam - pass key buffers with typesafe pointers crypto: arm64/aes-ce-ccm - Fix AEAD decryption length MAINTAINERS: add crypto headers to crypto entry crypt: doc - remove misleading mention of async API crypto: doc - fix header file name crypto: api - fix comment typo crypto: skcipher - Add separate walker for AEAD decryption ..

arm64: dts: marvell: Fixup config-space DT warning For Armada 7K/8K ------config-space has a ranges property so the unit name should contain an address.

arm64: dts: marvell: add unique identifiers for Armada A8k SPI controllers ------Enabling SPI controllers, which are attached to different busses inside an SoC, may result in overlapping enumeration and cause sysfs registration failure. Example log after enabling two controllers on Armada 8040 SoC with same identifiers:

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[ 3.740415] sysfs: cannot create duplicate filename '/class/spi_master/spi0' [ 3.747510] ------[ cut here ]------[ 3.752145] WARNING: at fs/sysfs/dir.c:31 [...] [ 4.002299] orion_spi: probe of f4700600.spi failed with error -17

spi-orion driver offers dedicated DT property ('cell-index'), that allow setting unique identifiers. Recently added support for CP110-slave HW block introduced two new SPI controllers' nodes with same ID as ones from CP110-master.

This commit fixes the issue by assigning different 'cell-index' values for CP110-slave SPI controllers.

Fixes: 4eef78a0091b ("arm64: dts: marvell: add description for the slave CP110 in Armada 8K")

3184 arch\arm64\boot\dts\marvell\armada-cp110-slave.dtsi#0167 3185 arch\arm64\boot\dts\marvell\berlin4ct-dmp.dts#0057 Repo: 40fdc6b0d2b9 Jisheng Tue Sep 6 16:51:23 2016 +0800 Description: arm64: dts: berlin4ct-dmp: add missing unit name to /memory node ------This patch fixes the following DTC warning with W=1:

"Node /memory has a reg or ranges property, but no unit name"

3186 arch\arm64\boot\dts\marvell\berlin4ct-stb.dts#0057 Repo: c71aa0e20020 Jisheng Tue Sep 6 16:49:17 2016 +0800 Description: arm64: dts: berlin4ct-stb: add missing unit name to /memory node ------This patch fixes the following DTC warning with W=1:

"Node /memory has a reg or ranges property, but no unit name"

3187 arch\arm64\boot\dts\marvell\berlin4ct.dtsi#0145 Repo: 47d56462fce4 Jisheng Tue Sep 6 16:44:59 2016 +0800 Description: arm64: dts: berlin4ct: add missing unit name to /soc node ------This patch fixes the following DTC warning with W=1:

"Node /soc has a reg or ranges property, but no unit name"

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arm64: dts: berlin4ct: Add L2 cache topology ------This patch adds the L2 cache topology for berlin4ct which has 1MB L2 cache.

[Sebastian: rename cache node from "l2-cache" to "cache"]

arm64: dts: berlin4ct: enable all wdt nodes unconditionally ------After commit f29a72c24ad4 ("watchdog: dw_wdt: Convert to use watchdog infrastructure"), the dw_wdt driver can support multiple variants, so unconditionally enable all dw_wdt nodes now.

3188 arch\arm64\boot\dts\marvell\Makefile#0007 Repo: e735aaf8fc4a Romain Thu Oct 6 11:14:29 2016 +0200 Description: arm64: dts: marvell: Add definition for the Globalscale Marvell ESPRESSOBin Board ------This is a high performance 64 bit dual core low power consuming networking computing platform based on the ARMv8 architecture. It contains an Armada 3720 running up to 1.2Ghz.

This commit adds a basic definition for this board.

3189 arch\arm64\boot\dts\marvell\armada-3720-espressobin.dts#newFile Repo: 3684534548d4 Gregory Mon Nov 7 15:03:51 2016 +0100 Description: ARM64: dts: marvell: Fixup memory DT warning for Armada 37xx ------memory has a reg property so the unit name should contain an address.

arch\arm64\boot\dts\mediatek\ 3190 arch\arm64\boot\dts\mediatek\mt8173-evb.dts#0037 Repo: c0891284a74a Chunfeng Wed Oct 19 10:28:27 2016 +0800 Description: arm64: dts: mediatek: add USB3 DRD driver ------USB3 DRD driver is added for MT8173-EVB, and xHCI driver becomes its subnode

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3191 arch\arm64\boot\dts\mediatek\mt8173-evb.dts#0057 3192 arch\arm64\boot\dts\mediatek\mt8173-evb.dts#0260 3193 arch\arm64\boot\dts\mediatek\mt8173-evb.dts#0500 3194 arch\arm64\boot\dts\mediatek\mt8173-evb.dts#0517 3195 arch\arm64\boot\dts\mediatek\mt8173-evb.dts#0520 3196 arch\arm64\boot\dts\mediatek\mt8173.dtsi#0044 Repo: bd9999cd6a5e Linus Fri Dec 16 09:39:16 2016 -0800 Description: Merge tag 'media/v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux- media ------Pull media updates from Mauro Carvalho Chehab:

- new Mediatek drivers: mtk-mdp and mtk-vcodec

- some additions at the media documentation

- the CEC core and drivers were promoted from staging to mainstream

- some cleanups at the DVB core

- the LIRC serial driver got promoted from staging to mainstream

- added a driver for Renesas R-Car FDP1 driver

- add DVBv5 statistics support to mn88473 driver

- several fixes related to printk continuation lines

- add support for HSV encoding formats

- lots of other cleanups, fixups and driver improvements.

* tag 'media/v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (496 commits) [media] v4l: tvp5150: Add missing break in set control handler [media] v4l: tvp5150: Don't inline the tvp5150_selmux() function [media] v4l: tvp5150: Compile tvp5150_link_setup out if !CONFIG_MEDIA_CONTROLLER [media] em28xx: don't store usb_device at struct em28xx [media] em28xx: use usb_interface for dev_foo() calls [media] em28xx: don't change the device's name [media] mn88472: fix chip id check on probe [media] mn88473: fix chip id check on probe [media] lirc: fix error paths in lirc_cdev_add() [media] s5p-mfc: Add support for MFC v8 available in Exynos 5433 SoCs [media] s5p-mfc: Rework clock handling

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[media] s5p-mfc: Don't keep clock prepared all the time [media] s5p-mfc: Kill all IS_ERR_OR_NULL in clocks management code [media] s5p-mfc: Remove dead conditional code [media] s5p-mfc: Ensure that clock is disabled before turning power off [media] s5p-mfc: Remove special clock rate management [media] s5p-mfc: Use printk_ratelimited for reporting ioctl errors [media] s5p-mfc: Set DMA_ATTR_ALLOC_SINGLE_PAGES [media] vivid: Set color_enc on HSV formats [media] v4l2-tpg: Init hv_enc field with a valid value ...

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together.

We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board:

- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors

These are commercially available consumer platforms we now support:

- Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385

And a couple of new boards targeted at developers, makers or industrial integration:

- Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms

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- TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module

Other changes:

- added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq

- Continued fixes for W=1 dtc warnings

- The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST

- The exynos4415 dtsi file is removed as nothing uses it.

- Intel PXA25x can now be booted using devicetree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...

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arm64: dts: mt8173: Fix auxadc node ------The devicetree node for mt8173-auxadc lacks the clock and io-channel-cells property. This leads to a non-working driver.

mt6577-auxadc 11001000.auxadc: failed to get auxadc clock mt6577-auxadc: probe of 11001000.auxadc failed with error -2

Fix these fields to get the device up and running.

Fixes: 748c7d4de46a ("ARM64: dts: mt8173: Add thermal/auxadc device nodes")

arm64: dts: mediatek: add USB3 DRD driver ------USB3 DRD driver is added for MT8173-EVB, and xHCI driver becomes its subnode

[media] arm64: dts: mediatek: Add MDP for MT8173 ------Add MDP node for MT8173

[media] arm64: dts: mediatek: Add Video Decoder for MT8173 ------Add video decoder node for MT8173

3197 arch\arm64\boot\dts\mediatek\mt8173.dtsi#0461 3198 arch\arm64\boot\dts\mediatek\mt8173.dtsi#0721 3199 arch\arm64\boot\dts\mediatek\mt8173.dtsi#0725 3200 arch\arm64\boot\dts\mediatek\mt8173.dtsi#0736 3201 arch\arm64\boot\dts\mediatek\mt8173.dtsi#0737 3202 arch\arm64\boot\dts\mediatek\mt8173.dtsi#0784 3203 arch\arm64\boot\dts\mediatek\mt8173.dtsi#1156 arch\arm64\boot\dts\nvidia\ 3204 arch\arm64\boot\dts\nvidia\Makefile#0006 Repo: 99575bceebd6 Joseph Lo Tue Jul 5 17:04:31 2016 +0800 Description: arm64: tegra: Add NVIDIA P2771 board support ------The NVIDIA P2771 is composed of a P3310 processor module that connects

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to the P2597 I/O board. It comes with a 1200x1920 MIPI DSI panel that is connected via the P2597's display connector and has several connectors such as HDMI, USB 3.0, PCIe and ethernet.

3205 arch\arm64\boot\dts\nvidia\tegra210-p2180.dtsi#0024 Repo: 5e6b9a89afce Alexandre Fri Dec 2 20:57:55 2016 +0100 Description: arm64: tegra: Add VDD_GPU regulator to Jetson TX1 ------Add the VDD_GPU regulator (a GPIO-enabled PWM regulator) to the Jetson TX1 board. This addition allows the GPU to be used provided the bootloader properly enabled the GPU node.

arm64: tegra: Enable debug serial on Jetson TX1 ------Add a chosen node to the device tree that contains a stdout-path property which defines the debug serial port.

3206 arch\arm64\boot\dts\nvidia\tegra210-p2180.dtsi#0298 3207 arch\arm64\boot\dts\nvidia\tegra210-p2371-2180.dts#0010 Repo: af099eab35c3 Thierry Fri Nov 25 11:57:18 2016 +0100 Description: arm64: tegra: Enable PCIe on Jetson TX1 ------Enable the x4 PCIe and M.2 Key E slots on Jetson TX1. The Key E slot is currently untested due to lack of hardware.

arm64: tegra: Add DSI panel on Jetson TX1 ------Some variants of the Jetson TX1 ship with a 8.0" WUXGA TFT LCD panel connected via four DSI lanes.

3208 arch\arm64\boot\dts\nvidia\tegra210-smaug.dts#0014 Repo: 816c60c131d9 Alexandre Fri Dec 2 20:57:56 2016 +0100 Description: arm64: tegra: Add missing Smaug revision ------The "google,smaug-rev2" string is missing from the compatible list of Smaug's DT. The differences of rev2 are not relevant at our current level of support and it boots just fine, so add it.

arm64: tegra: Enable XUSB controller on Tegra210 Smaug ------

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Enable the XUSB controller on Tegra210 Smaug. The Smaug has a USB Type-C connector with one of the USB2.0 lanes and one of the USB3.0 lanes populated.

arm64: tegra: Add the various audio devices for Tegra210 Smaug ------The Tegra210 Smaug includes the Realtek RT5677 audio codec, Nuvoton NAU8825 headset codec and the Maxim MAX98357a audio amplifier. Add the nodes for these devices for the Tegra210 Smaug.

arm64: tegra: Enable DPAUX for Tegra210 Smaug ------The Tegra210 Smaug uses I2C6 for interfacing to various audio chips. I2C6 shares pads with the DPAUX interface and to allow I2C6 to request the pads owned by DPAUX, the DPAUX device needs to be enabled. Enable DPAUX for Tegra210 Smaug.

3209 arch\arm64\boot\dts\nvidia\tegra210.dtsi#0014 Repo: 589a2d3f18be Thierry Fri Nov 25 11:57:17 2016 +0100 Description: arm64: tegra: Add PCIe host bridge on Tegra210 ------Add the PCIe host bridge found on Tegra X1. It implements two root ports that support x4 and x1 configurations, respectively.

3210 arch\arm64\boot\dts\nvidia\tegra186-p2771-0000.dts#newFile Repo: 99575bceebd6 Joseph Lo Tue Jul 5 17:04:31 2016 +0800 Description: arm64: tegra: Add NVIDIA P2771 board support ------The NVIDIA P2771 is composed of a P3310 processor module that connects to the P2597 I/O board. It comes with a 1200x1920 MIPI DSI panel that is connected via the P2597's display connector and has several connectors such as HDMI, USB 3.0, PCIe and ethernet.

3211 arch\arm64\boot\dts\nvidia\tegra186-p3310.dtsi#newFile Repo: 0dfde1332509 Thierry Thu Nov 17 17:36:56 2016 +0100 Description: arm64: tegra: Enable PSCI on P3310 ------The P3310 processor module comes ships with a firmware that implements PSCI 1.0. Enable and use it to bring up all CPUs.

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3212 arch\arm64\boot\dts\nvidia\tegra186.dtsi#newFile Repo: fc4bb754c81c Thierry Fri Aug 19 16:31:53 2016 +0200 Description: arm64: tegra: Add GPIO controllers on Tegra186 ------Tegra186 has two GPIO controllers that are no longer compatible with the controller found on earlier generations. One of these controllers exists in an always-on partition of the SoC whereas the other can be clock- and powergated.

arm64: tegra: Add SDHCI controllers on Tegra186 ------Tegra186 has a total of four SDHCI controllers that each support SD 4.2 (up to UHS-I speed), SDIO 4.1 (up to UHS-I speed), eSD 2.1, eMMC 5.1 and SDHOST 4.1 (up to UHS-I speed).

arm64: tegra: Add I2C controllers on Tegra186 ------Tegra186 has a total of nine I2C controllers that are compatible with the I2C controllers introduced in Tegra114. Two of these controllers share pads with two DPAUX controllers (for AUX transactions).

arm64: tegra: Add serial ports on Tegra186 ------The initial patch only added UARTA, but there's no reason we shouldn't be adding all of them. While at it, also specify the missing clocks and resets for UARTA.

arm64: tegra: Add CPU nodes for Tegra186 ------Tegra186 has six CPUs: two CPUs are second generation Denver CPUs that support ARMv8 and four CPUs are Cortex-A57 CPUs.

arch\arm64\boot\dts\qcom\ 3213 arch\arm64\boot\dts\qcom\apq8016-sbc.dtsi#0018 Repo: 5582fcb3829f Srinivas Thu Oct 20 15:20:49 2016 +0100 Description: arm64: dts: apq8016-sbc: add analog audio support with multicodec ------This patch add support to Analog audio both Playback and Capture via msm8916 WCD muti codec.

arm64: dts: apq8016-sbc: Set up LDO2, LDO6 and LDO17 regulator voltage ranges

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------On the APQ8016 SBC, the LDO2 PM8916 regulator feeds 1.2V to the following:

- VDDA_1P2_MIPI_DSI and VDDA_MIPI_CSI pins on APQ8016. - VCCCAD pins on the LPDDR3 chip. - VDDPX_1 pins on APQ8016.

The LDO6 regulator feeds 1.8V to: - VDAA_MIPI_DSI0_PLL pin on APQ8016. - QFPROM_BLOW_VDD pin on PM8916. - The AVDD, A2VDD and DVDD pins on ADV7533 bridge.

The LDO17 regulator feeds 3.3V to: - The V3P3 pin on ADV7533 bridge.

Currently, the regulator min/max voltages for all the LDOs are set to the range of what the PMIC supports. Set the ranges for L2, L6 and L17 to what we need, i.e. 1.2V, 1.8V and 3.3V respectively.

3214 arch\arm64\boot\dts\qcom\apq8016-sbc.dtsi#0255 3215 arch\arm64\boot\dts\qcom\apq8016-sbc.dtsi#0336 3216 arch\arm64\boot\dts\qcom\apq8016-sbc.dtsi#0372 3217 arch\arm64\boot\dts\qcom\apq8016-sbc.dtsi#0392 3218 arch\arm64\boot\dts\qcom\apq8016-sbc.dtsi#0452 3219 arch\arm64\boot\dts\qcom\apq8096-db820c.dtsi#0015 Repo: 50784e61032d Srinivas Fri Sep 16 18:41:21 2016 +0100 Description: dts: arm64: db820c: add pmic pins specific dts file ------This patch adds pmic specific dts which are configured specially for db820c. One of such pin is GPIO_F on the Low Speed expansion which has default output voltage of 2.7v. This patch fixes setup for that pin to have an output voltage of 1.8v to comply with 96boards LS expansion specs.

arm64: dts: db820c: add support to external sd card. ------This patch adds support to external sd card.

arm64: dts: db820c: add support to SPI on HS ------This patch adds support to SPI on HS expansion connector.

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arm64: dts: db820c: add support to LS-SPI0 ------This patch adds support to SPI on LS expansion connector.

arm64: dts: db820c: add support to I2C on HS ------This patch adds support to i2c bus on High speed connector.

arm64: dts: db820c: add support to LS-I2C1 ------This patch adds support to LS_I2C1 on LS expansion connector.

arm64: dts: db820c: add support to LS-I2C0 ------This patch adds support to LS-I2C0 on LS expansion connector.

arm64: dts: db820c: add support to LS-UART0 ------This patch adds support to 4 pin UART0 on LS expansion connector.

3220 arch\arm64\boot\dts\qcom\apq8096-db820c.dtsi#0017 3221 arch\arm64\boot\dts\qcom\Makefile#0001 Repo: feeaf56ac78d Bastian Fri Nov 4 13:56:36 2016 -0700 Description: arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support ------Initial device tree support for Qualcomm MSM8994 SoC and Huawei Angler / Google Nexus 6P support.

The device tree is based on the Google 3.10 kernel tree.

The device can be booted into the initrd with only one CPU running.

arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support ------Initial device tree support for Qualcomm MSM8992 SoC and LG Bullhead / Google Nexus 5X support.

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3222 arch\arm64\boot\dts\qcom\Makefile#0004 3223 arch\arm64\boot\dts\qcom\msm8916.dtsi#0080 Repo: c987775aa4af Ritesh Mon Nov 21 12:07:22 2016 +0530 Description: arm64: dts: qcom: msm8916: Add ddr support to sdhc1 ------This adds mmc-ddr-1_8v support to DT for sdhc1 of msm8916.

ARM: dts: Add xo to sdhc clock node on qcom platforms ------Add xo entry to sdhc clock node on all qcom platforms.

arm64: dts: apq8016-sbc: add analog audio support with multicodec ------This patch add support to Analog audio both Playback and Capture via msm8916 WCD muti codec.

arm64: dts: qcom: msm8916: Add Hexagon PIL node ------The Hexagon core on the msm8916 provides services for audio control, audio output, sensors and the Hexagon SDK. The Hexagon remoteproc node allows us to boot this core.

Although its part of the core platform its left disabled as it will crash without the rmtfs QMI service and we do not yet handle crashes gracefully.

arm64: dts: qcom: msm8916: Add Hexagon SMD edge ------Add the Hexagon SMD edge, so that QRTR is probed when the Hexagon is booted.

arm64: dts: msm8916: Add display support ------The MSM8916 SoC contains a MDP5 based display block, and one DSI output. Add the top level MDSS DT node, and the MDP5, DSI and DSI PHY children sub-blocks. Establish the link between MDP5's INTF1 output port and DSI's input port.

arm64: dts: msm8916: Add thermal zones, tsens and qfprom nodes ------Add thermal zones, tsens and qfprom nodes

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arm64: dts: qcom: Fix broken interrupt trigger settings ------When a device uses the GIC as its interrupt controller and generates SPIs, only the values 1 (edge rising) and 4 (level high) are legal.

Anything else is just plain wrong (can't be programmed into the HW), and leads to aborted driver probes (USB doesn't work with 4.8-rc1 on a Dragonboard 410C).

arm64: dts: qcom: msm8916: Add tcsr syscon ------The TCSR memory segment includes various functionality, among other things the halt-registers for the Hexagon.

arm64: dts: qcom: msm8916: Make scm a reset-controller ------On msm8916 SCM acts as a controller for the MSS_RESET found in the GCC, update the DT node so that we can address this.

arm64: dts: qcom: msm8916: Add mba memory reserve ------The modem boot authenticator needs space to play in, this is supposed to be relocatable and as such could later be replaced with a dynamically allocated chunk of memory. But let's give it a reserve for now, as we know that works.

3224 arch\arm64\boot\dts\qcom\msm8916.dtsi#0507 3225 arch\arm64\boot\dts\qcom\msm8916.dtsi#0524 3226 arch\arm64\boot\dts\qcom\msm8916.dtsi#0541 3227 arch\arm64\boot\dts\qcom\msm8916.dtsi#0816 3228 arch\arm64\boot\dts\qcom\msm8916.dtsi#0906 3229 arch\arm64\boot\dts\qcom\msm8996.dtsi#0033 Repo: e9112936f240 Stephen Wed Dec 21 16:03:42 2016 -0600 Description: arm64: dts: msm8996: Add required memory carveouts ------This patch adds required memory carveouts so that the kernel does not access memory that is in use or has been reserved for use by other remote processors.

ARM: dts: Add xo to sdhc clock node on qcom platforms

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------Add xo entry to sdhc clock node on all qcom platforms.

arm64: dts: msm8996: Add SMP2P and APCS nodes ------Add SMP2P and APCS DT nodes required for Qualcomm ADSP Peripheral Image Loader.

arm64: dts: msm8996: Add SMEM DT nodes ------Add SMEM and TCSR DT nodes on MSM8996.

arm64: dts: msm8996: Add reserve-memory nodes ------Add reserve-memory nodes required for Qualcomm Peripheral Image Loaders

arm64: dts: msm8996: Add SMEM reserve-memory node ------Add DT node to carveout memory for shared memory region.

arm64: dts: msm8996: Add thermal zones, tsens and qfprom nodes ------Add thermal zones and tsens node

3230 arch\arm64\boot\dts\qcom\msm8996.dtsi#0241 3231 arch\arm64\boot\dts\qcom\msm8996.dtsi#0248 3232 arch\arm64\boot\dts\qcom\msm8996.dtsi#0261 3233 arch\arm64\boot\dts\qcom\msm8996.dtsi#0279 3234 arch\arm64\boot\dts\qcom\msm8996.dtsi#0295 3235 arch\arm64\boot\dts\qcom\msm8996.dtsi#0418 3236 arch\arm64\boot\dts\qcom\msm8996.dtsi#0420 3237 arch\arm64\boot\dts\qcom\msm8996.dtsi#0530 3238 arch\arm64\boot\dts\qcom\pm8916.dtsi#0094 Repo: 5582fcb3829f Srinivas Thu Oct 20 15:20:49 2016 +0100 Description: arm64: dts: apq8016-sbc: add analog audio support with multicodec ------This patch add support to Analog audio both Playback and Capture via

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msm8916 WCD muti codec.

ARM64: dts: qcom: Remove size elements from pmic reg properties ------The #size-cells for the pmics are 0, but we specify a size in the reg property so that MPP and GPIO modules can figure out how many pins there are. Now that we've done that by counting irqs, we can remove the size elements in the reg properties and be DT compliant.

3239 arch\arm64\boot\dts\qcom\pm8916.dtsi#0098 3240 arch\arm64\boot\dts\qcom\pm8994.dtsi#0032 Repo: 29ac9652a210 Rajendra Wed Oct 5 14:41:23 2016 +0530 Description: arm64: dts: qcom: Add missing interrupt entry for pm8994 gpios ------pm8994 has 22 gpios, so add the missing interrupts entry for one of the gpios

arm64: dts: qcom: Add pm8994 gpios and MPPs ------Add the gpio and MPP devices to the pm8994 pmic dts.

3241 arch\arm64\boot\dts\qcom\apq8096-db820c-pmic-pins.dtsi#newFile Repo: f98121f3ef3d Arnd Wed Nov 30 15:08:55 2016 +0100 Description: arm64: dts: fix build errors from missing dependencies ------Two branches were incorrectly sent without having the necessary header file changes. Rather than back those out now, I'm replacing the symbolic names for the clks and resets with the numeric values to get 'make allmodconfig dtbs' back to work.

After the header file changes are merged, we can revert this patch.

Fixes: 6bc37fa ("arm64: dts: add Allwinner A64 SoC .dtsi") Fixes: 50784e6 ("dts: arm64: db820c: add pmic pins specific dts file")

3242 arch\arm64\boot\dts\qcom\msm8992-bullhead-rev-101.dts#newFile Repo: 6a6d1978f9c0 Jeremy Fri Nov 4 13:56:31 2016 -0700 Description: arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support ------Initial device tree support for Qualcomm MSM8992 SoC and

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LG Bullhead / Google Nexus 5X support.

3243 arch\arm64\boot\dts\qcom\msm8992-pins.dtsi#newFile Repo: 6a6d1978f9c0 Jeremy Fri Nov 4 13:56:31 2016 -0700 Description: arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support ------Initial device tree support for Qualcomm MSM8992 SoC and LG Bullhead / Google Nexus 5X support.

3244 arch\arm64\boot\dts\qcom\msm8992.dtsi#newFile Repo: 6a6d1978f9c0 Jeremy Fri Nov 4 13:56:31 2016 -0700 Description: arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support ------Initial device tree support for Qualcomm MSM8992 SoC and LG Bullhead / Google Nexus 5X support.

3245 arch\arm64\boot\dts\qcom\msm8994-angler-rev-101.dts#newFile Repo: feeaf56ac78d Bastian Fri Nov 4 13:56:36 2016 -0700 Description: arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support ------Initial device tree support for Qualcomm MSM8994 SoC and Huawei Angler / Google Nexus 6P support.

The device tree is based on the Google 3.10 kernel tree.

The device can be booted into the initrd with only one CPU running.

3246 arch\arm64\boot\dts\qcom\msm8994-pins.dtsi#newFile Repo: feeaf56ac78d Bastian Fri Nov 4 13:56:36 2016 -0700 Description: arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support ------Initial device tree support for Qualcomm MSM8994 SoC and Huawei Angler / Google Nexus 6P support.

The device tree is based on the Google 3.10 kernel tree.

The device can be booted into the initrd with only one CPU running.

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3247 arch\arm64\boot\dts\qcom\msm8994.dtsi#newFile Repo: feeaf56ac78d Bastian Fri Nov 4 13:56:36 2016 -0700 Description: arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support ------Initial device tree support for Qualcomm MSM8994 SoC and Huawei Angler / Google Nexus 6P support.

The device tree is based on the Google 3.10 kernel tree.

The device can be booted into the initrd with only one CPU running.

arch\arm64\boot\dts\renesas\ 3248 arch\arm64\boot\dts\renesas\Makefile#0002 Repo: d9b1c7538783 Vladimir Thu Nov 3 21:07:09 2016 +0300 Description: arm64: dts: m3ulcb: initial device tree ------Add the initial device tree for the R8A7796 SoC based M3ULCB low cost board (R-Car Starter Kit Pro)

This commit supports the following peripherals: - SCIF (console)

3249 arch\arm64\boot\dts\renesas\r8a7795-h3ulcb.dts#0002 Repo: 8ebcb400af61 Simon Thu Dec 1 10:07:26 2016 +0100 Description: arm64: dts: h3ulcb: Provide sd0_uhs node ------Provide separaate sd0 and sd0_uhs nodes rather than duplicate sd0 nodes.

arm64: dts: h3ulcb: rename SDHI0 pins ------This changes SDHI0 pin names for H3ULCB board

arm64: dts: h3ulcb: enable SDHI2 ------This supports SDHI2 for H3ULCB onboard eMMC

arm64: dts: h3ulcb: update header ------This updates H3ULCB device tree header with official board name

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arm64: dts: h3ulcb: enable GPIO leds ------This supports GPIO leds on H3ULCB board

arm64: dts: h3ulcb: Sound SSI support ------This supports SSI sound for H3ULCB board. SSI DMA mode used. CS2000 used as AUDIO_CLK_B.

arm64: dts: h3ulcb: enable SDHI0 ------This supports SDHI0 on H3ULCB board SD card slot

arm64: dts: h3ulcb: enable GPIO keys ------This supports GPIO keys on H3ULCB board

arm64: dts: h3ulcb: enable USB2.0 Host channel 1 ------This supports USB2.0 Host channel 1 on H3ULCB board

arm64: dts: h3ulcb: enable USB2 PHY of channel 1 ------This supports USB2 PHY channel #1 on H3ULCB board

arm64: dts: h3ulcb: enable WDT ------This supports watchdog timer for H3ULCB board

arm64: dts: h3ulcb: enable EXTALR clk ------This enables EXTALR clock that can be used for the watchdog.

arm64: dts: h3ulcb: enable I2C2 ------This supports I2C2 bus on H3ULCB board

arm64: dts: h3ulcb: enable EthernetAVB ------This supports Ethernet AVB on H3ULCB board

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arm64: dts: h3ulcb: enable SCIF clk and pins ------This enables the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

3250 arch\arm64\boot\dts\renesas\r8a7795-h3ulcb.dts#0065 3251 arch\arm64\boot\dts\renesas\r8a7795-h3ulcb.dts#0166 3252 arch\arm64\boot\dts\renesas\r8a7795-h3ulcb.dts#0172 3253 arch\arm64\boot\dts\renesas\r8a7795-h3ulcb.dts#0178 3254 arch\arm64\boot\dts\renesas\r8a7795-h3ulcb.dts#0294 3255 arch\arm64\boot\dts\renesas\r8a7795-h3ulcb.dts#0306 3256 arch\arm64\boot\dts\renesas\r8a7795-salvator-x.dts#0065 Repo: 0751e1bd1e9e Yoshihiro Thu Oct 27 19:29:27 2016 +0900 Description: arm64: dts: r8a7795: salvator-x: add bias setting for usb1_pins ------Since this board doesn't mount pull-up/down registers for USB1_{OVC,PWEN} pins, we should enable bias setting to pull these pins up/down.

arm64: dts: r8a7795: salvator: enable on-board eMMC ------

arm64: dts: r8a7795: salvator-x: Add DU LVDS output endpoint ------Declaring the endpoint makes LVDS enablement easier by just including the corresponding panel's dtsi file.

arm64: dts: r8a7795: salvator-x: enable UHS for SDHI 0 & 3 ------

arm64: dts: r8a7795: salvator-x: Configure pins for the DU RGB output ------

arm64: dts: r8a7795: renesas: salvator-x: Enable DU ------Only the VGA output is supported for now.

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arm64: dts: r8a7795: salvator-x: enable HSUSB ------

arm64: dts: r8a7795: salvator-x: enable USB 2.0 Host channel 0 ------We have to set SW15 to pin 2-3 side on the board before we use CN9 as USB host or peripheral.

3257 arch\arm64\boot\dts\renesas\r8a7795-salvator-x.dts#0212 3258 arch\arm64\boot\dts\renesas\r8a7795-salvator-x.dts#0262 3259 arch\arm64\boot\dts\renesas\r8a7795-salvator-x.dts#0265 3260 arch\arm64\boot\dts\renesas\r8a7795-salvator-x.dts#0286 3261 arch\arm64\boot\dts\renesas\r8a7795-salvator-x.dts#0289 3262 arch\arm64\boot\dts\renesas\r8a7795-salvator-x.dts#0312 3263 arch\arm64\boot\dts\renesas\r8a7795-salvator-x.dts#0434 3264 arch\arm64\boot\dts\renesas\r8a7795-salvator-x.dts#0442 3265 arch\arm64\boot\dts\renesas\r8a7795-salvator-x.dts#0446 3266 arch\arm64\boot\dts\renesas\r8a7795-salvator-x.dts#0461 3267 arch\arm64\boot\dts\renesas\r8a7795-salvator-x.dts#0469 3268 arch\arm64\boot\dts\renesas\r8a7795.dtsi#0324 Repo: 482c3e8835e9 Linus Thu Dec 15 15:58:28 2016 -0800 Description: Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources:

- Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer

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product line - Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips

Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time:

- Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board

For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits) arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...

arm64: dts: r8a7795: Add device node for PRR ------Add a device node for the Product Register, which provides SoC product and revision information.

arm64: renesas: r8a7795 dtsi: Add device node for RST module

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------Add a device node for the RST module, which provides a.o. reset control and mode pin monitoring.

arm64: dts: r8a7795: Remove FCP SoC-specific compatible strings ------The SoC-specific compatible strings have been removed from the FCP DT bindings, removed them from the device tree.

arm64: dts: r8a7795: remove unnecessary cap-mmc-highspeed property ------Remove cap-mmc-highspeed property from SDHI2 and SDHI3.

This property is unnecessary as the driver automatically sets the highspeed capability. Furthermore its use is inconsistent with SDHI0 and SDHI1 which are also highspeed capable but do not have this property present.

Found by inspection.

arm64: dts: r8a7795: Add SoC-specific compatible property to audio-dmac nodes ------The audio-dmac nodes used the generic compatible property only. Add the SoC-specific one, to make it future proof.

arm64: dts: renesas: r8a7795: Add DU device to DT ------Add the DU device to r8a7795.dtsi in a disabled state.

arm64: dts: renesas: r8a7795: Add VSP instances ------The r8a7795 has 9 VSP instances.

arm64: dts: renesas: r8a7795: Add FCPV nodes ------The FCPs handle the interface between various IP cores and memory. Add the instances related to the VSP2s.

arm64: dts: r8a7795: Add HSUSB device node ------

arm64: dts: r8a7795: set maximum frequency for SDHI clocks

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------Define the upper limit otherwise the driver cannot utilize max speeds.

arm64: dts: r8a7795: add FDP1 device nodes ------

3269 arch\arm64\boot\dts\renesas\r8a7795.dtsi#1319 3270 arch\arm64\boot\dts\renesas\r8a7795.dtsi#1326 3271 arch\arm64\boot\dts\renesas\r8a7795.dtsi#1333 3272 arch\arm64\boot\dts\renesas\r8a7795.dtsi#1340 3273 arch\arm64\boot\dts\renesas\r8a7795.dtsi#1357 3274 arch\arm64\boot\dts\renesas\r8a7795.dtsi#1374 3275 arch\arm64\boot\dts\renesas\r8a7795.dtsi#1391 3276 arch\arm64\boot\dts\renesas\r8a7795.dtsi#1408 3277 arch\arm64\boot\dts\renesas\r8a7795.dtsi#1425 3278 arch\arm64\boot\dts\renesas\r8a7795.dtsi#1442 3279 arch\arm64\boot\dts\renesas\r8a7795.dtsi#1459 3280 arch\arm64\boot\dts\renesas\r8a7795.dtsi#1476 3281 arch\arm64\boot\dts\renesas\r8a7796-salvator-x.dts#0013 Repo: 20b93fbb08bd Ulrich Hecht Wed Oct 26 16:14:09 2016 +0200 Description: arm64: dts: r8a7796: salvator-x: enable I2C ------

arm64: dts: r8a7796: salvator: enable on board eMMC ------

arm64: dts: r8a7796: salvator-x: enable UHS for SDHI 0 & 3 ------

arm64: dts: r8a7796: salvator-x: enable SDHI0 & 3 ------

arm64: dts: r8a7796: salvator-x: Populate EXTALR ------

3282 arch\arm64\boot\dts\renesas\r8a7796-salvator-x.dts#0033

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3283 arch\arm64\boot\dts\renesas\r8a7796-salvator-x.dts#0113 3284 arch\arm64\boot\dts\renesas\r8a7796-salvator-x.dts#0160 3285 arch\arm64\boot\dts\renesas\r8a7796-salvator-x.dts#0216 3286 arch\arm64\boot\dts\renesas\r8a7796.dtsi#0020 Repo: 482c3e8835e9 Linus Thu Dec 15 15:58:28 2016 -0800 Description: Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources:

- Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line - Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips

Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time:

- Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board

For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits) arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X

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ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...

arm64: dts: r8a7796: Add device node for PRR ------Add a device node for the Product Register, which provides SoC product and revision information.

arm64: dts: r8a7796: Enable I2C DMA ------

arm64: dts: r8a7796: add I2C support ------

arm64: renesas: r8a7796: add SYS-DMAC controller nodes ------

arm64: renesas: r8a7796 dtsi: Add device node for RST module ------Add a device node for the RST module, which provides a.o. reset control and mode pin monitoring.

arm64: dts: r8a7796: add SDHI nodes ------Add SDHI nodes to the DT of the r8a7796 SoC.

Based on the DT of the r8a7795 SoC.

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arm64: dts: r8a7796: Add GPIO device nodes ------Add GPIO device nodes to the DT of the r8a7796 SoC.

3287 arch\arm64\boot\dts\renesas\r8a7796.dtsi#0246 3288 arch\arm64\boot\dts\renesas\r8a7796.dtsi#0262 3289 arch\arm64\boot\dts\renesas\r8a7796.dtsi#0375 3290 arch\arm64\boot\dts\renesas\r8a7796-m3ulcb.dts#newFile Repo: fd51baee7abc Vladimir Tue Nov 8 17:14:42 2016 +0300 Description: arm64: dts: m3ulcb: enable SDHI2 ------This supports SDHI2 for M3ULCB onboard eMMC

arm64: dts: m3ulcb: enable SDHI0 ------This supports SDHI0 on M3ULCB board SD card slot

arm64: dts: m3ulcb: enable WDT ------This supports watchdog timer for M3ULCB board

arm64: dts: m3ulcb: enable EXTALR clk ------This enables EXTALR clock that can be used for the watchdog.

arm64: dts: m3ulcb: enable GPIO keys ------This supports GPIO keys on M3ULCB board

arm64: dts: m3ulcb: enable GPIO leds ------This supports GPIO leds on M3ULCB board

arm64: dts: m3ulcb: enable SCIF clk and pins ------This enables the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

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Line Link NR. Descriptions arch\arm64\boot\dts\rockchip\ 3291 arch\arm64\boot\dts\rockchip\Makefile#0004 Repo: 76c923bb6492 Andy Yan Sun Sep 11 01:47:03 2016 +0800 Description: arm64: dts: rockchip: Add PX5 Evaluation board ------PX5 EVB is designed by Rockchip for automotive field with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS HDMI video input/output interface, audio codec ES8396, WIFI/BT (on RTL8723BS), Gsensor BMA250E and light&proximity sensor STK3410.

3292 arch\arm64\boot\dts\rockchip\rk3368-orion-r68-meta.dts#0347 Repo: fce566ff9706 Olof Thu Nov 17 23:32:45 2016 -0800 Description: Merge tag 'v4.10-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64 ------64bit devicetree changes including the px5 evaluation board a fix for wrong i2c registers on rk3368 a new nvmem cell and power-domain on rk3399 as well as moving mmc frequency properties to the more generic max-frequency one.

* tag 'v4.10-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux- rockchip: arm64: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max" arm64: dts: rockchip: add cpu-id nvmem cell node for rk3399 arm64: dts: rockchip: add sdmmc support for px5-evb arm64: dts: rockchip: Add more properties for emmc on px5-evb arm64: dts: rockchip: Add PX5 Evaluation board arm64: dts: rockchip: add powerdomain for typec on rk3399 arm64: dts: rockchip: fix i2c resource error of rk3368

arm64: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max" ------In drivers/mmc/core/host.c, there is "max-freqeuncy" property. It should be same behavior, So Use the "max-frequency" instead of "clock-freq-min-max".

3293 arch\arm64\boot\dts\rockchip\rk3368.dtsi#0234 Repo: 482c3e8835e9 Linus Thu Dec 15 15:58:28 2016 -0800 Description: Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are

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the respective DTS sources:

- Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line - Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips

Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time:

- Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board

For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits) arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1

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arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...

usb: dwc2: Deprecate g-use-dma binding ------This is not needed as the gadget now fully supports DMA and it can autodetect it. This was initially added because gadget DMA mode was only partially implemented so could not be automatically enabled.

arm64: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max" ------In drivers/mmc/core/host.c, there is "max-freqeuncy" property. It should be same behavior, So Use the "max-frequency" instead of "clock-freq-min-max".

arm64: dts: rockchip: fix i2c resource error of rk3368 ------According to the TRM and downstream code from rockchip, the register address of i2c1 on rk3368 is 0xff660000 and i2c2 is 0xff140000.

This patch fix the i2c1 & i2c2 register address definition error, also fix the clk and pinctrl reference error.

3294 arch\arm64\boot\dts\rockchip\rk3368.dtsi#0246 3295 arch\arm64\boot\dts\rockchip\rk3368.dtsi#0258 3296 arch\arm64\boot\dts\rockchip\rk3368.dtsi#0318 3297 arch\arm64\boot\dts\rockchip\rk3368.dtsi#0325 3298 arch\arm64\boot\dts\rockchip\rk3368.dtsi#0327 3299 arch\arm64\boot\dts\rockchip\rk3368.dtsi#0540 3300 arch\arm64\boot\dts\rockchip\rk3368.dtsi#0557 3301 arch\arm64\boot\dts\rockchip\rk3368.dtsi#0564 3302 arch\arm64\boot\dts\rockchip\rk3368.dtsi#0566 3303 arch\arm64\boot\dts\rockchip\rk3399-evb.dts#0052 Repo: 578c0e7e8363 Yakir Yang Wed Nov 9 21:21:57 2016 +0800 Description: arm64: dts: rockchip: add backlight support for rk3399 evb board

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------Add backlight node for evb board, perpare for panel device node.

arm64: dts: rockchip: enable the gmac for rk3399 evb board ------We add the required and optional properties for evb board. See the [0] to get the detail information.

[0]: Documentation/devicetree/bindings/net/rockchip-dwmac.txt

3304 arch\arm64\boot\dts\rockchip\rk3399.dtsi#0177 Repo: 482c3e8835e9 Linus Thu Dec 15 15:58:28 2016 -0800 Description: Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources:

- Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line - Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips

Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time:

- Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board

For the existing platforms, we get bug fixes and new peripheral

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support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits) arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...

Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip ------Pull timer updates from Thomas Gleixner: "The time/timekeeping/timer folks deliver with this update:

- Fix a reintroduced signed/unsigned issue and cleanup the whole signed/unsigned mess in the timekeeping core so this wont happen accidentaly again.

- Add a new trace clock based on boot time

- Prevent injection of random sleep times when PM tracing abuses the RTC for storage

- Make posix timers configurable for real tiny systems

- Add tracepoints for the alarm timer subsystem so timer based suspend wakeups can be instrumented

- The usual pile of fixes and updates to core and drivers"

* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits)

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timekeeping: Use mul_u64_u32_shr() instead of open coding it timekeeping: Get rid of pointless typecasts timekeeping: Make the conversion call chain consistently unsigned timekeeping_Force_unsigned_clocksource_to_nanoseconds_conversion alarmtimer: Add tracepoints for alarm timers trace: Update documentation for mono, mono_raw and boot clock trace: Add an option for boot clock as trace clock timekeeping: Add a fast and NMI safe boot clock timekeeping/clocksource_cyc2ns: Document intended range limitation timekeeping: Ignore the bogus sleep time if pm_trace is enabled selftests/timers: Fix spelling mistake "Asyncrhonous" -> "Asynchronous" clocksource/drivers/bcm2835_timer: Unmap region obtained by of_iomap clocksource/drivers/arm_arch_timer: Map frame with of_io_request_and_map() arm64: dts: rockchip: Arch counter doesn't tick in system suspend clocksource/drivers/arm_arch_timer: Don't assume clock runs in suspend posix-timers: Make them configurable posix_cpu_timers: Move the add_device_randomness() call to a proper place timer: Move sys_alarm from timer.c to itimer.c ptp_clock: Allow for it to be optional Kconfig: Regenerate *.c_shipped files after previous changes ...

arm64: dts: rockchip: Arch counter doesn't tick in system suspend ------The "arm,no-tick-in-suspend" property was introduced to note implementations where the system counter does not quite follow the ARM specification that it "must be implemented in an always-on power domain".

Particularly, RK3399's counter stops ticking when we switch from the 24MHz clock to the 32KHz clock in low-power suspend, so let's mark it as such.

arm64: dts: rockchip: add usb2-phy otg-port support for rk3399 ------Add otg-port nodes for both u2phy0 and u2phy1. The otg-port can be used for USB2.0 part of USB3.0 OTG controller.

arm64: dts: rockchip: add pd_sd power-domain node for rk3399 ------Add the sd power-domain, its qos area and assign it to the sdmmc device node.

arm64: dts: rockchip: add eMMC's power domain support for rk3399 ------Control power domain for eMMC via genpd to reduce power consumption.

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arm64: dts: rockchip: add gmac needed pclk for rk3399 pd ------This patch fixes that sometimes hang at start-up time of the system. As the below log: ... [ 11.136543] calling pm_genpd_debug_init+0x0/0x60 @ 1 [ 11.141602] initcall pm_genpd_debug_init+0x0/0x60 returned 0 after 11 usecs [ 11.148558] calling genpd_poweroff_unused+0x0/0x84 @ 1

In some cases, the rk3399 should turn off the gmac power domain to save power if some boards didn't register the gmac device node for rk3399. Then, rk3399 need to make sure the gmac's pclk enabled if we need operate the gmac power domain. (Due to the NOC had enabled always)

3305 arch\arm64\boot\dts\rockchip\rk3399.dtsi#0239 3306 arch\arm64\boot\dts\rockchip\rk3399.dtsi#0252 3307 arch\arm64\boot\dts\rockchip\rk3399.dtsi#0257 3308 arch\arm64\boot\dts\rockchip\rk3399.dtsi#0274 3309 arch\arm64\boot\dts\rockchip\rk3399.dtsi#0699 3310 arch\arm64\boot\dts\rockchip\rk3399.dtsi#0842 3311 arch\arm64\boot\dts\rockchip\rk3399.dtsi#0849 3312 arch\arm64\boot\dts\rockchip\rk3399.dtsi#0853 3313 arch\arm64\boot\dts\rockchip\rk3399.dtsi#1054 3314 arch\arm64\boot\dts\rockchip\rk3399.dtsi#1135 3315 arch\arm64\boot\dts\rockchip\rk3399.dtsi#1162 3316 arch\arm64\boot\dts\rockchip\rk3399.dtsi#1202 3317 arch\arm64\boot\dts\rockchip\rk3399.dtsi#1231 3318 arch\arm64\boot\dts\rockchip\rk3368-px5-evb.dts#newFile Repo: 41a603b9337c Shawn Lin Thu Sep 22 12:02:18 2016 +0800 Description: arm64: dts: rockchip: add sdmmc support for px5-evb ------px5-evb has one sdmmc slot, so we could support sdmmc.

arm64: dts: rockchip: Add more properties for emmc on px5-evb ------The emmc on px5-evb can support hs200, so let's add mmc-hs200-1_8v.

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And in order to speed up the boot time, we could add no-sdio and no-sd to simplify the initialization.

arch\arm64\boot\dts\socionext\ 3319 arch\arm64\boot\dts\socionext\uniphier-ld11.dtsi#0046 Repo: fb28cef06a90 Masahiro Sat Nov 5 23:30:11 2016 +0900 Description: arm64: dts: uniphier: make compatible of syscon nodes SoC-specific ------These hardware blocks are SoC-specific, so their compatible strings should be SoC-specific as well. This change has no impact on the actual behavior since it is controlled by the generic "simple-mfd", "syscon" compatible strings.

arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC ------Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver.

Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency.

arm64: dts: uniphier: increase register region size of sysctrl node ------The System Control node has 0x10000 byte of registers. The current reg size must be expanded to use the cpufreq driver because the registers controlling CPU frequency are located at offset 0x8000.

arm64: dts: uniphier: switch over to PSCI enable method ------At the first system bring-up, I chose to use spin-table because ARM Trusted Firmware was not ready for this platform at that moment.

Actually, these SoCs are equipped with EL3 and able to provide PSCI. Now I finished porting the ATF BL31 for the UniPhier platform, so it is ready to migrate to PSCI enable method.

3320 arch\arm64\boot\dts\socionext\uniphier-ld11.dtsi#0073

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3321 arch\arm64\boot\dts\socionext\uniphier-ld11.dtsi#0082 3322 arch\arm64\boot\dts\socionext\uniphier-ld11.dtsi#0088 3323 arch\arm64\boot\dts\socionext\uniphier-ld11.dtsi#0277 3324 arch\arm64\boot\dts\socionext\uniphier-ld11.dtsi#0326 3325 arch\arm64\boot\dts\socionext\uniphier-ld11.dtsi#0343 3326 arch\arm64\boot\dts\socionext\uniphier-ld11.dtsi#0364 3327 arch\arm64\boot\dts\socionext\uniphier-ld20.dtsi#0046 Repo: fb28cef06a90 Masahiro Sat Nov 5 23:30:11 2016 +0900 Description: arm64: dts: uniphier: make compatible of syscon nodes SoC-specific ------These hardware blocks are SoC-specific, so their compatible strings should be SoC-specific as well. This change has no impact on the actual behavior since it is controlled by the generic "simple-mfd", "syscon" compatible strings.

arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC ------Add a CPU clock to every CPU node and CPU OPP tables to use the generic cpufreq driver. All the CPUs in each cluster share the same OPP table.

Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency.

arm64: dts: uniphier: increase register region size of sysctrl node ------The System Control node has 0x10000 byte of registers. The current reg size must be expanded to use the cpufreq driver because the registers controlling CPU frequency are located at offset 0x8000.

arm64: dts: uniphier: switch over to PSCI enable method ------At the first system bring-up, I chose to use spin-table because ARM Trusted Firmware was not ready for this platform at that moment.

Actually, these SoCs are equipped with EL3 and able to provide PSCI. Now I finished porting the ATF BL31 for the UniPhier platform, so it is ready to migrate to PSCI enable method.

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3328 arch\arm64\boot\dts\socionext\uniphier-ld20.dtsi#0082 3329 arch\arm64\boot\dts\socionext\uniphier-ld20.dtsi#0091 3330 arch\arm64\boot\dts\socionext\uniphier-ld20.dtsi#0100 3331 arch\arm64\boot\dts\socionext\uniphier-ld20.dtsi#0109 3332 arch\arm64\boot\dts\socionext\uniphier-ld20.dtsi#0115 3333 arch\arm64\boot\dts\socionext\uniphier-ld20.dtsi#0362 3334 arch\arm64\boot\dts\socionext\uniphier-ld20.dtsi#0378 3335 arch\arm64\boot\dts\socionext\uniphier-ld20.dtsi#0397 3336 arch\arm64\boot\dts\socionext\uniphier-ld20.dtsi#0399 arch\arm64\boot\dts\xilinx\ 3337 arch\arm64\boot\dts\xilinx\zynqmp-ep108.dts#0030 Repo: 4ea2a6be9565 Michal SimekTue Nov 15 14:53:13 2016 +0100 Description: ARM64: zynqmp: Fix W=1 dtc 1.4 warnings ------The patch removes these warnings reported by dtc 1.4: Warning (unit_address_vs_reg): Node /amba_apu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

ARM64: zynqmp: Use 64bit size cell format ------Use 64bit size cell format instead of 32bit for memory description. Change 64bit sizes also for all others IPs.

3338 arch\arm64\boot\dts\xilinx\zynqmp.dtsi#0075 Repo: c415f9e8304a Moritz Thu Dec 22 09:19:25 2016 -0800 Description: ARM64: zynqmp: Fix i2c node's compatible string ------The Zynq Ultrascale MP uses version 1.4 of the Cadence IP core which fixes some silicon bugs that needed software workarounds in Version 1.0 that was used on Zynq systems.

ARM64: zynqmp: Fix W=1 dtc 1.4 warnings ------The patch removes these warnings reported by dtc 1.4: Warning (unit_address_vs_reg): Node /amba_apu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /memory has a reg or ranges

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property, but no unit name

3339 arch\arm64\boot\dts\xilinx\zynqmp.dtsi#0178 3340 arch\arm64\boot\dts\xilinx\zynqmp.dtsi#0188 arch\arm64\boot\dts\zte\ 3341 arch\arm64\boot\dts\zte\zx296718.dtsi#0242 Repo: 482c3e8835e9 Linus Thu Dec 15 15:58:28 2016 -0800 Description: Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources:

- Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line - Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips

Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time:

- Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board

For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits)

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arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...

arm64: dts: zte: clean up gic-v3 redistributor properties ------The gic-v3 property redistributor-stride is only meant as a workaround for broken platforms that have a redistributor stride deviating what the architecture defines, i.e. 128KiB for GICv3, 256KiB for GICv4. This is not the case for ZX296718, and redistributor-stride is not really necessary. Let's drop it.

Also, #redistributor-regions is only required when there is more than one such region is present. Let's remove it as well.

arm64: dts: zx: Fix gic GICR property ------GICR for multiple CPU can be described with start address and stride, or with multiple address. Current multiple address and stride are both used. Fix it.

vmalloc patch 727a7f5a9 triggered this bug: [ 0.097146] Unable to handle kernel paging request at virtual address ffff000008060008 [ 0.097150] pgd = ffff000008602000 [ 0.097160] [ffff000008060008] *pgd=000000007fffe003, *pud=000000007fffd003, *pmd=000000007fffc003, *pte=0000000000000000 [ 0.097165] Internal error: Oops: 96000007 [#1] PREEMPT SMP [ 0.097170] Modules linked in: [ 0.097177] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 4.8.0+ #1474

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[ 0.097179] Hardware name: ZTE zx296718 evaluation board (DT) [ 0.097183] task: ffff80003e8c8b80 task.stack: ffff80003e8d0000 [ 0.097197] PC is at gic_populate_rdist+0x74/0x15c [ 0.097202] LR is at gic_starting_cpu+0xc/0x20 [ 0.097206] pc : [] lr : [] pstate: 600001c5

arm64: dts: zx: Add clock controller nodes ------Add clock controller nodes, including one top controller two low speed controllers and one audio controller.

3342 arch\arm64\boot\dts\zte\zx296718.dtsi#0246 3343 arch\arm64\boot\dts\zte\zx296718.dtsi#0287 3344 arch\arm64\boot\dts\zte\zx296718.dtsi#0302 arch\arm64\boot\dts\allwinner\ 3345 arch\arm64\boot\dts\allwinner\Makefile#newFile Repo: 4e3886081848 Andre Tue Jan 19 10:36:39 2016 +0000 Description: arm64: dts: add Pine64 support ------The Pine64 is a cost-efficient development board based on the Allwinner A64 SoC. There are three models: the basic version with Fast Ethernet and 512 MB of DRAM (Pine64) and two Pine64+ versions, which both feature Gigabit Ethernet and additional connectors for touchscreens and a camera. Or as my son put it: "Those are smaller and these are missing." ;-) The two Pine64+ models just differ in the amount of DRAM (1GB vs. 2GB). Since U-Boot will figure out the right size for us and patches the DT accordingly we just need to provide one DT for the Pine64+.

3346 arch\arm64\boot\dts\allwinner\sun50i-a64-pine64-plus.dts#newFile Repo: 4e3886081848 Andre Tue Jan 19 10:36:39 2016 +0000 Description: arm64: dts: add Pine64 support ------The Pine64 is a cost-efficient development board based on the Allwinner A64 SoC. There are three models: the basic version with Fast Ethernet and 512 MB of DRAM (Pine64) and two Pine64+ versions, which both feature Gigabit Ethernet and additional connectors for touchscreens and a camera. Or as my son put it: "Those are smaller and these are missing." ;-)

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The two Pine64+ models just differ in the amount of DRAM (1GB vs. 2GB). Since U-Boot will figure out the right size for us and patches the DT accordingly we just need to provide one DT for the Pine64+.

3347 arch\arm64\boot\dts\allwinner\sun50i-a64-pine64.dts#newFile Repo: 4e3886081848 Andre Tue Jan 19 10:36:39 2016 +0000 Description: arm64: dts: add Pine64 support ------The Pine64 is a cost-efficient development board based on the Allwinner A64 SoC. There are three models: the basic version with Fast Ethernet and 512 MB of DRAM (Pine64) and two Pine64+ versions, which both feature Gigabit Ethernet and additional connectors for touchscreens and a camera. Or as my son put it: "Those are smaller and these are missing." ;-) The two Pine64+ models just differ in the amount of DRAM (1GB vs. 2GB). Since U-Boot will figure out the right size for us and patches the DT accordingly we just need to provide one DT for the Pine64+.

3348 arch\arm64\boot\dts\allwinner\sun50i-a64.dtsi#newFile Repo: f98121f3ef3d Arnd Wed Nov 30 15:08:55 2016 +0100 Description: arm64: dts: fix build errors from missing dependencies ------Two branches were incorrectly sent without having the necessary header file changes. Rather than back those out now, I'm replacing the symbolic names for the clks and resets with the numeric values to get 'make allmodconfig dtbs' back to work.

After the header file changes are merged, we can revert this patch.

Fixes: 6bc37fa ("arm64: dts: add Allwinner A64 SoC .dtsi") Fixes: 50784e6 ("dts: arm64: db820c: add pmic pins specific dts file") arch\arm64\configs\ 3349 arch\arm64\configs\defconfig#0014 Repo: fcdaf1a2a7a0 Kevin HilmanThu Dec 8 16:56:23 2016 -0800 Description: ARM64: defconfig: enable DRM_MESON as module ------

Merge tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ------

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Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux ------

Merge tag 'v4.10-rockchip-defconfig64' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/arm64 ------

arm64: defconfig: drop GPIO_SYSFS on multiplatforms ------

Merge tag 'arm-soc/for-4.10/defconfig-arm64' of http://github.com/Broadcom/stblinux into next/arm64 ------

arm64: defconfig: Do not lower CONFIG_LOG_BUF_SHIFT ------

arm64: Enable HIBERNATION in defconfig ------

Merge tag 'bcm2835-defconfig-64-next-2016-11-18' into defconfig-arm64/next ------

Merge tag 'tegra-for-4.10-arm64-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/arm64 ------

Merge tag 'amlogic-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux- amlogic into next/arm64 ------

Merge tag 'qcom-arm64-defconfig-for-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/arm64 ------

arm64: defconfig: allow rk3399-based boards to boot from mmc and usb ------

arm64: defconfig: enable RK808 components ------

arm64: defconfig: enable I2C and DW MMC controller on rockchip platform ------

arm64: defconfig: Enable Tegra186 SoC ------

ARM64: configs: Activate Internal PHY for Meson GXL ------

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arm64: configs: enable configs for msm899(2/4) basic support ------

ARM64: bcm2835: add thermal driver to default config ------

Merge tag 'renesas-arm64-defconfig-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/arm64 ------

ARM64: configs: Add Platform MHU in defconfig ------

arm64: defconfig: enable EEPROM_AT25 config option ------

arm64: Enable HIBERNATION in defconfig ------

arm64: defconfig: Enable DRM DU and V4L2 FCP + VSP modules ------

ARM64: defconfig: Enable MMC related configs ------

arm64: Add BCM2835 (Raspberry Pi 3) support to the defconfig ------

arm64: xgene: defconfig: Enable Standby GPIO ------

3350 arch\arm64\configs\defconfig#0037 3351 arch\arm64\configs\defconfig#0085 3352 arch\arm64\configs\defconfig#0151 3353 arch\arm64\configs\defconfig#0188 3354 arch\arm64\configs\defconfig#0190 3355 arch\arm64\configs\defconfig#0202 3356 arch\arm64\configs\defconfig#0215 3357 arch\arm64\configs\defconfig#0241 3358 arch\arm64\configs\defconfig#0247

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3359 arch\arm64\configs\defconfig#0254 3360 arch\arm64\configs\defconfig#0265 3361 arch\arm64\configs\defconfig#0269 3362 arch\arm64\configs\defconfig#0273 3363 arch\arm64\configs\defconfig#0288 3364 arch\arm64\configs\defconfig#0291 3365 arch\arm64\configs\defconfig#0297 3366 arch\arm64\configs\defconfig#0311 3367 arch\arm64\configs\defconfig#0313 3368 arch\arm64\configs\defconfig#0325 3369 arch\arm64\configs\defconfig#0330 3370 arch\arm64\configs\defconfig#0334 3371 arch\arm64\configs\defconfig#0346 3372 arch\arm64\configs\defconfig#0379 3373 arch\arm64\configs\defconfig#0383 3374 arch\arm64\configs\defconfig#0392 3375 arch\arm64\configs\defconfig#0408 3376 arch\arm64\configs\defconfig#0414 3377 arch\arm64\configs\defconfig#0430 3378 arch\arm64\configs\defconfig#0435 3379 arch\arm64\configs\defconfig#0440 3380 arch\arm64\configs\defconfig#0444 3381 arch\arm64\configs\defconfig#0448 3382 arch\arm64\configs\defconfig#0451 3383 arch\arm64\configs\defconfig#0454 3384 arch\arm64\configs\defconfig#0457 3385 arch\arm64\configs\defconfig#0461 3386 arch\arm64\configs\defconfig#0470 arch\arm64\crypto\ 3387 arch\arm64\crypto\aes-ce-ccm-core.S#0012 Repo: 56e4e76c68fc Ard Tue Oct 11 19:15:17 2016 +0100

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Description: crypto: arm64/aes-ccm-ce: fix for big endian ------The AES-CCM implementation that uses ARMv8 Crypto Extensions instructions refers to the AES round keys as pairs of 64-bit quantities, which causes failures when building the code for big endian. In addition, it byte swaps the input counter unconditionally, while this is only required for little endian builds. So fix both issues.

Fixes: 12ac3efe74f8 ("arm64/crypto: use crypto instructions to generate AES key schedule")

3388 arch\arm64\crypto\aes-ce-ccm-core.S#0023 3389 arch\arm64\crypto\aes-ce-ccm-core.S#0035 3390 arch\arm64\crypto\aes-ce-ccm-core.S#0045 3391 arch\arm64\crypto\aes-ce-ccm-core.S#0048 3392 arch\arm64\crypto\aes-ce-ccm-core.S#0051 3393 arch\arm64\crypto\aes-ce-ccm-core.S#0055 3394 arch\arm64\crypto\aes-ce-ccm-core.S#0064 3395 arch\arm64\crypto\aes-ce-ccm-core.S#0083 3396 arch\arm64\crypto\aes-ce-ccm-core.S#0093 3397 arch\arm64\crypto\aes-ce-ccm-core.S#0097 3398 arch\arm64\crypto\aes-ce-ccm-core.S#0103 3399 arch\arm64\crypto\aes-ce-ccm-core.S#0108 3400 arch\arm64\crypto\aes-ce-ccm-core.S#0113 3401 arch\arm64\crypto\aes-ce-ccm-core.S#0124 3402 arch\arm64\crypto\aes-ce-ccm-core.S#0130 3403 arch\arm64\crypto\aes-ce-ccm-core.S#0133 3404 arch\arm64\crypto\aes-ce-ccm-core.S#0140 3405 arch\arm64\crypto\aes-ce-ccm-core.S#0147 3406 arch\arm64\crypto\aes-ce-ccm-core.S#0153 3407 arch\arm64\crypto\aes-ce-ccm-core.S#0158 3408 arch\arm64\crypto\aes-ce-ccm-core.S#0164 3409 arch\arm64\crypto\aes-ce-ccm-core.S#0181

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3410 arch\arm64\crypto\aes-ce-ccm-core.S#0188 3411 arch\arm64\crypto\aes-ce-ccm-glue.c#0014 Repo: 0be8a270b3f4 Herbert Xu Wed Nov 30 21:17:24 2016 +0800 Description: crypto: arm64/aes-ce-ccm - Fix AEAD decryption length ------This patch fixes the ARM64 CE CCM implementation decryption by using skcipher_walk_aead_decrypt instead of skcipher_walk_aead, which ensures the correct length is used when doing the walk.

Fixes: cf2c0fe74084 ("crypto: aes-ce-ccm - Use skcipher walk interface")

crypto: aes-ce-ccm - Use skcipher walk interface ------This patch makes use of the new skcipher walk interface instead of the obsolete blkcipher walk interface.

3412 arch\arm64\crypto\aes-ce-ccm-glue.c#0017 3413 arch\arm64\crypto\aes-ce-ccm-glue.c#0152 3414 arch\arm64\crypto\aes-ce-ccm-glue.c#0175 3415 arch\arm64\crypto\aes-ce-ccm-glue.c#0180 3416 arch\arm64\crypto\aes-ce-ccm-glue.c#0187 3417 arch\arm64\crypto\aes-ce-ccm-glue.c#0194 3418 arch\arm64\crypto\aes-ce-ccm-glue.c#0206 3419 arch\arm64\crypto\aes-ce-ccm-glue.c#0217 3420 arch\arm64\crypto\aes-ce-ccm-glue.c#0240 3421 arch\arm64\crypto\aes-ce-ccm-glue.c#0245 3422 arch\arm64\crypto\aes-ce-ccm-glue.c#0252 3423 arch\arm64\crypto\aes-ce-ccm-glue.c#0259 3424 arch\arm64\crypto\aes-ce-ccm-glue.c#0271 3425 arch\arm64\crypto\aes-ce-ccm-glue.c#0290 3426 arch\arm64\crypto\aes-ce-cipher.c#0050 Repo: 1803b9a52c4e Ard Tue Oct 11 19:15:13 2016 +0100 Description: crypto: arm64/aes-ce - fix for big endian ------The core AES cipher implementation that uses ARMv8 Crypto Extensions instructions erroneously loads the round keys as 64-bit quantities, which causes the algorithm to fail when built for big endian. In addition, the key schedule generation routine fails to take endianness

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into account as well, when loading the combining the input key with the round constants. So fix both issues.

Fixes: 12ac3efe74f8 ("arm64/crypto: use crypto instructions to generate AES key schedule")

3427 arch\arm64\crypto\aes-ce-cipher.c#0057 3428 arch\arm64\crypto\aes-ce-cipher.c#0060 3429 arch\arm64\crypto\aes-ce-cipher.c#0063 3430 arch\arm64\crypto\aes-ce-cipher.c#0067 3431 arch\arm64\crypto\aes-ce-cipher.c#0095 3432 arch\arm64\crypto\aes-ce-cipher.c#0102 3433 arch\arm64\crypto\aes-ce-cipher.c#0105 3434 arch\arm64\crypto\aes-ce-cipher.c#0108 3435 arch\arm64\crypto\aes-ce-cipher.c#0112 3436 arch\arm64\crypto\aes-ce-cipher.c#0176 3437 arch\arm64\crypto\aes-ce-cipher.c#0178 3438 arch\arm64\crypto\aes-ce.S#0013 Repo: caf4b9e2b326 Ard Tue Oct 11 19:15:19 2016 +0100 Description: crypto: arm64/aes-xts-ce: fix for big endian ------Emit the XTS tweak literal constants in the appropriate order for a single 128-bit scalar literal load.

Fixes: 49788fe2a128 ("arm64/crypto: AES-ECB/CBC/CTR/XTS using ARMv8 NEON and Crypto Extensions")

3439 arch\arm64\crypto\aes-glue.c#0014 Repo: b3e1e0cbd9ee Ard Tue Nov 29 13:05:33 2016 +0000 Description: crypto: arm64/aes-ce-ctr - fix skcipher conversion ------Fix a missing statement that got lost in the skcipher conversion of the CTR transform.

crypto: arm/aes-ce - fix broken monolithic build ------When building the arm64 kernel with both CONFIG_CRYPTO_AES_ARM64_CE_BLK=y and CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y configured, the build breaks with the following error:

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arch/arm64/crypto/aes-neon-blk.o:(.bss+0x0): multiple definition of `aes_simd_algs' arch/arm64/crypto/aes-ce-blk.o:(.bss+0x0): first defined here

Fix this by making aes_simd_algs 'static'.

crypto: arm64/aes - Convert to skcipher ------This patch converts arm64/aes over to the skcipher interface.

3440 arch\arm64\crypto\aes-glue.c#0083 3441 arch\arm64\crypto\aes-glue.c#0092 3442 arch\arm64\crypto\aes-glue.c#0095 3443 arch\arm64\crypto\aes-glue.c#0106 3444 arch\arm64\crypto\aes-glue.c#0110 3445 arch\arm64\crypto\aes-glue.c#0112 3446 arch\arm64\crypto\aes-glue.c#0115 3447 arch\arm64\crypto\aes-glue.c#0118 3448 arch\arm64\crypto\aes-glue.c#0124 3449 arch\arm64\crypto\aes-glue.c#0130 3450 arch\arm64\crypto\aes-glue.c#0132 3451 arch\arm64\crypto\aes-glue.c#0135 3452 arch\arm64\crypto\aes-glue.c#0138 3453 arch\arm64\crypto\aes-glue.c#0144 3454 arch\arm64\crypto\aes-glue.c#0150 3455 arch\arm64\crypto\aes-glue.c#0152 3456 arch\arm64\crypto\aes-glue.c#0155 3457 arch\arm64\crypto\aes-glue.c#0158 3458 arch\arm64\crypto\aes-glue.c#0165 3459 arch\arm64\crypto\aes-glue.c#0171 3460 arch\arm64\crypto\aes-glue.c#0174 3461 arch\arm64\crypto\aes-glue.c#0176

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3462 arch\arm64\crypto\aes-glue.c#0179 3463 arch\arm64\crypto\aes-glue.c#0188 3464 arch\arm64\crypto\aes-glue.c#0194 3465 arch\arm64\crypto\aes-glue.c#0197 3466 arch\arm64\crypto\aes-glue.c#0199 3467 arch\arm64\crypto\aes-glue.c#0202 3468 arch\arm64\crypto\aes-glue.c#0212 3469 arch\arm64\crypto\aes-glue.c#0213 3470 arch\arm64\crypto\aes-glue.c#0219 3471 arch\arm64\crypto\aes-glue.c#0223 3472 arch\arm64\crypto\aes-glue.c#0233 3473 arch\arm64\crypto\aes-glue.c#0240 3474 arch\arm64\crypto\aes-glue.c#0243 3475 arch\arm64\crypto\aes-glue.c#0245 3476 arch\arm64\crypto\aes-glue.c#0248 3477 arch\arm64\crypto\aes-glue.c#0257 3478 arch\arm64\crypto\aes-glue.c#0264 3479 arch\arm64\crypto\aes-glue.c#0267 3480 arch\arm64\crypto\aes-glue.c#0269 3481 arch\arm64\crypto\aes-glue.c#0272 3482 arch\arm64\crypto\aes-glue.c#0281 3483 arch\arm64\crypto\aes-glue.c#0288 3484 arch\arm64\crypto\aes-glue.c#0307 3485 arch\arm64\crypto\aes-glue.c#0308 3486 arch\arm64\crypto\aes-glue.c#0326 3487 arch\arm64\crypto\aes-glue.c#0327 3488 arch\arm64\crypto\aes-glue.c#0345 3489 arch\arm64\crypto\aes-glue.c#0346 3490 arch\arm64\crypto\aes-glue.c#0364

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3491 arch\arm64\crypto\aes-glue.c#0446 3492 arch\arm64\crypto\aes-glue.c#0448 3493 arch\arm64\crypto\aes-glue.c#0451 3494 arch\arm64\crypto\aes-glue.c#0453 3495 arch\arm64\crypto\aes-modes.S#0196 Repo: 11e3b725cfc2 Ard Tue Jan 17 13:46:29 2017 +0000 Description: crypto: arm64/aes-blk - honour iv_out requirement in CBC and CTR modes ------Update the ARMv8 Crypto Extensions and the plain NEON AES implementations in CBC and CTR modes to return the next IV back to the skcipher API client. This is necessary for chaining to work correctly.

Note that for CTR, this is only done if the request is a round multiple of the block size, since otherwise, chaining is impossible anyway.

crypto: arm64/aes-xts-ce: fix for big endian ------Emit the XTS tweak literal constants in the appropriate order for a single 128-bit scalar literal load.

Fixes: 49788fe2a128 ("arm64/crypto: AES-ECB/CBC/CTR/XTS using ARMv8 NEON and Crypto Extensions")

3496 arch\arm64\crypto\aes-modes.S#0201 3497 arch\arm64\crypto\aes-modes.S#0205 3498 arch\arm64\crypto\aes-modes.S#0215 3499 arch\arm64\crypto\aes-modes.S#0252 3500 arch\arm64\crypto\aes-modes.S#0260 3501 arch\arm64\crypto\aes-modes.S#0272 3502 arch\arm64\crypto\aes-modes.S#0284 3503 arch\arm64\crypto\aes-modes.S#0287 3504 arch\arm64\crypto\aes-modes.S#0295 3505 arch\arm64\crypto\aes-modes.S#0298 3506 arch\arm64\crypto\aes-modes.S#0308 3507 arch\arm64\crypto\aes-modes.S#0326

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3508 arch\arm64\crypto\aes-modes.S#0328 3509 arch\arm64\crypto\aes-modes.S#0332 3510 arch\arm64\crypto\aes-modes.S#0333 3511 arch\arm64\crypto\aes-modes.S#0345 3512 arch\arm64\crypto\aes-modes.S#0350 3513 arch\arm64\crypto\aes-modes.S#0366 3514 arch\arm64\crypto\aes-modes.S#0369 3515 arch\arm64\crypto\aes-modes.S#0389 3516 arch\arm64\crypto\aes-neon.S#0012 Repo: a2c435cc9986 Ard Tue Oct 11 19:15:18 2016 +0100 Description: crypto: arm64/aes-neon - fix for big endian ------The AES implementation using pure NEON instructions relies on the generic AES key schedule generation routines, which store the round keys as arrays of 32-bit quantities stored in memory using native endianness. This means we should refer to these round keys using 4x4 loads rather than 16x1 loads. In addition, the ShiftRows tables are loading using a single scalar load, which is also affected by endianness, so emit these tables in the correct order depending on whether we are building for big endian or not.

Fixes: 49788fe2a128 ("arm64/crypto: AES-ECB/CBC/CTR/XTS using ARMv8 NEON and Crypto Extensions")

3517 arch\arm64\crypto\aes-neon.S#0087 3518 arch\arm64\crypto\aes-neon.S#0093 3519 arch\arm64\crypto\aes-neon.S#0233 3520 arch\arm64\crypto\aes-neon.S#0241 3521 arch\arm64\crypto\aes-neon.S#0258 3522 arch\arm64\crypto\aes-neon.S#0270 3523 arch\arm64\crypto\aes-neon.S#0310 3524 arch\arm64\crypto\aes-neon.S#0316 3525 arch\arm64\crypto\ghash-ce-core.S#0032 Repo: 9c433ad5083f Ard Tue Oct 11 19:15:14 2016 +0100 Description: crypto: arm64/ghash-ce - fix for big endian ------The GHASH key and digest are both pairs of 64-bit quantities, but the GHASH code does not always refer to them as such, causing failures when built for big endian. So replace the 16x1 loads and stores with 2x8 ones.

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Fixes: b913a6404ce2 ("arm64/crypto: improve performance of GHASH algorithm")

3526 arch\arm64\crypto\ghash-ce-core.S#0077 3527 arch\arm64\crypto\Kconfig#0011 Repo: 8fefde90e90c Ard Mon Dec 5 18:42:27 2016 +0000 Description: crypto: arm64/crc32 - accelerated support based on x86 SSE implementation ------This is a combination of the the Intel algorithm implemented using SSE and PCLMULQDQ instructions from arch/x86/crypto/crc32-pclmul_asm.S, and the new CRC32 extensions introduced for both 32-bit and 64-bit ARM in version 8 of the architecture. Two versions of the above combo are provided, one for CRC32 and one for CRC32C.

The PMULL/NEON algorithm is faster, but operates on blocks of at least 64 bytes, and on multiples of 16 bytes only. For the remaining input, or for all input on systems that lack the PMULL 64x64->128 instructions, the CRC32 instructions will be used.

crypto: arm64/crct10dif - port x86 SSE implementation to arm64 ------This is a transliteration of the Intel algorithm implemented using SSE and PCLMULQDQ instructions that resides in the file arch/x86/crypto/crct10dif-pcl-asm_64.S, but simplified to only operate on buffers that are 16 byte aligned (but of any size)

crypto: arm/aes - Select SIMD in Kconfig ------The skcipher conversion for ARM missed the select on CRYPTO_SIMD, causing build failures if SIMD was not otherwise enabled.

Fixes: da40e7a4ba4d ("crypto: aes-ce - Convert to skcipher") Fixes: 211f41af534a ("crypto: aesbs - Convert to skcipher")

crypto: arm64/sha2 - integrate OpenSSL implementations of SHA256/SHA512 ------This integrates both the accelerated scalar and the NEON implementations of SHA-224/256 as well as SHA-384/512 from the OpenSSL project.

Relative performance compared to the respective generic C versions:

| SHA256-scalar | SHA256-NEON* | SHA512 | ------+------+------+------+ Cortex-A53 | 1.63x | 1.63x | 2.34x | Cortex-A57 | 1.43x | 1.59x | 1.95x | Cortex-A73 | 1.26x | 1.56x | ? |

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The core crypto code was authored by Andy Polyakov of the OpenSSL project, in collaboration with whom the upstream code was adapted so that this module can be built from the same version of sha512-armv8.pl.

The version in this patch was taken from OpenSSL commit 32bbb62ea634 ("sha/asm/sha512-armv8.pl: fix big-endian support in __KERNEL__ case.")

* The core SHA algorithm is fundamentally sequential, but there is a secondary transformation involved, called the schedule update, which can be performed independently. The NEON version of SHA-224/SHA-256 only implements this part of the algorithm using NEON instructions, the sequential part is always done using scalar instructions.

3528 arch\arm64\crypto\Kconfig#0034 3529 arch\arm64\crypto\Kconfig#0061 3530 arch\arm64\crypto\Kconfig#0068 3531 arch\arm64\crypto\Kconfig#0074 3532 arch\arm64\crypto\Makefile#0020 Repo: 8fefde90e90c Ard Mon Dec 5 18:42:27 2016 +0000 Description: crypto: arm64/crc32 - accelerated support based on x86 SSE implementation ------This is a combination of the the Intel algorithm implemented using SSE and PCLMULQDQ instructions from arch/x86/crypto/crc32-pclmul_asm.S, and the new CRC32 extensions introduced for both 32-bit and 64-bit ARM in version 8 of the architecture. Two versions of the above combo are provided, one for CRC32 and one for CRC32C.

The PMULL/NEON algorithm is faster, but operates on blocks of at least 64 bytes, and on multiples of 16 bytes only. For the remaining input, or for all input on systems that lack the PMULL 64x64->128 instructions, the CRC32 instructions will be used.

crypto: arm64/crct10dif - port x86 SSE implementation to arm64 ------This is a transliteration of the Intel algorithm implemented using SSE and PCLMULQDQ instructions that resides in the file arch/x86/crypto/crct10dif-pcl-asm_64.S, but simplified to only operate on buffers that are 16 byte aligned (but of any size)

crypto: arm64/sha2 - integrate OpenSSL implementations of SHA256/SHA512 ------This integrates both the accelerated scalar and the NEON implementations

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of SHA-224/256 as well as SHA-384/512 from the OpenSSL project.

Relative performance compared to the respective generic C versions:

| SHA256-scalar | SHA256-NEON* | SHA512 | ------+------+------+------+ Cortex-A53 | 1.63x | 1.63x | 2.34x | Cortex-A57 | 1.43x | 1.59x | 1.95x | Cortex-A73 | 1.26x | 1.56x | ? |

The core crypto code was authored by Andy Polyakov of the OpenSSL project, in collaboration with whom the upstream code was adapted so that this module can be built from the same version of sha512-armv8.pl.

The version in this patch was taken from OpenSSL commit 32bbb62ea634 ("sha/asm/sha512-armv8.pl: fix big-endian support in __KERNEL__ case.")

* The core SHA algorithm is fundamentally sequential, but there is a secondary transformation involved, called the schedule update, which can be performed independently. The NEON version of SHA-224/SHA-256 only implements this part of the algorithm using NEON instructions, the sequential part is always done using scalar instructions.

3533 arch\arm64\crypto\Makefile#0038 3534 arch\arm64\crypto\Makefile#0055 3535 arch\arm64\crypto\sha1-ce-core.S#0081 Repo: ee71e5f1e7d2 Ard Tue Oct 11 19:15:15 2016 +0100 Description: crypto: arm64/sha1-ce - fix for big endian ------The SHA1 digest is an array of 5 32-bit quantities, so we should refer to them as such in order for this code to work correctly when built for big endian. So replace 16 byte scalar loads and stores with 4x4 vector ones where appropriate.

Fixes: 2c98833a42cd ("arm64/crypto: SHA-1 using ARMv8 Crypto Extensions")

3536 arch\arm64\crypto\sha1-ce-core.S#0147 3537 arch\arm64\crypto\sha2-ce-core.S#0088 Repo: 174122c39c36 Ard Tue Oct 11 19:15:16 2016 +0100 Description: crypto: arm64/sha2-ce - fix for big endian ------The SHA256 digest is an array of 8 32-bit quantities, so we should refer to them as such in order for this code to work correctly when built for big endian. So replace 16 byte scalar loads and stores with 4x32 vector ones where appropriate.

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Fixes: 6ba6c74dfc6b ("arm64/crypto: SHA-224/SHA-256 using ARMv8 Crypto Extensions")

3538 arch\arm64\crypto\sha2-ce-core.S#0151 3539 arch\arm64\crypto\.gitignore#newFile Repo: a4b15bed547a Ard Mon Nov 28 14:37:49 2016 +0100 Description: crypto: arm64/sha2 - add generated .S files to .gitignore ------Add the files that are generated by the recently merged OpenSSL SHA-256/512 implementation to .gitignore so Git disregards them when showing untracked files.

3540 arch\arm64\crypto\crc32-ce-core.S#newFile Repo: 8fefde90e90c Ard Mon Dec 5 18:42:27 2016 +0000 Description: crypto: arm64/crc32 - accelerated support based on x86 SSE implementation ------This is a combination of the the Intel algorithm implemented using SSE and PCLMULQDQ instructions from arch/x86/crypto/crc32-pclmul_asm.S, and the new CRC32 extensions introduced for both 32-bit and 64-bit ARM in version 8 of the architecture. Two versions of the above combo are provided, one for CRC32 and one for CRC32C.

The PMULL/NEON algorithm is faster, but operates on blocks of at least 64 bytes, and on multiples of 16 bytes only. For the remaining input, or for all input on systems that lack the PMULL 64x64->128 instructions, the CRC32 instructions will be used.

3541 arch\arm64\crypto\crc32-ce-glue.c#newFile Repo: 8fefde90e90c Ard Mon Dec 5 18:42:27 2016 +0000 Description: crypto: arm64/crc32 - accelerated support based on x86 SSE implementation ------This is a combination of the the Intel algorithm implemented using SSE and PCLMULQDQ instructions from arch/x86/crypto/crc32-pclmul_asm.S, and the new CRC32 extensions introduced for both 32-bit and 64-bit ARM in version 8 of the architecture. Two versions of the above combo are provided, one for CRC32 and one for CRC32C.

The PMULL/NEON algorithm is faster, but operates on blocks of at least 64 bytes, and on multiples of 16 bytes only. For the remaining input, or for all input on systems that lack the PMULL 64x64->128 instructions, the CRC32 instructions will be used.

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3542 arch\arm64\crypto\crct10dif-ce-core.S#newFile Repo: 6ef5737f3931 Ard Mon Dec 5 18:42:25 2016 +0000 Description: crypto: arm64/crct10dif - port x86 SSE implementation to arm64 ------This is a transliteration of the Intel algorithm implemented using SSE and PCLMULQDQ instructions that resides in the file arch/x86/crypto/crct10dif-pcl-asm_64.S, but simplified to only operate on buffers that are 16 byte aligned (but of any size)

3543 arch\arm64\crypto\crct10dif-ce-glue.c#newFile Repo: 6ef5737f3931 Ard Mon Dec 5 18:42:25 2016 +0000 Description: crypto: arm64/crct10dif - port x86 SSE implementation to arm64 ------This is a transliteration of the Intel algorithm implemented using SSE and PCLMULQDQ instructions that resides in the file arch/x86/crypto/crct10dif-pcl-asm_64.S, but simplified to only operate on buffers that are 16 byte aligned (but of any size)

3544 arch\arm64\crypto\sha256-core.S_shipped#newFile Repo: 7918ecef073f Ard Sun Nov 20 11:42:01 2016 +0000 Description: crypto: arm64/sha2 - integrate OpenSSL implementations of SHA256/SHA512 ------This integrates both the accelerated scalar and the NEON implementations of SHA-224/256 as well as SHA-384/512 from the OpenSSL project.

Relative performance compared to the respective generic C versions:

| SHA256-scalar | SHA256-NEON* | SHA512 | ------+------+------+------+ Cortex-A53 | 1.63x | 1.63x | 2.34x | Cortex-A57 | 1.43x | 1.59x | 1.95x | Cortex-A73 | 1.26x | 1.56x | ? |

The core crypto code was authored by Andy Polyakov of the OpenSSL project, in collaboration with whom the upstream code was adapted so that this module can be built from the same version of sha512-armv8.pl.

The version in this patch was taken from OpenSSL commit 32bbb62ea634 ("sha/asm/sha512-armv8.pl: fix big-endian support in __KERNEL__ case.")

* The core SHA algorithm is fundamentally sequential, but there is a secondary transformation involved, called the schedule update, which can be performed independently. The NEON version of SHA-224/SHA-256 only implements this part of the algorithm using NEON instructions,

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the sequential part is always done using scalar instructions.

3545 arch\arm64\crypto\sha256-glue.c#newFile Repo: 7918ecef073f Ard Sun Nov 20 11:42:01 2016 +0000 Description: crypto: arm64/sha2 - integrate OpenSSL implementations of SHA256/SHA512 ------This integrates both the accelerated scalar and the NEON implementations of SHA-224/256 as well as SHA-384/512 from the OpenSSL project.

Relative performance compared to the respective generic C versions:

| SHA256-scalar | SHA256-NEON* | SHA512 | ------+------+------+------+ Cortex-A53 | 1.63x | 1.63x | 2.34x | Cortex-A57 | 1.43x | 1.59x | 1.95x | Cortex-A73 | 1.26x | 1.56x | ? |

The core crypto code was authored by Andy Polyakov of the OpenSSL project, in collaboration with whom the upstream code was adapted so that this module can be built from the same version of sha512-armv8.pl.

The version in this patch was taken from OpenSSL commit 32bbb62ea634 ("sha/asm/sha512-armv8.pl: fix big-endian support in __KERNEL__ case.")

* The core SHA algorithm is fundamentally sequential, but there is a secondary transformation involved, called the schedule update, which can be performed independently. The NEON version of SHA-224/SHA-256 only implements this part of the algorithm using NEON instructions, the sequential part is always done using scalar instructions.

3546 arch\arm64\crypto\sha512-armv8.pl#newFile Repo: 7918ecef073f Ard Sun Nov 20 11:42:01 2016 +0000 Description: crypto: arm64/sha2 - integrate OpenSSL implementations of SHA256/SHA512 ------This integrates both the accelerated scalar and the NEON implementations of SHA-224/256 as well as SHA-384/512 from the OpenSSL project.

Relative performance compared to the respective generic C versions:

| SHA256-scalar | SHA256-NEON* | SHA512 | ------+------+------+------+ Cortex-A53 | 1.63x | 1.63x | 2.34x | Cortex-A57 | 1.43x | 1.59x | 1.95x | Cortex-A73 | 1.26x | 1.56x | ? |

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The core crypto code was authored by Andy Polyakov of the OpenSSL project, in collaboration with whom the upstream code was adapted so that this module can be built from the same version of sha512-armv8.pl.

The version in this patch was taken from OpenSSL commit 32bbb62ea634 ("sha/asm/sha512-armv8.pl: fix big-endian support in __KERNEL__ case.")

* The core SHA algorithm is fundamentally sequential, but there is a secondary transformation involved, called the schedule update, which can be performed independently. The NEON version of SHA-224/SHA-256 only implements this part of the algorithm using NEON instructions, the sequential part is always done using scalar instructions.

3547 arch\arm64\crypto\sha512-core.S_shipped#newFile Repo: 7918ecef073f Ard Sun Nov 20 11:42:01 2016 +0000 Description: crypto: arm64/sha2 - integrate OpenSSL implementations of SHA256/SHA512 ------This integrates both the accelerated scalar and the NEON implementations of SHA-224/256 as well as SHA-384/512 from the OpenSSL project.

Relative performance compared to the respective generic C versions:

| SHA256-scalar | SHA256-NEON* | SHA512 | ------+------+------+------+ Cortex-A53 | 1.63x | 1.63x | 2.34x | Cortex-A57 | 1.43x | 1.59x | 1.95x | Cortex-A73 | 1.26x | 1.56x | ? |

The core crypto code was authored by Andy Polyakov of the OpenSSL project, in collaboration with whom the upstream code was adapted so that this module can be built from the same version of sha512-armv8.pl.

The version in this patch was taken from OpenSSL commit 32bbb62ea634 ("sha/asm/sha512-armv8.pl: fix big-endian support in __KERNEL__ case.")

* The core SHA algorithm is fundamentally sequential, but there is a secondary transformation involved, called the schedule update, which can be performed independently. The NEON version of SHA-224/SHA-256 only implements this part of the algorithm using NEON instructions, the sequential part is always done using scalar instructions.

3548 arch\arm64\crypto\sha512-glue.c#newFile Repo: 7918ecef073f Ard Sun Nov 20 11:42:01 2016 +0000 Description: crypto: arm64/sha2 - integrate OpenSSL implementations of SHA256/SHA512 ------

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This integrates both the accelerated scalar and the NEON implementations of SHA-224/256 as well as SHA-384/512 from the OpenSSL project.

Relative performance compared to the respective generic C versions:

| SHA256-scalar | SHA256-NEON* | SHA512 | ------+------+------+------+ Cortex-A53 | 1.63x | 1.63x | 2.34x | Cortex-A57 | 1.43x | 1.59x | 1.95x | Cortex-A73 | 1.26x | 1.56x | ? |

The core crypto code was authored by Andy Polyakov of the OpenSSL project, in collaboration with whom the upstream code was adapted so that this module can be built from the same version of sha512-armv8.pl.

The version in this patch was taken from OpenSSL commit 32bbb62ea634 ("sha/asm/sha512-armv8.pl: fix big-endian support in __KERNEL__ case.")

* The core SHA algorithm is fundamentally sequential, but there is a secondary transformation involved, called the schedule update, which can be performed independently. The NEON version of SHA-224/SHA-256 only implements this part of the algorithm using NEON instructions, the sequential part is always done using scalar instructions.

arch\arm64\include\asm\ 3549 arch\arm64\include\asm\acpi.h#0020 Repo: c8e008e2a6f9 Rafael J. Thu Dec 22 14:34:24 2016 +0100 Description: Merge branches 'acpica' and 'acpi-scan' ------* acpica: ACPI / osl: Remove deprecated acpi_get_table_with_size()/early_acpi_os_unmap_memory() ACPI / osl: Remove acpi_get_table_with_size()/early_acpi_os_unmap_memory() users ACPICA: Tables: Allow FADT to be customized with virtual address ACPICA: Tables: Back port acpi_get_table_with_size() and early_acpi_os_unmap_memory() from Linux kernel

* acpi-scan: ACPI: do not warn if _BQC does not exist

ACPI / osl: Remove deprecated acpi_get_table_with_size()/early_acpi_os_unmap_memory() ------Since all users are cleaned up, remove the 2 deprecated APIs due to no users. As a Linux variable rather than an ACPICA variable, acpi_gbl_permanent_mmap

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is renamed to acpi_permanent_mmap to have a consistent coding style across entire Linux ACPI subsystem.

ACPI / APEI / ARM64: APEI initial support for ARM64 ------This patch provides APEI arch-specific bits for ARM64

Meanwhile, (1) Move HEST type (ACPI_HEST_TYPE_IA32_CORRECTED_CHECK) checking to a generic place. (2) Select HAVE_ACPI_APEI when EFI and ACPI is set on ARM64, because arch_apei_get_mem_attribute is using efi_mem_attributes() on ARM64.

3550 arch\arm64\include\asm\acpi.h#0032 Review: COMMENT stecan Thu, 11 Jan 2018 07:26:57 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:57 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:26:57 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:57 +0100 Automatic commented! 3551 arch\arm64\include\asm\acpi.h#0118 3552 arch\arm64\include\asm\acpi.h#0127 3553 arch\arm64\include\asm\acpi.h#0128 3554 arch\arm64\include\asm\arch_gicv3.h#0082 Repo: 0968a61918a9 Vladimir Wed Nov 2 11:54:06 2016 +0000 Description: irqchip/gic-v3-its: Specialise readq and writeq accesses ------readq and writeq type of assessors are not supported in AArch32, so we need to specialise them and glue later with series of 32-bit accesses on AArch32 side.

irqchip/gic-v3-its: Specialise flush_dcache operation ------It'd be better to switch to CMA... but before that done redirect flush_dcache operation, so 32-bit implementation could be wired latter.

irqchip/gic-v3: Use nops macro for Cavium ThunderX erratum 23154

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------The workaround for Cavium ThunderX erratum 23154 has a pipeflush built out of NOP sequences around the read of the IAR.

This patch converts the code to use the new nops macro, which makes it a little easier to read.

irqchip/gic-v3: Convert arm64 GIC accessors to {read,write}_sysreg_s ------The GIC system registers are accessed using open-coded wrappers around the mrs_s/msr_s asm macros.

This patch moves the code over to the {read,wrote}_sysreg_s accessors instead, reducing the amount of explicit asm blocks in the arch headers.

3555 arch\arm64\include\asm\arch_gicv3.h#0084 3556 arch\arm64\include\asm\arch_gicv3.h#0090 3557 arch\arm64\include\asm\arch_gicv3.h#0105 3558 arch\arm64\include\asm\arch_gicv3.h#0111 3559 arch\arm64\include\asm\arch_gicv3.h#0119 3560 arch\arm64\include\asm\arch_gicv3.h#0135 3561 arch\arm64\include\asm\arch_gicv3.h#0148 3562 arch\arm64\include\asm\arch_gicv3.h#0153 3563 arch\arm64\include\asm\arch_gicv3.h#0159 3564 arch\arm64\include\asm\arch_gicv3.h#0165 3565 arch\arm64\include\asm\arch_gicv3.h#0170 3566 arch\arm64\include\asm\arch_gicv3.h#0178 3567 arch\arm64\include\asm\arch_gicv3.h#0190 3568 arch\arm64\include\asm\assembler.h#0044 Repo: 41c066f2c4d4 Ard Wed Jan 11 14:54:53 2017 +0000 Description: arm64: assembler: make adr_l work in modules under KASLR ------When CONFIG_RANDOMIZE_MODULE_REGION_FULL=y, the offset between loaded modules and the core kernel may exceed 4 GB, putting symbols exported by the core kernel out of the reach of the ordinary adrp/add instruction pairs used to generate relative symbol references. So make the adr_l macro emit a movz/movk sequence instead when executing in module context.

While at it, remove the pointless special case for the stack pointer.

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arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1 ------This patch adds the uaccess macros/functions to disable access to user space by setting TTBR0_EL1 to a reserved zeroed page. Since the value written to TTBR0_EL1 must be a physical address, for simplicity this patch introduces a reserved_ttbr0 page at a constant offset from swapper_pg_dir. The uaccess_disable code uses the ttbr1_el1 value adjusted by the reserved_ttbr0 offset.

Enabling access to user is done by restoring TTBR0_EL1 with the value from the struct thread_info ttbr0 variable. Interrupts must be disabled during the uaccess_ttbr0_enable code to ensure the atomicity of the thread_info.ttbr0 read and TTBR0_EL1 write. This patch also moves the get_thread_info asm macro from entry.S to assembler.h for reuse in the uaccess_ttbr0_* macros.

arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro ------This patch takes the errata workaround code out of cpu_do_switch_mm into a dedicated post_ttbr0_update_workaround macro which will be reused in a subsequent patch.

arm64: assembler: introduce ldr_this_cpu ------Shortly we will want to load a percpu variable in the return from userspace path. We can save an instruction by folding the addition of the percpu offset into the load instruction, and this patch adds a new helper to do so.

At the same time, we clean up this_cpu_ptr for consistency. As with {adr,ldr,str}_l, we change the template to take the destination register first, and name this dst. Secondly, we rename the macro to adr_this_cpu, following the scheme of adr_l, and matching the newly added ldr_this_cpu.

arm64: barriers: introduce nops and __nops macros for NOP sequences ------NOP sequences tend to get used for padding out alternative sections and uarch-specific pipeline flushes in errata workarounds.

This patch adds macros for generating these sequences as both inline asm blocks, but also as strings suitable for embedding in other asm blocks directly.

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arm64: Work around systems with mismatched cache line sizes ------Systems with differing CPU i-cache/d-cache line sizes can cause problems with the cache management by software when the execution is migrated from one to another. Usually, the application reads the cache size on a CPU and then uses that length to perform cache operations. However, if it gets migrated to another CPU with a smaller cache line size, things could go completely wrong. To prevent such cases, always use the smallest cache line size among the CPUs. The kernel CPU feature infrastructure already keeps track of the safe value for all CPUID registers including CTR. This patch works around the problem by :

For kernel, dynamically patch the kernel to read the cache size from the system wide copy of CTR_EL0.

For applications, trap read accesses to CTR_EL0 (by clearing the SCTLR.UCT) and emulate the mrs instruction to return the system wide safe value of CTR_EL0.

For faster access (i.e, avoiding to lookup the system wide value of CTR_EL0 via read_system_reg), we keep track of the pointer to table entry for CTR_EL0 in the CPU feature infrastructure.

3569 arch\arm64\include\asm\assembler.h#0167 Review: COMMENT stecan Thu, 11 Jan 2018 07:26:57 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:57 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:26:57 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:57 +0100 Automatic commented! 3570 arch\arm64\include\asm\assembler.h#0175 Review: COMMENT stecan Thu, 11 Jan 2018 07:26:57 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:57 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:26:57 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:57 +0100 Automatic commented!

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3571 arch\arm64\include\asm\assembler.h#0176 3572 arch\arm64\include\asm\assembler.h#0180 3573 arch\arm64\include\asm\assembler.h#0196 3574 arch\arm64\include\asm\assembler.h#0204 3575 arch\arm64\include\asm\assembler.h#0222 3576 arch\arm64\include\asm\assembler.h#0225 3577 arch\arm64\include\asm\assembler.h#0232 Review: COMMENT stecan Thu, 11 Jan 2018 07:26:57 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:57 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:26:57 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:57 +0100 Automatic commented! 3578 arch\arm64\include\asm\assembler.h#0234 Review: COMMENT stecan Thu, 11 Jan 2018 07:26:57 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:57 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:26:57 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:57 +0100 Automatic commented! 3579 arch\arm64\include\asm\assembler.h#0236 3580 arch\arm64\include\asm\assembler.h#0239 3581 arch\arm64\include\asm\assembler.h#0242 3582 arch\arm64\include\asm\assembler.h#0436 3583 arch\arm64\include\asm\cacheflush.h#0068 Repo: ee6a7fce8e5e Catalin Wed Nov 23 18:05:52 2016 +0000 Description: arm64: Remove I-cache invalidation from flush_cache_range() ------The flush_cache_range() function (similarly for flush_cache_page()) is called when the kernel is changing an existing VA->PA mapping range to either a new PA or to different attributes. Since ARMv8 has PIPT-like D-caches, this function does not need to perform any D-cache maintenance. The I-cache maintenance is already handled via set_pte_at() and flush_cache_range() cannot anyway guarantee that there are no cache

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lines left after invalidation due to the speculative loads.

This patch makes flush_cache_range() a no-op.

arm64: Add uprobe support ------This patch adds support for uprobe on ARM64 architecture.

Unit tests for following have been done so far and they have been found working 1. Step-able instructions, like sub, ldr, add etc. 2. Simulation-able like ret, cbnz, cbz etc. 3. uretprobe 4. Reject-able instructions like sev, wfe etc. 5. trapped and abort xol path 6. probe at unaligned user address. 7. longjump test cases

Currently it does not support aarch32 instruction probing.

3584 arch\arm64\include\asm\cacheflush.h#0074 3585 arch\arm64\include\asm\cacheflush.h#0084 3586 arch\arm64\include\asm\cpucaps.h#0037 Repo: f4000cd99750 Linus Tue Dec 13 16:39:21 2016 -0800 Description: Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux ------Pull arm64 updates from Catalin Marinas:

- struct thread_info moved off-stack (also touching include/linux/thread_info.h and include/linux/restart_block.h)

- cpus_have_cap() reworked to avoid __builtin_constant_p() for static key use (also touching drivers/irqchip/irq-gic-v3.c)

- uprobes support (currently only for native 64-bit tasks)

- Emulation of kernel Privileged Access Never (PAN) using TTBR0_EL1 switching to a reserved page table

- CPU capacity information passing via DT or sysfs (used by the scheduler)

- support for systems without FP/SIMD (IOW, kernel avoids touching these registers; there is no soft-float ABI, nor kernel emulation for AArch64 FP/SIMD)

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- handling of hardware watchpoint with unaligned addresses, varied lengths and offsets from base

- use of the page table contiguous hint for kernel mappings

- hugetlb fixes for sizes involving the contiguous hint

- remove unnecessary I-cache invalidation in flush_cache_range()

- CNTHCTL_EL2 access fix for CPUs with VHE support (ARMv8.1)

- boot-time checks for writable+executable kernel mappings

- simplify asm/opcodes.h and avoid including the 32-bit ARM counterpart and make the arm64 kernel headers self-consistent (Xen headers patch merged separately)

- Workaround for broken .inst support in certain binutils versions

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (60 commits) arm64: Disable PAN on uaccess_enable() arm64: Work around broken .inst when defective gas is detected arm64: Add detection code for broken .inst support in binutils arm64: Remove reference to asm/opcodes.h arm64: Get rid of asm/opcodes.h arm64: smp: Prevent raw_smp_processor_id() recursion arm64: head.S: Fix CNTHCTL_EL2 access on VHE system arm64: Remove I-cache invalidation from flush_cache_range() arm64: Enable HIBERNATION in defconfig arm64: Enable CONFIG_ARM64_SW_TTBR0_PAN arm64: xen: Enable user access before a privcmd hvc call arm64: Handle faults caused by inadvertent user access with PAN enabled arm64: Disable TTBR0_EL1 during normal kernel execution arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1 arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro arm64: Factor out PAN enabling/disabling into separate uaccess_* macros arm64: Update the synchronous external abort fault description selftests: arm64: add test for unaligned/inexact watchpoint handling arm64: Allow hw watchpoint of length 3,5,6 and 7 arm64: hw_breakpoint: Handle inexact watchpoint addresses ...

3587 arch\arm64\include\asm\cpucaps.h#0039

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3588 arch\arm64\include\asm\cpufeature.h#0012 Repo: f4000cd99750 Linus Tue Dec 13 16:39:21 2016 -0800 Description: Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux ------Pull arm64 updates from Catalin Marinas:

- struct thread_info moved off-stack (also touching include/linux/thread_info.h and include/linux/restart_block.h)

- cpus_have_cap() reworked to avoid __builtin_constant_p() for static key use (also touching drivers/irqchip/irq-gic-v3.c)

- uprobes support (currently only for native 64-bit tasks)

- Emulation of kernel Privileged Access Never (PAN) using TTBR0_EL1 switching to a reserved page table

- CPU capacity information passing via DT or sysfs (used by the scheduler)

- support for systems without FP/SIMD (IOW, kernel avoids touching these registers; there is no soft-float ABI, nor kernel emulation for AArch64 FP/SIMD)

- handling of hardware watchpoint with unaligned addresses, varied lengths and offsets from base

- use of the page table contiguous hint for kernel mappings

- hugetlb fixes for sizes involving the contiguous hint

- remove unnecessary I-cache invalidation in flush_cache_range()

- CNTHCTL_EL2 access fix for CPUs with VHE support (ARMv8.1)

- boot-time checks for writable+executable kernel mappings

- simplify asm/opcodes.h and avoid including the 32-bit ARM counterpart and make the arm64 kernel headers self-consistent (Xen headers patch merged separately)

- Workaround for broken .inst support in certain binutils versions

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (60 commits) arm64: Disable PAN on uaccess_enable() arm64: Work around broken .inst when defective gas is detected arm64: Add detection code for broken .inst support in binutils arm64: Remove reference to asm/opcodes.h

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arm64: Get rid of asm/opcodes.h arm64: smp: Prevent raw_smp_processor_id() recursion arm64: head.S: Fix CNTHCTL_EL2 access on VHE system arm64: Remove I-cache invalidation from flush_cache_range() arm64: Enable HIBERNATION in defconfig arm64: Enable CONFIG_ARM64_SW_TTBR0_PAN arm64: xen: Enable user access before a privcmd hvc call arm64: Handle faults caused by inadvertent user access with PAN enabled arm64: Disable TTBR0_EL1 during normal kernel execution arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1 arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro arm64: Factor out PAN enabling/disabling into separate uaccess_* macros arm64: Update the synchronous external abort fault description selftests: arm64: add test for unaligned/inexact watchpoint handling arm64: Allow hw watchpoint of length 3,5,6 and 7 arm64: hw_breakpoint: Handle inexact watchpoint addresses ...

arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1 ------This patch adds the uaccess macros/functions to disable access to user space by setting TTBR0_EL1 to a reserved zeroed page. Since the value written to TTBR0_EL1 must be a physical address, for simplicity this patch introduces a reserved_ttbr0 page at a constant offset from swapper_pg_dir. The uaccess_disable code uses the ttbr1_el1 value adjusted by the reserved_ttbr0 offset.

Enabling access to user is done by restoring TTBR0_EL1 with the value from the struct thread_info ttbr0 variable. Interrupts must be disabled during the uaccess_ttbr0_enable code to ensure the atomicity of the thread_info.ttbr0 read and TTBR0_EL1 write. This patch also moves the get_thread_info asm macro from entry.S to assembler.h for reuse in the uaccess_ttbr0_* macros.

arm64: Support systems without FP/ASIMD ------The arm64 kernel assumes that FP/ASIMD units are always present and accesses the FP/ASIMD specific registers unconditionally. This could cause problems when they are absent. This patch adds the support for kernel handling systems without FP/ASIMD by skipping the register access within the kernel. For kvm, we trap the accesses to FP/ASIMD and inject an undefined instruction exception to the VM.

The callers of the exported kernel_neon_begin_partial() should make sure that the FP/ASIMD is supported.

arm64: Add hypervisor safe helper for checking constant capabilities

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------The hypervisor may not have full access to the kernel data structures and hence cannot safely use cpus_have_cap() helper for checking the system capability. Add a safe helper for to check a constant system capability, which *doesn't* fall back to checking the bitmap maintained by the kernel. With this, make the cpus_have_cap() only check the bitmask and force constant cap checks to use the new API for quicker checks.

3589 arch\arm64\include\asm\cpufeature.h#0030 3590 arch\arm64\include\asm\cpufeature.h#0107 3591 arch\arm64\include\asm\cpufeature.h#0119 3592 arch\arm64\include\asm\cpufeature.h#0208 3593 arch\arm64\include\asm\cpufeature.h#0216 3594 arch\arm64\include\asm\debug-monitors.h#0071 Repo: 9842ceae9fa8 Pratyush Wed Nov 2 14:40:46 2016 +0530 Description: arm64: Add uprobe support ------This patch adds support for uprobe on ARM64 architecture.

Unit tests for following have been done so far and they have been found working 1. Step-able instructions, like sub, ldr, add etc. 2. Simulation-able like ret, cbnz, cbz etc. 3. uretprobe 4. Reject-able instructions like sev, wfe etc. 5. trapped and abort xol path 6. probe at unaligned user address. 7. longjump test cases

Currently it does not support aarch32 instruction probing.

3595 arch\arm64\include\asm\efi.h#0004 Repo: f4000cd99750 Linus Tue Dec 13 16:39:21 2016 -0800 Description: Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux ------Pull arm64 updates from Catalin Marinas:

- struct thread_info moved off-stack (also touching include/linux/thread_info.h and include/linux/restart_block.h)

- cpus_have_cap() reworked to avoid __builtin_constant_p() for static key use (also touching drivers/irqchip/irq-gic-v3.c)

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- uprobes support (currently only for native 64-bit tasks)

- Emulation of kernel Privileged Access Never (PAN) using TTBR0_EL1 switching to a reserved page table

- CPU capacity information passing via DT or sysfs (used by the scheduler)

- support for systems without FP/SIMD (IOW, kernel avoids touching these registers; there is no soft-float ABI, nor kernel emulation for AArch64 FP/SIMD)

- handling of hardware watchpoint with unaligned addresses, varied lengths and offsets from base

- use of the page table contiguous hint for kernel mappings

- hugetlb fixes for sizes involving the contiguous hint

- remove unnecessary I-cache invalidation in flush_cache_range()

- CNTHCTL_EL2 access fix for CPUs with VHE support (ARMv8.1)

- boot-time checks for writable+executable kernel mappings

- simplify asm/opcodes.h and avoid including the 32-bit ARM counterpart and make the arm64 kernel headers self-consistent (Xen headers patch merged separately)

- Workaround for broken .inst support in certain binutils versions

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (60 commits) arm64: Disable PAN on uaccess_enable() arm64: Work around broken .inst when defective gas is detected arm64: Add detection code for broken .inst support in binutils arm64: Remove reference to asm/opcodes.h arm64: Get rid of asm/opcodes.h arm64: smp: Prevent raw_smp_processor_id() recursion arm64: head.S: Fix CNTHCTL_EL2 access on VHE system arm64: Remove I-cache invalidation from flush_cache_range() arm64: Enable HIBERNATION in defconfig arm64: Enable CONFIG_ARM64_SW_TTBR0_PAN arm64: xen: Enable user access before a privcmd hvc call arm64: Handle faults caused by inadvertent user access with PAN enabled arm64: Disable TTBR0_EL1 during normal kernel execution arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1 arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro arm64: Factor out PAN enabling/disabling into separate uaccess_* macros

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arm64: Update the synchronous external abort fault description selftests: arm64: add test for unaligned/inexact watchpoint handling arm64: Allow hw watchpoint of length 3,5,6 and 7 arm64: hw_breakpoint: Handle inexact watchpoint addresses ...

arm64: Disable TTBR0_EL1 during normal kernel execution ------When the TTBR0 PAN feature is enabled, the kernel entry points need to disable access to TTBR0_EL1. The PAN status of the interrupted context is stored as part of the saved pstate, reusing the PSR_PAN_BIT (22). Restoring access to TTBR0_EL1 is done on exception return if returning to user or returning to a context where PAN was disabled.

Context switching via switch_mm() must defer the update of TTBR0_EL1 until a return to user or an explicit uaccess_enable() call.

Special care needs to be taken for two cases where TTBR0_EL1 is set outside the normal kernel operation: EFI run-time services (via efi_set_pgd) and CPU suspend (via cpu_(un)install_idmap). Code has been added to avoid deferred TTBR0_EL1 switching as in switch_mm() and restore the reserved TTBR0_EL1 when uninstalling the special TTBR0_EL1.

User cache maintenance (user_cache_maint_handler and __flush_cache_user_range) needs the TTBR0_EL1 re-instated since the operations are performed by user virtual address.

This patch also removes a stale comment on the switch_mm() function.

efi: Allow bitness-agnostic protocol calls ------We already have a macro to invoke boot services which on x86 adapts automatically to the bitness of the EFI firmware: efi_call_early().

The macro allows sharing of functions across arches and bitness variants as long as those functions only call boot services. However in practice functions in the EFI stub contain a mix of boot services calls and protocol calls.

Add an efi_call_proto() macro for bitness-agnostic protocol calls to allow sharing more code across arches as well as deduplicating 32 bit and 64 bit code paths.

On x86, implement it using a new efi_table_attr() macro for bitness- agnostic table lookups. Refactor efi_call_early() to make use of the same macro. (The resulting object code remains identical.)

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3596 arch\arm64\include\asm\efi.h#0055 3597 arch\arm64\include\asm\efi.h#0082 3598 arch\arm64\include\asm\elf.h#0141 Repo: 06beb72fbe23 Pratyush Wed Nov 2 14:40:45 2016 +0530 Description: arm64: introduce mm context flag to keep 32 bit task information ------We need to decide in some cases like uprobe instruction analysis that whether the current mm context belongs to a 32 bit task or 64 bit.

This patch has introduced an unsigned flag variable in mm_context_t. Currently, we set and clear TIF_32BIT depending on the condition that whether an elf binary load sets personality for 32 bit or 64 bit respectively.

3599 arch\arm64\include\asm\elf.h#0190 3600 arch\arm64\include\asm\.h#0024 Repo: bd38967d406f Catalin Fri Jul 1 14:58:21 2016 +0100 Description: arm64: Factor out PAN enabling/disabling into separate uaccess_* macros ------This patch moves the directly coded alternatives for turning PAN on/off into separate uaccess_{enable,disable} macros or functions. The asm macros take a few arguments which will be used in subsequent patches.

Note that any (unlikely) access that the compiler might generate between uaccess_enable() and uaccess_disable(), other than those explicitly specified by the user access code, will not be protected by PAN.

arm64: switch to relative exception tables ------Instead of using absolute addresses for both the exception location and the fixup, use offsets relative to the exception table entry values. Not only does this cut the size of the exception table in half, it is also a prerequisite for KASLR, since absolute exception table entries are subject to dynamic relocation, which is incompatible with the sorting of the exception table that occurs at build time.

This patch also introduces the _ASM_EXTABLE preprocessor macro (which exists on x86 as well) and its _asm_extable assembly counterpart, as shorthands to emit exception table entries.

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3601 arch\arm64\include\asm\futex.h#0027 3602 arch\arm64\include\asm\futex.h#0030 3603 arch\arm64\include\asm\futex.h#0031 3604 arch\arm64\include\asm\futex.h#0047 3605 arch\arm64\include\asm\futex.h#0051 3606 arch\arm64\include\asm\futex.h#0121 3607 arch\arm64\include\asm\futex.h#0122 3608 arch\arm64\include\asm\futex.h#0137 3609 arch\arm64\include\asm\futex.h#0141 3610 arch\arm64\include\asm\hw_breakpoint.h#0080 Repo: 0ddb8e0b784b Pratyush Mon Nov 14 19:32:45 2016 +0530 Description: arm64: Allow hw watchpoint of length 3,5,6 and 7 ------Since, arm64 can support all offset within a double word limit. Therefore, now support other lengths within that range as well.

arm64: Allow hw watchpoint at varied offset from base address ------ARM64 hardware supports watchpoint at any double word aligned address. However, it can select any consecutive bytes from offset 0 to 7 from that base address. For example, if base address is programmed as 0x420030 and byte select is 0x1C, then access of 0x420032,0x420033 and 0x420034 will generate a watchpoint exception.

Currently, we do not have such modularity. We can only program byte, halfword, word and double word access exception from any base address.

This patch adds support to overcome above limitations.

3611 arch\arm64\include\asm\hw_breakpoint.h#0082 3612 arch\arm64\include\asm\hw_breakpoint.h#0126 3613 arch\arm64\include\asm\io.h#0025 Repo: fe8ecc86fa83 Christoph Tue Nov 1 07:40:14 2016 -0600 Description: arm, arm64: don't include blk_types.h in ------No need for it - we only use struct bio_vec in prototypes and already have forward declarations for it.

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3614 arch\arm64\include\asm\Kbuild#0004 Repo: f4000cd99750 Linus Tue Dec 13 16:39:21 2016 -0800 Description: Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux ------Pull arm64 updates from Catalin Marinas:

- struct thread_info moved off-stack (also touching include/linux/thread_info.h and include/linux/restart_block.h)

- cpus_have_cap() reworked to avoid __builtin_constant_p() for static key use (also touching drivers/irqchip/irq-gic-v3.c)

- uprobes support (currently only for native 64-bit tasks)

- Emulation of kernel Privileged Access Never (PAN) using TTBR0_EL1 switching to a reserved page table

- CPU capacity information passing via DT or sysfs (used by the scheduler)

- support for systems without FP/SIMD (IOW, kernel avoids touching these registers; there is no soft-float ABI, nor kernel emulation for AArch64 FP/SIMD)

- handling of hardware watchpoint with unaligned addresses, varied lengths and offsets from base

- use of the page table contiguous hint for kernel mappings

- hugetlb fixes for sizes involving the contiguous hint

- remove unnecessary I-cache invalidation in flush_cache_range()

- CNTHCTL_EL2 access fix for CPUs with VHE support (ARMv8.1)

- boot-time checks for writable+executable kernel mappings

- simplify asm/opcodes.h and avoid including the 32-bit ARM counterpart and make the arm64 kernel headers self-consistent (Xen headers patch merged separately)

- Workaround for broken .inst support in certain binutils versions

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (60 commits) arm64: Disable PAN on uaccess_enable() arm64: Work around broken .inst when defective gas is detected arm64: Add detection code for broken .inst support in binutils arm64: Remove reference to asm/opcodes.h

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arm64: Get rid of asm/opcodes.h arm64: smp: Prevent raw_smp_processor_id() recursion arm64: head.S: Fix CNTHCTL_EL2 access on VHE system arm64: Remove I-cache invalidation from flush_cache_range() arm64: Enable HIBERNATION in defconfig arm64: Enable CONFIG_ARM64_SW_TTBR0_PAN arm64: xen: Enable user access before a privcmd hvc call arm64: Handle faults caused by inadvertent user access with PAN enabled arm64: Disable TTBR0_EL1 during normal kernel execution arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1 arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro arm64: Factor out PAN enabling/disabling into separate uaccess_* macros arm64: Update the synchronous external abort fault description selftests: arm64: add test for unaligned/inexact watchpoint handling arm64: Allow hw watchpoint of length 3,5,6 and 7 arm64: hw_breakpoint: Handle inexact watchpoint addresses ...

arm64: split thread_info from task stack ------This patch moves arm64's struct thread_info from the task stack into task_struct. This protects thread_info from corruption in the case of stack overflows, and makes its address harder to determine if stack addresses are leaked, making a number of attacks more difficult. Precise detection and handling of overflow is left for subsequent patches.

Largely, this involves changing code to store the task_struct in sp_el0, and acquire the thread_info from the task struct. Core code now implements current_thread_info(), and as noted in this relies on offsetof(task_struct, thread_info) == 0, enforced by core code.

This change means that the 'tsk' register used in entry.S now points to a task_struct, rather than a thread_info as it used to. To make this clear, the TI_* field offsets are renamed to TSK_TI_*, with asm-offsets appropriately updated to account for the structural change.

Userspace clobbers sp_el0, and we can no longer restore this from the stack. Instead, the current task is cached in a per-cpu variable that we can safely access from early assembly as interrupts are disabled (and we are thus not preemptible).

Both secondary entry and idle are updated to stash the sp and task pointer separately.

locking/mutex: Kill arch specific code ------Its all generic atomic_long_t stuff now.

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Review der Linux Kernel Sourcen von 4.9 auf 4.10

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3615 arch\arm64\include\asm\Kbuild#0027 3616 arch\arm64\include\asm\kernel-pgtable.h#0022 Repo: 4b65a5db3627 Catalin Fri Jul 1 16:53:00 2016 +0100 Description: arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1 ------This patch adds the uaccess macros/functions to disable access to user space by setting TTBR0_EL1 to a reserved zeroed page. Since the value written to TTBR0_EL1 must be a physical address, for simplicity this patch introduces a reserved_ttbr0 page at a constant offset from swapper_pg_dir. The uaccess_disable code uses the ttbr1_el1 value adjusted by the reserved_ttbr0 offset.

Enabling access to user is done by restoring TTBR0_EL1 with the value from the struct thread_info ttbr0 variable. Interrupts must be disabled during the uaccess_ttbr0_enable code to ensure the atomicity of the thread_info.ttbr0 read and TTBR0_EL1 write. This patch also moves the get_thread_info asm macro from entry.S to assembler.h for reuse in the uaccess_ttbr0_* macros.

3617 arch\arm64\include\asm\kernel-pgtable.h#0058 3618 arch\arm64\include\asm\memory.h#0168 Repo: 1c8a946bf375 Oleksandr Wed Jan 18 09:09:25 2017 +0200 Description: arm64: mm: avoid name clash in __page_to_voff() ------The arm64 __page_to_voff() macro takes a parameter called 'page', and also refers to 'struct page'. Thus, if the value passed in is not called 'page', we'll refer to the wrong struct name (which might not exist).

Fixes: 3fa72fe9c614 ("arm64: mm: fix __page_to_voff definition")

arm64: setup: introduce kaslr_offset() ------Introduce kaslr_offset() similar to x86_64 to fix kcov.

[ Updated by Will Deacon ]

Link: http://lkml.kernel.org/r/[email protected]

3619 arch\arm64\include\asm\memory.h#0225 3620 arch\arm64\include\asm\mmu.h#0022 Repo: 06beb72fbe23 Pratyush Wed Nov 2 14:40:45 2016 +0530 Description: arm64: introduce mm context flag to keep 32 bit task information ------

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We need to decide in some cases like uprobe instruction analysis that whether the current mm context belongs to a 32 bit task or 64 bit.

This patch has introduced an unsigned flag variable in mm_context_t. Currently, we set and clear TIF_32BIT depending on the condition that whether an elf binary load sets personality for 32 bit or 64 bit respectively.

arm64: mm: replace 'block_mappings_allowed' with 'page_mappings_only' ------In preparation of adding support for contiguous PTE and PMD mappings, let's replace 'block_mappings_allowed' with 'page_mappings_only', which will be a more accurate description of the nature of the setting once we add such contiguous mappings into the mix.

3621 arch\arm64\include\asm\mmu.h#0038 3622 arch\arm64\include\asm\mmu_context.h#0026 Repo: 39bc88e5e38e Catalin Fri Sep 2 14:54:03 2016 +0100 Description: arm64: Disable TTBR0_EL1 during normal kernel execution ------When the TTBR0 PAN feature is enabled, the kernel entry points need to disable access to TTBR0_EL1. The PAN status of the interrupted context is stored as part of the saved pstate, reusing the PSR_PAN_BIT (22). Restoring access to TTBR0_EL1 is done on exception return if returning to user or returning to a context where PAN was disabled.

Context switching via switch_mm() must defer the update of TTBR0_EL1 until a return to user or an explicit uaccess_enable() call.

Special care needs to be taken for two cases where TTBR0_EL1 is set outside the normal kernel context switch operation: EFI run-time services (via efi_set_pgd) and CPU suspend (via cpu_(un)install_idmap). Code has been added to avoid deferred TTBR0_EL1 switching as in switch_mm() and restore the reserved TTBR0_EL1 when uninstalling the special TTBR0_EL1.

User cache maintenance (user_cache_maint_handler and __flush_cache_user_range) needs the TTBR0_EL1 re-instated since the operations are performed by user virtual address.

This patch also removes a stale comment on the switch_mm() function.

arm64: simplify contextidr_thread_switch ------When CONFIG_PID_IN_CONTEXTIDR is not selected, we use an empty stub

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definition of contextidr_thread_switch(). As everything we rely upon exists regardless of CONFIG_PID_IN_CONTEXTIDR, we don't strictly require an empty stub.

By using IS_ENABLED() rather than ifdeffery, we avoid duplication, and get compiler coverage on all the code even when CONFIG_PID_IN_CONTEXTIDR is not selected and the code is optimised away.

3623 arch\arm64\include\asm\mmu_context.h#0107 3624 arch\arm64\include\asm\mmu_context.h#0167 3625 arch\arm64\include\asm\mmu_context.h#0176 3626 arch\arm64\include\asm\mmu_context.h#0188 3627 arch\arm64\include\asm\mmu_context.h#0200 3628 arch\arm64\include\asm\mmu_context.h#0219 3629 arch\arm64\include\asm\neon.h#0012 Repo: 82e0191a1aa1 Suzuki K Tue Nov 8 13:56:21 2016 +0000 Description: arm64: Support systems without FP/ASIMD ------The arm64 kernel assumes that FP/ASIMD units are always present and accesses the FP/ASIMD specific registers unconditionally. This could cause problems when they are absent. This patch adds the support for kernel handling systems without FP/ASIMD by skipping the register access within the kernel. For kvm, we trap the accesses to FP/ASIMD and inject an undefined instruction exception to the VM.

The callers of the exported kernel_neon_begin_partial() should make sure that the FP/ASIMD is supported.

3630 arch\arm64\include\asm\neon.h#0014 3631 arch\arm64\include\asm\numa.h#0018 Repo: aec03f89e905 Boris Mon Dec 12 23:18:29 2016 -0500 Description: ACPI/NUMA: Do not map pxm to node when NUMA is turned off ------acpi_map_pxm_to_node() unconditially maps nodes even when NUMA is turned off. So acpi_get_node() might return a node > 0, which is fatal when NUMA is disabled as the rest of the kernel assumes that only node 0 exists.

Expose numa_off to the acpi code and return NUMA_NO_NODE when it's set.

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3632 arch\arm64\include\asm\opcodes.h#fileDeleted Repo: bca8f17f57bd Marc Zyngier Thu Dec 1 10:44:33 2016 +0000 Description: arm64: Get rid of asm/opcodes.h ------The opcodes.h drags in a lot of definition from the 32bit port, most of which is not required at all. Clean things up a bit by moving the bare minimum of what is required next to the actual users, and drop the include file.

3633 arch\arm64\include\asm\percpu.h#0019 Repo: a9ea0017ebe8 Mark RutlandThu Nov 3 20:23:05 2016 +0000 Description: arm64: factor out current_stack_pointer ------We define current_stack_pointer in , though other files and header relying upon it do not have this necessary include, and are thus fragile to changes in the header .

Subsequent patches will affect the header soup such that directly including may result in a circular header include in some of these cases, so we can't simply include .

Instead, factor current_thread_info into its own header, and have all existing users include this explicitly.

arm64: percpu: kill off final ACCESS_ONCE() uses ------For several reasons it is preferable to use {READ,WRITE}_ONCE() rather than ACCESS_ONCE(). For example, these handle aggregate types, result in shorter source code, and better document the intended access (which may be useful for instrumentation features such as the upcoming KTSAN).

Over a number of patches, most uses of ACCESS_ONCE() in arch/arm64 have been migrated to {READ,WRITE}_ONCE(). For consistency, and the above reasons, this patch migrates the final remaining uses.

arm64: percpu: rewrite ll/sc loops in assembly ------Writing the outer loop of an LL/SC sequence using do {...} while constructs potentially allows the compiler to hoist memory accesses between the STXR and the branch back to the LDXR. On CPUs that do not guarantee forward progress of LL/SC loops when faced with memory accesses to the same ERG (up to 2k) between the failed STXR and the branch back, we may end up livelocking.

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This patch avoids this issue in our percpu atomics by rewriting the outer loop as part of the LL/SC inline assembly block.

3634 arch\arm64\include\asm\percpu.h#0106 3635 arch\arm64\include\asm\percpu.h#0109 3636 arch\arm64\include\asm\percpu.h#0112 3637 arch\arm64\include\asm\percpu.h#0115 3638 arch\arm64\include\asm\percpu.h#0128 3639 arch\arm64\include\asm\percpu.h#0131 3640 arch\arm64\include\asm\percpu.h#0134 3641 arch\arm64\include\asm\percpu.h#0137 3642 arch\arm64\include\asm\perf_event.h#0020 Repo: f4000cd99750 Linus Tue Dec 13 16:39:21 2016 -0800 Description: Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux ------Pull arm64 updates from Catalin Marinas:

- struct thread_info moved off-stack (also touching include/linux/thread_info.h and include/linux/restart_block.h)

- cpus_have_cap() reworked to avoid __builtin_constant_p() for static key use (also touching drivers/irqchip/irq-gic-v3.c)

- uprobes support (currently only for native 64-bit tasks)

- Emulation of kernel Privileged Access Never (PAN) using TTBR0_EL1 switching to a reserved page table

- CPU capacity information passing via DT or sysfs (used by the scheduler)

- support for systems without FP/SIMD (IOW, kernel avoids touching these registers; there is no soft-float ABI, nor kernel emulation for AArch64 FP/SIMD)

- handling of hardware watchpoint with unaligned addresses, varied lengths and offsets from base

- use of the page table contiguous hint for kernel mappings

- hugetlb fixes for sizes involving the contiguous hint

- remove unnecessary I-cache invalidation in flush_cache_range()

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- CNTHCTL_EL2 access fix for CPUs with VHE support (ARMv8.1)

- boot-time checks for writable+executable kernel mappings

- simplify asm/opcodes.h and avoid including the 32-bit ARM counterpart and make the arm64 kernel headers self-consistent (Xen headers patch merged separately)

- Workaround for broken .inst support in certain binutils versions

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (60 commits) arm64: Disable PAN on uaccess_enable() arm64: Work around broken .inst when defective gas is detected arm64: Add detection code for broken .inst support in binutils arm64: Remove reference to asm/opcodes.h arm64: Get rid of asm/opcodes.h arm64: smp: Prevent raw_smp_processor_id() recursion arm64: head.S: Fix CNTHCTL_EL2 access on VHE system arm64: Remove I-cache invalidation from flush_cache_range() arm64: Enable HIBERNATION in defconfig arm64: Enable CONFIG_ARM64_SW_TTBR0_PAN arm64: xen: Enable user access before a privcmd hvc call arm64: Handle faults caused by inadvertent user access with PAN enabled arm64: Disable TTBR0_EL1 during normal kernel execution arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1 arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro arm64: Factor out PAN enabling/disabling into separate uaccess_* macros arm64: Update the synchronous external abort fault description selftests: arm64: add test for unaligned/inexact watchpoint handling arm64: Allow hw watchpoint of length 3,5,6 and 7 arm64: hw_breakpoint: Handle inexact watchpoint addresses ...

3643 arch\arm64\include\asm\probes.h#0018 Repo: 49f5522e495a Marc Zyngier Sat Dec 3 14:05:37 2016 +0000 Description: arm64: Remove reference to asm/opcodes.h ------The asm/opcodes.h file is now gone, but probes.h still references it for not obvious reason. Removing the #include directive fixes the compilation.

arm64: kprobe: protect/rename few definitions to be reused by uprobe ------decode-insn code has to be reused by arm64 uprobe implementation as well. Therefore, this patch protects some portion of kprobe code and renames few

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other, so that decode-insn functionality can be reused by uprobe even when CONFIG_KPROBES is not defined.

kprobe_opcode_t and struct arch_specific_insn are also defined by linux/kprobes.h, when CONFIG_KPROBES is not defined. So, protect these definitions in asm/probes.h.

linux/kprobes.h already includes asm/kprobes.h. Therefore, remove inclusion of asm/kprobes.h from decode-insn.c.

There are some definitions like kprobe_insn and kprobes_handler_t etc can be re-used by uprobe. So, it would be better to remove 'k' from their names.

struct arch_specific_insn is specific to kprobe. Therefore, introduce a new struct arch_probe_insn which will be common for both kprobe and uprobe, so that decode-insn code can be shared. Modify kprobe code accordingly.

Function arm_probe_decode_insn() will be needed by uprobe as well. So make it global.

arm64: kprobes instruction simulation support ------Kprobes needs simulation of instructions that cannot be stepped from a different memory location, e.g.: those instructions that uses PC-relative addressing. In simulation, the behaviour of the instruction is implemented using a copy of pt_regs.

The following instruction categories are simulated: - All branching instructions(conditional, register, and immediate) - Literal access instructions(load-literal, adr/adrp)

Conditional execution is limited to branching instructions in ARM v8. If conditions at PSTATE do not match the condition fields of , the instruction is effectively NOP.

Thanks to Will Cohen for assorted suggested changes.

3644 arch\arm64\include\asm\probes.h#0021 3645 arch\arm64\include\asm\probes.h#0027 3646 arch\arm64\include\asm\probes.h#0030 3647 arch\arm64\include\asm\probes.h#0034

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3648 arch\arm64\include\asm\processor.h#0152 Repo: 6d0d287891a0 Christian Wed Nov 16 13:23:05 2016 +0100 Description: locking/core: Provide common cpu_relax_yield() definition ------No need to duplicate the same define everywhere. Since the only user is stop-machine and the only provider is s390, we can use a default implementation of cpu_relax_yield() in sched.h.

locking/core, arch: Remove cpu_relax_lowlatency() ------As there are no users left, we can remove cpu_relax_lowlatency() implementations from every architecture.

locking/core: Introduce cpu_relax_yield() ------For spinning loops people do often use barrier() or cpu_relax(). For most architectures cpu_relax and barrier are the same, but on some architectures cpu_relax can add some latency. For example on power,sparc64 and arc, cpu_relax can shift the CPU towards other hardware threads in an SMT environment. On s390 cpu_relax does even more, it uses an hypercall to the hypervisor to give up the timeslice. In contrast to the SMT yielding this can result in larger latencies. In some places this latency is unwanted, so another variant "cpu_relax_lowlatency" was introduced. Before this is used in more and more places, lets revert the logic and provide a cpu_relax_yield that can be called in places where yielding is more important than latency. By default this is the same as cpu_relax on all architectures.

3649 arch\arm64\include\asm\ptdump.h#0019 Repo: 1404d6f13e47 Laura Abbott Thu Oct 27 09:27:34 2016 -0700 Description: arm64: dump: Add checking for writable and exectuable pages ------Page mappings with full RWX permissions are a security risk. x86 has an option to walk the page tables and dump any bad pages. (See e1a58320a38d ("x86/mm: Warn on W^X mappings")). Add a similar implementation for arm64.

arm64: dump: Remove max_addr ------max_addr was added as part of struct ptdump_info but has never actually been used. Remove it.

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arm64: dump: Make ptdump debugfs a separate option ------ptdump_register currently initializes a set of page table information and registers debugfs. There are uses for the ptdump option without wanting the debugfs options. Split this out to make it a separate option.

3650 arch\arm64\include\asm\ptdump.h#0022 3651 arch\arm64\include\asm\ptdump.h#0033 3652 arch\arm64\include\asm\ptdump.h#0035 3653 arch\arm64\include\asm\ptdump.h#0039 3654 arch\arm64\include\asm\ptdump.h#0044 3655 arch\arm64\include\asm\ptdump.h#0048 3656 arch\arm64\include\asm\ptrace.h#0220 Repo: 9842ceae9fa8 Pratyush Wed Nov 2 14:40:46 2016 +0530 Description: arm64: Add uprobe support ------This patch adds support for uprobe on ARM64 architecture.

Unit tests for following have been done so far and they have been found working 1. Step-able instructions, like sub, ldr, add etc. 2. Simulation-able like ret, cbnz, cbz etc. 3. uretprobe 4. Reject-able instructions like sev, wfe etc. 5. trapped and abort xol path 6. probe at unaligned user address. 7. longjump test cases

Currently it does not support aarch32 instruction probing.

3657 arch\arm64\include\asm\smp.h#0032 Repo: 34a6980c82fb Robin Thu Dec 1 15:55:13 2016 +0000 Description: arm64: smp: Prevent raw_smp_processor_id() recursion ------Under CONFIG_DEBUG_PREEMPT=y, this_cpu_ptr() ends up calling back into raw_smp_processor_id(), resulting in some hilariously catastrophic infinite recursion. In the normal case, we have:

#define this_cpu_ptr(ptr) raw_cpu_ptr(ptr)

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and everything is dandy. However for CONFIG_DEBUG_PREEMPT, this_cpu_ptr() is defined in terms of my_cpu_offset, wherein the fun begins:

#define my_cpu_offset per_cpu_offset(smp_processor_id()) ... #define smp_processor_id() debug_smp_processor_id() ... notrace unsigned int debug_smp_processor_id(void) { return check_preemption_disabled("smp_processor_id", ""); ... notrace static unsigned int check_preemption_disabled(const char *what1, const char *what2) { int this_cpu = raw_smp_processor_id();

and bang. Use raw_cpu_ptr() directly to avoid that.

Fixes: 57c82954e77f ("arm64: make cpu number a percpu variable")

arm64: split thread_info from task stack ------This patch moves arm64's struct thread_info from the task stack into task_struct. This protects thread_info from corruption in the case of stack overflows, and makes its address harder to determine if stack addresses are leaked, making a number of attacks more difficult. Precise detection and handling of overflow is left for subsequent patches.

Largely, this involves changing code to store the task_struct in sp_el0, and acquire the thread_info from the task struct. Core code now implements current_thread_info(), and as noted in this relies on offsetof(task_struct, thread_info) == 0, enforced by core code.

This change means that the 'tsk' register used in entry.S now points to a task_struct, rather than a thread_info as it used to. To make this clear, the TI_* field offsets are renamed to TSK_TI_*, with asm-offsets appropriately updated to account for the structural change.

Userspace clobbers sp_el0, and we can no longer restore this from the stack. Instead, the current task is cached in a per-cpu variable that we can safely access from early assembly as interrupts are disabled (and we are thus not preemptible).

Both secondary entry and idle are updated to stash the sp and task pointer separately.

arm64: make cpu number a percpu variable ------

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In the absence of CONFIG_THREAD_INFO_IN_TASK, core code maintains thread_info::cpu, and low-level architecture code can access this to build raw_smp_processor_id(). With CONFIG_THREAD_INFO_IN_TASK, core code maintains task_struct::cpu, which for reasons of hte header soup is not accessible to low-level arch code.

Instead, we can maintain a percpu variable containing the cpu number.

For both the old and new implementation of raw_smp_processor_id(), we read a syreg into a GPR, add an offset, and load the result. As the offset is now larger, it may not be folded into the load, but otherwise the assembly shouldn't change much.

3658 arch\arm64\include\asm\smp.h#0038 3659 arch\arm64\include\asm\smp.h#0040 3660 arch\arm64\include\asm\smp.h#0087 3661 arch\arm64\include\asm\suspend.h#0004 Repo: 623b476fc815 Mark RutlandThu Nov 3 20:23:09 2016 +0000 Description: arm64: move sp_el0 and tpidr_el1 into cpu_suspend_ctx ------When returning from idle, we rely on the fact that thread_info lives at the end of the kernel stack, and restore this by masking the saved stack pointer. Subsequent patches will sever the relationship between the stack and thread_info, and to cater for this we must save/restore sp_el0 explicitly, storing it in cpu_suspend_ctx.

As cpu_suspend_ctx must be doubleword aligned, this leaves us with an extra slot in cpu_suspend_ctx. We can use this to save/restore tpidr_el1 in the same way, which simplifies the code, avoiding pointer chasing on the restore path (as we no longer need to load thread_info::cpu followed by the relevant slot in __per_cpu_offset based on this).

This patch stashes both registers in cpu_suspend_ctx.

3662 arch\arm64\include\asm\sysreg.h#0025 Repo: cd9e1927a525 Marc Zyngier Tue Dec 6 15:27:45 2016 +0000 Description: arm64: Work around broken .inst when defective gas is detected ------.inst being largely broken with older binutils, it'd be better not to emit it altogether when detecting such configuration (as it leads to all kind of horrors when using alternatives).

Generalize the __emit_inst macro and use it extensively in asm/sysreg.h, and make it generate a .long when a broken gas is

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detected. The disassembly will be crap, but at least we can write semi-sane code.

arm64: Get rid of asm/opcodes.h ------The opcodes.h drags in a lot of definition from the 32bit port, most of which is not required at all. Clean things up a bit by moving the bare minimum of what is required next to the actual users, and drop the include file.

3663 arch\arm64\include\asm\sysreg.h#0040 3664 arch\arm64\include\asm\sysreg.h#0109 3665 arch\arm64\include\asm\sysreg.h#0256 3666 arch\arm64\include\asm\sysreg.h#0260 3667 arch\arm64\include\asm\sysreg.h#0274 3668 arch\arm64\include\asm\sysreg.h#0278 3669 arch\arm64\include\asm\thread_info.h#0039 Repo: 4b65a5db3627 Catalin Fri Jul 1 16:53:00 2016 +0100 Description: arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1 ------This patch adds the uaccess macros/functions to disable access to user space by setting TTBR0_EL1 to a reserved zeroed page. Since the value written to TTBR0_EL1 must be a physical address, for simplicity this patch introduces a reserved_ttbr0 page at a constant offset from swapper_pg_dir. The uaccess_disable code uses the ttbr1_el1 value adjusted by the reserved_ttbr0 offset.

Enabling access to user is done by restoring TTBR0_EL1 with the value from the struct thread_info ttbr0 variable. Interrupts must be disabled during the uaccess_ttbr0_enable code to ensure the atomicity of the thread_info.ttbr0 read and TTBR0_EL1 write. This patch also moves the get_thread_info asm macro from entry.S to assembler.h for reuse in the uaccess_ttbr0_* macros.

arm64: split thread_info from task stack ------This patch moves arm64's struct thread_info from the task stack into task_struct. This protects thread_info from corruption in the case of stack overflows, and makes its address harder to determine if stack addresses are leaked, making a number of attacks more difficult. Precise detection and handling of overflow is left for subsequent patches.

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Largely, this involves changing code to store the task_struct in sp_el0, and acquire the thread_info from the task struct. Core code now implements current_thread_info(), and as noted in this relies on offsetof(task_struct, thread_info) == 0, enforced by core code.

This change means that the 'tsk' register used in entry.S now points to a task_struct, rather than a thread_info as it used to. To make this clear, the TI_* field offsets are renamed to TSK_TI_*, with asm-offsets appropriately updated to account for the structural change.

Userspace clobbers sp_el0, and we can no longer restore this from the stack. Instead, the current task is cached in a per-cpu variable that we can safely access from early assembly as interrupts are disabled (and we are thus not preemptible).

Both secondary entry and idle are updated to stash the sp and task pointer separately.

arm64: factor out current_stack_pointer ------We define current_stack_pointer in , though other files and header relying upon it do not have this necessary include, and are thus fragile to changes in the header soup.

Subsequent patches will affect the header soup such that directly including may result in a circular header include in some of these cases, so we can't simply include .

Instead, factor current_thread_info into its own header, and have all existing users include this explicitly.

arm64: thread_info remove stale items ------We have a comment claiming __switch_to() cares about where cpu_context is located relative to cpu_domain in thread_info. However arm64 has never had a thread_info::cpu_domain field, and neither __switch_to nor cpu_switch_to care where the cpu_context field is relative to others.

Additionally, the init_thread_info alias is never used anywhere in the kernel, and will shortly become problematic when thread_info is moved into task_struct.

This patch removes both.

arm64: Add uprobe support ------

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This patch adds support for uprobe on ARM64 architecture.

Unit tests for following have been done so far and they have been found working 1. Step-able instructions, like sub, ldr, add etc. 2. Simulation-able like ret, cbnz, cbz etc. 3. uretprobe 4. Reject-able instructions like sev, wfe etc. 5. trapped and abort xol path 6. probe at unaligned user address. 7. longjump test cases

Currently it does not support aarch32 instruction probing.

3670 arch\arm64\include\asm\thread_info.h#0046 Review: COMMENT stecan Thu, 11 Jan 2018 07:26:58 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:58 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:26:58 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:58 +0100 Automatic commented! 3671 arch\arm64\include\asm\thread_info.h#0050 3672 arch\arm64\include\asm\thread_info.h#0054 3673 arch\arm64\include\asm\thread_info.h#0058 3674 arch\arm64\include\asm\thread_info.h#0063 3675 arch\arm64\include\asm\thread_info.h#0066 3676 arch\arm64\include\asm\thread_info.h#0115 3677 arch\arm64\include\asm\thread_info.h#0135 3678 arch\arm64\include\asm\thread_info.h#0138 3679 arch\arm64\include\asm\uaccess.h#0021 Repo: b4b8664d291a Al Viro Mon Dec 26 04:10:19 2016 -0500 Description: arm64: don't pull uaccess.h into *.S ------Split asm-only parts of arm64 uaccess.h into a new header and use that from *.S.

arm64: Disable PAN on uaccess_enable() ------

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Commit 4b65a5db3627 ("arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1") added conditional user access enable/disable. Unfortunately, a typo prevents the PAN bit from being cleared for user access functions.

Restore the PAN functionality by adding the missing '!'.

Fixes: b65a5db3627 ("arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1")

arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1 ------This patch adds the uaccess macros/functions to disable access to user space by setting TTBR0_EL1 to a reserved zeroed page. Since the value written to TTBR0_EL1 must be a physical address, for simplicity this patch introduces a reserved_ttbr0 page at a constant offset from swapper_pg_dir. The uaccess_disable code uses the ttbr1_el1 value adjusted by the reserved_ttbr0 offset.

Enabling access to user is done by restoring TTBR0_EL1 with the value from the struct thread_info ttbr0 variable. Interrupts must be disabled during the uaccess_ttbr0_enable code to ensure the atomicity of the thread_info.ttbr0 read and TTBR0_EL1 write. This patch also moves the get_thread_info asm macro from entry.S to assembler.h for reuse in the uaccess_ttbr0_* macros.

arm64: Factor out PAN enabling/disabling into separate uaccess_* macros ------This patch moves the directly coded alternatives for turning PAN on/off into separate uaccess_{enable,disable} macros or functions. The asm macros take a few arguments which will be used in subsequent patches.

Note that any (unlikely) access that the compiler might generate between uaccess_enable() and uaccess_disable(), other than those explicitly specified by the user access code, will not be protected by PAN.

3680 arch\arm64\include\asm\uaccess.h#0033 3681 arch\arm64\include\asm\uaccess.h#0035 3682 arch\arm64\include\asm\uaccess.h#0125 3683 arch\arm64\include\asm\uaccess.h#0244 3684 arch\arm64\include\asm\uaccess.h#0265

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3685 arch\arm64\include\asm\uaccess.h#0267 3686 arch\arm64\include\asm\uaccess.h#0311 3687 arch\arm64\include\asm\uaccess.h#0332 3688 arch\arm64\include\asm\virt.h#0050 Repo: 488f94d7212b Jintack Lim Thu Dec 1 14:32:05 2016 -0500 Description: KVM: arm64: Access CNTHCTL_EL2 bit fields correctly on VHE systems ------Current KVM world switch code is unintentionally setting wrong bits to CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical timer. Bit positions of CNTHCTL_EL2 are changing depending on HCR_EL2.E2H bit. EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is not set, but they are 11th and 10th bits respectively when E2H is set.

In fact, on VHE we only need to set those bits once, not for every world switch. This is because the host kernel runs in EL2 with HCR_EL2.TGE == 1, which makes those bits have no effect for the host kernel execution. So we just set those bits once for guests, and that's it.

3689 arch\arm64\include\asm\virt.h#0084 3690 arch\arm64\include\asm\word-at-a-time.h#0019 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro arch\arm64\include\asm\xen\ 3691 arch\arm64\include\asm\xen\hypercall.h#dublicatedFile Repo: 2fbadc3002c5 Marc Zyngier Fri Dec 2 14:19:35 2016 +0000 Description: arm/arm64: xen: Move shared architecture headers to include/xen/arm ------ARM and arm64 Xen ports share a number of headers, leading to packaging issues when these headers needs to be exported, as it breaks the reasonable requirement that an architecture port has self-contained headers.

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Fix the issue by moving the 5 header files to include/xen/arm, and keep local placeholders to include the relevant files.

Review: N.A. stecan Thu, 11 Jan 2018 07:44:27 +0100 Short Description: stecan Thu, 11 Jan 2018 07:44:27 +0100 Dublicate: Not applicable Test: N.A. stecan Thu, 11 Jan 2018 07:44:27 +0100 Short Description: stecan Thu, 11 Jan 2018 07:44:27 +0100 Dublicate: Not applicable 3692 arch\arm64\include\asm\xen\hypervisor.h#dublicatedFile Repo: 2fbadc3002c5 Marc Zyngier Fri Dec 2 14:19:35 2016 +0000 Description: arm/arm64: xen: Move shared architecture headers to include/xen/arm ------ARM and arm64 Xen ports share a number of headers, leading to packaging issues when these headers needs to be exported, as it breaks the reasonable requirement that an architecture port has self-contained headers.

Fix the issue by moving the 5 header files to include/xen/arm, and keep local placeholders to include the relevant files.

Review: N.A. stecan Thu, 11 Jan 2018 07:44:27 +0100 Short Description: stecan Thu, 11 Jan 2018 07:44:27 +0100 Dublicate: Not applicable Test: N.A. stecan Thu, 11 Jan 2018 07:44:27 +0100 Short Description: stecan Thu, 11 Jan 2018 07:44:27 +0100 Dublicate: Not applicable 3693 arch\arm64\include\asm\xen\interface.h#dublicatedFile Repo: 2fbadc3002c5 Marc Zyngier Fri Dec 2 14:19:35 2016 +0000 Description: arm/arm64: xen: Move shared architecture headers to include/xen/arm ------ARM and arm64 Xen ports share a number of headers, leading to packaging issues when these headers needs to be exported, as it breaks the reasonable requirement that an architecture port has self-contained headers.

Fix the issue by moving the 5 header files to include/xen/arm,

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and keep local placeholders to include the relevant files.

Review: N.A. stecan Thu, 11 Jan 2018 07:44:27 +0100 Short Description: stecan Thu, 11 Jan 2018 07:44:27 +0100 Dublicate: Not applicable Test: N.A. stecan Thu, 11 Jan 2018 07:44:27 +0100 Short Description: stecan Thu, 11 Jan 2018 07:44:27 +0100 Dublicate: Not applicable 3694 arch\arm64\include\asm\xen\page-coherent.h#dublicatedFile Repo: 2fbadc3002c5 Marc Zyngier Fri Dec 2 14:19:35 2016 +0000 Description: arm/arm64: xen: Move shared architecture headers to include/xen/arm ------ARM and arm64 Xen ports share a number of headers, leading to packaging issues when these headers needs to be exported, as it breaks the reasonable requirement that an architecture port has self-contained headers.

Fix the issue by moving the 5 header files to include/xen/arm, and keep local placeholders to include the relevant files.

xen/arm/arm64: merge xen/mm32.c into xen/mm.c ------Merge xen/mm32.c into xen/mm.c. As a consequence the code gets compiled on arm64 too.

Review: N.A. stecan Thu, 11 Jan 2018 07:44:27 +0100 Short Description: stecan Thu, 11 Jan 2018 07:44:27 +0100 Dublicate: Not applicable Test: N.A. stecan Thu, 11 Jan 2018 07:44:27 +0100 Short Description: stecan Thu, 11 Jan 2018 07:44:27 +0100 Dublicate: Not applicable 3695 arch\arm64\include\asm\xen\page.h#dublicatedFile Repo: 2fbadc3002c5 Marc Zyngier Fri Dec 2 14:19:35 2016 +0000 Description: arm/arm64: xen: Move shared architecture headers to include/xen/arm ------ARM and arm64 Xen ports share a number of headers, leading to packaging issues when these headers needs to be exported, as it

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breaks the reasonable requirement that an architecture port has self-contained headers.

Fix the issue by moving the 5 header files to include/xen/arm, and keep local placeholders to include the relevant files.

Review: N.A. stecan Thu, 11 Jan 2018 07:44:27 +0100 Short Description: stecan Thu, 11 Jan 2018 07:44:27 +0100 Dublicate: Not applicable Test: N.A. stecan Thu, 11 Jan 2018 07:44:27 +0100 Short Description: stecan Thu, 11 Jan 2018 07:44:27 +0100 Dublicate: Not applicable arch\arm64\include\asm\ 3696 arch\arm64\include\asm\asm-uaccess.h#newFile Repo: b4b8664d291a Al Viro Mon Dec 26 04:10:19 2016 -0500 Description: arm64: don't pull uaccess.h into *.S ------Split asm-only parts of arm64 uaccess.h into a new header and use that from *.S.

3697 arch\arm64\include\asm\current.h#newFile Repo: 9d84fb27fa13 Mark RutlandTue Jan 3 18:27:01 2017 +0000 Description: arm64: restore get_current() optimisation ------Commit c02433dd6de32f04 ("arm64: split thread_info from task stack") inverted the relationship between get_current() and current_thread_info(), with sp_el0 now holding the current task_struct rather than the current thead_info. The new implementation of get_current() prevents the compiler from being able to optimize repeated calls to either, resulting in a noticeable penalty in some microbenchmarks.

This patch restores the previous optimisation by implementing get_current() in the same way as our old current_thread_info(), using a non-volatile asm statement.

3698 arch\arm64\include\asm\stack_pointer.h#newFile Repo: a9ea0017ebe8 Mark RutlandThu Nov 3 20:23:05 2016 +0000 Description: arm64: factor out current_stack_pointer

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------We define current_stack_pointer in , though other files and header relying upon it do not have this necessary include, and are thus fragile to changes in the header soup.

Subsequent patches will affect the header soup such that directly including may result in a circular header include in some of these cases, so we can't simply include .

Instead, factor current_thread_info into its own header, and have all existing users include this explicitly.

3699 arch\arm64\include\asm\uprobes.h#newFile Repo: 9842ceae9fa8 Pratyush Wed Nov 2 14:40:46 2016 +0530 Description: arm64: Add uprobe support ------This patch adds support for uprobe on ARM64 architecture.

Unit tests for following have been done so far and they have been found working 1. Step-able instructions, like sub, ldr, add etc. 2. Simulation-able like ret, cbnz, cbz etc. 3. uretprobe 4. Reject-able instructions like sev, wfe etc. 5. trapped and abort xol path 6. probe at unaligned user address. 7. longjump test cases

Currently it does not support aarch32 instruction probing.

arch\arm64\include\uapi\asm\ 3700 arch\arm64\include\uapi\asm\ptrace.h#0080 Repo: aeb1f39d814b Dave Martin Wed Jan 18 16:25:23 2017 +0000 Description: arm64/ptrace: Avoid uninitialised struct padding in fpr_set() ------This patch adds an explicit __reserved[] field to user_fpsimd_state to replace what was previously unnamed padding.

This ensures that data in this region are propagated across assignment rather than being left possibly uninitialised at the destination.

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Line Link NR. Descriptions arch\arm64\kernel\ 3701 arch\arm64\kernel\acpi.c#0135 Repo: 6b11d1d67713 Lv Zheng Wed Dec 14 15:04:39 2016 +0800 Description: ACPI / osl: Remove acpi_get_table_with_size()/early_acpi_os_unmap_memory() users ------This patch removes the users of the deprectated APIs: acpi_get_table_with_size() early_acpi_os_unmap_memory() The following APIs should be used instead of: acpi_get_table() acpi_put_table()

The deprecated APIs are invented to be a replacement of acpi_get_table() during the early stage so that the early mapped pointer will not be stored in ACPICA core and thus the late stage acpi_get_table() won't return a wrong pointer. The mapping size is returned just because it is required by early_acpi_os_unmap_memory() to unmap the pointer during early stage.

But as the mapping size equals to the acpi_table_header.length (see acpi_tb_init_table_descriptor() and acpi_tb_validate_table()), when such a convenient result is returned, driver code will start to use it instead of accessing acpi_table_header to obtain the length.

Thus this patch cleans up the drivers by replacing returned table size with acpi_table_header.length, and should be a no-op.

3702 arch\arm64\kernel\acpi.c#0142 3703 arch\arm64\kernel\acpi.c#0173 Review: COMMENT stecan Thu, 11 Jan 2018 07:26:59 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:59 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:26:59 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:59 +0100 Automatic commented! 3704 arch\arm64\kernel\acpi.c#0176 3705 arch\arm64\kernel\armv8_deprecated.c#0017 Repo: b272f732f888 Linus Sun Dec 25 14:05:56 2016 -0800 Description: Merge branch 'smp-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip ------Pull SMP hotplug notifier removal from Thomas Gleixner: "This is the final cleanup of the hotplug notifier infrastructure. The

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series has been reintgrated in the last two days because there came a new driver using the old infrastructure via the SCSI tree.

Summary:

- convert the last leftover drivers utilizing notifiers

- fixup for a completely broken hotplug user

- prevent setup of already used states

- removal of the notifiers

- treewide cleanup of hotplug state names

- consolidation of state space

There is a sphinx based documentation pending, but that needs review from the documentation folks"

* 'smp-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/armada-xp: Consolidate hotplug state space irqchip/gic: Consolidate hotplug state space coresight/etm3/4x: Consolidate hotplug state space cpu/hotplug: Cleanup state names cpu/hotplug: Remove obsolete cpu hotplug register/unregister functions staging/lustre/libcfs: Convert to hotplug state machine scsi/bnx2i: Convert to hotplug state machine scsi/bnx2fc: Convert to hotplug state machine cpu/hotplug: Prevent overwriting of callbacks x86/msr: Remove bogus cleanup from the error path bus: arm-ccn: Prevent hotplug callback leak perf/x86/intel/cstate: Prevent hotplug callback leak ARM/imx/mmcd: Fix broken cpu hotplug handling scsi: qedi: Convert to hotplug state machine

cpu/hotplug: Cleanup state names ------When the state names got added a script was used to add the extra argument to the calls. The script basically converted the state constant to a string, but the cleanup to convert these strings into meaningful ones did not happen.

Replace all the useless strings with 'subsys/xxx/yyy:state' strings which are used in all the other places already.

Replace with globally ------

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This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

arm64: Get rid of asm/opcodes.h ------The opcodes.h drags in a lot of definition from the 32bit port, most of which is not required at all. Clean things up a bit by moving the bare minimum of what is required next to the actual users, and drop the include file.

arm64: Factor out PAN enabling/disabling into separate uaccess_* macros ------This patch moves the directly coded alternatives for turning PAN on/off into separate uaccess_{enable,disable} macros or functions. The asm macros take a few arguments which will be used in subsequent patches.

Note that any (unlikely) access that the compiler might generate between uaccess_enable() and uaccess_disable(), other than those explicitly specified by the user access code, will not be protected by PAN.

arm64: swp emulation: bound LL/SC retries before rescheduling ------If a CPU does not implement a global monitor for certain memory types, then userspace can attempt a kernel DoS by issuing SWP instructions targetting the problematic memory (for example, a framebuffer mapped with non-cacheable attributes).

The SWP emulation code protects against these sorts of attacks by checking for pending signals and potentially rescheduling when the STXR instruction fails during the emulation. Whilst this is good for avoiding livelock, it harms emulation of legitimate SWP instructions on CPUs where forward progress is not guaranteed if there are memory accesses to the same reservation granule (up to 2k) between the failing STXR and the retry of the LDXR.

This patch solves the problem by retrying the STXR a bounded number of times (4) before breaking out of the LL/SC loop and looking for something else to do.

Merge branch 'smp-hotplug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

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------Pull smp hotplug updates from Thomas Gleixner: "This is the next part of the hotplug rework.

- Convert all notifiers with a priority assigned

- Convert all CPU_STARTING/DYING notifiers

The final removal of the STARTING/DYING infrastructure will happen when the merge window closes.

Another 700 hundred line of unpenetrable maze gone :)"

* 'smp-hotplug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (70 commits) timers/core: Correct callback order during CPU hot plug leds/trigger/cpu: Move from CPU_STARTING to ONLINE level powerpc/numa: Convert to hotplug state machine arm/perf: Fix hotplug state machine conversion irqchip/armada: Avoid unused function warnings ARC/time: Convert to hotplug state machine clocksource/atlas7: Convert to hotplug state machine clocksource/armada-370-xp: Convert to hotplug state machine clocksource/exynos_mct: Convert to hotplug state machine clocksource/arm_global_timer: Convert to hotplug state machine rcu: Convert rcutree to hotplug state machine KVM/arm/arm64/vgic-new: Convert to hotplug state machine smp/cfd: Convert core to hotplug state machine x86/x2apic: Convert to CPU hotplug state machine profile: Convert to hotplug state machine timers/core: Convert to hotplug state machine hrtimer: Convert to hotplug state machine x86/tboot: Convert to hotplug state machine arm64/armv8 deprecated: Convert to hotplug state machine hwtracing/coresight-etm4x: Convert to hotplug state machine ...

Merge branch 'for-next/kprobes' into for-next/core ------* kprobes: arm64: kprobes: Add KASAN instrumentation around stack accesses arm64: kprobes: Cleanup jprobe_return arm64: kprobes: Fix overflow when saving stack arm64: kprobes: WARN if attempting to step with PSTATE.D=1 kprobes: Add arm64 case in kprobe example module arm64: Add kernel return probes support (kretprobes) arm64: Add trampoline code for kretprobes arm64: kprobes instruction simulation support arm64: Treat all entry code as non-kprobe-able arm64: Blacklist non-kprobe-able symbol

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arm64: Kprobes with single stepping support arm64: add conditional instruction simulation support arm64: Add more test functions to insn.c arm64: Add HAVE_REGS_AND_STACK_ACCESS_API feature

arm64: add conditional instruction simulation support ------Cease using the arm32 arm_check_condition() function and replace it with a local version for use in deprecated instruction support on arm64. Also make the function table used by this available for future use by kprobes and/or uprobes.

This function is derived from code written by Sandeepa Prabhu.

3706 arch\arm64\kernel\armv8_deprecated.c#0020 3707 arch\arm64\kernel\armv8_deprecated.c#0024 3708 arch\arm64\kernel\armv8_deprecated.c#0288 3709 arch\arm64\kernel\armv8_deprecated.c#0290 3710 arch\arm64\kernel\armv8_deprecated.c#0309 3711 arch\arm64\kernel\armv8_deprecated.c#0314 3712 arch\arm64\kernel\armv8_deprecated.c#0355 3713 arch\arm64\kernel\armv8_deprecated.c#0643 3714 arch\arm64\kernel\asm-offsets.c#0039 Repo: 4b65a5db3627 Catalin Fri Jul 1 16:53:00 2016 +0100 Description: arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1 ------This patch adds the uaccess macros/functions to disable access to user space by setting TTBR0_EL1 to a reserved zeroed page. Since the value written to TTBR0_EL1 must be a physical address, for simplicity this patch introduces a reserved_ttbr0 page at a constant offset from swapper_pg_dir. The uaccess_disable code uses the ttbr1_el1 value adjusted by the reserved_ttbr0 offset.

Enabling access to user is done by restoring TTBR0_EL1 with the value from the struct thread_info ttbr0 variable. Interrupts must be disabled during the uaccess_ttbr0_enable code to ensure the atomicity of the thread_info.ttbr0 read and TTBR0_EL1 write. This patch also moves the get_thread_info asm macro from entry.S to assembler.h for reuse in the uaccess_ttbr0_* macros.

arm64: split thread_info from task stack

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------This patch moves arm64's struct thread_info from the task stack into task_struct. This protects thread_info from corruption in the case of stack overflows, and makes its address harder to determine if stack addresses are leaked, making a number of attacks more difficult. Precise detection and handling of overflow is left for subsequent patches.

Largely, this involves changing code to store the task_struct in sp_el0, and acquire the thread_info from the task struct. Core code now implements current_thread_info(), and as noted in this relies on offsetof(task_struct, thread_info) == 0, enforced by core code.

This change means that the 'tsk' register used in entry.S now points to a task_struct, rather than a thread_info as it used to. To make this clear, the TI_* field offsets are renamed to TSK_TI_*, with asm-offsets appropriately updated to account for the structural change.

Userspace clobbers sp_el0, and we can no longer restore this from the stack. Instead, the current task is cached in a per-cpu variable that we can safely access from early assembly as interrupts are disabled (and we are thus not preemptible).

Both secondary entry and idle are updated to stash the sp and task pointer separately.

arm64: asm-offsets: remove unused definitions ------Subsequent patches will move the thread_info::{task,cpu} fields, and the current TI_{TASK,CPU} offset definitions are not used anywhere.

This patch removes the redundant definitions.

3715 arch\arm64\kernel\asm-offsets.c#0128 3716 arch\arm64\kernel\cpufeature.c#0050 Repo: 4b65a5db3627 Catalin Fri Jul 1 16:53:00 2016 +0100 Description: arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1 ------This patch adds the uaccess macros/functions to disable access to user space by setting TTBR0_EL1 to a reserved zeroed page. Since the value written to TTBR0_EL1 must be a physical address, for simplicity this patch introduces a reserved_ttbr0 page at a constant offset from swapper_pg_dir. The uaccess_disable code uses the ttbr1_el1 value adjusted by the reserved_ttbr0 offset.

Enabling access to user is done by restoring TTBR0_EL1 with the value

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from the struct thread_info ttbr0 variable. Interrupts must be disabled during the uaccess_ttbr0_enable code to ensure the atomicity of the thread_info.ttbr0 read and TTBR0_EL1 write. This patch also moves the get_thread_info asm macro from entry.S to assembler.h for reuse in the uaccess_ttbr0_* macros.

arm64: Support systems without FP/ASIMD ------The arm64 kernel assumes that FP/ASIMD units are always present and accesses the FP/ASIMD specific registers unconditionally. This could cause problems when they are absent. This patch adds the support for kernel handling systems without FP/ASIMD by skipping the register access within the kernel. For kvm, we trap the accesses to FP/ASIMD and inject an undefined instruction exception to the VM.

The callers of the exported kernel_neon_begin_partial() should make sure that the FP/ASIMD is supported.

arm64: Add hypervisor safe helper for checking constant capabilities ------The hypervisor may not have full access to the kernel data structures and hence cannot safely use cpus_have_cap() helper for checking the system capability. Add a safe helper for hypervisors to check a constant system capability, which *doesn't* fall back to checking the bitmap maintained by the kernel. With this, make the cpus_have_cap() only check the bitmask and force constant cap checks to use the new API for quicker checks.

3717 arch\arm64\kernel\cpufeature.c#0750 3718 arch\arm64\kernel\cpufeature.c#0841 3719 arch\arm64\kernel\cpufeature.c#1121 3720 arch\arm64\kernel\cpuinfo.c#0230 Repo: a7ce95e1741f Anna-Maria Sun Nov 27 00:13:44 2016 +0100 Description: arm64/cpuinfo: Convert to hotplug state machine ------Install the callbacks via the state machine and let the core invoke the callbacks on the already online CPUs.

arm64/cpuinfo: Make hotplug notifier symmetric ------There is no requirement to keep the sysfs files around until the CPU is completely dead. Remove them during the DOWN_PREPARE notification. This is a preparatory patch for converting to the hotplug state machine.

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arm64: Rearrange CPU errata workaround checks ------Right now we run through the work around checks on a CPU from __cpuinfo_store_cpu. There are some problems with that:

1) We initialise the system wide CPU feature registers only after the Boot CPU updates its cpuinfo. Now, if a work around depends on the variance of a CPU ID feature (e.g, check for Cache Line size mismatch), we have no way of performing it cleanly for the boot CPU.

2) It is out of place, invoked from __cpuinfo_store_cpu() in cpuinfo.c. It is not an obvious place for that.

This patch rearranges the CPU specific capability(aka work around) checks.

1) At the moment we use verify_local_cpu_capabilities() to check if a new CPU has all the system advertised features. Use this for the secondary CPUs to perform the work around check. For that we rename verify_local_cpu_capabilities() => check_local_cpu_capabilities() which:

If the system wide capabilities haven't been initialised (i.e, the CPU is activated at the boot), update the system wide detected work arounds.

Otherwise (i.e a CPU hotplugged in later) verify that this CPU conforms to the system wide capabilities.

2) Boot CPU updates the work arounds from smp_prepare_boot_cpu() after we have initialised the system wide CPU feature values.

3721 arch\arm64\kernel\cpuinfo.c#0251 3722 arch\arm64\kernel\cpuinfo.c#0267 3723 arch\arm64\kernel\cpuinfo.c#0287 3724 arch\arm64\kernel\cpuinfo.c#0289 3725 arch\arm64\kernel\cpuinfo.c#0295 3726 arch\arm64\kernel\cpuinfo.c#0298 3727 arch\arm64\kernel\cpuinfo.c#0300 3728 arch\arm64\kernel\debug-monitors.c#0143 Repo: 73c1b41e63f0 Thomas Wed Dec 21 20:19:54 2016 +0100 Description: cpu/hotplug: Cleanup state names ------

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When the state names got added a script was used to add the extra argument to the calls. The script basically converted the state constant to a string, but the cleanup to convert these strings into meaningful ones did not happen.

Replace all the useless strings with 'subsys/xxx/yyy:state' strings which are used in all the other places already.

arm64: Handle TRAP_BRKPT for user mode as well ------uprobe is registered at break_hook with a unique ESR code. So, when a TRAP_BRKPT occurs, call_break_hook checks if it was for uprobe. If not, then send a SIGTRAP to user.

arm64: Handle TRAP_TRACE for user mode as well ------uprobe registers a handler at step_hook. So, single_step_handler now checks for user mode as well if there is a valid hook.

3729 arch\arm64\kernel\debug-monitors.c#0229 3730 arch\arm64\kernel\debug-monitors.c#0238 3731 arch\arm64\kernel\debug-monitors.c#0255 3732 arch\arm64\kernel\debug-monitors.c#0309 3733 arch\arm64\kernel\debug-monitors.c#0312 3734 arch\arm64\kernel\debug-monitors.c#0317 3735 arch\arm64\kernel\efi.c#0065 Repo: f14c66ce81b5 Ard Fri Oct 21 12:22:57 2016 +0100 Description: arm64: mm: replace 'block_mappings_allowed' with 'page_mappings_only' ------In preparation of adding support for contiguous PTE and PMD mappings, let's replace 'block_mappings_allowed' with 'page_mappings_only', which will be a more accurate description of the nature of the setting once we add such contiguous mappings into the mix.

arm64: efi: avoid block mappings for unaligned UEFI memory regions ------When running the OS with a page size > 4 KB, we need to round up mappings for regions that are not aligned to the OS's page size. We already avoid block mappings for EfiRuntimeServicesCode/Data regions for other reasons, but in the unlikely event that other unaliged regions exists that have the EFI_MEMORY_RUNTIME attribute set, ensure that unaligned regions are always

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mapped down to pages. This way, the overlapping page is guaranteed not to be covered by a block mapping that needs to be split.

arm64: efi: always map runtime services code and data regions down to pages ------To avoid triggering diagnostics in the MMU code that are finicky about splitting block mappings into more granular mappings, ensure that regions that are likely to appear in the Memory Attributes table as well as the UEFI memory map are always mapped down to pages. This way, we can use apply_to_page_range() instead of create_pgd_mapping() for the second pass, which cannot split or merge block entries, and operates strictly on PTEs.

Note that this aligns the arm64 Memory Attributes table handling code with the ARM code, which already uses apply_to_page_range() to set the strict permissions.

3736 arch\arm64\kernel\efi.c#0079 3737 arch\arm64\kernel\efi.c#0084 3738 arch\arm64\kernel\entry.S#0032 Repo: 7d9e8f71b989 Mark RutlandWed Jan 18 17:23:41 2017 +0000 Description: arm64: avoid returning from bad_mode ------Generally, taking an unexpected exception should be a fatal event, and bad_mode is intended to cater for this. However, it should be possible to contain unexpected synchronous exceptions from EL0 without bringing the kernel down, by sending a SIGILL to the task.

We tried to apply this approach in commit 9955ac47f4ba1c95 ("arm64: don't kill the kernel on a bad esr from el0"), by sending a signal for any bad_mode call resulting from an EL0 exception.

However, this also applies to other unexpected exceptions, such as SError and FIQ. The entry paths for these exceptions branch to bad_mode without configuring the link register, and have no kernel_exit. Thus, if we take one of these exceptions from EL0, bad_mode will eventually return to the original user link register value.

This patch fixes this by introducing a new bad_el0_sync handler to cater for the recoverable case, and restoring bad_mode to its original state, whereby it calls panic() and never returns. The recoverable case branches to bad_el0_sync with a bl, and returns to userspace via the usual ret_to_user mechanism.

arm64: don't pull uaccess.h into *.S

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------Split asm-only parts of arm64 uaccess.h into a new header and use that from *.S.

Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

arm64: Disable TTBR0_EL1 during normal kernel execution ------When the TTBR0 PAN feature is enabled, the kernel entry points need to disable access to TTBR0_EL1. The PAN status of the interrupted context is stored as part of the saved pstate, reusing the PSR_PAN_BIT (22). Restoring access to TTBR0_EL1 is done on exception return if returning to user or returning to a context where PAN was disabled.

Context switching via switch_mm() must defer the update of TTBR0_EL1 until a return to user or an explicit uaccess_enable() call.

Special care needs to be taken for two cases where TTBR0_EL1 is set outside the normal kernel context switch operation: EFI run-time services (via efi_set_pgd) and CPU suspend (via cpu_(un)install_idmap). Code has been added to avoid deferred TTBR0_EL1 switching as in switch_mm() and restore the reserved TTBR0_EL1 when uninstalling the special TTBR0_EL1.

User cache maintenance (user_cache_maint_handler and __flush_cache_user_range) needs the TTBR0_EL1 re-instated since the operations are performed by user virtual address.

This patch also removes a stale comment on the switch_mm() function.

arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1 ------This patch adds the uaccess macros/functions to disable access to user space by setting TTBR0_EL1 to a reserved zeroed page. Since the value written to TTBR0_EL1 must be a physical address, for simplicity this patch introduces a reserved_ttbr0 page at a constant offset from swapper_pg_dir. The uaccess_disable code uses the ttbr1_el1 value adjusted by the reserved_ttbr0 offset.

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Enabling access to user is done by restoring TTBR0_EL1 with the value from the struct thread_info ttbr0 variable. Interrupts must be disabled during the uaccess_ttbr0_enable code to ensure the atomicity of the thread_info.ttbr0 read and TTBR0_EL1 write. This patch also moves the get_thread_info asm macro from entry.S to assembler.h for reuse in the uaccess_ttbr0_* macros.

arm64: split thread_info from task stack ------This patch moves arm64's struct thread_info from the task stack into task_struct. This protects thread_info from corruption in the case of stack overflows, and makes its address harder to determine if stack addresses are leaked, making a number of attacks more difficult. Precise detection and handling of overflow is left for subsequent patches.

Largely, this involves changing code to store the task_struct in sp_el0, and acquire the thread_info from the task struct. Core code now implements current_thread_info(), and as noted in this relies on offsetof(task_struct, thread_info) == 0, enforced by core code.

This change means that the 'tsk' register used in entry.S now points to a task_struct, rather than a thread_info as it used to. To make this clear, the TI_* field offsets are renamed to TSK_TI_*, with asm-offsets appropriately updated to account for the structural change.

Userspace clobbers sp_el0, and we can no longer restore this from the stack. Instead, the current task is cached in a per-cpu variable that we can safely access from early assembly as interrupts are disabled (and we are thus not preemptible).

Both secondary entry and idle are updated to stash the sp and task pointer separately.

arm64: assembler: introduce ldr_this_cpu ------Shortly we will want to load a percpu variable in the return from userspace path. We can save an instruction by folding the addition of the percpu offset into the load instruction, and this patch adds a new helper to do so.

At the same time, we clean up this_cpu_ptr for consistency. As with {adr,ldr,str}_l, we change the template to take the destination register first, and name this dst. Secondly, we rename the macro to adr_this_cpu, following the scheme of adr_l, and matching the newly added ldr_this_cpu.

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3739 arch\arm64\kernel\entry.S#0034 3740 arch\arm64\kernel\entry.S#0095 3741 arch\arm64\kernel\entry.S#0104 3742 arch\arm64\kernel\entry.S#0107 3743 arch\arm64\kernel\entry.S#0113 3744 arch\arm64\kernel\entry.S#0169 3745 arch\arm64\kernel\entry.S#0177 3746 arch\arm64\kernel\entry.S#0226 3747 arch\arm64\kernel\entry.S#0249 3748 arch\arm64\kernel\entry.S#0253 3749 arch\arm64\kernel\entry.S#0257 3750 arch\arm64\kernel\entry.S#0262 3751 arch\arm64\kernel\entry.S#0489 3752 arch\arm64\kernel\entry.S#0491 3753 arch\arm64\kernel\entry.S#0506 3754 arch\arm64\kernel\entry.S#0686 3755 arch\arm64\kernel\entry.S#0736 3756 arch\arm64\kernel\entry.S#0747 3757 arch\arm64\kernel\entry.S#0767 3758 arch\arm64\kernel\entry.S#0774 3759 arch\arm64\kernel\entry.S#0807 3760 arch\arm64\kernel\fpsimd.c#0130 Repo: 82e0191a1aa1 Suzuki K Tue Nov 8 13:56:21 2016 +0000 Description: arm64: Support systems without FP/ASIMD ------The arm64 kernel assumes that FP/ASIMD units are always present and accesses the FP/ASIMD specific registers unconditionally. This could cause problems when they are absent. This patch adds the support for kernel handling systems without FP/ASIMD by skipping the register access within the kernel. For kvm, we trap the accesses to FP/ASIMD and inject an undefined instruction exception to the VM.

The callers of the exported kernel_neon_begin_partial() should make sure that the FP/ASIMD is supported.

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3761 arch\arm64\kernel\fpsimd.c#0162 3762 arch\arm64\kernel\fpsimd.c#0175 3763 arch\arm64\kernel\fpsimd.c#0190 3764 arch\arm64\kernel\fpsimd.c#0210 3765 arch\arm64\kernel\fpsimd.c#0241 3766 arch\arm64\kernel\fpsimd.c#0267 3767 arch\arm64\kernel\head.S#0329 Repo: 1650ac49c2a0 Jintack Mon Nov 28 21:13:02 2016 -0500 Description: arm64: head.S: Fix CNTHCTL_EL2 access on VHE system ------Bit positions of CNTHCTL_EL2 are changing depending on HCR_EL2.E2H bit. EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is not set, but they are 11th and 10th bits respectively when E2H is set. Current code is unintentionally setting wrong bits to CNTHCTL_EL2 with E2H set.

In fact, we don't need to set those two bits, which allow EL1 and EL0 to access physical timer and counter respectively, if E2H and TGE are set for the host kernel. They will be configured later as necessary. First, we don't need to configure those bits for EL1, since the host kernel runs in EL2. It is a hypervisor's responsibility to configure them before entering a VM, which runs in EL0 and EL1. Second, EL0 accesses are configured in the later stage of boot process.

arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1 ------This patch adds the uaccess macros/functions to disable access to user space by setting TTBR0_EL1 to a reserved zeroed page. Since the value written to TTBR0_EL1 must be a physical address, for simplicity this patch introduces a reserved_ttbr0 page at a constant offset from swapper_pg_dir. The uaccess_disable code uses the ttbr1_el1 value adjusted by the reserved_ttbr0 offset.

Enabling access to user is done by restoring TTBR0_EL1 with the value from the struct thread_info ttbr0 variable. Interrupts must be disabled during the uaccess_ttbr0_enable code to ensure the atomicity of the thread_info.ttbr0 read and TTBR0_EL1 write. This patch also moves the get_thread_info asm macro from entry.S to assembler.h for reuse in the uaccess_ttbr0_* macros.

arm64: split thread_info from task stack ------This patch moves arm64's struct thread_info from the task stack into task_struct. This protects thread_info from corruption in the case of

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stack overflows, and makes its address harder to determine if stack addresses are leaked, making a number of attacks more difficult. Precise detection and handling of overflow is left for subsequent patches.

Largely, this involves changing code to store the task_struct in sp_el0, and acquire the thread_info from the task struct. Core code now implements current_thread_info(), and as noted in this relies on offsetof(task_struct, thread_info) == 0, enforced by core code.

This change means that the 'tsk' register used in entry.S now points to a task_struct, rather than a thread_info as it used to. To make this clear, the TI_* field offsets are renamed to TSK_TI_*, with asm-offsets appropriately updated to account for the structural change.

Userspace clobbers sp_el0, and we can no longer restore this from the stack. Instead, the current task is cached in a per-cpu variable that we can safely access from early assembly as interrupts are disabled (and we are thus not preemptible).

Both secondary entry and idle are updated to stash the sp and task pointer separately.

3768 arch\arm64\kernel\head.S#0336 3769 arch\arm64\kernel\head.S#0415 3770 arch\arm64\kernel\head.S#0431 3771 arch\arm64\kernel\head.S#0528 3772 arch\arm64\kernel\head.S#0542 3773 arch\arm64\kernel\head.S#0714 3774 arch\arm64\kernel\hibernate.c#0139 Repo: 9165dabb2500 Masanari Sat Sep 17 23:44:17 2016 +0900 Description: treewide: Fix printk() message errors ------This patch fix spelling typos in printk and kconfig.

Revert "arm64: hibernate: Refuse to hibernate if the boot cpu is offline" ------Now that we use the MPIDR to resume on the same CPU that we hibernated on, we no longer need to refuse to hibernate if the boot cpu is offline. (Which we can't possibly know if kexec causes logical CPUs to be renumbered).

This reverts commit 1fe492ce6482b77807b25d29690a48c46456beee.

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arm64: hibernate: Resume when hibernate image created on non-boot CPU ------disable_nonboot_cpus() assumes that the lowest numbered online CPU is the boot CPU, and that this is the correct CPU to run any power management code on.

On arm64 CPU0 can be taken offline. For hibernate/resume this means we may hibernate on a CPU other than CPU0. If the system is rebooted with kexec 'CPU0' will be assigned to a different CPU. This complicates hibernate/resume as now we can't trust the CPU numbers.

We currently forbid hibernate if CPU0 has been hotplugged out to avoid this situation without kexec.

Save the MPIDR of the CPU we hibernated on in the hibernate arch-header, use hibernate_resume_nonboot_cpu_disable() to direct which CPU we should resume on based on the MPIDR of the CPU we hibernated on. This allows us to hibernate/resume on any CPU, even if the logical numbers have been shuffled by kexec.

arm64: hibernate: Support DEBUG_PAGEALLOC ------DEBUG_PAGEALLOC removes the valid bit of page table entries to prevent any access to unallocated memory. Hibernate uses this as a hint that those pages don't need to be saved/restored. This patch adds the kernel_page_present() function it uses.

hibernate.c copies the resume kernel's linear map for use during restore. Add _copy_pte() to fill-in the holes made by DEBUG_PAGEALLOC in the resume kernel, so we can restore data the original kernel had at these addresses.

Finally, DEBUG_PAGEALLOC means the linear-map alias of KERNEL_START to KERNEL_END may have holes in it, so we can't lazily clean this whole area to the PoC. Only clean the new mmuoff region, and the kernel/kvm idmaps.

This reverts commit da24eb1f3f9e2c7b75c5f8c40d8e48e2c4789596.

3775 arch\arm64\kernel\hibernate.c#0550 3776 arch\arm64\kernel\hw_breakpoint.c#0320 Repo: 73c1b41e63f0 Thomas Wed Dec 21 20:19:54 2016 +0100 Description: cpu/hotplug: Cleanup state names ------When the state names got added a script was used to add the extra argument to the calls. The script basically converted the state constant to a

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string, but the cleanup to convert these strings into meaningful ones did not happen.

Replace all the useless strings with 'subsys/xxx/yyy:state' strings which are used in all the other places already.

arm64: Allow hw watchpoint of length 3,5,6 and 7 ------Since, arm64 can support all offset within a double word limit. Therefore, now support other lengths within that range as well.

arm64: hw_breakpoint: Handle inexact watchpoint addresses ------Arm64 hardware does not always report a watchpoint hit address that matches one of the watchpoints set. It can also report an address "near" the watchpoint if a single instruction access both watched and unwatched addresses. There is no straight-forward way, short of disassembling the offending instruction, to map that address back to the watchpoint.

Previously, when the hardware reported a watchpoint hit on an address that did not match our watchpoint (this happens in case of instructions which access large chunks of memory such as "stp") the process would enter a loop where we would be continually resuming it (because we did not recognise that watchpoint hit) and it would keep hitting the watchpoint again and again. The tracing process would never get notified of the watchpoint hit.

This commit fixes the problem by looking at the watchpoints near the address reported by the hardware. If the address does not exactly match one of the watchpoints we have set, it attributes the hit to the nearest watchpoint we have. This heuristic is a bit dodgy, but I don't think we can do much more, given the hardware limitations.

arm64: Allow hw watchpoint at varied offset from base address ------ARM64 hardware supports watchpoint at any double word aligned address. However, it can select any consecutive bytes from offset 0 to 7 from that base address. For example, if base address is programmed as 0x420030 and byte select is 0x1C, then access of 0x420032,0x420033 and 0x420034 will generate a watchpoint exception.

Currently, we do not have such modularity. We can only program byte, halfword, word and double word access exception from any base address.

This patch adds support to overcome above limitations.

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3777 arch\arm64\kernel\hw_breakpoint.c#0326 3778 arch\arm64\kernel\hw_breakpoint.c#0364 3779 arch\arm64\kernel\hw_breakpoint.c#0384 3780 arch\arm64\kernel\hw_breakpoint.c#0389 3781 arch\arm64\kernel\hw_breakpoint.c#0396 3782 arch\arm64\kernel\hw_breakpoint.c#0402 3783 arch\arm64\kernel\hw_breakpoint.c#0454 3784 arch\arm64\kernel\hw_breakpoint.c#0460 3785 arch\arm64\kernel\hw_breakpoint.c#0560 3786 arch\arm64\kernel\hw_breakpoint.c#0565 3787 arch\arm64\kernel\hw_breakpoint.c#0568 3788 arch\arm64\kernel\hw_breakpoint.c#0703 3789 arch\arm64\kernel\hw_breakpoint.c#0740 3790 arch\arm64\kernel\hw_breakpoint.c#0743 3791 arch\arm64\kernel\hw_breakpoint.c#0752 3792 arch\arm64\kernel\hw_breakpoint.c#0758 3793 arch\arm64\kernel\hw_breakpoint.c#0759 3794 arch\arm64\kernel\hw_breakpoint.c#0760 3795 arch\arm64\kernel\hw_breakpoint.c#0762 3796 arch\arm64\kernel\hw_breakpoint.c#0769 3797 arch\arm64\kernel\hw_breakpoint.c#0771 3798 arch\arm64\kernel\hw_breakpoint.c#0791 3799 arch\arm64\kernel\hw_breakpoint.c#0799 3800 arch\arm64\kernel\hw_breakpoint.c#0803 3801 arch\arm64\kernel\hw_breakpoint.c#1004 3802 arch\arm64\kernel\insn.c#0033 Repo: bca8f17f57bd Marc Zyngier Thu Dec 1 10:44:33 2016 +0000 Description: arm64: Get rid of asm/opcodes.h ------The opcodes.h drags in a lot of definition from the 32bit port, most of which is not required at all. Clean things up a bit by moving the bare minimum of what is required next to the actual users, and drop the include file.

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3803 arch\arm64\kernel\kgdb.c#0250 Repo: b66c9870e974 Pratyush Wed Nov 2 14:40:42 2016 +0530 Description: arm64: kgdb_step_brk_fn: ignore other's exception ------ARM64 step exception does not have any syndrome information. So, it is responsibility of exception handler to take care that they handle it only if exception was raised for them.

Since kgdb_step_brk_fn() always returns 0, therefore we might have problem when we will have other step handler registered as well.

This patch fixes kgdb_step_brk_fn() to return error in case of step handler was not meant for kgdb.

3804 arch\arm64\kernel\pci.c#0117 Repo: 13983eb89d5a Tomasz Fri Sep 9 21:24:03 2016 +0200 Description: PCI/ACPI: Extend pci_mcfg_lookup() to return ECAM config accessors ------pci_mcfg_lookup() is the external interface to the generic MCFG code. Previously it merely looked up the ECAM base address for a given domain and bus range. We want a way to add MCFG quirks, some of which may require special config accessors and adjustments to the ECAM address range.

Extend pci_mcfg_lookup() so it can return a pointer to a pci_ecam_ops structure and a struct resource for the ECAM address space. For now, it always returns &pci_generic_ecam_ops (the standard accessor) and the resource described by the MCFG.

No functional changes intended.

[bhelgaas: changelog]

arm64: PCI: Exclude ACPI "consumer" resources from host bridge windows ------On x86 and ia64, we have treated all ACPI _CRS resources of PNP0A03 host bridge devices as "producers", i.e., as host bridge windows. That's partly because some x86 BIOSes improperly used "consumer" descriptors to describe windows and partly because Linux didn't have good support for handling consumer and producer descriptors differently.

One result is that x86 BIOSes describe host bridge "consumer" resources in the _CRS of a PNP0C02 device, not the PNP0A03 device itself. On arm64 we don't have a legacy of firmware that has this consumer/producer confusion, so we can handle PNP0A03 "consumer" descriptors as host bridge registers instead of windows.

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Exclude non-window ("consumer") resources from the list of host bridge windows. This allows the use of "consumer" PNP0A03 descriptors for bridge register space.

arm64: PCI: Manage controller-specific data on per-controller basis ------Currently we use one shared global acpi_pci_root_ops structure to keep controller-specific ops. We pass its pointer to acpi_pci_root_create() and associate it with a host bridge instance for good. Such a design implies serious drawback. Any potential manipulation on the single system-wide acpi_pci_root_ops leads to kernel crash. The structure content is not really changing even across multiple host bridges creation; thus it was not an issue so far.

In preparation for adding ECAM quirks mechanism (where controller-specific PCI ops may be different for each host bridge) allocate new acpi_pci_root_ops and fill in with data for each bridge. Now it is safe to have different controller-specific info. As a consequence free acpi_pci_root_ops when host bridge is released.

No functional changes in this patch.

arm64: PCI: Search ACPI namespace to ensure ECAM space is reserved ------The static MCFG table tells us the base of ECAM space, but it does not reserve the space -- the reservation should be done via a device in the ACPI namespace whose _CRS includes the ECAM region.

Use acpi_resource_consumer() to check whether the ECAM space is reserved by an ACPI namespace device. If it is, emit a message showing which device reserves it. If not, emit a "[Firmware Bug]" warning.

arm64: PCI: Add local struct device pointers ------Use a local "struct device *dev" for brevity. No functional change intended.

3805 arch\arm64\kernel\pci.c#0137 3806 arch\arm64\kernel\pci.c#0140 3807 arch\arm64\kernel\pci.c#0142

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3808 arch\arm64\kernel\pci.c#0146 3809 arch\arm64\kernel\pci.c#0152 3810 arch\arm64\kernel\pci.c#0162 3811 arch\arm64\kernel\pci.c#0177 3812 arch\arm64\kernel\pci.c#0181 3813 arch\arm64\kernel\pci.c#0187 3814 arch\arm64\kernel\pci.c#0193 3815 arch\arm64\kernel\pci.c#0200 3816 arch\arm64\kernel\pci.c#0204 3817 arch\arm64\kernel\process.c#0048 Repo: a4023f682739 Suzuki K Tue Nov 8 13:56:20 2016 +0000 Description: arm64: Add hypervisor safe helper for checking constant capabilities ------The hypervisor may not have full access to the kernel data structures and hence cannot safely use cpus_have_cap() helper for checking the system capability. Add a safe helper for hypervisors to check a constant system capability, which *doesn't* fall back to checking the bitmap maintained by the kernel. With this, make the cpus_have_cap() only check the bitmask and force constant cap checks to use the new API for quicker checks.

arm64: split thread_info from task stack ------This patch moves arm64's struct thread_info from the task stack into task_struct. This protects thread_info from corruption in the case of stack overflows, and makes its address harder to determine if stack addresses are leaked, making a number of attacks more difficult. Precise detection and handling of overflow is left for subsequent patches.

Largely, this involves changing code to store the task_struct in sp_el0, and acquire the thread_info from the task struct. Core code now implements current_thread_info(), and as noted in this relies on offsetof(task_struct, thread_info) == 0, enforced by core code.

This change means that the 'tsk' register used in entry.S now points to a task_struct, rather than a thread_info as it used to. To make this clear, the TI_* field offsets are renamed to TSK_TI_*, with asm-offsets appropriately updated to account for the structural change.

Userspace clobbers sp_el0, and we can no longer restore this from the stack. Instead, the current task is cached in a per-cpu variable that we

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can safely access from early assembly as interrupts are disabled (and we are thus not preemptible).

Both secondary entry and idle are updated to stash the sp and task pointer separately.

arm64: prep stack walkers for THREAD_INFO_IN_TASK ------When CONFIG_THREAD_INFO_IN_TASK is selected, task stacks may be freed before a task is destroyed. To account for this, the stacks are refcounted, and when manipulating the stack of another task, it is necessary to get/put the stack to ensure it isn't freed and/or re-used while we do so.

This patch reworks the arm64 stack walking code to account for this. When CONFIG_THREAD_INFO_IN_TASK is not selected these perform no refcounting, and this should only be a structural change that does not affect behaviour.

3818 arch\arm64\kernel\process.c#0286 3819 arch\arm64\kernel\process.c#0326 3820 arch\arm64\kernel\process.c#0351 3821 arch\arm64\kernel\process.c#0369 3822 arch\arm64\kernel\process.c#0374 3823 arch\arm64\kernel\process.c#0384 3824 arch\arm64\kernel\process.c#0388 3825 arch\arm64\kernel\process.c#0394 3826 arch\arm64\kernel\ptrace.c#0330 Repo: ad9e202aa1ce Dave Martin Wed Jan 18 16:25:24 2017 +0000 Description: arm64/ptrace: Reject attempts to set incomplete hardware breakpoint fields ------We cannot preserve partial fields for hardware breakpoints, because the values written by userspace to the hardware breakpoint registers can't subsequently be recovered intact from the hardware.

So, just reject attempts to write incomplete fields with -EINVAL.

arm64/ptrace: Preserve previous registers for short regset write ------Ensure that if userspace supplies insufficient data to PTRACE_SETREGSET to fill all the registers, the thread's old

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registers are preserved.

arm64/ptrace: Preserve previous registers for short regset write ------Ensure that if userspace supplies insufficient data to PTRACE_SETREGSET to fill all the registers, the thread's old registers are preserved.

arm64/ptrace: Preserve previous registers for short regset write ------Ensure that if userspace supplies insufficient data to PTRACE_SETREGSET to fill all the registers, the thread's old registers are preserved.

arm64: Allow hw watchpoint at varied offset from base address ------ARM64 hardware supports watchpoint at any double word aligned address. However, it can select any consecutive bytes from offset 0 to 7 from that base address. For example, if base address is programmed as 0x420030 and byte select is 0x1C, then access of 0x420032,0x420033 and 0x420034 will generate a watchpoint exception.

Currently, we do not have such modularity. We can only program byte, halfword, word and double word access exception from any base address.

This patch adds support to overcome above limitations.

3827 arch\arm64\kernel\ptrace.c#0336 3828 arch\arm64\kernel\ptrace.c#0355 3829 arch\arm64\kernel\ptrace.c#0408 Review: COMMENT stecan Thu, 11 Jan 2018 07:26:59 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:59 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:26:59 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:59 +0100 Automatic commented! 3830 arch\arm64\kernel\ptrace.c#0554

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3831 arch\arm64\kernel\ptrace.c#0565 3832 arch\arm64\kernel\ptrace.c#0603 3833 arch\arm64\kernel\ptrace.c#0633 3834 arch\arm64\kernel\ptrace.c#0658 3835 arch\arm64\kernel\ptrace.c#0684 3836 arch\arm64\kernel\ptrace.c#0957 3837 arch\arm64\kernel\return_address.c#0015 Repo: a9ea0017ebe8 Mark RutlandThu Nov 3 20:23:05 2016 +0000 Description: arm64: factor out current_stack_pointer ------We define current_stack_pointer in , though other files and header relying upon it do not have this necessary include, and are thus fragile to changes in the header soup.

Subsequent patches will affect the header soup such that directly including may result in a circular header include in some of these cases, so we can't simply include .

Instead, factor current_thread_info into its own header, and have all existing users include this explicitly.

arm64: ftrace: fix a stack tracer's output under function graph tracer ------Function graph tracer modifies a return address (LR) in a stack frame to hook a function return. This will result in many useless entries (return_to_handler) showing up in a) a stack tracer's output b) perf call graph (with perf record -g) c) dump_backtrace (at panic et al.)

For example, in case of a), $ echo function_graph > /sys/kernel/debug/tracing/current_tracer $ echo 1 > /proc/sys/kernel/stack_trace_enabled $ cat /sys/kernel/debug/tracing/stack_trace Depth Size Location (54 entries) ------0) 4504 16 gic_raise_softirq+0x28/0x150 1) 4488 80 smp_cross_call+0x38/0xb8 2) 4408 48 return_to_handler+0x0/0x40 3) 4360 32 return_to_handler+0x0/0x40 ...

In case of b), $ echo function_graph > /sys/kernel/debug/tracing/current_tracer

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$ perf record -e mem:XXX:x -ag -- sleep 10 $ perf report ... | | |--0.22%-- 0x550f8 | | | 0x10888 | | | el0_svc_naked | | | sys_openat | | | return_to_handler | | | return_to_handler ...

In case of c), $ echo function_graph > /sys/kernel/debug/tracing/current_tracer $ echo c > /proc/sysrq-trigger ... Call trace: [] sysrq_handle_crash+0x24/0x30 [] return_to_handler+0x0/0x40 [] return_to_handler+0x0/0x40 ...

This patch replaces such entries with real addresses preserved in current->ret_stack[] at unwind_frame(). This way, we can cover all the cases.

3838 arch\arm64\kernel\setup.c#0294 Repo: 7ede8665f27c Alexander Mon Dec 19 16:23:06 2016 -0800 Description: arm64: setup: introduce kaslr_offset() ------Introduce kaslr_offset() similar to x86_64 to fix kcov.

[ Updated by Will Deacon ]

Link: http://lkml.kernel.org/r/[email protected]

arm64: Disable TTBR0_EL1 during normal kernel execution ------When the TTBR0 PAN feature is enabled, the kernel entry points need to disable access to TTBR0_EL1. The PAN status of the interrupted context is stored as part of the saved pstate, reusing the PSR_PAN_BIT (22). Restoring access to TTBR0_EL1 is done on exception return if returning to user or returning to a context where PAN was disabled.

Context switching via switch_mm() must defer the update of TTBR0_EL1 until a return to user or an explicit uaccess_enable() call.

Special care needs to be taken for two cases where TTBR0_EL1 is set outside the normal kernel context switch operation: EFI run-time

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services (via efi_set_pgd) and CPU suspend (via cpu_(un)install_idmap). Code has been added to avoid deferred TTBR0_EL1 switching as in switch_mm() and restore the reserved TTBR0_EL1 when uninstalling the special TTBR0_EL1.

User cache maintenance (user_cache_maint_handler and __flush_cache_user_range) needs the TTBR0_EL1 re-instated since the operations are performed by user virtual address.

This patch also removes a stale comment on the switch_mm() function.

3839 arch\arm64\kernel\setup.c#0341 3840 arch\arm64\kernel\setup.c#0343 3841 arch\arm64\kernel\signal.c#0417 Repo: 9842ceae9fa8 Pratyush Wed Nov 2 14:40:46 2016 +0530 Description: arm64: Add uprobe support ------This patch adds support for uprobe on ARM64 architecture.

Unit tests for following have been done so far and they have been found working 1. Step-able instructions, like sub, ldr, add etc. 2. Simulation-able like ret, cbnz, cbz etc. 3. uretprobe 4. Reject-able instructions like sev, wfe etc. 5. trapped and abort xol path 6. probe at unaligned user address. 7. longjump test cases

Currently it does not support aarch32 instruction probing.

3842 arch\arm64\kernel\signal32.c#0029 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

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arm64: Fix misspellings in comments. ------

3843 arch\arm64\kernel\sleep.S#0128 Repo: 623b476fc815 Mark RutlandThu Nov 3 20:23:09 2016 +0000 Description: arm64: move sp_el0 and tpidr_el1 into cpu_suspend_ctx ------When returning from idle, we rely on the fact that thread_info lives at the end of the kernel stack, and restore this by masking the saved stack pointer. Subsequent patches will sever the relationship between the stack and thread_info, and to cater for this we must save/restore sp_el0 explicitly, storing it in cpu_suspend_ctx.

As cpu_suspend_ctx must be doubleword aligned, this leaves us with an extra slot in cpu_suspend_ctx. We can use this to save/restore tpidr_el1 in the same way, which simplifies the code, avoiding pointer chasing on the restore path (as we no longer need to load thread_info::cpu followed by the relevant slot in __per_cpu_offset based on this).

This patch stashes both registers in cpu_suspend_ctx.

3844 arch\arm64\kernel\smp.c#0061 Repo: c02433dd6de3 Mark RutlandThu Nov 3 20:23:13 2016 +0000 Description: arm64: split thread_info from task stack ------This patch moves arm64's struct thread_info from the task stack into task_struct. This protects thread_info from corruption in the case of stack overflows, and makes its address harder to determine if stack addresses are leaked, making a number of attacks more difficult. Precise detection and handling of overflow is left for subsequent patches.

Largely, this involves changing code to store the task_struct in sp_el0, and acquire the thread_info from the task struct. Core code now implements current_thread_info(), and as noted in this relies on offsetof(task_struct, thread_info) == 0, enforced by core code.

This change means that the 'tsk' register used in entry.S now points to a task_struct, rather than a thread_info as it used to. To make this clear, the TI_* field offsets are renamed to TSK_TI_*, with asm-offsets appropriately updated to account for the structural change.

Userspace clobbers sp_el0, and we can no longer restore this from the stack. Instead, the current task is cached in a per-cpu variable that we can safely access from early assembly as interrupts are disabled (and we

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are thus not preemptible).

Both secondary entry and idle are updated to stash the sp and task pointer separately.

arm64: make cpu number a percpu variable ------In the absence of CONFIG_THREAD_INFO_IN_TASK, core code maintains thread_info::cpu, and low-level architecture code can access this to build raw_smp_processor_id(). With CONFIG_THREAD_INFO_IN_TASK, core code maintains task_struct::cpu, which for reasons of hte header soup is not accessible to low-level arch code.

Instead, we can maintain a percpu variable containing the cpu number.

For both the old and new implementation of raw_smp_processor_id(), we read a syreg into a GPR, add an offset, and load the result. As the offset is now larger, it may not be folded into the load, but otherwise the assembly shouldn't change much.

arm64: smp: prepare for smp_processor_id() rework ------Subsequent patches will make smp_processor_id() use a percpu variable. This will make smp_processor_id() dependent on the percpu offset, and thus we cannot use smp_processor_id() to figure out what to initialise the offset to.

Prepare for this by initialising the percpu offset based on current::cpu, which will work regardless of how smp_processor_id() is implemented. Also, make this relationship obvious by placing this code together at the start of secondary_start_kernel().

3845 arch\arm64\kernel\smp.c#0152 3846 arch\arm64\kernel\smp.c#0177 3847 arch\arm64\kernel\smp.c#0216 3848 arch\arm64\kernel\smp.c#0218 3849 arch\arm64\kernel\smp.c#0228 3850 arch\arm64\kernel\smp.c#0727 3851 arch\arm64\kernel\stacktrace.c#0025 Repo: 9bbd4c56b0b6 Mark RutlandThu Nov 3 20:23:08 2016 +0000 Description: arm64: prep stack walkers for THREAD_INFO_IN_TASK ------

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When CONFIG_THREAD_INFO_IN_TASK is selected, task stacks may be freed before a task is destroyed. To account for this, the stacks are refcounted, and when manipulating the stack of another task, it is necessary to get/put the stack to ensure it isn't freed and/or re-used while we do so.

This patch reworks the arm64 stack walking code to account for this. When CONFIG_THREAD_INFO_IN_TASK is not selected these perform no refcounting, and this should only be a structural change that does not affect behaviour.

arm64: unexport walk_stackframe ------The walk_stackframe functions is architecture-specific, with a varying prototype, and common code should not use it directly. None of its current users can be built as modules. With THREAD_INFO_IN_TASK, users will also need to hold a stack reference before calling it.

There's no reason for it to be exported, and it's very easy to misuse, so unexport it for now.

arm64: factor out current_stack_pointer ------We define current_stack_pointer in , though other files and header relying upon it do not have this necessary include, and are thus fragile to changes in the header soup.

Subsequent patches will affect the header soup such that directly including may result in a circular header include in some of these cases, so we can't simply include .

Instead, factor current_thread_info into its own header, and have all existing users include this explicitly.

3852 arch\arm64\kernel\stacktrace.c#0132 3853 arch\arm64\kernel\stacktrace.c#0184 3854 arch\arm64\kernel\stacktrace.c#0208 3855 arch\arm64\kernel\suspend.c#0050 Repo: 623b476fc815 Mark RutlandThu Nov 3 20:23:09 2016 +0000 Description: arm64: move sp_el0 and tpidr_el1 into cpu_suspend_ctx ------When returning from idle, we rely on the fact that thread_info lives at the end of the kernel stack, and restore this by masking the saved stack pointer. Subsequent patches will sever the relationship between the

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stack and thread_info, and to cater for this we must save/restore sp_el0 explicitly, storing it in cpu_suspend_ctx.

As cpu_suspend_ctx must be doubleword aligned, this leaves us with an extra slot in cpu_suspend_ctx. We can use this to save/restore tpidr_el1 in the same way, which simplifies the code, avoiding pointer chasing on the restore path (as we no longer need to load thread_info::cpu followed by the relevant slot in __per_cpu_offset based on this).

This patch stashes both registers in cpu_suspend_ctx.

3856 arch\arm64\kernel\topology.c#0014 Repo: 606f42265d38 Prashanth Thu Jan 26 11:08:32 2017 -0700 Description: arm64: skip register_cpufreq_notifier on ACPI-based systems ------On ACPI based systems where the topology is setup using the API store_cpu_topology, at the moment we do not have necessary code to parse cpu capacity and handle cpufreq notifier, thus resulting in a kernel panic.

Stack: init_cpu_capacity_callback+0xb4/0x1c8 notifier_call_chain+0x5c/0xa0 __blocking_notifier_call_chain+0x58/0xa0 blocking_notifier_call_chain+0x3c/0x50 cpufreq_set_policy+0xe4/0x328 cpufreq_init_policy+0x80/0x100 cpufreq_online+0x418/0x710 cpufreq_add_dev+0x118/0x180 subsys_interface_register+0xa4/0xf8 cpufreq_register_driver+0x1c0/0x298 cppc_cpufreq_init+0xdc/0x1000 [cppc_cpufreq] do_one_initcall+0x5c/0x168 do_init_module+0x64/0x1e4 load_module+0x130c/0x14d0 SyS_finit_module+0x108/0x120 el0_svc_naked+0x24/0x28

Fixes: 7202bde8b7ae ("arm64: parse cpu capacity-dmips-mhz from DT")

arm64: add sysfs cpu_capacity attribute ------Add a sysfs cpu_capacity attribute with which it is possible to read and write (thus over-writing default values) CPUs capacity. This might be useful in situations where values needs changing after boot.

The new attribute shows up as:

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/sys/devices/system/cpu/cpu*/cpu_capacity

arm64: parse cpu capacity-dmips-mhz from DT ------With the introduction of cpu capacity-dmips-mhz bindings, CPU capacities can now be calculated from values extracted from DT and information coming from cpufreq. Add parsing of DT information at boot time, and complement it with cpufreq information. Also, store such information using per CPU variables, as we do for arm.

Caveat: the information provided by this patch will start to be used in the future. We need to #define arch_scale_cpu_capacity to something provided in arch, so that scheduler's default implementation (which gets used if arch_scale_cpu_capacity is not defined) is overwritten.

3857 arch\arm64\kernel\topology.c#0023 3858 arch\arm64\kernel\topology.c#0027 3859 arch\arm64\kernel\topology.c#0031 3860 arch\arm64\kernel\topology.c#0259 3861 arch\arm64\kernel\topology.c#0404 3862 arch\arm64\kernel\topology.c#0407 3863 arch\arm64\kernel\topology.c#0413 3864 arch\arm64\kernel\traps.c#0041 Repo: 7d9e8f71b989 Mark RutlandWed Jan 18 17:23:41 2017 +0000 Description: arm64: avoid returning from bad_mode ------Generally, taking an unexpected exception should be a fatal event, and bad_mode is intended to cater for this. However, it should be possible to contain unexpected synchronous exceptions from EL0 without bringing the kernel down, by sending a SIGILL to the task.

We tried to apply this approach in commit 9955ac47f4ba1c95 ("arm64: don't kill the kernel on a bad esr from el0"), by sending a signal for any bad_mode call resulting from an EL0 exception.

However, this also applies to other unexpected exceptions, such as SError and FIQ. The entry paths for these exceptions branch to bad_mode without configuring the link register, and have no kernel_exit. Thus, if we take one of these exceptions from EL0, bad_mode will eventually return to the original user link register value.

This patch fixes this by introducing a new bad_el0_sync handler to cater for the recoverable case, and restoring bad_mode to its original state,

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whereby it calls panic() and never returns. The recoverable case branches to bad_el0_sync with a bl, and returns to userspace via the usual ret_to_user mechanism.

arm64: Disable TTBR0_EL1 during normal kernel execution ------When the TTBR0 PAN feature is enabled, the kernel entry points need to disable access to TTBR0_EL1. The PAN status of the interrupted context is stored as part of the saved pstate, reusing the PSR_PAN_BIT (22). Restoring access to TTBR0_EL1 is done on exception return if returning to user or returning to a context where PAN was disabled.

Context switching via switch_mm() must defer the update of TTBR0_EL1 until a return to user or an explicit uaccess_enable() call.

Special care needs to be taken for two cases where TTBR0_EL1 is set outside the normal kernel context switch operation: EFI run-time services (via efi_set_pgd) and CPU suspend (via cpu_(un)install_idmap). Code has been added to avoid deferred TTBR0_EL1 switching as in switch_mm() and restore the reserved TTBR0_EL1 when uninstalling the special TTBR0_EL1.

User cache maintenance (user_cache_maint_handler and __flush_cache_user_range) needs the TTBR0_EL1 re-instated since the operations are performed by user virtual address.

This patch also removes a stale comment on the switch_mm() function.

arm64: prep stack walkers for THREAD_INFO_IN_TASK ------When CONFIG_THREAD_INFO_IN_TASK is selected, task stacks may be freed before a task is destroyed. To account for this, the stacks are refcounted, and when manipulating the stack of another task, it is necessary to get/put the stack to ensure it isn't freed and/or re-used while we do so.

This patch reworks the arm64 stack walking code to account for this. When CONFIG_THREAD_INFO_IN_TASK is not selected these perform no refcounting, and this should only be a structural change that does not affect behaviour.

arm64: traps: simplify die() and __die() ------In arm64's die and __die routines we pass around a thread_info, and subsequently use this to determine the relevant task_struct, and the end of the thread's stack. Subsequent patches will decouple thread_info from the stack, and this approach will no longer work.

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To figure out the end of the stack, we can use the new generic end_of_stack() helper. As we only call __die() from die(), and die() always deals with the current task, we can remove the parameter and have both acquire current directly, which also makes it clear that __die can't be called for arbitrary tasks.

arm64: factor out current_stack_pointer ------We define current_stack_pointer in , though other files and header relying upon it do not have this necessary include, and are thus fragile to changes in the header soup.

Subsequent patches will affect the header soup such that directly including may result in a circular header include in some of these cases, so we can't simply include .

Instead, factor current_thread_info into its own header, and have all existing users include this explicitly.

arm64: cpufeature: Schedule enable() calls instead of calling them via IPI ------The enable() call for a cpufeature/errata is called using on_each_cpu(). This issues a cross-call IPI to get the work done. Implicitly, this stashes the running PSTATE in SPSR when the CPU receives the IPI, and restores it when we return. This means an enable() call can never modify PSTATE.

To allow PAN to do this, change the on_each_cpu() call to use stop_machine(). This schedules the work on each CPU which allows us to modify PSTATE.

This involves changing the protype of all the enable() functions.

enable_cpu_capabilities() is called during boot and enables the feature on all online CPUs. This path now uses stop_machine(). CPU features for hotplug'd CPUs are enabled by verify_local_cpu_features() which only acts on the local CPU, and can already modify the running PSTATE as it is called from secondary_start_kernel().

3865 arch\arm64\kernel\traps.c#0151 3866 arch\arm64\kernel\traps.c#0219

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3867 arch\arm64\kernel\traps.c#0236 3868 arch\arm64\kernel\traps.c#0238 3869 arch\arm64\kernel\traps.c#0253 3870 arch\arm64\kernel\traps.c#0273 3871 arch\arm64\kernel\traps.c#0280 3872 arch\arm64\kernel\traps.c#0282 3873 arch\arm64\kernel\traps.c#0443 3874 arch\arm64\kernel\traps.c#0445 3875 arch\arm64\kernel\traps.c#0458 3876 arch\arm64\kernel\traps.c#0607 Review: COMMENT stecan Thu, 11 Jan 2018 07:26:59 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:59 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:26:59 +0100 Short Description: stecan Thu, 11 Jan 2018 07:26:59 +0100 Automatic commented! 3877 arch\arm64\kernel\traps.c#0612 3878 arch\arm64\kernel\traps.c#0617 3879 arch\arm64\kernel\traps.c#0642 3880 arch\arm64\kernel\.lds.S#0219 Repo: 4b65a5db3627 Catalin Fri Jul 1 16:53:00 2016 +0100 Description: arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1 ------This patch adds the uaccess macros/functions to disable access to user space by setting TTBR0_EL1 to a reserved zeroed page. Since the value written to TTBR0_EL1 must be a physical address, for simplicity this patch introduces a reserved_ttbr0 page at a constant offset from swapper_pg_dir. The uaccess_disable code uses the ttbr1_el1 value adjusted by the reserved_ttbr0 offset.

Enabling access to user is done by restoring TTBR0_EL1 with the value from the struct thread_info ttbr0 variable. Interrupts must be disabled during the uaccess_ttbr0_enable code to ensure the atomicity of the thread_info.ttbr0 read and TTBR0_EL1 write. This patch also moves the get_thread_info asm macro from entry.S to assembler.h for reuse in the uaccess_ttbr0_* macros.

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Line Link NR. Descriptions arch\arm64\kernel\probes\ 3881 arch\arm64\kernel\probes\decode-insn.c#0020 Repo: 7b03b6223105 Pratyush Mon Nov 7 23:07:22 2016 +0530 Description: arm64: fix error: conflicting types for 'kprobe_fault_handler' ------When CONFIG_KPROBE is disabled but CONFIG_UPROBE_EVENT is enabled, we get following compilation error:

In file included from .../arch/arm64/kernel/probes/decode-insn.c:20:0: .../arch/arm64/include/asm/kprobes.h:52:5: error: conflicting types for 'kprobe_fault_handler' int kprobe_fault_handler(struct pt_regs *regs, unsigned int fsr); ^~~~~~~~~~~~~~~~~~~~ In file included from .../arch/arm64/kernel/probes/decode-insn.c:17:0: .../include/linux/kprobes.h:398:90: note: previous definition of 'kprobe_fault_handler' was here static inline int kprobe_fault_handler(struct pt_regs *regs, int trapnr) ^ .../scripts/Makefile.build:290: recipe for target 'arch/arm64/kernel/probes/decode-insn.o' failed

is already included from under #ifdef CONFIG_KPROBE. So, this patch fixes the error by removing it from decode-insn.c.

arm64: kprobe: protect/rename few definitions to be reused by uprobe ------decode-insn code has to be reused by arm64 uprobe implementation as well. Therefore, this patch protects some portion of kprobe code and renames few other, so that decode-insn functionality can be reused by uprobe even when CONFIG_KPROBES is not defined.

kprobe_opcode_t and struct arch_specific_insn are also defined by linux/kprobes.h, when CONFIG_KPROBES is not defined. So, protect these definitions in asm/probes.h.

linux/kprobes.h already includes asm/kprobes.h. Therefore, remove inclusion of asm/kprobes.h from decode-insn.c.

There are some definitions like kprobe_insn and kprobes_handler_t etc can be re-used by uprobe. So, it would be better to remove 'k' from their names.

struct arch_specific_insn is specific to kprobe. Therefore, introduce a new struct arch_probe_insn which will be common for both kprobe and uprobe, so

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that decode-insn code can be shared. Modify kprobe code accordingly.

Function arm_probe_decode_insn() will be needed by uprobe as well. So make it global.

3882 arch\arm64\kernel\probes\decode-insn.c#0081 3883 arch\arm64\kernel\probes\decode-insn.c#0092 3884 arch\arm64\kernel\probes\decode-insn.c#0095 3885 arch\arm64\kernel\probes\decode-insn.c#0098 3886 arch\arm64\kernel\probes\decode-insn.c#0100 3887 arch\arm64\kernel\probes\decode-insn.c#0103 3888 arch\arm64\kernel\probes\decode-insn.c#0107 3889 arch\arm64\kernel\probes\decode-insn.c#0109 3890 arch\arm64\kernel\probes\decode-insn.c#0111 3891 arch\arm64\kernel\probes\decode-insn.c#0123 3892 arch\arm64\kernel\probes\decode-insn.c#0141 3893 arch\arm64\kernel\probes\decode-insn.c#0144 3894 arch\arm64\kernel\probes\decode-insn.c#0165 3895 arch\arm64\kernel\probes\decode-insn.c#0173 3896 arch\arm64\kernel\probes\decode-insn.h#0026 Repo: c2249707ee53 Pratyush Wed Nov 2 14:40:41 2016 +0530 Description: arm64: kprobe: protect/rename few definitions to be reused by uprobe ------decode-insn code has to be reused by arm64 uprobe implementation as well. Therefore, this patch protects some portion of kprobe code and renames few other, so that decode-insn functionality can be reused by uprobe even when CONFIG_KPROBES is not defined.

kprobe_opcode_t and struct arch_specific_insn are also defined by linux/kprobes.h, when CONFIG_KPROBES is not defined. So, protect these definitions in asm/probes.h.

linux/kprobes.h already includes asm/kprobes.h. Therefore, remove inclusion of asm/kprobes.h from decode-insn.c.

There are some definitions like kprobe_insn and kprobes_handler_t etc can be re-used by uprobe. So, it would be better to remove 'k' from their names.

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struct arch_specific_insn is specific to kprobe. Therefore, introduce a new struct arch_probe_insn which will be common for both kprobe and uprobe, so that decode-insn code can be shared. Modify kprobe code accordingly.

Function arm_probe_decode_insn() will be needed by uprobe as well. So make it global.

arm64: kprobes instruction simulation support ------Kprobes needs simulation of instructions that cannot be stepped from a different memory location, e.g.: those instructions that uses PC-relative addressing. In simulation, the behaviour of the instruction is implemented using a copy of pt_regs.

The following instruction categories are simulated: - All branching instructions(conditional, register, and immediate) - Literal access instructions(load-literal, adr/adrp)

Conditional execution is limited to branching instructions in ARM v8. If conditions at PSTATE do not match the condition fields of opcode, the instruction is effectively NOP.

Thanks to Will Cohen for assorted suggested changes.

3897 arch\arm64\kernel\probes\decode-insn.h#0032 3898 arch\arm64\kernel\probes\decode-insn.h#0035 3899 arch\arm64\kernel\probes\kprobes.c#0032 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

arm64: kprobe: protect/rename few definitions to be reused by uprobe ------decode-insn code has to be reused by arm64 uprobe implementation as well. Therefore, this patch protects some portion of kprobe code and renames few other, so that decode-insn functionality can be reused by uprobe even when

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CONFIG_KPROBES is not defined.

kprobe_opcode_t and struct arch_specific_insn are also defined by linux/kprobes.h, when CONFIG_KPROBES is not defined. So, protect these definitions in asm/probes.h.

linux/kprobes.h already includes asm/kprobes.h. Therefore, remove inclusion of asm/kprobes.h from decode-insn.c.

There are some definitions like kprobe_insn and kprobes_handler_t etc can be re-used by uprobe. So, it would be better to remove 'k' from their names.

struct arch_specific_insn is specific to kprobe. Therefore, introduce a new struct arch_probe_insn which will be common for both kprobe and uprobe, so that decode-insn code can be shared. Modify kprobe code accordingly.

Function arm_probe_decode_insn() will be needed by uprobe as well. So make it global.

3900 arch\arm64\kernel\probes\kprobes.c#0047 3901 arch\arm64\kernel\probes\kprobes.c#0049 3902 arch\arm64\kernel\probes\kprobes.c#0056 3903 arch\arm64\kernel\probes\kprobes.c#0063 3904 arch\arm64\kernel\probes\kprobes.c#0070 3905 arch\arm64\kernel\probes\kprobes.c#0101 3906 arch\arm64\kernel\probes\kprobes.c#0105 3907 arch\arm64\kernel\probes\kprobes.c#0112 3908 arch\arm64\kernel\probes\kprobes.c#0145 3909 arch\arm64\kernel\probes\kprobes.c#0247 3910 arch\arm64\kernel\probes\kprobes.c#0249 3911 arch\arm64\kernel\probes\kprobes.c#0298 3912 arch\arm64\kernel\probes\Makefile#0004 Repo: 9842ceae9fa8 Pratyush Wed Nov 2 14:40:46 2016 +0530 Description: arm64: Add uprobe support ------This patch adds support for uprobe on ARM64 architecture.

Unit tests for following have been done so far and they have been found working

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1. Step-able instructions, like sub, ldr, add etc. 2. Simulation-able like ret, cbnz, cbz etc. 3. uretprobe 4. Reject-able instructions like sev, wfe etc. 5. trapped and abort xol path 6. probe at unaligned user address. 7. longjump test cases

Currently it does not support aarch32 instruction probing.

arm64: Add trampoline code for kretprobes ------The trampoline code is used by kretprobes to capture a return from a probed function. This is done by saving the registers, calling the handler, and restoring the registers. The code then returns to the original saved caller return address. It is necessary to do this directly instead of using a software breakpoint because the code used in processing that breakpoint could itself be kprobe'd and cause a problematic reentry into the debug exception handler.

arm64: kprobes instruction simulation support ------Kprobes needs simulation of instructions that cannot be stepped from a different memory location, e.g.: those instructions that uses PC-relative addressing. In simulation, the behaviour of the instruction is implemented using a copy of pt_regs.

The following instruction categories are simulated: - All branching instructions(conditional, register, and immediate) - Literal access instructions(load-literal, adr/adrp)

Conditional execution is limited to branching instructions in ARM v8. If conditions at PSTATE do not match the condition fields of opcode, the instruction is effectively NOP.

Thanks to Will Cohen for assorted suggested changes.

3913 arch\arm64\kernel\probes\simulate-insn.c#0016 Repo: 4890ae46911c Robin Tue Oct 18 13:46:27 2016 +0100 Description: arm64/kprobes: Tidy up sign-extension usage ------Kprobes does not need its own homebrewed (and frankly inscrutable) sign extension macro; just use the standard kernel functions instead. Since the compiler actually recognises the sign-extension idiom of the latter, we also get the small bonus of some nicer codegen, as each displacement calculation helper then compiles to a single optimal SBFX instruction.

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3914 arch\arm64\kernel\probes\simulate-insn.c#0022 3915 arch\arm64\kernel\probes\simulate-insn.c#0025 3916 arch\arm64\kernel\probes\simulate-insn.c#0028 3917 arch\arm64\kernel\probes\simulate-insn.c#0031 3918 arch\arm64\kernel\probes\simulate-insn.c#0034 3919 arch\arm64\kernel\probes\simulate-insn.c#0037 3920 arch\arm64\kernel\probes\simulate-insn.c#0109 3921 arch\arm64\kernel\probes\uprobes.c#newFile Repo: 9842ceae9fa8 Pratyush Wed Nov 2 14:40:46 2016 +0530 Description: arm64: Add uprobe support ------This patch adds support for uprobe on ARM64 architecture.

Unit tests for following have been done so far and they have been found working 1. Step-able instructions, like sub, ldr, add etc. 2. Simulation-able like ret, cbnz, cbz etc. 3. uretprobe 4. Reject-able instructions like sev, wfe etc. 5. trapped and abort xol path 6. probe at unaligned user address. 7. longjump test cases

Currently it does not support aarch32 instruction probing.

arch\arm64\kvm\ 3922 arch\arm64\kvm\guest.c#0029 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

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3923 arch\arm64\kvm\handle_exit.c#0060 Repo: 82e0191a1aa1 Suzuki K Tue Nov 8 13:56:21 2016 +0000 Description: arm64: Support systems without FP/ASIMD ------The arm64 kernel assumes that FP/ASIMD units are always present and accesses the FP/ASIMD specific registers unconditionally. This could cause problems when they are absent. This patch adds the support for kernel handling systems without FP/ASIMD by skipping the register access within the kernel. For kvm, we trap the accesses to FP/ASIMD and inject an undefined instruction exception to the VM.

The callers of the exported kernel_neon_begin_partial() should make sure that the FP/ASIMD is supported.

arm64: KVM: Inject a Virtual SError if it was pending ------If we have caught an SError whilst exiting, we've tagged the exit code with the pending information. In that case, let's re-inject the error into the guest, after having adjusted the PC if required.

3924 arch\arm64\kvm\handle_exit.c#0157 3925 arch\arm64\kvm\Kconfig#0019 Repo: 2988509dd8a0 Vladimir Wed Nov 2 11:55:34 2016 +0000 Description: ARM: KVM: Support vGICv3 ITS ------This patch allows to build and use vGICv3 ITS in 32-bit mode.

ARM: KVM: Support vgic-v3 ------This patch allows to build and use vgic-v3 in 32-bit mode.

Unfortunately, it can not be split in several steps without extra stubs to keep patches independent and bisectable. For instance, virt/kvm/arm/vgic/vgic-v3.c uses function from vgic-v3-sr.c, handling access to GICv3 cpu interface from the guest requires vgic_v3.vgic_sre to be already defined.

It is how support has been done:

* handle SGI requests from the guest

* report configured SRE on access to GICv3 cpu interface from the guest

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* required vgic-v3 macros are provided via uapi.h

* static keys are used to select GIC backend

* to make vgic-v3 build KVM_ARM_VGIC_V3 guard is removed along with the static inlines

3926 arch\arm64\kvm\Kconfig#0037 3927 arch\arm64\kvm\reset.c#0089 Repo: 2988509dd8a0 Vladimir Wed Nov 2 11:55:34 2016 +0000 Description: ARM: KVM: Support vGICv3 ITS ------This patch allows to build and use vGICv3 ITS in 32-bit mode.

KVM: arm64: vgic-its: Enable ITS emulation as a virtual MSI controller ------Now that all ITS emulation functionality is in place, we advertise MSI functionality to userland and also the ITS device to the guest - if userland has configured that.

arch\arm64\kvm\hyp\ 3928 arch\arm64\kvm\hyp\hyp-entry.S#0109 Repo: 82e0191a1aa1 Suzuki K Tue Nov 8 13:56:21 2016 +0000 Description: arm64: Support systems without FP/ASIMD ------The arm64 kernel assumes that FP/ASIMD units are always present and accesses the FP/ASIMD specific registers unconditionally. This could cause problems when they are absent. This patch adds the support for kernel handling systems without FP/ASIMD by skipping the register access within the kernel. For kvm, we trap the accesses to FP/ASIMD and inject an undefined instruction exception to the VM.

The callers of the exported kernel_neon_begin_partial() should make sure that the FP/ASIMD is supported.

arm64: KVM: Handle async aborts delivered while at EL2 ------If EL1 generates an asynchronous abort and then traps into EL2 before the abort has been delivered, we may end-up with the abort firing at the worse possible place: on the host.

In order to avoid this, it is necessary to take the abort at EL2,

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by clearing the PSTATE.A bit. In order to survive this abort, we do it at a point where we're in a known state with respect to the world switch, and handle the resulting exception, overloading the exit code in the process.

arm64: KVM: Route asynchronous aborts ------As we now have some basic handling to EL1-triggered aborts, we can actually report them to KVM.

3929 arch\arm64\kvm\hyp\hyp-entry.S#0118 3930 arch\arm64\kvm\hyp\switch.c#0024 Repo: f4000cd99750 Linus Tue Dec 13 16:39:21 2016 -0800 Description: Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux ------Pull arm64 updates from Catalin Marinas:

- struct thread_info moved off-stack (also touching include/linux/thread_info.h and include/linux/restart_block.h)

- cpus_have_cap() reworked to avoid __builtin_constant_p() for static key use (also touching drivers/irqchip/irq-gic-v3.c)

- uprobes support (currently only for native 64-bit tasks)

- Emulation of kernel Privileged Access Never (PAN) using TTBR0_EL1 switching to a reserved page table

- CPU capacity information passing via DT or sysfs (used by the scheduler)

- support for systems without FP/SIMD (IOW, kernel avoids touching these registers; there is no soft-float ABI, nor kernel emulation for AArch64 FP/SIMD)

- handling of hardware watchpoint with unaligned addresses, varied lengths and offsets from base

- use of the page table contiguous hint for kernel mappings

- hugetlb fixes for sizes involving the contiguous hint

- remove unnecessary I-cache invalidation in flush_cache_range()

- CNTHCTL_EL2 access fix for CPUs with VHE support (ARMv8.1)

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- boot-time checks for writable+executable kernel mappings

- simplify asm/opcodes.h and avoid including the 32-bit ARM counterpart and make the arm64 kernel headers self-consistent (Xen headers patch merged separately)

- Workaround for broken .inst support in certain binutils versions

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (60 commits) arm64: Disable PAN on uaccess_enable() arm64: Work around broken .inst when defective gas is detected arm64: Add detection code for broken .inst support in binutils arm64: Remove reference to asm/opcodes.h arm64: Get rid of asm/opcodes.h arm64: smp: Prevent raw_smp_processor_id() recursion arm64: head.S: Fix CNTHCTL_EL2 access on VHE system arm64: Remove I-cache invalidation from flush_cache_range() arm64: Enable HIBERNATION in defconfig arm64: Enable CONFIG_ARM64_SW_TTBR0_PAN arm64: xen: Enable user access before a privcmd hvc call arm64: Handle faults caused by inadvertent user access with PAN enabled arm64: Disable TTBR0_EL1 during normal kernel execution arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1 arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro arm64: Factor out PAN enabling/disabling into separate uaccess_* macros arm64: Update the synchronous external abort fault description selftests: arm64: add test for unaligned/inexact watchpoint handling arm64: Allow hw watchpoint of length 3,5,6 and 7 arm64: hw_breakpoint: Handle inexact watchpoint addresses ...

arm64: KVM: pmu: Reset PMSELR_EL0.SEL to a sane value before entering the guest ------The ARMv8 architecture allows the cycle counter to be configured by setting PMSELR_EL0.SEL==0x1f and then accessing PMXEVTYPER_EL0, hence accessing PMCCFILTR_EL0. But it disallows the use of PMSELR_EL0.SEL==0x1f to access the cycle counter itself through PMXEVCNTR_EL0.

Linux itself doesn't violate this rule, but we may end up with PMSELR_EL0.SEL being set to 0x1f when we enter a guest. If that guest accesses PMXEVCNTR_EL0, the access may UNDEF at EL1, despite the guest not having done anything wrong.

In order to avoid this unfortunate course of events (haha!), let's sanitize PMSELR_EL0 on guest entry. This ensures that the guest won't explode unexpectedly.

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arm64: Support systems without FP/ASIMD ------The arm64 kernel assumes that FP/ASIMD units are always present and accesses the FP/ASIMD specific registers unconditionally. This could cause problems when they are absent. This patch adds the support for kernel handling systems without FP/ASIMD by skipping the register access within the kernel. For kvm, we trap the accesses to FP/ASIMD and inject an undefined instruction exception to the VM.

The callers of the exported kernel_neon_begin_partial() should make sure that the FP/ASIMD is supported.

3931 arch\arm64\kvm\hyp\switch.c#0080 Review: COMMENT stecan Thu, 11 Jan 2018 07:27:00 +0100 Short Description: stecan Thu, 11 Jan 2018 07:27:00 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:27:00 +0100 Short Description: stecan Thu, 11 Jan 2018 07:27:00 +0100 Automatic commented! 3932 arch\arm64\kvm\hyp\switch.c#0084 3933 arch\arm64\kvm\hyp\switch.c#0091 arch\arm64\mm\ 3934 arch\arm64\mm\cache.S#0026 Repo: b4b8664d291a Al Viro Mon Dec 26 04:10:19 2016 -0500 Description: arm64: don't pull uaccess.h into *.S ------Split asm-only parts of arm64 uaccess.h into a new header and use that from *.S.

Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

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arm64: Disable TTBR0_EL1 during normal kernel execution ------When the TTBR0 PAN feature is enabled, the kernel entry points need to disable access to TTBR0_EL1. The PAN status of the interrupted context is stored as part of the saved pstate, reusing the PSR_PAN_BIT (22). Restoring access to TTBR0_EL1 is done on exception return if returning to user or returning to a context where PAN was disabled.

Context switching via switch_mm() must defer the update of TTBR0_EL1 until a return to user or an explicit uaccess_enable() call.

Special care needs to be taken for two cases where TTBR0_EL1 is set outside the normal kernel context switch operation: EFI run-time services (via efi_set_pgd) and CPU suspend (via cpu_(un)install_idmap). Code has been added to avoid deferred TTBR0_EL1 switching as in switch_mm() and restore the reserved TTBR0_EL1 when uninstalling the special TTBR0_EL1.

User cache maintenance (user_cache_maint_handler and __flush_cache_user_range) needs the TTBR0_EL1 re-instated since the operations are performed by user virtual address.

This patch also removes a stale comment on the switch_mm() function.

3935 arch\arm64\mm\cache.S#0052 3936 arch\arm64\mm\cache.S#0074 3937 arch\arm64\mm\cache.S#0079 3938 arch\arm64\mm\context.c#0224 Repo: 39bc88e5e38e Catalin Fri Sep 2 14:54:03 2016 +0100 Description: arm64: Disable TTBR0_EL1 during normal kernel execution ------When the TTBR0 PAN feature is enabled, the kernel entry points need to disable access to TTBR0_EL1. The PAN status of the interrupted context is stored as part of the saved pstate, reusing the PSR_PAN_BIT (22). Restoring access to TTBR0_EL1 is done on exception return if returning to user or returning to a context where PAN was disabled.

Context switching via switch_mm() must defer the update of TTBR0_EL1 until a return to user or an explicit uaccess_enable() call.

Special care needs to be taken for two cases where TTBR0_EL1 is set outside the normal kernel context switch operation: EFI run-time services (via efi_set_pgd) and CPU suspend (via cpu_(un)install_idmap). Code has been added to avoid deferred TTBR0_EL1 switching as in switch_mm() and restore the reserved TTBR0_EL1 when uninstalling the

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special TTBR0_EL1.

User cache maintenance (user_cache_maint_handler and __flush_cache_user_range) needs the TTBR0_EL1 re-instated since the operations are performed by user virtual address.

This patch also removes a stale comment on the switch_mm() function.

3939 arch\arm64\mm\dma-mapping.c#0527 Repo: 2fd8774c79a4 Linus Fri Jan 6 10:53:21 2017 -0800 Description: Merge branch 'stable/for-linus-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/swiotlb ------Pull swiotlb fixes from Konrad Rzeszutek Wilk: "This has one fix to make i915 work when using Xen SWIOTLB, and a feature from Geert to aid in debugging of devices that can't do DMA outside the 32-bit address space.

The feature from Geert is on top of v4.10 merge window commit (specifically you pulling my previous branch), as his changes were dependent on the Documentation/ movement patches.

I figured it would just easier than me trying than to cherry-pick the Documentation patches to satisfy git.

The patches have been soaking since 12/20, albeit I updated the last patch due to linux-next catching an compiler error and adding an Tested-and

swiotlb: Convert swiotlb_force from int to enum ------Convert the flag swiotlb_force from an int to an enum, to prepare for the advent of more possible values.

Merge tag 'iommu-updates-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu ------Pull IOMMU updates from Joerg Roedel: "These changes include:

- support for the ACPI IORT table on ARM systems and patches to make the ARM-SMMU driver make use of it

- conversion of the Exynos IOMMU driver to device dependency links and implementation of runtime pm support based on that conversion

- update the Mediatek IOMMU driver to use the new struct

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device->iommu_fwspec member

- implementation of dma_map/unmap_resource in the generic ARM dma-iommu layer

- a number of smaller fixes and improvements all over the place"

* tag 'iommu-updates-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (44 commits) ACPI/IORT: Make dma masks set-up IORT specific iommu/amd: Missing error code in amd_iommu_init_device() iommu/s390: Drop duplicate header pci.h ACPI/IORT: Introduce iort_iommu_configure ACPI/IORT: Add single mapping function ACPI/IORT: Replace rid map type with type mask iommu/arm-smmu: Add IORT configuration iommu/arm-smmu: Split probe functions into DT/generic portions iommu/arm-smmu-v3: Add IORT configuration iommu/arm-smmu-v3: Split probe functions into DT/generic portions ACPI/IORT: Add support for ARM SMMU platform devices creation ACPI/IORT: Add node match function ACPI: Implement acpi_dma_configure iommu/arm-smmu-v3: Convert struct device of_node to fwnode usage iommu/arm-smmu: Convert struct device of_node to fwnode usage iommu: Make of_iommu_set/get_ops() DT agnostic ACPI/IORT: Add support for IOMMU fwnode registration ACPI/IORT: Introduce linker section for IORT entries probing ACPI: Add FWNODE_ACPI_STATIC fwnode type iommu/arm-smmu: Set SMTNMB_TLBEN in ACR to enable caching of bypass entries ...

arm64: Wire up iommu_dma_{map, unmap}_resource() ------With no coherency to worry about, just plug'em straight in.

arm64: Remove pointless WARN_ON in DMA teardown ------We expect arch_teardown_dma_ops() to be called very late in a device's life, after it has been removed from its bus, and thus after the IOMMU bus notifier has run. As such, even if this funny little check did make sense, it's unlikely to achieve what it thinks it's trying to do anyway. It's a residual trace of an earlier implementation which didn't belong here from the start; belatedly snuff it out.

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3940 arch\arm64\mm\dma-mapping.c#0800 3941 arch\arm64\mm\dma-mapping.c#0944 3942 arch\arm64\mm\dump.c#0053 Repo: 1404d6f13e47 Laura Abbott Thu Oct 27 09:27:34 2016 -0700 Description: arm64: dump: Add checking for writable and exectuable pages ------Page mappings with full RWX permissions are a security risk. x86 has an option to walk the page tables and dump any bad pages. (See e1a58320a38d ("x86/mm: Warn on W^X mappings")). Add a similar implementation for arm64.

arm64: dump: Make the page table dumping seq_file optional ------The page table dumping code always assumes it will be dumping to a seq_file to userspace. Future code will be taking advantage of the page table dumping code but will not need the seq_file. Make the seq_file optional for these cases.

arm64: dump: Make ptdump debugfs a separate option ------ptdump_register currently initializes a set of page table information and registers debugfs. There are uses for the ptdump option without wanting the debugfs options. Split this out to make it a separate option.

arm64: Fix shift warning in arch/arm64/mm/dump.c ------When building with 48-bit VAs and 16K page configuration, it's possible to get the following warning when building the arm64 page table dumping code:

arch/arm64/mm/dump.c: In function ‘walk_pud’: arch/arm64/mm/dump.c:274:102: warning: right shift count >= width of type [-Wshift- count-overflow]

This is because pud_offset(pgd, 0) performs a shift to the right by 36 while the value 0 has the type 'int' by default, therefore 32-bit.

This patch modifies all the p*_offset() uses in arch/arm64/mm/dump.c to use 0UL for the address argument.

arm64: mm: dump: make page table dumping reusable ------For debugging purposes, it would be nice if we could export page tables

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other than the swapper_pg_dir to userspace. To enable this, this patch refactors the arm64 page table dumping code such that multiple tables may be registered with the framework, and exported under debugfs.

arm64: mm: dump: log span level ------The page table dump code logs spans of entries at the same level (pgd/pud/pmd/pte) which have the same attributes. While we log the (decoded) attributes, we don't log the level, which leaves the output ambiguous and/or confusing in some cases.

For example:

0xffff800800000000-0xffff800980000000 6G RW NX SHD AF BLK UXN MEM/NORMAL

If using 4K pages, this may describe a span of 6 1G block entries at the PGD/PUD level, or 3072 2M block entries at the PMD level.

This patch adds the page table level to each output line, removing this ambiguity. For the example above, this will produce:

0xffffffc800000000-0xffffffc980000000 6G PUD RW NX SHD AF BLK UXN MEM/NORMAL

When 3 level tables are in use, and we use the asm-generic/nopud.h definitions, the dump code treats each entry in the PGD as a 1 element table at the PUD level, and logs spans as being PUDs, which can be confusing. To counteract this, the "PUD" mnemonic is replaced with "PGD" when CONFIG_PGTABLE_LEVELS <= 3. Likewise for "PMD" when CONFIG_PGTABLE_LEVELS <= 2.

arm64: ptdump: add region marker for kasan shadow region ------Annotate the KASAN shadow region with boundary markers, so that its mappings stand out in the page table dumper output.

arm64: ptdump: use static initializers for vmemmap region boundaries ------There is no need to initialize the vmemmap region boundaries dynamically, since they are compile time constants. So just add these constants to the global struct initializer, and drop the dynamic assignment and related code.

arm64: mm: move vmemmap region right below the linear region ------This moves the vmemmap region right below PAGE_OFFSET, aka the start

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of the linear region, and redefines its size to be a power of two. Due to the placement of PAGE_OFFSET in the middle of the address space, whose size is a power of two as well, this guarantees that virt to page conversions and vice versa can be implemented efficiently, by masking and shifting rather than ordinary arithmetic.

arm64: mm: dump: Use VA_START directly instead of private LOWEST_ADDR ------Use VA_START macro in asm/memory.h instead of private LOWEST_ADDR definition in dump.c.

arm64: move kernel image to base of vmalloc area ------This moves the module area to right before the vmalloc area, and moves the kernel image to the base of the vmalloc area. This is an intermediate step towards implementing KASLR, which allows the kernel image to be located anywhere in the vmalloc area.

Since other subsystems such as hibernate may still need to refer to the kernel text or data segments via their linears addresses, both are mapped in the linear region as well. The linear alias of the text region is mapped read-only/non-executable to prevent inadvertent modification or execution.

arm64: ptdump: Indicate whether memory should be faulting ------With CONFIG_DEBUG_PAGEALLOC, pages do not have the valid bit set when free in the buddy allocator. Add an indiciation to the page table dumping code that the valid bit is not set, 'F' for fault, to make this easier to understand.

arm64: Fix an enum typo in mm/dump.c ------This patch fixes a typo in mm/dump.c: "MODUELS_END_NR" should be "MODULES_END_NR".

arm64: Make the kernel page dump utility aware of the CONT bit ------The kernel page dump utility needs to be aware of the CONT bit before it will break up pages ranges for display.

arm64: mm: Fix build error with CONFIG_SPARSEMEM_VMEMMAP disabled ------This fix the below build error:

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arch/arm64/mm/dump.c: In function ‘ptdump_init’: arch/arm64/mm/dump.c:331:18: error: ‘VMEMMAP_START_NR’ undeclared (first use in this function) address_markers[VMEMMAP_START_NR].start_address = ^ arch/arm64/mm/dump.c:331:18: note: each undeclared identifier is reported only once for each function it appears in arch/arm64/mm/dump.c:333:18: error: ‘VMEMMAP_END_NR’ undeclared (first use in this function) address_markers[VMEMMAP_END_NR].start_address = ^

Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux ------Pull arm64 updates from Catalin Marinas: "arm64 updates for 3.20:

- reimplementation of the virtual remapping of UEFI Runtime Services in a way that is stable across kexec - emulation of the "setend" instruction for 32-bit tasks (user endianness switching trapped in the kernel, SCTLR_EL1.E0E bit set accordingly) - compat_sys_call_table implemented in C (from asm) and made it a constant array together with sys_call_table - export CPU cache information via /sys (like other architectures) - DMA API implementation clean-up in preparation for IOMMU support - macros clean-up for KVM - dropped some unnecessary cache+tlb maintenance - CONFIG_ARM64_CPU_SUSPEND clean-up - defconfig update (CPU_IDLE)

The EFI changes going via the arm64 tree have been acked by Matt Fleming. There is also a patch adding sys_*stat64 prototypes to include/linux/syscalls.h, acked by Andrew Morton"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (47 commits) arm64: compat: Remove incorrect comment in compat_siginfo arm64: Fix section mismatch on alloc_init_p[mu]d() arm64: Avoid breakage caused by .altmacro in fpsimd save/restore macros arm64: mm: use *_sect to check for section maps arm64: drop unnecessary cache+tlb maintenance arm64:mm: free the useless initial page table arm64: Enable CPU_IDLE in defconfig arm64: kernel: remove ARM64_CPU_SUSPEND config option arm64: make sys_call_table const arm64: Remove asm/syscalls.h arm64: Implement the compat_sys_call_table in C

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syscalls: Declare sys_*stat64 prototypes if __ARCH_WANT_(COMPAT_)STAT64 compat: Declare compat_sys_sigpending and compat_sys_sigprocmask prototypes arm64: uapi: expose our struct ucontext to the uapi headers smp, ARM64: Kill SMP single function call interrupt arm64: Emulate SETEND for AArch32 tasks arm64: Consolidate hotplug notifier for instruction emulation arm64: Track system support for mixed endian EL0 arm64: implement generic IOMMU configuration arm64: Combine coherent and non-coherent swiotlb dma_ops ...

arm64: mm: use *_sect to check for section maps ------The {pgd,pud,pmd}_bad family of macros have slightly fuzzy cross-architecture semantics, and seem to imply a populated entry that is not a next-level table, rather than a particular type of entry (e.g. a section map).

In arm64 code, for those cases where we care about whether an entry is a section mapping, we can instead use the {pud,pmd}_sect macros to explicitly check for this case. This helps to document precisely what we care about, making the code easier to read, and allows for future relaxation of the *_bad macros to check for other "bad" entries.

To that end this patch updates the table dumping and initial table setup to check for section mappings with {pud,pmd}_sect, and adds/restores BUG_ON(*_bad((*p)) checks after we've handled the *_sect and *_none cases so as to catch remaining "bad" cases.

In the fault handling code, show_pte is left with *_bad checks as it only cares about whether it can walk the next level table, and this path is used for both kernel and userspace fault handling. The former case will be followed by a die() where we'll report the address that triggered the fault, which can be useful context for debugging.

arm64: mm: dump: add missing includes ------The arm64 dump code is currently relying on some definitions which are pulled in via transitive dependencies. It seems we have implicit dependencies on the following definitions:

* MODULES_VADDR (asm/memory.h) * MODULES_END (asm/memory.h) * PAGE_OFFSET (asm/memory.h) * PTE_* (asm/pgtable-hwdef.h) * ENOMEM (linux/errno.h) * device_initcall (linux/init.h)

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This patch ensures we explicitly include the relevant headers for the above items, fixing the observed build issue and hopefully preventing future issues as headers are refactored.

arm64: Fix overlapping VA allocations ------PCI IO space was intended to be 16MiB, at 32MiB below MODULES_VADDR, but commit d1e6dc91b532d3d3 ("arm64: Add architectural support for PCI") extended this to cover the full 32MiB. The final 8KiB of this 32MiB is also allocated for the fixmap, allowing for potential clashes between the two.

This change was masked by assumptions in mem_init and the page table dumping code, which assumed the I/O space to be 16MiB long through seaparte hard-coded definitions.

This patch changes the definition of the PCI I/O space allocation to live in asm/memory.h, along with the other VA space allocations. As the fixmap allocation depends on the number of fixmap entries, this is moved below the PCI I/O space allocation. Both the fixmap and PCI I/O space are guarded with 2MB of padding. Sites assuming the I/O space was 16MiB are moved over use new PCI_IO_{START,END} definitions, which will keep in sync with the size of the IO space (now restored to 16MiB).

As a useful side effect, the use of the new PCI_IO_{START,END} definitions prevents a build issue in the dumping code due to a (now redundant) missing include of io.h for PCI_IOBASE.

arm64: dump: Fix implicit inclusion of definition for PCI_IOBASE ------Since c9465b4ec37a68425 (arm64: add support to dump the kernel page tables) allmodconfig has failed to build on arm64 as a result of:

../arch/arm64/mm/dump.c:55:20: error: 'PCI_IOBASE' undeclared here (not in a function)

Fix this by explicitly including io.h to ensure that a definition is present.

arm64: mm: dump: don't skip final region ------If the final page table entry we walk is a valid mapping, the page table dumping code will not log the region this entry is part of, as the final note_page call in ptdump_show will trigger an early return. Luckily this isn't seen on contemporary systems as they typically don't have enough RAM to extend the linear mapping right to the end of the address space.

In note_page, we log a region when we reach its end (i.e. we hit an

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entry immediately afterwards which has different prot bits or is invalid). The final entry has no subsequent entry, so we will not log this immediately. We try to cater for this with a subsequent call to note_page in ptdump_show, but this returns early as 0 < LOWEST_ADDR, and hence we will skip a valid mapping if it spans to the final entry we note.

Unlike 32-bit ARM, the pgd with the kernel mapping is never shared with user mappings, so we do not need the check to ensure we don't log user page tables. Due to the way addr is constructed in the walk_* functions, it can never be less than LOWEST_ADDR when walking the page tables, so it is not necessary to avoid dereferencing invalid table addresses. The existing checks for st->current_prot and st->marker[1].start_address are sufficient to ensure we will not print and/or dereference garbage when trying to log information.

This patch removes the unnecessary check against LOWEST_ADDR, ensuring we log all regions in the kernel page table, including those which span right to the end of the address space.

3943 arch\arm64\mm\dump.c#0077 3944 arch\arm64\mm\dump.c#0204 3945 arch\arm64\mm\dump.c#0208 3946 arch\arm64\mm\dump.c#0247 3947 arch\arm64\mm\dump.c#0254 3948 arch\arm64\mm\dump.c#0264 3949 arch\arm64\mm\dump.c#0269 3950 arch\arm64\mm\dump.c#0274 3951 arch\arm64\mm\dump.c#0284 3952 arch\arm64\mm\dump.c#0353 3953 arch\arm64\mm\dump.c#0355 3954 arch\arm64\mm\dump.c#0363 3955 arch\arm64\mm\dump.c#0365 3956 arch\arm64\mm\dump.c#0367 3957 arch\arm64\mm\dump.c#0373 3958 arch\arm64\mm\dump.c#0381

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3959 arch\arm64\mm\dump.c#0403 3960 arch\arm64\mm\fault.c#0091 Repo: 6ef4fb387d50 Mark RutlandTue Jan 3 14:27:26 2017 +0000 Description: arm64: mm: fix show_pte KERN_CONT fallout ------Recent changes made KERN_CONT mandatory for continued lines. In the absence of KERN_CONT, a newline may be implicit inserted by the core printk code.

In show_pte, we (erroneously) use printk without KERN_CONT for continued prints, resulting in output being split across a number of lines, and not matching the intended output, e.g.

[ff000000000000] *pgd=00000009f511b003 , *pud=00000009f4a80003 , *pmd=0000000000000000

Fix this by using pr_cont() for all the continuations.

arm64: Handle faults caused by inadvertent user access with PAN enabled ------When TTBR0_EL1 is set to the reserved page, an erroneous kernel access to user space would generate a translation fault. This patch adds the checks for the software-set PSR_PAN_BIT to emulate a permission fault and report it accordingly.

arm64: Update the synchronous external abort fault description ------This patch updates the description of the synchronous external aborts on translation table walks.

arm64: mm: Set PSTATE.PAN from the cpu_enable_pan() call ------Commit 338d4f49d6f7 ("arm64: kernel: Add support for Privileged Access Never") enabled PAN by enabling the 'SPAN' feature-bit in SCTLR_EL1. This means the PSTATE.PAN bit won't be set until the next return to the kernel from userspace. On a preemptible kernel we may schedule work that accesses userspace on a CPU before it has done this.

Now that cpufeature enable() calls are scheduled via stop_machine(), we can set PSTATE.PAN from the cpu_enable_pan() call.

Add WARN_ON_ONCE(in_interrupt()) to check the PSTATE value we updated is not immediately discarded.

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3961 arch\arm64\mm\fault.c#0096 3962 arch\arm64\mm\fault.c#0101 3963 arch\arm64\mm\fault.c#0105 3964 arch\arm64\mm\fault.c#0272 3965 arch\arm64\mm\fault.c#0277 3966 arch\arm64\mm\fault.c#0324 3967 arch\arm64\mm\fault.c#0516 3968 arch\arm64\mm\flush.c#0028 Repo: ee6a7fce8e5e Catalin Wed Nov 23 18:05:52 2016 +0000 Description: arm64: Remove I-cache invalidation from flush_cache_range() ------The flush_cache_range() function (similarly for flush_cache_page()) is called when the kernel is changing an existing VA->PA mapping range to either a new PA or to different attributes. Since ARMv8 has PIPT-like D-caches, this function does not need to perform any D-cache maintenance. The I-cache maintenance is already handled via set_pte_at() and flush_cache_range() cannot anyway guarantee that there are no cache lines left after invalidation due to the speculative loads.

This patch makes flush_cache_range() a no-op.

arm64: Add uprobe support ------This patch adds support for uprobe on ARM64 architecture.

Unit tests for following have been done so far and they have been found working 1. Step-able instructions, like sub, ldr, add etc. 2. Simulation-able like ret, cbnz, cbz etc. 3. uretprobe 4. Reject-able instructions like sev, wfe etc. 5. trapped and abort xol path 6. probe at unaligned user address. 7. longjump test cases

Currently it does not support aarch32 instruction probing.

3969 arch\arm64\mm\flush.c#0031

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3970 arch\arm64\mm\hugetlbpage.c#0054 Repo: 69d012345a1a Huang Shijie Wed Jan 11 14:02:00 2017 +0800 Description: arm64: hugetlb: fix the wrong return value for huge_ptep_set_access_flags ------In current code, the @changed always returns the last one's status for the huge page with the contiguous bit set. This is really not what we want. Even one of the PTEs is changed, we should tell it to the caller.

This patch fixes this issue.

Fixes: 66b3923a1a0f ("arm64: hugetlb: add support for PTE contiguous bit")

arm64: hugetlb: fix the wrong address for several functions ------The libhugetlbfs meets several failures since the following functions do not use the correct address: huge_ptep_get_and_clear() huge_ptep_set_access_flags() huge_ptep_set_wrprotect() huge_ptep_clear_flush()

This patch fixes the wrong address for them.

arm64: hugetlb: remove the wrong pmd check in find_num_contig() ------The find_num_contig() will return 1 when the pmd is not present. It will cause a kernel dead loop in the following scenaro:

1.) pmd entry is not present.

2.) the occurs: ... hugetlb_fault() --> hugetlb_no_page() --> set_huge_pte_at()

3.) set_huge_pte_at() will only set the first PMD entry, since the find_num_contig just return 1 in this case. So the PMD entries are all empty except the first one.

4.) when kernel accesses the address mapped by the second PMD entry, a new page fault occurs: ... hugetlb_fault() --> huge_ptep_set_access_flags()

The second PMD entry is still empty now.

5.) When the kernel returns, the access will cause a page fault again. The kernel will run like the "4)" above. We will see a dead loop since here.

The dead loop is caught in the 32M hugetlb page (2M PMD + Contiguous bit).

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This patch removes wrong pmd check, and fixes this dead loop.

This patch also removes the redundant checks for PGD/PUD in the find_num_contig().

arm64: Fix typo in add_default_hugepagesz() for 64K pages ------The default hugepage size when 64K pages are enabled is set to 2MB using the contiguous PTE bit. The add_default_hugepagesz(), however, uses CONT_PMD_SHIFT instead of CONT_PTE_SHIFT. There is no functional change since the values are the same.

3971 arch\arm64\mm\hugetlbpage.c#0059 3972 arch\arm64\mm\hugetlbpage.c#0064 3973 arch\arm64\mm\hugetlbpage.c#0215 3974 arch\arm64\mm\hugetlbpage.c#0253 3975 arch\arm64\mm\hugetlbpage.c#0276 3976 arch\arm64\mm\hugetlbpage.c#0294 3977 arch\arm64\mm\hugetlbpage.c#0326 3978 arch\arm64\mm\init.c#0404 Repo: 524dabe1c68e Alexander Mon Jan 16 12:46:33 2017 +0100 Description: arm64: Fix swiotlb fallback allocation ------Commit b67a8b29df introduced logic to skip swiotlb allocation when all memory is DMA accessible anyway.

While this is a great idea, __dma_alloc still calls swiotlb code unconditionally to allocate memory when there is no CMA memory available. The swiotlb code is called to ensure that we at least try get_free_pages().

Without initialization, swiotlb allocation code tries to access io_tlb_list which is NULL. That results in a stack trace like this:

Unable to handle kernel NULL pointer dereference at virtual address 00000000 [...] [] swiotlb_tbl_map_single+0xd0/0x2b0 [] swiotlb_alloc_coherent+0x10c/0x198 [] __dma_alloc+0x68/0x1a8 [] drm_gem_cma_create+0x98/0x108 [drm] [] drm_fbdev_cma_create_with_funcs+0xbc/0x368 [drm_kms_helper]

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[] drm_fbdev_cma_create+0x2c/0x40 [drm_kms_helper] [] drm_fb_helper_initial_config+0x238/0x410 [drm_kms_helper] [] drm_fbdev_cma_init_with_funcs+0x98/0x160 [drm_kms_helper] [] drm_fbdev_cma_init+0x40/0x58 [drm_kms_helper] [] vc4_kms_load+0x90/0xf0 [vc4] [] vc4_drm_bind+0xec/0x168 [vc4] [...]

Thankfully swiotlb code just learned how to not do allocations with the FORCE_NO option. This patch configures the swiotlb code to use that if we decide not to initialize the swiotlb framework.

Fixes: b67a8b29df ("arm64: mm: only initialize swiotlb when necessary")

swiotlb: Convert swiotlb_force from int to enum ------Convert the flag swiotlb_force from an int to an enum, to prepare for the advent of more possible values.

3979 arch\arm64\mm\init.c#0407 3980 arch\arm64\mm\Makefile#0006 Repo: 4ddb9bf83349 Laura Abbott Thu Oct 27 09:27:31 2016 -0700 Description: arm64: dump: Make ptdump debugfs a separate option ------ptdump_register currently initializes a set of page table information and registers debugfs. There are uses for the ptdump option without wanting the debugfs options. Split this out to make it a separate option.

3981 arch\arm64\mm\mmu.c#0031 Repo: 1404d6f13e47 Laura Abbott Thu Oct 27 09:27:34 2016 -0700 Description: arm64: dump: Add checking for writable and exectuable pages ------Page mappings with full RWX permissions are a security risk. x86 has an option to walk the page tables and dump any bad pages. (See e1a58320a38d ("x86/mm: Warn on W^X mappings")). Add a similar implementation for arm64.

arm64: mm: set the contiguous bit for kernel mappings where appropriate ------Now that we no longer allow live kernel PMDs to be split, it is safe to start using the contiguous bit for kernel mappings. So set the contiguous bit in the kernel page mappings for regions whose size and alignment are suitable for this.

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This enables the following contiguous range sizes for the virtual mapping of the kernel image, and for the linear mapping:

granule size | cont PTE | cont PMD | ------+------+------+ 4 KB | 64 KB | 32 MB | 16 KB | 2 MB | 1 GB* | 64 KB | 2 MB | 16 GB* |

* Only when built for 3 or more levels of translation. This is due to the fact that a 2 level configuration only consists of PGDs and PTEs, and the added complexity of dealing with folded PMDs is not justified considering that 16 GB contiguous ranges are likely to be ignored by the hardware (and 16k/2 levels is a niche configuration)

arm64: mm: replace 'block_mappings_allowed' with 'page_mappings_only' ------In preparation of adding support for contiguous PTE and PMD mappings, let's replace 'block_mappings_allowed' with 'page_mappings_only', which will be a more accurate description of the nature of the setting once we add such contiguous mappings into the mix.

arm64: mm: BUG on unsupported manipulations of live kernel mappings ------Now that we take care not manipulate the live kernel page tables in a way that may lead to TLB conflicts, the case where a table mapping is replaced by a block mapping can no longer occur. So remove the handling of this at the PUD and PMD levels, and instead, BUG() on any occurrence of live kernel page table manipulations that modify anything other than the permission bits.

Since mark_rodata_ro() is the only caller where the kernel mappings that are being manipulated are actually live, drop the various conditional flush_tlb_all() invocations, and add a single call to mark_rodata_ro() instead.

3982 arch\arm64\mm\mmu.c#0045 3983 arch\arm64\mm\mmu.c#0098 3984 arch\arm64\mm\mmu.c#0111 3985 arch\arm64\mm\mmu.c#0114 3986 arch\arm64\mm\mmu.c#0130

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3987 arch\arm64\mm\mmu.c#0145 3988 arch\arm64\mm\mmu.c#0160 3989 arch\arm64\mm\mmu.c#0162 3990 arch\arm64\mm\mmu.c#0182 3991 arch\arm64\mm\mmu.c#0185 3992 arch\arm64\mm\mmu.c#0188 3993 arch\arm64\mm\mmu.c#0190 Review: COMMENT stecan Thu, 11 Jan 2018 07:27:00 +0100 Short Description: stecan Thu, 11 Jan 2018 07:27:00 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:27:00 +0100 Short Description: stecan Thu, 11 Jan 2018 07:27:00 +0100 Automatic commented! 3994 arch\arm64\mm\mmu.c#0193 3995 arch\arm64\mm\mmu.c#0200 3996 arch\arm64\mm\mmu.c#0210 3997 arch\arm64\mm\mmu.c#0237 3998 arch\arm64\mm\mmu.c#0252 3999 arch\arm64\mm\mmu.c#0259 4000 arch\arm64\mm\mmu.c#0263 Review: COMMENT stecan Thu, 11 Jan 2018 07:27:00 +0100 Short Description: stecan Thu, 11 Jan 2018 07:27:00 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:27:00 +0100 Short Description: stecan Thu, 11 Jan 2018 07:27:00 +0100 Automatic commented! 4001 arch\arm64\mm\mmu.c#0266 4002 arch\arm64\mm\mmu.c#0270 4003 arch\arm64\mm\mmu.c#0285

Review_4.10_0_to_1000.pdf Page 777 of 793 May 04, 2018

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4004 arch\arm64\mm\mmu.c#0305 4005 arch\arm64\mm\mmu.c#0334 4006 arch\arm64\mm\mmu.c#0339 4007 arch\arm64\mm\mmu.c#0344 4008 arch\arm64\mm\mmu.c#0357 4009 arch\arm64\mm\mmu.c#0375 4010 arch\arm64\mm\mmu.c#0388 4011 arch\arm64\mm\mmu.c#0394 4012 arch\arm64\mm\mmu.c#0404 4013 arch\arm64\mm\mmu.c#0439 4014 arch\arm64\mm\mmu.c#0456 4015 arch\arm64\mm\numa.c#0038 Repo: aec03f89e905 Boris Mon Dec 12 23:18:29 2016 -0500 Description: ACPI/NUMA: Do not map pxm to node when NUMA is turned off ------acpi_map_pxm_to_node() unconditially maps nodes even when NUMA is turned off. So acpi_get_node() might return a node > 0, which is fatal when NUMA is disabled as the rest of the kernel assumes that only node 0 exists.

Expose numa_off to the acpi code and return NUMA_NO_NODE when it's set.

arm64/numa: fix incorrect log for memory-less node ------When booting on NUMA system with memory-less node (no memory dimm on this memory controller), the print for setup_node_data() is incorrect:

NUMA: Initmem setup node 2 [mem 0x00000000-0xffffffffffffffff]

It can be fixed by printing [mem 0x00000000-0x00000000] when end_pfn is 0, but print will be more useful.

Fixes: 1a2db300348b ("arm64, numa: Add NUMA support for arm64 platforms.")

4016 arch\arm64\mm\proc.S#0073 Repo: f33bcf03e607 Catalin Fri Jul 1 15:48:55 2016 +0100 Description: arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro ------This patch takes the errata workaround code out of cpu_do_switch_mm into a dedicated post_ttbr0_update_workaround macro which will be reused in a

Review_4.10_0_to_1000.pdf Page 778 of 793 May 04, 2018

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subsequent patch.

arm64: move sp_el0 and tpidr_el1 into cpu_suspend_ctx ------When returning from idle, we rely on the fact that thread_info lives at the end of the kernel stack, and restore this by masking the saved stack pointer. Subsequent patches will sever the relationship between the stack and thread_info, and to cater for this we must save/restore sp_el0 explicitly, storing it in cpu_suspend_ctx.

As cpu_suspend_ctx must be doubleword aligned, this leaves us with an extra slot in cpu_suspend_ctx. We can use this to save/restore tpidr_el1 in the same way, which simplifies the code, avoiding pointer chasing on the restore path (as we no longer need to load thread_info::cpu followed by the relevant slot in __per_cpu_offset based on this).

This patch stashes both registers in cpu_suspend_ctx.

4017 arch\arm64\mm\proc.S#0080 4018 arch\arm64\mm\proc.S#0096 4019 arch\arm64\mm\proc.S#0119 4020 arch\arm64\mm\proc.S#0145 4021 arch\arm64\mm\ptdump_debugfs.c#newFile Repo: 4ddb9bf83349 Laura Abbott Thu Oct 27 09:27:31 2016 -0700 Description: arm64: dump: Make ptdump debugfs a separate option ------ptdump_register currently initializes a set of page table information and registers debugfs. There are uses for the ptdump option without wanting the debugfs options. Split this out to make it a separate option.

arch\arm64\xen\ 4022 arch\arm64\xen\hypercall.S#0052 Repo: b4b8664d291a Al Viro Mon Dec 26 04:10:19 2016 -0500 Description: arm64: don't pull uaccess.h into *.S ------Split asm-only parts of arm64 uaccess.h into a new header and use that from *.S.

Replace with globally ------

Review_4.10_0_to_1000.pdf Page 779 of 793 May 04, 2018

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This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

arm64: xen: Enable user access before a privcmd hvc call ------Privcmd calls are issued by the userspace. The kernel needs to enable access to TTBR0_EL1 as the hypervisor would issue stage 1 translations to user memory via AT instructions. Since AT instructions are not affected by the PAN bit (ARMv8.1), we only need the explicit uaccess_enable/disable if the TTBR0 PAN option is enabled.

4023 arch\arm64\xen\hypercall.S#0095 4024 arch\arm64\xen\hypercall.S#0105 arch\avr32\include\asm\ 4025 arch\avr32\include\asm\mutex.h#fileDeleted Repo: 890658b7ab48 Peter Zijlstra Tue Aug 23 13:36:04 2016 +0200 Description: locking/mutex: Kill arch specific code ------Its all generic atomic_long_t stuff now.

4026 arch\avr32\include\asm\processor.h#0095 Repo: 6d0d287891a0 Christian Wed Nov 16 13:23:05 2016 +0100 Description: locking/core: Provide common cpu_relax_yield() definition ------No need to duplicate the same define everywhere. Since the only user is stop-machine and the only provider is s390, we can use a default implementation of cpu_relax_yield() in sched.h.

locking/core, arch: Remove cpu_relax_lowlatency() ------As there are no users left, we can remove cpu_relax_lowlatency() implementations from every architecture.

locking/core: Introduce cpu_relax_yield()

Review_4.10_0_to_1000.pdf Page 780 of 793 May 04, 2018

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------For spinning loops people do often use barrier() or cpu_relax(). For most architectures cpu_relax and barrier are the same, but on some architectures cpu_relax can add some latency. For example on power,sparc64 and arc, cpu_relax can shift the CPU towards other hardware threads in an SMT environment. On s390 cpu_relax does even more, it uses an hypercall to the hypervisor to give up the timeslice. In contrast to the SMT yielding this can result in larger latencies. In some places this latency is unwanted, so another variant "cpu_relax_lowlatency" was introduced. Before this is used in more and more places, lets revert the logic and provide a cpu_relax_yield that can be called in places where yielding is more important than latency. By default this is the same as cpu_relax on all architectures.

arch\avr32\include\uapi\asm\ 4027 arch\avr32\include\uapi\asm\socket.h#0093 Repo: 2bb148785ed7 Yuchung Sat Dec 3 14:46:22 2016 -0800 Description: tcp: fix the missing avr32 SOF_TIMESTAMPING_OPT_STATS ------The commit of SOF_TIMESTAMPING_OPT_STATS didn't include the new header for avr32, causing build to break. The patch fixes it.

Fixes: 1c885808e456 ("tcp: SOF_TIMESTAMPING_OPT_STATS option for SO_TIMESTAMPING")

4028 arch\avr32\include\uapi\asm\unistd.h#0343 Repo: 8712a5b80750 Hans- Mon Dec 12 09:23:09 2016 +0100 Description: avr32: wire up pkey syscalls ------This patch wires up the new pkey_mprotect, pkey_alloc and pkey_free syscalls on AVR32.

avr32: fixup code style in unistd.h and syscall_table.S ------This patch swaps the mix of tabs and space for alignment of comment after code to use spaces only.

Also document why recvmmsg was defined twice in the syscall_table.S table, but only once in unistd.h. In short, wired in the table by generic arch patch, but forgotten in unistd.h (review slip).

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Line Link NR. Descriptions arch\avr32\kernel\ 4029 arch\avr32\kernel\avr32_ksyms.c#0015 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

4030 arch\avr32\kernel\ptrace.c#0020 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

ptrace: cleanup arch_ptrace() on avr32 ------use new 'datap' variable type of void pointer in order to remove unnecessary castings.

4031 arch\avr32\kernel\signal.c#0020 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Review_4.10_0_to_1000.pdf Page 782 of 793 May 04, 2018

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Requested-by: Al Viro

4032 arch\avr32\kernel\syscall_table.S#0344 Repo: 8712a5b80750 Hans- Mon Dec 12 09:23:09 2016 +0100 Description: avr32: wire up pkey syscalls ------This patch wires up the new pkey_mprotect, pkey_alloc and pkey_free syscalls on AVR32.

avr32: fixup code style in unistd.h and syscall_table.S ------This patch swaps the mix of tabs and space for alignment of comment after code to use spaces only.

Also document why recvmmsg was defined twice in the syscall_table.S table, but only once in unistd.h. In short, wired in the table by generic arch patch, but forgotten in unistd.h (review slip).

4033 arch\avr32\kernel\time.c#0023 Repo: a5a1d1c2914b Thomas Wed Dec 21 20:32:01 2016 +0100 Description: clocksource: Use a plain u64 instead of cycle_t ------There is no point in having an extra type for extra confusion. u64 is unambiguous.

Conversion was done with the following coccinelle script:

@rem@ @@ -typedef u64 cycle_t;

@fix@ typedef cycle_t; @@ -cycle_t +u64

4034 arch\avr32\kernel\time.c#0025 arch\avr32\mach-at32ap\ 4035 arch\avr32\mach-at32ap\clock.c#0245 Repo: 017e7d024691 Markus Sun Oct 16 22:04:10 2016 +0200

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Description: AVR32-clock: Combine nine seq_printf() calls into one call in clk_show() ------Some data were printed into a sequence by nine separate function calls. Print the same data by a single function call instead.

AVR32-clock: Use seq_putc() in two functions ------A single character (line break) should be put into two sequences. Thus use the corresponding function "seq_putc".

This issue was detected by using the Coccinelle software.

4036 arch\avr32\mach-at32ap\clock.c#0264 4037 arch\avr32\mach-at32ap\clock.c#0289 4038 arch\avr32\mach-at32ap\pio.c#0370 Repo: 79ba1814dafc Markus Sun Oct 16 22:18:31 2016 +0200 Description: AVR32-pio: Replace two seq_printf() calls by seq_puts() in pio_bank_show() ------Strings which did not contain data format specifications should be put into a sequence. Thus use the corresponding function "seq_puts".

This issue was detected by using the Coccinelle software.

AVR32-pio: Use seq_putc() in pio_bank_show() ------A single character (line break) should be put into a sequence. Thus use the corresponding function "seq_putc".

This issue was detected by using the Coccinelle software.

4039 arch\avr32\mach-at32ap\pio.c#0372 4040 arch\avr32\mach-at32ap\pio.c#0376 arch\avr32\mm\ 4041 arch\avr32\mm\cache.c#0015 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*'

Review_4.10_0_to_1000.pdf Page 784 of 793 May 04, 2018

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sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

4042 arch\avr32\mm\dma-coherent.c#0149 Repo: e8b4762c2258 Alexander Wed Dec 14 15:04:35 2016 -0800 Description: arch/avr32: add option to skip sync on DMA map ------The use of DMA_ATTR_SKIP_CPU_SYNC was not consistent across all of the DMA APIs in the arch/arm folder. This change is meant to correct that so that we get consistent behavior.

Link: http://lkml.kernel.org/r/20161110113430.76501.79737.stgit@ahduyck-blue- test.jf.intel.com

4043 arch\avr32\mm\dma-coherent.c#0166 arch\blackfin\include\asm\ 4044 arch\blackfin\include\asm\Kbuild#0027 Repo: 890658b7ab48 Peter Zijlstra Tue Aug 23 13:36:04 2016 +0200 Description: locking/mutex: Kill arch specific code ------Its all generic atomic_long_t stuff now.

4045 arch\blackfin\include\asm\processor.h#0095 Repo: 6d0d287891a0 Christian Wed Nov 16 13:23:05 2016 +0100 Description: locking/core: Provide common cpu_relax_yield() definition ------No need to duplicate the same define everywhere. Since the only user is stop-machine and the only provider is s390, we can use a default implementation of cpu_relax_yield() in sched.h.

locking/core, arch: Remove cpu_relax_lowlatency() ------As there are no users left, we can remove cpu_relax_lowlatency() implementations from every architecture.

locking/core: Introduce cpu_relax_yield() ------

Review_4.10_0_to_1000.pdf Page 785 of 793 May 04, 2018

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For spinning loops people do often use barrier() or cpu_relax(). For most architectures cpu_relax and barrier are the same, but on some architectures cpu_relax can add some latency. For example on power,sparc64 and arc, cpu_relax can shift the CPU towards other hardware threads in an SMT environment. On s390 cpu_relax does even more, it uses an hypercall to the hypervisor to give up the timeslice. In contrast to the SMT yielding this can result in larger latencies. In some places this latency is unwanted, so another variant "cpu_relax_lowlatency" was introduced. Before this is used in more and more places, lets revert the logic and provide a cpu_relax_yield that can be called in places where yielding is more important than latency. By default this is the same as cpu_relax on all architectures.

arch\blackfin\kernel\ 4046 arch\blackfin\kernel\bfin_dma.c#0022 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

4047 arch\blackfin\kernel\dma-mapping.c#0121 Repo: 8c16a2e209d5 Alexander Wed Dec 14 15:04:38 2016 -0800 Description: arch/blackfin: add option to skip sync on DMA map ------The use of DMA_ATTR_SKIP_CPU_SYNC was not consistent across all of the DMA APIs in the arch/arm folder. This change is meant to correct that so that we get consistent behavior.

Link: http://lkml.kernel.org/r/20161110113436.76501.13386.stgit@ahduyck-blue- test.jf.intel.com

4048 arch\blackfin\kernel\dma-mapping.c#0150 4049 arch\blackfin\kernel\kgdb_test.c#0015 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally

Review_4.10_0_to_1000.pdf Page 786 of 793 May 04, 2018

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------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

4050 arch\blackfin\kernel\module.c#0017 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

4051 arch\blackfin\kernel\perf_event.c#0478 Repo: 73c1b41e63f0 Thomas Wed Dec 21 20:19:54 2016 +0100 Description: cpu/hotplug: Cleanup state names ------When the state names got added a script was used to add the extra argument to the calls. The script basically converted the state constant to a string, but the cleanup to convert these strings into meaningful ones did not happen.

Replace all the useless strings with 'subsys/xxx/yyy:state' strings which are used in all the other places already.

4052 arch\blackfin\kernel\ptrace.c#0273 Repo: 84d77d3f06e7 Eric W. Tue Nov 22 12:06:50 2016 -0600 Description: ptrace: Don't allow accessing an undumpable mm ------It is the reasonable expectation that if an executable file is not readable there will be no way for a user without special privileges to read the file. This is enforced in ptrace_attach but if ptrace is already attached before exec there is no enforcement for read-only

Review_4.10_0_to_1000.pdf Page 787 of 793 May 04, 2018

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executables.

As the only way to read such an mm is through access_process_vm spin a variant called ptrace_access_vm that will fail if the target process is not being ptraced by the current process, or the current process did not have sufficient privileges when ptracing began to read the target processes mm.

In the ptrace implementations replace access_process_vm by ptrace_access_vm. There remain several ptrace sites that still use access_process_vm as they are reading the target executables instructions (for kernel consumption) or register stacks. As such it does not appear necessary to add a permission check to those calls.

This bug has always existed in Linux.

Fixes: v1.0

4053 arch\blackfin\kernel\ptrace.c#0326 4054 arch\blackfin\kernel\time-ts.c#0029 Repo: a5a1d1c2914b Thomas Wed Dec 21 20:32:01 2016 +0100 Description: clocksource: Use a plain u64 instead of cycle_t ------There is no point in having an extra type for extra confusion. u64 is unambiguous.

Conversion was done with the following coccinelle script:

@rem@ @@ -typedef u64 cycle_t;

@fix@ typedef cycle_t; @@ -cycle_t +u64

4055 arch\blackfin\kernel\time-ts.c#0083 arch\blackfin\mach-bf561\ 4056 arch\blackfin\mach-bf561\coreb.c#0003 Repo: 2d4d3b5d45f2 Paul Sat Oct 29 16:38:42 2016 -0400 Description: blackfin: make-bf561/coreb.c explicitly non-modular ------The Kconfig currently controlling compilation of this code is:

Review_4.10_0_to_1000.pdf Page 788 of 793 May 04, 2018

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config BF561_COREB bool "Enable Core B loader"

...meaning that it currently is not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only.

Since module_misc_device translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit.

We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments.

Review: COMMENT stecan Thu, 11 Jan 2018 07:27:05 +0100 Short Description: stecan Thu, 11 Jan 2018 07:27:05 +0100 Automatic commented! Test: COMMENT stecan Thu, 11 Jan 2018 07:27:05 +0100 Short Description: stecan Thu, 11 Jan 2018 07:27:05 +0100 Automatic commented! 4057 arch\blackfin\mach-bf561\coreb.c#0019 4058 arch\blackfin\mach-bf561\coreb.c#0022 4059 arch\blackfin\mach-bf561\coreb.c#0064 arch\c6x\include\asm\ 4060 arch\c6x\include\asm\mutex.h#fileDeleted Repo: 890658b7ab48 Peter Zijlstra Tue Aug 23 13:36:04 2016 +0200 Description: locking/mutex: Kill arch specific code ------Its all generic atomic_long_t stuff now.

4061 arch\c6x\include\asm\processor.h#0124 Repo: 6d0d287891a0 Christian Wed Nov 16 13:23:05 2016 +0100 Description: locking/core: Provide common cpu_relax_yield() definition ------No need to duplicate the same define everywhere. Since the only user is stop-machine and the only provider is s390, we can use a default implementation of cpu_relax_yield() in sched.h.

Review_4.10_0_to_1000.pdf Page 789 of 793 May 04, 2018

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Line Link NR. Descriptions

locking/core, arch: Remove cpu_relax_lowlatency() ------As there are no users left, we can remove cpu_relax_lowlatency() implementations from every architecture.

locking/core: Introduce cpu_relax_yield() ------For spinning loops people do often use barrier() or cpu_relax(). For most architectures cpu_relax and barrier are the same, but on some architectures cpu_relax can add some latency. For example on power,sparc64 and arc, cpu_relax can shift the CPU towards other hardware threads in an SMT environment. On s390 cpu_relax does even more, it uses an hypercall to the hypervisor to give up the timeslice. In contrast to the SMT yielding this can result in larger latencies. In some places this latency is unwanted, so another variant "cpu_relax_lowlatency" was introduced. Before this is used in more and more places, lets revert the logic and provide a cpu_relax_yield that can be called in places where yielding is more important than latency. By default this is the same as cpu_relax on all architectures.

arch\c6x\kernel\ 4062 arch\c6x\kernel\dma.c#0045 Repo: 64c596b59c72 Alexander Wed Dec 14 15:04:41 2016 -0800 Description: arch/c6x: add option to skip sync on DMA map and unmap ------This change allows us to pass DMA_ATTR_SKIP_CPU_SYNC which allows us to avoid invoking cache line invalidation if the driver will just handle it later via a sync_for_cpu or sync_for_device call.

Link: http://lkml.kernel.org/r/20161110113442.76501.7673.stgit@ahduyck-blue- test.jf.intel.com

4063 arch\c6x\kernel\dma.c#0054 4064 arch\c6x\kernel\dma.c#0066 4065 arch\c6x\kernel\dma.c#0079 4066 arch\c6x\kernel\dma.c#0084 4067 arch\c6x\kernel\time.c#0029 Repo: a5a1d1c2914b Thomas Wed Dec 21 20:32:01 2016 +0100 Description: clocksource: Use a plain u64 instead of cycle_t ------There is no point in having an extra type for extra confusion. u64 is

Review_4.10_0_to_1000.pdf Page 790 of 793 May 04, 2018

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unambiguous.

Conversion was done with the following coccinelle script:

@rem@ @@ -typedef u64 cycle_t;

@fix@ typedef cycle_t; @@ -cycle_t +u64

arch\c6x\mm\ 4068 arch\c6x\mm\init.c#0021 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

mm/c6x: prepare for removing num_physpages and simplify mem_init() ------Prepare for removing num_physpages and simplify mem_init().

mm: concentrate modification of totalram_pages into the mm core ------Concentrate code to modify totalram_pages into the mm core, so the arch memory initialized code doesn't need to take care of it. With these changes applied, only following functions from mm core modify global variable totalram_pages: free_bootmem_late(), free_all_bootmem(), free_all_bootmem_node(), adjust_managed_page_count().

With this patch applied, it will be much more easier for us to keep totalram_pages and zone->managed_pages in consistence.

mm: enhance free_reserved_area() to support poisoning memory with zero

Review_4.10_0_to_1000.pdf Page 791 of 793 May 04, 2018

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------Address more review comments from last round of code review. 1) Enhance free_reserved_area() to support poisoning freed memory with pattern '0'. This could be used to get rid of poison_init_mem() on ARM64. 2) A previous patch has disabled memory poison for initmem on s390 by mistake, so restore to the original behavior. 3) Remove redundant PAGE_ALIGN() when calling free_reserved_area().

mm: change signature of free_reserved_area() to fix building warnings ------Change signature of free_reserved_area() according to Russell King's suggestion to fix following build warnings:

arch/arm/mm/init.c: In function 'mem_init': arch/arm/mm/init.c:603:2: warning: passing argument 1 of 'free_reserved_area' makes integer from pointer without a cast [enabled by default] free_reserved_area(__va(PHYS_PFN_OFFSET), swapper_pg_dir, 0, NULL); ^ In file included from include/linux/mman.h:4:0, from arch/arm/mm/init.c:15: include/linux/mm.h:1301:22: note: expected 'long unsigned int' but argument is of type 'void *' extern unsigned long free_reserved_area(unsigned long start, unsigned long end,

mm/page_alloc.c: In function 'free_reserved_area': >> mm/page_alloc.c:5134:3: warning: passing argument 1 of 'virt_to_phys' makes pointer from integer without a cast [enabled by default] In file included from arch/mips/include/asm/page.h:49:0, from include/linux/mmzone.h:20, from include/linux/gfp.h:4, from include/linux/mm.h:8, from mm/page_alloc.c:18: arch/mips/include/asm/io.h:119:29: note: expected 'const volatile void *' but argument is of type 'long unsigned int' mm/page_alloc.c: In function 'free_area_init_nodes': mm/page_alloc.c:5030:34: warning: array subscript is below array bounds [-Warray- bounds]

Also address some minor code review comments.

arch\cris\arch-v10\drivers\ 4069 arch\cris\arch-v10\drivers\eeprom.c#0032 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------

Review_4.10_0_to_1000.pdf Page 792 of 793 May 04, 2018

Review der Linux Kernel Sourcen von 4.9 auf 4.10

Line Link NR. Descriptions

This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

4070 arch\cris\arch-v10\drivers\sync_serial.c#0030 Repo: 7c0f6ba682b9 Linus Sat Dec 24 11:46:01 2016 -0800 Description: Replace with globally ------This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*' sed -i -e "s!$PATT!#include !" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro

Review_4.10_0_to_1000.pdf Page 793 of 793 May 04, 2018