FD-SOI Technology
Bich-Yen Nguyen Soitec Agenda
1 FD-SOI technology overview
2 Markets, foundries offers
3 FD-SOI material & roadmap
4 Summary
10/10/20172 SOITEC Confidential FD-SOI technology Challenge of Traditional Planar Bulk Transistor Scaling
Source: IBM, T.C. Chen, ISSCC 2006 • Increased standby power dissipation • Amplified V variability th new transistor architectures and ⇒Impact Yield materials are needed ⇒Limit Vdd scaling
10/10/20173 SOITEC Confidential FD-SOI technology Continue Moore Law with New Materials & Device Architectures 2003 2005 2007 2009 2011 2012
Hartmann, GSA12 90nm 45 nm 22nm
65nm 32nm
Strained Silicon
Introduction of High-K / Metal Gate New Materials
Introduction of Fully Depleted New Device Devices Architecture 10/10/2017 4 SOITEC Confidential FD-SOI technology Leakage Power is still a Major Issue Despite the Use of Hi-K Dielectric
High-K/Metal Gate Stack
Source: IBS
SiON/Poly Gate Stack
Technology node Leakage power is still tremendously growing after insertion of the High- K/MG gate stack at 28nm node as demands for more performance and functionality
10/10/20175 SOITEC Confidential FD-SOI technology New Device Architecture: Planar FDSOI or Multi-Gate Transistor
Minimum Design Max Disruption scalability G G D SD S Buried OX S G D
Bulk Si Bulk Si Buried oxide
Conventional Planar Planar Single-or double Multiple-Gate, FinFET or Bulk Transistor Gate FDSOI Nanowire Transistor FDSOI : Fully Depleted Silicon-on Insulator
Thin channels (Fully depleted) with multi gates for better gate or short channel (SCE) control Better gate control ⇒ better transistors scaling
10/10/20176 SOITEC Confidential FD-SOI technology FD-SOI Transistor Advantages
UTBB FDSOI Transistor Advantages
Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage • Latch-up immunity
Ultra thin Body • Excellent SCE (SS, DIBL) • No History Effect • Lower SER
• Improved V T variability No channel doping • Improved mismatch (SRAM & analog) • Better analog gain • Reduced process cost Courtesy of STM Body Biasing Ultra thin BOX option • Enables Extended body biasing Knobs to control Perf/Power: Channel mobility boost • Scalable down to 10nm ß Gate bias ß Back Bias Conventional planar • Lower manufacturing risk processing • Equivalent bulk design UTBB: Ultra-Thin Body and BOX
10/10/20177 SOITEC Confidential FD-SOI technology FDSOI Device Physics
Body factor: n = …1.05… in FDSOI; …1.5… in Bulk FDSOI Vg G Bulk/PDSOI Vg G Coxf S D Cox F S D Csi s1 Oxide F F Silicon Cdepl s Coxb s2
W 1 2 Linear current: I = µ C ()V − V V − n V D ox L G TH D 2 D 1 W 2 Saturation current: I = µ C (()V − V ) Dsat 2n ox L G TH kT Sub-threshold slope: S = n ln(10 ) q µ gm = 2 Cox W L Gain (strong inversion): VA VA ID n ID
10/10/20178 SOITEC Confidential FD-SOI technology FD-SOI Transistor Advantages
UTBB FDSOI Transistor Advantages
Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage • Latch-up immunity
Ultra thin Body • Excellent SCE (SS, DIBL) • No History Effect • Lower SER
• Improved V T variability No channel doping • Improved mismatch (SRAM & analog) • Better analog gain • Reduced process cost Courtesy of STM Body Biasing Ultra thin BOX option • Enables Extended body biasing Knobs to control Perf/Power: Channel mobility boost • Scalable down to 10nm ß Gate bias ß Back Bias Conventional planar • Lower manufacturing risk processing • Equivalent bulk design
UTBB: Ultra-Thin Body and BOX
10/10/20179 SOITEC Confidential FD-SOI technology FD-SOI Transistor Level Benefits
BULK FD-SOI Thin and excellent Gate uniformity SOI defined Gate channel
Source Drain Source Top Si Drain BOX 2nd gate through ultra thin BOX Bulk wafer FD-SOI base wafer