EmergingEmerging ProtocolsProtocols && ApplicationsApplications

AnthonyAnthony DalleggioDalleggio ExecutiveExecutive ViceVice PresidentPresident Modelware,Modelware, Inc.Inc.

© 2001

ContentsContents

„ Historical System Bandwidth Trends − The PC Bus − SONET, UTOPIA, & POS-PHY „ Targeted Applications − SANs: Infiniband − Standard Interfaces z Control Plane Interfaces: RapidIO, HyperTransport, 3GIO z Framer/NP Interfaces: SPI-3/PL3, FB3, SPI-4 Ph1/FB4, SPI-4 Ph2/PL4, UTOPIA 4 z NP/Switch Fabric Interface: CSIX „ Creating Successful Standards

© 2001

1 TheThe PCPC BusBus

100,000 ?

10,000 PCI-X PCI 2.0

Mbps 1,000 VESA PCI 1.0 MCA EISA ISA 16 100 ISA 8 10 1970 1980 1990 2000 2010

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© 2001

SONET,SONET, UTOPIA,UTOPIA, && POS-PHYPOS-PHY

100,000

OC-192 10,000 UL4/PL4

OC-48 UL3/PL3 Mbps 1,000 UL2 OC-12 PL2 UTOPIA OC-3 100 UL1 POS-PHY SONET

10 1990 1995 2000 2005

621(7Ã%DQGZLGWKÃ+DVÃ,QFUHDVHGÃ[Ã(YHU\ÃÃ

© 2001

2 TargetedTargeted ApplicationsApplications

StorageStorage AreaArea NetworkNetwork (SAN)(SAN)

Internet

© 2001

StorageStorage AreaArea NetworksNetworks „ Focused on Clustered Servers „ 2.5-Gbps Bandwidth „ Layer 2/3 Fabric

Infiniband

© 2001

3 StorageStorage AreaArea NetworksNetworks

„ Point-to-Point Switched Interconnect Used in IPC, Storage & Network I/O „ Architecture Elements: Links, Switches & Routers „ Scalable Number of Links: 1, 4 & 12 Links „ Virtual Lanes „ Several Independent Protocol Layers „ Supports Redundant Paths & Fabrics for RAS Support „ Copper & Optical „ High Bandwidth, up to 3 GBps (12 X 2.5 Gbps X (8/10) /8)

© 2001 Source: Intel IB Arch. Overview

TargetedTargeted ApplicationsApplications

StorageStorage AreaArea NetworkNetwork (SAN)(SAN)

Internet

© 2001

4 StandardStandard InterfacesInterfaces

Host Card

Line Switch Cards Card

© 2001

ControlControl PlanePlane InterfacesInterfaces

HostHost ProcessorProcessor CardCard

SDRAM 3URFHVVRU

SRAM PCI/PCI-X HyperTransport Host RapidIO Card

Line Switch Cards Card

© 2001

5 ControlControl PlanePlane InterfacesInterfaces

Host Processor Card RapidIO SDRAM 3URFHVVRU

SRAM „ Device-to-Device or Board-to-Board Rapid I/O Interconnect „ Data Bus Widths: 8 & 16 Bit „ In-Band Address & Control „ High Bandwidth—up to 32 Gbps (16 x 1 GHz x DDR) „ Low Latency „ Small Silicon Footprint „ Error Management „ Limited Impact on Existing Software Base „ Independent Logical & Physical Layers „ I/O— LP-LVDS— 40 Pins for 8-Bit Data, 76 Pins for 16-Bit Data

© 2001 Source: RapidIO White Paper

ControlControl PlanePlane InterfacesInterfaces

Host Processor Card HyperTransport SDRAM 3URFHVVRU

SRAM „ Device-to-Device HyperTransport „ Scalable Data Bus Widths: 2, 4, 8, 16 & 32 Bit „ In-Band Address & Control „ High Bandwidth—up to 25.6 Gbps (32 x 400 MHz X DDR) „ Low Latency „ Error Detection „ Multiple Tunnel Device Daisy Chaining (up to 32) „ Operating System (OS) Transparent, Small Impact on Drivers „ LVDS I/O: 40 Pins for 8-Bit Data, 76 Pins for 16-Bit Data

© 2001 Source: AMD Website

6 ControlControl PlanePlane InterfacesInterfaces

Host Processor Card 3GIO SDRAM 3URFHVVRU

SRAM „ Point-to-Point 3GIO „ Serial „ Copper & Optical Physical Interfaces „ Scalable Data Bus Widths „ Beyond 10-GHz Signaling Rates „ Draft of 3GIO Specification Made Available at Intel Developer Forum this Month

© 2001 Source: Microprocessor Report

Framer,Framer, NetworkNetwork ProcessorProcessor && SwitchSwitch FabricFabric InterfacesInterfaces

Host LineLine CardCard Card

1HWZRUNÃ O/E )UDPHU 3URFHVVRU SERDES SERDES Line Cards SPI CSIX Switch POS-PHY Card UTOPIA Flexbus Format

© 2001

7 PHY-LinkPHY-Link LayerLayer BusBus InterfacesInterfaces

155 Mbps 622 Mbps 2.5 Gbps 10 Gbps

UTOPIA UTOPIA UTOPIA UTOPIA Level 1 Level 2 Level 3 Level 4

POS-PHY POS-PHY POS-PHY Level 2 Level 3 Level 4

SPI-3 SPI-4 P2

Flexbus Flexbus Format 3 Cell-Based 4 Cell-or Packet-Based SPI-4 P1 © 2001

Framer,Framer, NetworkNetwork ProcessorProcessor

&& SwitchSwitch FabricFabric InterfacesInterfaces Line Card

SPI-3 / POS-PHY L3 O/E Framer 13 SERDES SERDES SERDES „ Device-to-Device SPI-3 / PL3 „ Data Bus Widths: 8 & 32 Bit „ In-Band Addressing Logical Channels Scalable up to 256 „ PHY & Link Layer Functions Data Source Determines Channel Order „ Polling Done Only by Link Layer in Tx Direction „ Bandwidth up to 3.3 Gbps (32 Bits x 104 MHz) for OC-48 Applications „ LVTTL I/O: 90 Pins for 48-Channel Packet Mode Configuration

© 2001 Source: OIF Specification

8 Framer,Framer, NetworkNetwork ProcessorProcessor

&& SwitchSwitch FabricFabric InterfacesInterfaces Line Card

Flexbus-3 O/E Framer 13 SERDES SERDES SERDES „ Device-to-Device Flexbus-3 „ UTOPIA L3-Compatible in ATM Mode Packet Mode Only Adds EOP, Mod, & Err „ Data Bus Widths: 8, 16 & 32 „ Scalable Logical Channels „ PHY & Link Layer Functions: Link Layer Determines Channel Order „ Polling Done Only by Link Layer in Rx & Tx Directions „ Bandwidth up to 3.3 Gbps (32 Bits x 104 MHz) for OC-48 Applications „ LVTTL I/O: 94 Pins for 48-Channel Configuration

© 2001 Source: AMCC

Framer,Framer, NetworkNetwork ProcessorProcessor

&& SwitchSwitch FabricFabric InterfacesInterfaces Line Card

SPI-4 Phase 1/ 13 Flexbus-4 Format O/E Framer SERDES SERDES SERDES „ Device-to-Device SPI-4 Ph1/FB4 „ Data Bus Width: 64 Bit „ Scalable Logical Channels „ PHY/Link Symmetrical Interface Data Source Determines Channel Order „ Source Synchronous Clocking „ Channel Status Reporting by Sink Side „ Bandwidth up to 12.8 Gbps & Higher (64 Bits x 200 MHz) for OC-192 Applications „ HSTL I I/O: 178 Pins for 192-Channel Configuration

© 2001 Source: OIF Specification

9 Framer,Framer, NetworkNetwork ProcessorProcessor

&& SwitchSwitch FabricFabric InterfacesInterfaces Line Card

SPI-4 Phase 2/ 13 POS-PHY L4 O/E Framer SERDES SERDES SERDES „ Device-to-Device SPI-4 Ph2/PL4 „ Data Bus Width: 16 Bit „ In-Band Addressing & Packet Signaling. Logical Channels Scalable up to 256 Bits (More with Extended-Control Word) „ PHY/Link Symmetrical Interface Data Source Determines Channel Order „ Source Synchronous Clocking „ Capability for Dynamic Alignment to Compensate for Trace Skew Between Data & Control Bits „ Channel Status Reporting by Sink Side „ Bandwidth up to 10 Gbps & Higher (16 Bits x 311 MHz x DDR) for OC-192 Applications „ LVDS I/O: 72 Pins, LVTTL I/O: 6 Pins for Any Number of Channels

© 2001 Source: OIF Specification

Framer,Framer, NetworkNetwork ProcessorProcessor

&& SwitchSwitch FabricFabric InterfacesInterfaces Line Card

UTOPIA L4 O/E Framer 13 SERDES SERDES SERDES „ Device-to-Device UTOPIA L4 „ Data Bus Widths: 8, 16 & 32 „ In-Band Addressing, Packet Signaling & Flow Control Logical Channels Scalable up to 256 „ PHY/Link Symmetrical Interface Data Source Determines Channel Order „ Source-Synchronous Clocking „ Bandwidth up to 13.3 Gbps (32 Bits x 415 MHz) for OC-192 Applications „ LVDS I/O: 136 Pins for Any Number of Channels

© 2001 Source: ATM Forum Specification

10 Framer,Framer, NetworkNetwork ProcessorProcessor && SwitchSwitch FabricFabric InterfacesInterfaces

CSIX RxClk „ Traffic Manager/Network Processor RxData to Switch Fabric Interface RxPar „ Data Bus Widths: 32, 64, 96 & 128 RxSOF NP TxClk Switch „ In-Band Addressing & Flow Control. TxData Supports up to 4,096 Ports TxPar „ Traffic Manager/Fabric Symmetrical Interface Data Source Determines TxSOF Channel Order CSIX „ Source Synchronous Clocking „ Bandwidth up to 32 Gbps (128 Bits x 250 MHz) „ I/O: HSTL or LVTTL: 140 Pins for Single OC-192 Port (64 Bits)

© 2001 Source: Source: CSIX/NPF Specification

CreatingCreating SuccessfulSuccessful StandardsStandards „ One Standard per Market Sector „ Vendor & User Involvement „ Easy to Use „ Open & Freely Available „ Can Be Implemented Using Existing Technology „ Backward-Compatible Accommodating Existing Products

© 2001

11 SummarySummary

„ Historical System Bandwidth Trends − The PC Bus − SONET, UTOPIA, & POS-PHY „ Targeted Applications − SANs: Infiniband − Standard Interfaces z Control Plane Interfaces: RapidIO, HyperTransport, 3GIO z Framer/NP Interfaces: SPI-3/PL3, FB3, SPI-4 Ph1/FB4, SPI-4 Ph2/PL4, UTOPIA 4 z NP/Switch Fabric Interface: CSIX „ Creating Successful Standards

© 2001

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