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Hardfails: Insights Into Software-Exploitable Hardware Bugs

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Hardfails: Insights Into Software-Exploitable Hardware Bugs HardFails: Insights into Software-Exploitable Hardware Bugs Ghada Dessouky and David Gens, Technische Universität Darmstadt; Patrick Haney and Garrett Persyn, Texas A&M University; Arun Kanuparthi, Hareesh Khattri, and Jason M. Fung, Intel Corporation; Ahmad-Reza Sadeghi, Technische Universität Darmstadt; Jeyavijayan Rajendran, Texas A&M University https://www.usenix.org/conference/usenixsecurity19/presentation/dessouky This paper is included in the Proceedings of the 28th USENIX Security Symposium. August 14–16, 2019 • Santa Clara, CA, USA 978-1-939133-06-9 Open access to the Proceedings of the 28th USENIX Security Symposium is sponsored by USENIX. HardFails: Insights into Software-Exploitable Hardware Bugs Ghada Dessouky†, David Gens†, Patrick Haney∗, Garrett Persyn∗, Arun Kanuparthi◦, Hareesh Khattri◦, Jason M. Fung◦, Ahmad-Reza Sadeghi†, Jeyavijayan Rajendran∗ †Technische Universität Darmstadt, Germany. ∗Texas A&M University, College Station, USA. ◦Intel Corporation, Hillsboro, OR, USA. [email protected],[email protected], [email protected],[email protected],[email protected], [email protected],[email protected], [email protected],[email protected] Abstract ticated attacks that combine software and hardware bugs to exploit computing platforms at runtime [20, 23, 36, 43, 45, 64, Modern computer systems are becoming faster, more efficient, 69, 72, 74]. These cross-layer attacks disrupt traditional threat and increasingly interconnected with each generation. Thus, models, which assume either hardware-only or software-only these platforms grow more complex, with new features con- adversaries. Such attacks may provoke physical effects to in- tinually introducing the possibility of new bugs. Although the duce hardware faults or trigger unintended microarchitectural semiconductor industry employs a combination of different states. They can make these effects visible to software adver- verification techniques to ensure the security of System-on- saries, enabling them to exploit these hardware vulnerabilities Chip (SoC) designs, a growing number of increasingly so- remotely. The affected targets range from low-end embedded phisticated attacks are starting to leverage cross-layer bugs. devices to complex servers, that are hardened with advanced These attacks leverage subtle interactions between hardware defenses, such as data-execution prevention, supervisor-mode and software, as recently demonstrated through a series of execution prevention, and control-flow integrity. real-world exploits that affected all major hardware vendors. In this paper, we take a deep dive into microarchitectural Hardware vulnerabilities. Cross-layer attacks circumvent security from a hardware designer’s perspective by reviewing many existing security mechanisms [20, 23, 43, 45, 64, 69, 72, state-of-the-art approaches used to detect hardware vulnera- 74], that focus on mitigating attacks exploiting software vul- bilities at design time. We show that a protection gap currently nerabilities. Moreover, hardware-security extensions are not exists, leaving chip designs vulnerable to software-based at- designed to tackle hardware vulnerabilities. Their implemen- tacks that can exploit these hardware vulnerabilities. Inspired tation remains vulnerable to potentially undetected hardware by real-world vulnerabilities and insights from our industry bugs committed at design-time. In fact, deployed extensions collaborator (a leading chip manufacturer), we construct the such as SGX [31] and TrustZone [3] have been targets of suc- first representative testbed of real-world software-exploitable cessful cross-layer attacks [69, 72]. Research projects such RTL bugs based on RISC-V SoCs. Patching these bugs may as Sanctum [18], Sanctuary [8], or Keystone [39] are also not not always be possible and can potentially result in a product designed to ensure security at the hardware implementation recall. Based on our testbed, we conduct two extensive case level. Hardware vulnerabilities can occur due to: (a) incor- studies to analyze the effectiveness of state-of-the-art security rect or ambiguous security specifications, (b) incorrect design, verification approaches and identify specific classes of vulner- (c) flawed implementation of the design, or (d) a combination abilities, which we call HardFails, which these approaches thereof. Hardware implementation bugs are introduced either fail to detect. Through our work, we focus the spotlight on through human error or faulty translation of the design in specific limitations of these approaches to propel future re- gate-level synthesis. search in these directions. We envision our RISC-V testbed SoC designs are typically implemented at register-transfer of RTL bugs providing a rich exploratory ground for future level (RTL) by engineers using hardware description lan- research in hardware security verification and contributing to guages (HDLs), such as Verilog and VHDL, which are synthe- the open-source hardware landscape. sized into a lower-level representation using automated tools. Just like software programmers introduce bugs to the high- level code, hardware engineers may accidentally introduce 1 Introduction bugs to the RTL code. While software errors typically cause a crash which triggers various fallback routines to ensure the The divide between hardware and software security research safety and security of other programs running on the platform, is starting to take its toll, as we witness increasingly sophis- no such safety net exists for hardware bugs. Thus, even mi- USENIX Association 28th USENIX Security Symposium 213 nor glitches in the implementation of a module within the first deploys formal verification to perform exhaustive and processor can compromise the SoC security objectives and complete verification of a hardware design, while the second result in persistent/permanent denial of service, IP leakage, or leverages formal verification and path sensitization to check exposure of assets to untrusted entities. for illegal data flows and fault tolerance. Our second case study revealed that certain properties of Detecting hardware security bugs. The semiconductor in- RTL bugs pose challenges for state-of-the-art verification dustry makes extensive use of a variety of techniques, such techniques with respect to black-box abstraction, timing flow, as simulation, emulation, and formal verification to detect and non-register states. This causes security bugs in the RTL such bugs. Examples of industry-standard tools include In- of real-world SoCs to slip through the verification process. cisive [10], Solidify [5], Questa Simulation and Questa For- Our results from the two case studies indicate that particu- mal [44], OneSpin 360 [66], and JasperGold [11]. These were lar classes of hardware bugs entirely evade detection—even originally designed for functional verification with security- when complementing systematic tool-based verification ap- specific verification incorporated into them later. proaches with manual inspection. RTL bugs arising from While a rich body of knowledge exists within the software complex and cross-modular interactions in SoCs render these community (e.g., regarding software exploitation and tech- bugs extremely difficult to detect in practice. Furthermore, niques to automatically detect software vulnerabilities [38, such bugs are exploitable from software, and thus can com- 46]), security-focused HDL analysis is currently lagging be- promise the entire platform. We call such bugs HardFails. hind [35, 57]. Hence, the industry has recently adopted a To the best of our knowledge, this is the first work to pro- security development lifecycle (SDL) for hardware [68]— vide a systematic and in-depth analysis of state-of-the-art inspired by software practices [26]. This process combines hardware verification approaches for security-relevant RTL different techniques and tools, such as RTL manual code au- bugs. Our findings shed light on the capacity of these tools and dits, assertion-based testing, dynamic simulation, and auto- demonstrate reproducibly how bugs can slip through current mated security verification. However, the recent outbreak of hardware security verification processes. Being also software- cross-layer attacks [20, 23, 37, 43, 45, 47, 48, 49, 51, 52, 53, exploitable, these bugs pose an immense security threat to 64, 69, 74] poses a spectrum of difficult challenges for these SoCs. Through our work, we highlight why further research security verification techniques, because they exploit complex is required to improve state-of-the-art security verification of and subtle inter-dependencies between hardware and software. hardware. To summarize, our main contributions are: Existing verification techniques are fundamentally limited in • Systematic evaluation and case studies: We compile modeling and verifying these interactions. Moreover, they a comprehensive test harness of real-world RTL bugs, on also do not scale with the size and complexity of real-world which we base our two case studies: (1) Hack@DAC’18, SoC designs. in which 54 independent teams of researchers competed Goals and Contributions. In this paper, we show that cur- worldwide over three months to find these bugs using rent hardware security verification techniques are fundamen- manual RTL inspection and simulation techniques, and tally limited. We provide a wide range of results using a (2) an investigation of the bugs using industry-leading comprehensive test harness, encompassing different
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