Hardware Security, Vulnerabilities, and Attacks: a Comprehensive Taxonomy∗
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Ghostbuster: Understanding and Overcoming the Pitfalls of Transient Execution Vulnerability Checkers
GhostBuster: understanding and overcoming the pitfalls of transient execution vulnerability checkers Andrea Mambretti∗y, Pasquale Convertiniy, Alessandro Sorniottiy, Alexandra Sandulescuy, Engin Kirda∗ and Anil Kurmusy ∗Khoury College of Computer Sciences, Northeastern University, Boston, USA Email: fmbr, [email protected] y IBM Research - Zurich, Rueschlikon, Switzerland Email: [email protected], faso, asa, [email protected] Abstract—Transient execution vulnerabilities require system co-located thread, and the threat model requires that the victim administrators to evaluate whether their systems are vulnerable process contains a side channel primitive allowing leakage of and whether available mitigations are enabled. They are aided sensitive data. While some of these attacks are exploitable in in this task by multiple community-developed tools, transient real-world settings, others have not left the realm of theoretical execution vulnerability checkers. Yet, no analysis of these tools vulnerabilities. exists, in particular with respect to their shortcomings and whether they might mislead administrators into a false sense Owing to the high number of transient execution attacks of security. In this paper, we provide the first comprehensive (both practical and theoretical) and the multitude of mitigation analysis of these tools and underpinning methodologies. We mechanisms, the degree to which systems are safe against run the tools on a large set of combinations of Intel/AMD speculative execution attackers is often hard to determine. The architectures and Linux kernel versions and report on their determination is made even more complex by the fact that a efficacy and shortcomings. We also run these tools on 17 of the most prominent cloud providers, report the collected results system might be affected by a certain microarchitectural attack and present the current status on the preparedness of the IT vector, while being safe in practice because the conditions of hosting industry against this class of attacks. -
Class-Action Lawsuit
Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 1 of 279 Steve D. Larson, OSB No. 863540 Email: [email protected] Jennifer S. Wagner, OSB No. 024470 Email: [email protected] STOLL STOLL BERNE LOKTING & SHLACHTER P.C. 209 SW Oak Street, Suite 500 Portland, Oregon 97204 Telephone: (503) 227-1600 Attorneys for Plaintiffs [Additional Counsel Listed on Signature Page.] UNITED STATES DISTRICT COURT DISTRICT OF OREGON PORTLAND DIVISION BLUE PEAK HOSTING, LLC, PAMELA Case No. GREEN, TITI RICAFORT, MARGARITE SIMPSON, and MICHAEL NELSON, on behalf of CLASS ACTION ALLEGATION themselves and all others similarly situated, COMPLAINT Plaintiffs, DEMAND FOR JURY TRIAL v. INTEL CORPORATION, a Delaware corporation, Defendant. CLASS ACTION ALLEGATION COMPLAINT Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 2 of 279 Plaintiffs Blue Peak Hosting, LLC, Pamela Green, Titi Ricafort, Margarite Sampson, and Michael Nelson, individually and on behalf of the members of the Class defined below, allege the following against Defendant Intel Corporation (“Intel” or “the Company”), based upon personal knowledge with respect to themselves and on information and belief derived from, among other things, the investigation of counsel and review of public documents as to all other matters. INTRODUCTION 1. Despite Intel’s intentional concealment of specific design choices that it long knew rendered its central processing units (“CPUs” or “processors”) unsecure, it was only in January 2018 that it was first revealed to the public that Intel’s CPUs have significant security vulnerabilities that gave unauthorized program instructions access to protected data. 2. A CPU is the “brain” in every computer and mobile device and processes all of the essential applications, including the handling of confidential information such as passwords and encryption keys. -
Public Clouds and Vulnerable Cpus: Are We Secure? FOSDEM 2020
Public clouds and vulnerable CPUs: are we secure? FOSDEM 2020 Vitaly Kuznetsov <[email protected]> About About myself ● Focusing (mostly) on Linux kernel ● My areas of interest include: ○ Linux as guest on public clouds (AWS, Azure, Aliyun,...) ○ Linux as guest on Hyper-V ○ Hyper-V Enlightenments in KVM ○ Running nested KVM on Hyper-V ○ Running nested Hyper-V on KVM Speculative vulnerabilities Speculative vulnerabilities discovered in the past few years: ● Spectre v1 ○ SWAPGS ● Spectre v2 ● Meltdown (Spectre v3) ● SSB (Spectre v4/NG) ● L1TF (AKA Foreshadow/Spectre v5) ● MDS & TAA Speculative vulnerabilities Speculative Execution Side Channel Methods Intel: “The concept behind speculative execution is that instructions are executed ahead of knowing that they are required. [...] By executing instructions speculatively, performance can be increased by minimizing latency and extracting greater parallelism. …. While speculative operations do not affect the architectural state of the processor, they can affect the microarchitectural state, such as information stored in Translation Lookaside Buffers (TLBs) and caches. ... A side channel method works by gaining information through observing the system, such as by measuring microarchitectural properties about the system. Unlike buffer overflows and other vulnerability classes, side channels do not directly influence the execution of the program, nor do they allow data to be modified or deleted. ” Speculative vulnerabilities and public clouds When running on a public cloud … but my cloud provider -
A Survey of Published Attacks on Intel
1 A Survey of Published Attacks on Intel SGX Alexander Nilsson∗y, Pegah Nikbakht Bideh∗, Joakim Brorsson∗zx falexander.nilsson,pegah.nikbakht_bideh,[email protected] ∗Lund University, Department of Electrical and Information Technology, Sweden yAdvenica AB, Sweden zCombitech AB, Sweden xHyker Security AB, Sweden Abstract—Intel Software Guard Extensions (SGX) provides a Unfortunately, a relatively large number of flaws and attacks trusted execution environment (TEE) to run code and operate against SGX have been published by researchers over the last sensitive data. SGX provides runtime hardware protection where few years. both code and data are protected even if other code components are malicious. However, recently many attacks targeting SGX have been identified and introduced that can thwart the hardware A. Contribution defence provided by SGX. In this paper we present a survey of all attacks specifically targeting Intel SGX that are known In this paper, we present the first comprehensive review to the authors, to date. We categorized the attacks based on that includes all known attacks specific to SGX, including their implementation details into 7 different categories. We also controlled channel attacks, cache-attacks, speculative execu- look into the available defence mechanisms against identified tion attacks, branch prediction attacks, rogue data cache loads, attacks and categorize the available types of mitigations for each presented attack. microarchitectural data sampling and software-based fault in- jection attacks. For most of the presented attacks, there are countermeasures and mitigations that have been deployed as microcode patches by Intel or that can be employed by the I. INTRODUCTION application developer herself to make the attack more difficult (or impossible) to exploit. -
Bypassing KPTI Using the Speculative Behavior of the SWAPGS Instruction White Paper
White Paper Bypassing KPTI Using the Speculative Behavior of the SWAPGS Instruction White Paper Contents Abstract ___________________________________________________________________________________________________________ 3 Disclaimer _________________________________________________________________________________________________________ 3 Introduction _______________________________________________________________________________________________________ 4 The SWAPGS instruction ___________________________________________________________________________________________ 4 The Exploit ________________________________________________________________________________________________________ 6 Challenges_________________________________________________________________________________________________________ 9 Mitigations _______________________________________________________________________________________________________ 13 Conclusions ______________________________________________________________________________________________________ 14 Glossary __________________________________________________________________________________________________________ 15 Timeline of the discovery__________________________________________________________________________________________ 16 References _______________________________________________________________________________________________________ 18 Authors: Andrei LUȚAȘ ([email protected]), Dan LUȚAȘ ([email protected]) [2] White Paper Abstract Speculative-execution based attacks and side-channels -
Red Hat Product Security Risk Report: 2019
Overview Red Hat Product Security Risk Report: 2019 Introduction The 2019 edition of the Red Hat® Product Security Risk Report is an overview of security vulnerabili- ties that impacted Red Hat products for the 2019 calendar year. We review large and small security vulnerabilities that were publicly announced throughout the year, as well as the data and metrics that were produced for these vulnerabilities across all of our solutions. We also review several high-impact, high-profile security vulnerabilities. By “product,” we mean a Red Hat offering listed at https://access.redhat.com/products. We reviewed vulnerabilities and the severity rating assigned to them by Red Hat, and then looked at which issues were of meaningful risk and which issues were exploited. This report is based on publicly avail- able data and was prepared by a group of security specialists within Red Hat referred to as Red Hat Product Security. Red Hat Product Security assigns a Common Vulnerabilities and Exposures (CVE) name to every security issue we fix. If we fix a general bug that later turns out to have had a secu- rity implication, we go back and assign a CVE name to that issue. Every CVE fixed has an entry in our public database in the Red Hat Customer Portal, as well as a public bug report with more technical detail. In this report, we use “vulnerabilities” and “CVEs” interchangeably. Every vulnerability reported to Red Hat Product Security is reviewed and analyzed by our team of open source security specialists. These specialists are experienced Red Hat engineers who under- stand how our offerings are composed, curated, hardened, packaged, delivered, and used by our customers. -
A Thesis Entitled Design of a Hardware Security PUF Immune To
A Thesis Entitled Design of a Hardware Security PUF Immune to Machine Learning Attacks By Nitin K. Pundir Submitted to the Graduate Faculty as partial fulfillment of the requirements for the Master of Science Degree in Electrical Engineering ________________________________________ Dr. Mohammed Niamat, Committee Chair ________________________________________ Dr. Mansoor Alam, Committee Member ________________________________________ Dr. Hong Wang, Committee Member ________________________________________ Dr. Amanda Bryant-Friedrich, Dean College of Graduate Studies The University of Toledo December 2017 Copyright 2017, Nitin K. Pundir This document is copyrighted material. Under copyright law, no parts of this document may be reproduced without the expressed permission of the author. An Abstract of Design of a Hardware Security PUF Immune to Machine Learning Attacks By Nitin K. Pundir Submitted to the Graduate Faculty as partial fulfillment of the requirements for the Master of Science Degree in Electrical Engineering The University of Toledo December 2017 The technology and cyberspace sector is losing billions each year to hardware security threats. The incidents of usage of counterfeiting chips are doubling each year. The Electronic Resellers Association International (ERAI) reported that in the year 2011 more than 1300 counterfeits were reported. The incidents were double of what were reported in 2008. The report from Federal Contracts acknowledges the threats emanating from counterfeit chips and says it threatens the successful operations of US Weapon Systems. Meanwhile, electronic counterfeiting of chips continues to be a very profitable business on the dark web by crooked operatives. Physical Unclonable Functions (PUFs) are emerging as hardware security primitives to deal with security issues such as cloning, hacking, copying, and detection of Trojans. -
Infrastructure and Primitives for Hardware Security in Integrated Circuits
INFRASTRUCTURE AND PRIMITIVES FOR HARDWARE SECURITY IN INTEGRATED CIRCUITS by ABHISHEK BASAK Submitted in partial fulfillment for the degree of Doctor of Philosophy in Electrical Engineering and Computer Science CASE WESTERN RESERVE UNIVERSITY May 2016 CASE WESTERN RESERVE UNIVERSITY SCHOOL OF GRADUATE STUDIES We hereby approve the dissertation of ABHSIHEK BASAK Candidate for the degree of Doctor of Philosophy Committee Chair Swarup Bhunia Committee Member Frank Merat Committee Member Soumyajit Mandal Committee Member Ming-Chun Huang Committee Member Sandip Ray Date of Defense 03/15/2016 We also certify that any written approval has been obtained for any proprietary material contained therein. To my Family and Friends i Contents List of Tables vi List of Figures viii Abbreviations xii Acknowledgements xiv Abstract xvi 1 Introduction 1 1.1 What are Counterfeit ICs? . 3 1.2 Related Work on Countermeasures against Counterfeit ICs . 6 1.3 Major Contributions of Research (Part I) . 8 1.4 System-on-Chip (SoC) Security . 11 1.4.1 Background on SoC Security Policies . 13 1.4.2 Issues with Current SoC Design Trends . 15 1.4.3 Related Work . 17 1.5 Major Contributions of Research (Part II) . 18 1.6 Organization of Thesis . 21 2 Antifuse based Active Protection against Counterfeit ICs 22 2.1 C-Lock Methodology . 23 2.1.1 Business Model . 25 2.1.2 Pin Lock Structure . 26 2.1.3 Lock Insertion in I/O Port Circuitry . 27 2.1.4 Programming the Key . 28 2.1.5 Design Circuitry for Chip Unlocking . 29 2.1.5.1 Lock/Unlock Controller State Transitions . -
Is Hardware More Secure Than Software?
Is Hardware More Secure than Software? Lianying Zhao Carleton University David Lie University of Toronto Abstract—Computer hardware is usually perceived as more secure than software. However, recent trends lead us to reexamine this belief. We draw attention to the “firmwarization” of hardware and argue for revisiting the role of hardware and software in systems security. TRADITIONALLY, computer systems can be quick search on Google Scholar returns at least thought of as composed of two types of compo- 1,750 academic papers with the title containing nents: hardware and software. Hardware refers to both “hardware” and “security” as of the time the physical components that perform a fixed set of writing. While this is a conservative under- of operations. Software on the other hand, defines approximation of the actual number of such pa- logical components, instantiated as data and in- pers (as it only checks the title), and regardless structions, which can specify arbitrary sequences of whether these papers propose a larger role of hardware operations, as well as inputs to those of hardware in security, or seek to examine the operations. A function can be implemented using vulnerability of hardware to security attacks, the a various mixes of hardware and software compo- sheer number informally illustrates that the se- nents (or even entirely in hardware). The mix of curity community has a strong interest in the hardware and software can have implications on relationship between computer hardware and se- certain properties of the function implementation curity. Another recent trend is the implementation (e.g., performance or security). of hardware mechanisms to address well-known Hardware Security. -
Introduction to Hardware Security
Electronics 2015, 4, 763-784; doi:10.3390/electronics4040763 OPEN ACCESS electronics ISSN 2079-9292 www.mdpi.com/journal/electronics Review Introduction to Hardware Security Yier Jin Department of Electrical Engineering and Computer Science, University of Central Florida, Orlando, FL 32765, USA; E-Mail: [email protected]; Tel.: +1-407-823-5321; Fax: +1-407-823-5835 Academic Editor: Dhananjay S. Phatak Received: 3 August 2015 / Accepted: 5 October 2015 / Published: 13 October 2015 Abstract: Hardware security has become a hot topic recently with more and more researchers from related research domains joining this area. However, the understanding of hardware security is often mixed with cybersecurity and cryptography, especially cryptographic hardware. For the same reason, the research scope of hardware security has never been clearly defined. To help researchers who have recently joined in this area better understand the challenges and tasks within the hardware security domain and to help both academia and industry investigate countermeasures and solutions to solve hardware security problems, we will introduce the key concepts of hardware security as well as its relations to related research topics in this survey paper. Emerging hardware security topics will also be clearly depicted through which the future trend will be elaborated, making this survey paper a good reference for the continuing research efforts in this area. Keywords: hardware security; hardware trojan; proof-carrying hardware; trusted hardware platform 1. Introduction Hardware has long been viewed as a trusted party supporting the whole computer system and is often treated as an abstract layer running instructions passed from the software layer. -
Design and Implementation of the Ascend Secure Processor
204 IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING, VOL. 16, NO. 2, MARCH/APRIL 2019 Design and Implementation of the Ascend Secure Processor Ling Ren , Christopher W. Fletcher, Albert Kwon, Marten van Dijk, and Srinivas Devadas Abstract—This paper presents post-silicon results for the Ascend secure processor, taped out in a 32 nm SOI process. Ascend prevents information leakage over a processor’s digital I/O pins—in particular, the processor’s requests to external memory—and certifies the program’s execution by verifying the integrity of the external memory. In secure processor design, encrypting main memory is not sufficient for security because where and when memory is accessed reveals secret information. To this end, Ascend is equipped with a hardware Oblivious RAM (ORAM) controller, which obfuscates the address bus by reshuffling memory as it is accessed. To our knowledge, Ascend is the first prototyping of ORAM in custom silicon. Ascend has also been carefully engineered to ensure its timing behaviors are independent of user private data. In 32 nm silicon, all security components combined (the ORAM controller, which includes 12 AES rounds and one SHA-3 hash unit) impose a moderate area overhead of 0.51 mm2. Post tape-out, the security components of the Ascend chip have been successfully tested at 857 MHz and 1.1 V,at which point they consume 299 mW of power. Index Terms—Computation outsourcing, secure processors, oblivious RAM, integrity verification, ASIC design Ç 1INTRODUCTION S embedded and mobile devices become ubiquitous, protects the user’s private data while it is being computed Ausers have become more computationally limited and upon. -
Transient-Execution Attacks and Defenses
Transient-Execution Attacks and Defenses Habilitation by Daniel Gruss June 2020 Daniel Gruss Transient-Execution Attacks and Defenses (Part I only) Habilitation June 2020 Institute for Applied Information Processing and Communications Graz University of Technology SCIENCE PASSION TECHNOLOGY Abstract The complexity of modern computer systems has dramatically increased over the past decades and continues to increase. The common solution to construct such complex systems is the divide-and-conquer strategy, dividing a complex system into smaller and less complex systems or system components. For a small system component, the complexity of the full system is hidden behind abstraction layers, allowing to develop, improve, and reason about it. As computers have become ubiquitous, so has computer security, which is now present in all aspects of our lives. One fundamental problem of security stems from the strategy that allowed building and maintaining complex systems: the isolated view of system components. Security problems often arise when abstractions are imperfect or incomplete, which they inherently need to be to hide complexity. In this habilitation, we focus on a very specific type of computer security problem, where an imperfect abstraction of the hardware can be observed from the software layer. The abstraction of the hardware, i.e., the defined hardware interface, is often called the \architecture". In contrast, the concrete implementation of the hardware interface, is called the \microar- chitecture". Architecture and microarchitecture often deviate enough to introduce software-exploitable behavior. This entirely new field of research, called \Transient-Execution Attacks", has not existed before our seminal works in 2018. Transient-execution attacks exploit that the hardware transiently performs operations it should not perform, in one of two cases: In one case deliberately (non-speculatively), as the operations will be architecturally discarded anyway.