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Research Article Volume 7 Issue No.3 Design of High Performance Full using FinFET D.Veena Sushmita1, B. Hemanth Nag2, S. Divya3, P. Santosh Kumar4 Department of and Communication Engineering LIET, Jonnada, JNTUK, India

Abstract: In this paper, a full subtractor is designed using different methods. In VLSI, a digital circuit can be designed with various techniques. And most popular techniques are CMOS, gate diffusion input (GDI), transmission gates (TG), complementary pass transistor logic(CPL), floating-gate MOS(FGMOS) and FinFET. As low power consumption has become one of the major requirements in design of digital VLSI circuits in recent years. So we prefer a circuit which have minimum number of transist ors with good performance, less power consumption, less propagation delay and fast switching. This paper presents a design of full subtractor using FinFET technique whose performance has been compared with full subtractor circuit employing CMOS, TG, CPL, GDI and FGMOS. It has been observed that the FinFET based full subtractor uses minimum number of transistors while consuming least power(1.75u), with lowest propagation delay(30s) in comparison to CMOS, TG, CPL, GDI and FGMOS based full subtractor available in literature, thus suitable for swift miniaturized applications.

Index Terms: Full subtractor, CMOS, TG, CPL, GDI, FGMOS, FINFET.

1. INTRODUCTION of full subtractor is shown in below table.

Due to the development of technology, it has become essential to Table. 1. Truth table of full subtractor. have a chip which requires minimum power, less power delay A B C Diff Borrow with efficient output. In this paper we tried to improve the logic 0 0 0 0 0 circuit design in terms of delay, average power, peak power, 0 0 1 1 1 power dissipation product. Various techniques used are FGMOS, 0 1 0 1 1 CMOS, CPL, TG, GDI, FINFET. All these techniques have their own advantages. For performing arithmetic operations in digital 0 1 1 0 1 circuits one of the basic unit is full subtractor. A full subtractor is 1 0 0 1 0 mostly used in . Due to the increase of 1 0 1 0 0 complexity on a chip the area and power consumption of the chip 1 1 0 0 0 gets increases. As the power consumption increases the 1 1 1 1 1 temperature on the chip increases which further changes the characteristics of the chip. In this paper we have designed a full subtractor using FinFET which consumes less power. FinFET (Fin shaped FET) is a field effect transistor(FET) device structure and method for forming FETs scaled semiconductor devices. A FinFET is fabricated in a silicon layer overlying an insulating layer with the device extending from insulting layer as a fin. In order to provide enhanced drive current and effectively suppressed short channel effects, double gates are provided over the sides of the channel in FinFET.

2. FULL SUBTRACTOR

A full subtractor is a combinational circuit which performs subtraction between three : A(minuend), B(subtrahend) and C (borrow in). Difference and borrow are the outputs of full subtractor. Here we have analysed the full subtractor using NOT gate, AND gate, and XOR gate. Full subtractor is designed by combining two half . Full subtractor circuit diagram using gates is shown in the figure 1. 3. FULL SUBTRACTOR USING CMOS

Complementary metal-oxide-semiconductor abbreviated as CMOS\\ is a technology for constructing integrated circuits. CMOS technology is widely used for several analog circuits such as data convertors, image sensors and Figure.1 . Full subtractor highly integrated transceivers. CMOS uses symmetrical and

International Journal of Engineering Science and Computing, March 2017 5885 http://ijesc.org/ complementary pairs of n-type and p-type metal oxide of full subtractor using Transmission gate is shown in figure semiconductor field effect transistor (MOSFETs) for logic 4. functions. PMOS gets on when the input is low (0) and NMOS gets on when the input is high (1). High noise immunity and low static power consumption are the two important characteristics of CMOS devices. Heat dissipation is low in CMOS circuits when compared to other forms of logic circuits. The circuit diagram of full subtractor using CMOS is shown in figure 2.

Figure.4. circuit diagram

5. FULL S UBTRACTOR USING CPL

The complex logics can be alternatively implemented using CPL (complementary pass transistor logic). CPL is extremely fast and efficient. Some of the examples of CPL circuits are shown in figure 5. Figure.2 .Subtractor using CMOS is shown in figure

4. FULL SUBTRACTOR USING TG

A Transmission gate (TG) is also called as pass gate. It is a bi-directional which is a parallel combination of NMOS and PMOS. A control signal input is given to the gate of NMOS and its compliment is given to the gate of PMOS. The schematic representation of transmission gate is shown in figure 3. Figure.4. CPL circuits

By eliminating the redundant transistors, it reduces the count of transistors used to make different logic gates. In order to pass logic levels between nodes of a circuit the transistors are used as . The main principle involved in CPL is the use of NMOS pass transistor for logic organisation and elimination of the PMOS latch. The circuit diagram of full subtractor using CPL is shown in figure 6.

Figure.3. Trans mission Gate

The voltage applied to the gate-source of NMOS is always negative and for the PMOS is always positive. Accordingly, neither of the two transistors will conduct and the transmission gate turns off. Complex gates can be Figure.6. eliminating the redundant transistors implemented using TG instead of traditional CMOS pull-up and pull-down networks. The problem of reduced noise 6.FULL S UBTRACTOR US ING GDI margin, increased switching resistance and increased static power dissipation can be avoided by the combination of both GDI(gate diffusion input) is a technique of low power digital PMOS and NMOS in Transmission gate. The circuit diagram circuit design which reduces power consumption, delay and

International Journal of Engineering Science and Computing, March 2017 5886 http://ijesc.org/ area. It is based on the use of a simple cell as shown in figure circuit diagram of full subtractor using FGMOS is shown in 7. It is similar to that of CMOS invertor but there are some figure 9. differences:GDI cell contains three inputs. They are G(common gate input of NMOS and PMOS), P(input to the source/drain of PMOS) and N(input to the source/drain of NMOS).

Figure.9. circuit diagram of full subtractor using FGMOS

8.FULL S UBTRACTOR USING FINFET

A finFET is a type of multi-gate metal oxide semiconductor Figure.7. drain of NMOS field effect transistor(MOSFET). FinFETs are multi-gate devices, and the two gates can be shorted the shorted two gates GDI technique allows implementation of a wide range of is named as shorted gate(SG) mode. A multi-gate transistor complex logic functions using only two transistors. This integrates more than one gate into one single device. The term method produces designs which are fast with low power FinFET is used somewhat generally. Sometimes it is used to dissipation by using less number of transistors. The circuit describe any fin-based multi-gate transistor architechture diagram of full subtractor using GDI technique is shown in despite number of gates. FinFETs operates at lower voltages figure 8. because of their lower threshold voltages. The static leakage current characteristically reduces upto 90%. These devices provide much lower power consumption which allows high integration levels. The excellent control of short channel effects and the ability to tune the performance for energy efficiency are the attractive features of FinFET technology. The circuit diagram of full subtractor using FinFET is shown in figure 10.

Figure.8. subtractor using GDI technique

7.FULL S UBTRACTOR USING FGMOS

The structure of Floating gate MOSFET (FGMOS) is similar to that of conventional MOSFET. Due to the unique feature of threshold voltage tunability these MOSFETs are proposed for the design of low voltage and low power applications both in analog and digital circuits. This technique provides reduced circuit complexity and threshold voltage programmability. FGMOS can be operated below the conventional threshold voltage of MOSFET leading to wider output signal swing at low supply voltage. It dissipates less power as compared to other logic devices. Floating gate MOSFETs have an ability to store an electrical charge for extended periods of time so that Figure10. full subtractor using FinFET they are used without any connection to a power supply. The

Table.2. Performance comparision of full subtractor is shown in table2 Technology Average power Delay(ps) Pdp

CMOS 462.8935u 141.01122 4243e-15 TG 228.0990u 242.9831 357.792e-15 CPL 613.8663u 469.1079 61843e-15 GDI 412.1726u 238.8733 14860e-15 FGInMOS 10.4409m 35.8237 728.4e-15

FINFET 1.75u 30s 52.5u

International Journal of Engineering Science and Computing, March 2017 5887 http://ijesc.org/ 9.CONCLUSION [11]. A. Morgenshtein, V. Yuzhaninov, A. Kovshilovsky, A. Fish, Full-swing gate diffusion input logic-case-study of low- In this paper, we have designed an efficient low power high power CLA design, Integr. VLSI J. 47 (2014) 62–70. speed full subtractor using FinFETs and campared its performance with other full subtractor designs.It has been found [12]. Naveen Balaji,V.Aathira,K.Ambhikavathi,S.Geeth iga, that the proposed FinFET based full subtractor cosumes least R.Havin, Cominational circuits using transmission gate logic for power (1.75u) amongstCMOS (462.893u),TG(228.0990u), CPL power optimization(2016). (613.8663u),GDI(412.1726u), FGMOS (10.4409m).The power delay product for FinFET based full subtractor has been found to [13].A. K. Nishad and R. Chandel, "Analysis of Low Power be (52.5e-6) and followed by CMOS(4243e-15),TG(357.792e- High Performance XOR Gate Using GDI Technique," in 15), GDI(14860e-15),CPL(61843e-15), FGMOS(728.4e-15). Computational Intelligence and Communication Networks Therefore, the presented FinFET based full subtractor cicruit (CICN), 2011 International Conference on, 2011, pp. 187-191. consumes less power exhibiting high operating speed.Thus, FinFET can be used to design high performance digital [14].T.Nagateja,T.Venkatarao,Avireni srinivasulu,Voltage,High integrated circuits suitable for high speed and low power speed FinFET based 1- BPL-PT Full adder IEEE(2015). applications. [15]. Shivani Sharma ,Gaurav soni,Comaprision analysis of 10. REFERENCES FinFET based 1-BIT Full adder cell Implemented using different logic styles At 10,22 and 32NM. [1]. A.P. Chandrakasan, R.W. Brodersen, Minimizing power consumption in digital CMOS circuits, Proc. IEEE 83 (1995) 498–523.

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