Viability of Ka-Band Solid-State Power Amplifiers
For High-Rate Data Transmission
In Space Communications
A thesis presented to
the Graduate School
of the University of Cincinnati
in partial fulfillment
of the requirements for the degree
Master of Science
in the School of Electrical Engineering and Computer Science
of the College of Engineering and Applied Science
Christopher A. Drummond
B.S. Ohio University
October 2019
Committee Chair: Dr. Altan Ferendeci
Abstract
The United States launches over 20 space vehicles every year. Each vehicle has an important mission to which large amounts of money have been allocated in order to support the growth of the ever-changing country and world as we move into the future. Earth science data gathered by satellites is transmitted down to Earth, and probes and rovers are sent out into our solar system to gather data about our solar system which must be transmitted back as well since these vehicles are generally expected to remain out in space forever. Sensors and other data- gathering devices are more capable now than ever of generating huge amounts of data, and it must be transmitted back to Earth at high rates with few errors.
The primary focus of the research performed here was to investigate the viability of Ka- band solid-state power amplifiers for use in future space programs as replacements for travelling- wave-tube amplifiers, as well as determining optimal design techniques to fit current flight-ready technology. The research was performed as part of an Internal Research and Development
(IRAD) project for L3 Technologies Cincinnati Electronics (L3 CE hereafter), which is a world- leading space communications developer. Many gain lineups were designed and simulated so that the best one could be built into a prototype. Simulations for the circuitry and microwave structures were performed in AWR Microwave Office and the best design was built and tested.
The amplifier prototype was built to maximize the power efficiency and transmit bandwidth so that high-rate modulated data could be transmitted without error and without consuming too much power or generating too much excessive heat to be managed by satellite systems. A battery of typical flight-readiness tests was performed on the prototype. Afterwards, analysis of the data gathered was performed in order to illuminate the discrepancies between the simulated data and the measured data.
The research demonstrated that Ka-band solid-state power amplifiers are indeed viable replacements for travelling-wave-tube amplifiers for high-rate data transmission. The power amplifier produced more than 10 watts across the bandwidth of interest. The transmit bandwidth of the prototype exceeded 1.5 GHz at a power-added efficiency (PAE) of 27.1% which is enormously beneficial for the efficient transmission of huge amounts of data. With that bandwidth and efficiency (and improvements on them in the future), flight-ready hardware will be capable of transmitting data at rates far exceeding 1 Gbps. There is now a viable argument to be made by space communication companies about the benefits of using solid-state power amplifiers over travelling-wave-tube amplifier for very high data rate transmission.
Acknowledgements
I am very thankful for all the people around me who were willing to support my efforts in this research. I thank my parents for creating the opportunity for me to pursue advanced education and the University of Cincinnati for fostering an environment for me to succeed.
I would like to thank Dr. Chris G. Bartone, my undergraduate advisor from Ohio
University. Without his guidance, I probably never would have pursued graduate studies in RF and never would have seen the benefits of knowledge, skill, and perseverance fostered by advanced education. Without him recognizing my talents and sponsoring me in my efforts, I never would have made it to where I am today. I would also like to thank Dr. Marc Cahay, the department chair of the school of Electrical Engineering and Computer Science at the University of Cincinnati College of Engineering and Applied Science. His gracious allowance for me to continue my graduate studies after the roughest times of my life nearly caused me to quit was a blessing and without it I would never have overcome the adversity presented to me in life to achieve the degree Master of Science.
I would like to thank many people at Cincinnati Electronics as well. Firstly, I thank Dr.
Bob Hayes, the fromer Director of Advanced Programs in charge of the IRAD project from which this thesis grew. Without his support, I likely would have forgone graduate study and research and never would have had the opportunity to contribute to space programs in this way. I would also like to thank Jim Lundt, my direct manager. His experience in the design, simulation, build, and implementation of RF systems made him a perfect mentor for me. Without his advice, my design may have never succeeded and I may never have finished this degree. I’d also like to thank the entire senior management team at L3 for making it possible to continue education after beginning full-time work and allowing the use of in-house equipment which allowed the full testing of this project to be performed at frequencies beyond the capabilities of the equipment at the University of Cincinnati. Cincinnati Electronics encourages all employees to reach for the stars in education, knowledge, and skill, and I can’t thank them enough for creating an environment which sets up so many to succeed.
Table of Contents
Abstract ...... 2 Acknowledgements ...... 5 Table of Contents ...... 7 Table of Figures ...... 8 Chapter 1: Introduction ...... 11 Background ...... 11 High-Frequency Data Links ...... 12 Replacing Travelling Wave Tube Amplifiers ...... 14 Methodology ...... 17 Chapter 2: Space-Qualifiable Ka-band Components ...... 20 Component Spaceflight Capability ...... 20 Space Environmental Effects ...... 21 Radiation Sources and Effects in Space...... 23 Radiation Effects on Electronic Components and Mitigation Techniques ...... 24 Support Component Selection ...... 26 Amplifier Devices ...... 28 Chapter 3: Analytical Design ...... 30 Concept of Operation ...... 30 Basic Power Amplifier Design and Background...... 35 Transmission Lines ...... 37 Ring Coupler Design and Analysis ...... 43 Final Amplifier Design ...... 47 Driver Amplifier Design ...... 49 Amplifier Stability ...... 51 Chapter 4: Software-Based Simulation and Data ...... 55 Scope ...... 55 Driver Amplifier Subassembly Simulation ...... 56 Final Amplifier Subassembly Simulation ...... 64 Top-Level Amplifier Simulation ...... 71 Chapter 5: Prototype Testing and Data ...... 74 Driver Amplifier Subassembly Measured Performance ...... 75 Final Amplifier Subassembly Measured Performance ...... 94 Full-System Measured Performance ...... 101 Chapter 6: Test Data Analysis and Comparison ...... 106 Scope ...... 106 Driver Amplifier Subassembly Comparison ...... 106 Final Amplifier Subassembly Comparison ...... 114 Top-Level Comparison ...... 118 Chapter 7: Conclusion ...... 121 References ...... 123 Table of Figures
Figure 1: Combination Loss Due to Relative Phase Shifts Up To 90 Degrees ...... 33 Figure 2 Ka-band Power Amplifier Concept of Operation ...... 34 Figure 3: Zc vs U = W/H for a Microstrip Line on RT 5880 ...... 40 Figure 4: εre vs U = W/H for a 50 Ω Microstrip Line on RT 5880...... 41 Figure 5: General Ring Coupler Design - Pozar’s Microwave Engineering 4th Edition ...... 44 Figure 6: Hatch and Williams Curve for Parallel RF Structures9 ...... 46 Figure 7: Final Amplifier Ring Coupler Gap ...... 47 Figure 8: Final Amplifier Layout ...... 49 Figure 9: Final Amplifier 3D Scale Rendering...... 49 Figure 10: Driver Amplifier Board Layout ...... 51 Figure 11: Driver Amplifier 3D Scale Rendering ...... 51 Figure 12 Driver Amplifier Subassembly Stability Over Frequency ...... 54 Figure 13 Final Amplifier Subassembly Stability Over Frequency ...... 54 Figure 14: Driver Amplifier Input Stage Electromagnetic Simulation Structure ...... 56 Figure 15: Driver Amplifier Input Stage Simulated S-Parameters ...... 57 Figure 16: Driver Amplifier Interstage Electromagnetic Simulation Structure ...... 58 Figure 17: Driver Amplifier Interstage Simulated S-Parameters ...... 59 Figure 18: Driver Amplifier Output Stage Electromagnetic Simulation Structure ...... 60 Figure 19: Driver Amplifier Output Stage Simulated S-Parameters ...... 61 Figure 20: Driver Amplifier Subassembly Simulated S-Parameters ...... 63 Figure 21: Final Amplifier Input Stage Electromagnetic Simulation Structure ...... 64 Figure 22: Final Amplifier Input Stage Simulated S-Parameters ...... 65 Figure 23: Final Amplifier Output Stage Electromagnetic Simulation Structure ...... 67 Figure 24: Final Amplifier Output Stage Simulated S-Parameters ...... 68 Figure 25: Final Amplifier Subassembly Simulated S-Parameters ...... 70 Figure 26: Full Power Amplifier Module Simulated S-Parameters ...... 72 Figure 27: Full Power Amplifier Module Simulated S-Parameters ...... 73 Figure 28: Power Amplifier Subassemblies Mounted on Heat Sinks ...... 74 Figure 29: Power Amplifier Test Setup ...... 75 Figure 30: Driver Amplifier Subassembly Measured Input Return Loss at J1 ...... 77 Figure 31: Driver Amplifier Subassembly Measured Output Return Loss at J2 ...... 78 Figure 32: Driver Amplifier Subassembly Measured Output Return Loss at J3 ...... 79 Figure 33: Driver Amplifier Subassembly Measured Output Return Loss at J4 ...... 80 Figure 34: Driver Amplifier Subassembly Measured J2-J3 Isolation ...... 81 Figure 35: Driver Amplifier Subassembly Measured Gain at J2 Output ...... 83 Figure 36: Driver Amplifier Subassembly Measured Gain At J3 ...... 84 Figure 37: Driver Amplifier Subassembly Measured Gain Comparison J2-J3 ...... 85 Figure 38: Driver Amplifier Subassembly Measured Gain Differential J2-J3 ...... 86 Figure 39: Driver Amplifier Subassembly Measured Output Phase Differential J2-J3 ...... 88 Figure 40: Driver Amplifier Measured Compression at J2 ...... 90 Figure 41: Driver Amplifier Measured Compression at J3 ...... 91 Figure 42: Driver Amplifier Subassembly Measured AM/PM at J2 ...... 92 Figure 43: Driver Amplifier Subassembly Measured AM/PM at J3 ...... 93 Figure 44: Final Amplifier Subassembly Measured Input Return Loss at J1 ...... 95 Figure 45: Final Amplifier Subassembly Measured Input Return Loss at J2 ...... 96 Figure 46: Final Amplifier Subassembly Measured Output Return Loss at J3 ...... 98 Figure 47: Final Amplifier Subassembly Measured Output Return Loss at J4 ...... 99 Figure 48: Final Amplifier Subassembly Measured J3-J4 Isolation ...... 100 Figure 49: Full Power Amplifier Measured System Gain ...... 102 Figure 50: Full Power Amplifier Measured System Phase-Nonlinearity ...... 104 Figure 51: Driver Amplifier Simulated vs Measured Input Return Loss at J1 ...... 107 Figure 52: Driver Amplifier Simulated vs Measured Output Return Loss at J2 ...... 108 Figure 53: Driver Amplifier Simulated vs Measured Output Return Loss at J3 ...... 109 Figure 54: Driver Amplifier Simulated vs Measured Output Return Loss at J4 ...... 110 Figure 55: Driver Amplifier Simulated vs Measured Gain at J2 ...... 111 Figure 56: Driver Amplifier Simulated vs Measured Gain at J3 ...... 112 Figure 57: Driver Amplifier Simulated vs Measured J2-J3 Isolation ...... 113 Figure 58: Final Amplifier Measured vs Simulated Input Return Loss at J1 ...... 114 Figure 59: Final Amplifier Measured vs Simulated Input Return Loss at J2 ...... 115 Figure 60: Final Amplifier Measured vs Simulated Output Return Loss at J3...... 116 Figure 61: Final Amplifier Measured vs Simulated Output Return Loss at J4...... 117 Figure 62: Final Amplifier Measured vs Simulated J3-J4 Isolation ...... 118 Figure 63: Full Power Amplifier Module Measured vs Simulated System Gain ...... 119
Chapter 1: Introduction
Background
In space communications, carrier signals in many frequency bands are commonly used to transmit low- and high- rate data effectively. Naturally, higher frequency carrier signals have more bandwidth to spare for modulated data, and so, at those frequencies we can achieve higher data rates than at lower frequencies. In particular, the maximum data rate (measured in symbols per second) achievable for a signal is twice the signal bandwidth, according to the Nyquist criterion:
1 푇 = 2퐵 where T = symbol period (the reciprocal of the data rate) and B = transmit bandwidth.
Obviously, as the transmit bandwidth of the channel increases, the required period for each encoded data symbol decreases. The Nyquist criterion holds true irrespective of modulation scheme; while more information can be transmitted with a greater library of symbols which represent more and more bits each, the total number of symbols transmitted in a time frame is limited by the Nyquist criterion. Attempting to exceed the Nyquist criterion results in aliasing which causes numerous bit errors, effectively rendering the data useless.
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In today’s world, communications systems are being forced into higher frequency bands than they have been in the past due to the growing capability to generate large amounts of data.
Huge amounts of earth science data are collected by satellites in orbit and exploration vehicles and the data is sent over extremely great distances with limited supplies of energy; efficiency and transmit power are an absolute premium if we wish to gather the science data of our solar system and beyond. Our daily lives are also directly affected by quality transmission from satellites; television, cellular service, GPS, and especially internet, are all often transmitted down to earth from satellite constellations and internet in particular has extreme bandwidth requirements for the amount of data being sent down.
The bandwidth of radio-frequency (RF) channels plays a significant role in the achievable modulated data rate the data link can put through. Quick transmission of large amounts of data with low errors is solved by the higher frequency carriers, but there are major challenges that must be addressed in order to actually use higher-frequency data links in spaceflight applications.
Efficiency and heat generation are both serious problems with space communications; as the bulk of the power consumed in a typical data link is used by the power amplifier, having efficient power amplifiers in such applications is an absolute must moving forward.
High-Frequency Data Links
In old space missions, mission data was transmitted back to earth at very slow rates compared to what is possible today. The ability of sensors and other data-gathering devices to generate data has long since exceeded the ability of L-band and S-band links to successfully
12 carry these data back to Earth. Currently, the majority of science data gathered by satellites sent to Earth on high-rate data links is carried in X-band frequencies. There are so many satellites that use X-band carriers that there is very little room left in the X-band to carry mission data; so, the push for higher frequency bands to alleviate the crowding in X-band as well as open up bandwidth for very high data rates has been a need for several years. K-band is widely ignored because the absorption spectrum of water peaks around 22.24 GHz (which is right in the middle of K-band). Ku-band is used quite often in satellite internet, satellite television (and other broadcasting), and radar, and the unused bandwidth is small enough that it makes more sense to aim at higher bands for a growing space program. So, Ka-band (27-40 GHz) is the next frequency band of interest for high-rate data transmission in the near future. One day, major strides will be taken to extend communications into V-band (40-75 GHz) and beyond, but we must make progress in Ka-band before attempting to develop high-reliability systems in even higher frequency ranges.
Ka-band offers much to us that other frequency bands cannot. Lower frequency bands suffer from bandwidth constraints. All high frequency bands have more room to transmit data; the need to be very efficient with bandwidth is far less pressing than at lower frequencies. It is expensive and difficult to produce high-reliability, high-density modulation schemes that have extremely low bit-error rates, so whenever it is possible to use simpler modulation schemes it is cheaper, more reliable, and easier. Historically, at high frequencies, TWTAs and waveguides were essentially the only method of transmission in the RF chain. Today it is possible to build an
SSPA at Ka-band that has the power to overcome some line loss between the SSPA and the antenna.
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Replacing Travelling Wave Tube Amplifiers
Historically, power amplifiers in space applications (and terrestrial, for that matter) have most often been travelling-wave-tube amplifiers (TWTAs) as opposed to solid-state power amplifiers (SSPAs). TWTAs utilize the varying RF field to modulate an accelerated electron beam across an extremely large potential difference; the constant current for a given bias voltage and input power results in a constant (and often very large) output power. TWTAs have several distinct advantages over SSPAs. Their gain and output power can be exceptionally high for single devices and they are generally more efficient than SSPAs. They typically produce less heat than SSPAs for a given power level and are also substantially less susceptible to overdrive conditions than solid-state devices; overdriving a solid-state device will puncture the transistor gates and destroy the device whereas TWTAs will simply be unable to generate the additional current to keep up with the drive level. However, they have noticeable warm-up times which prevent immediate amplifier function and, perhaps most importantly, have a much shorter usable life than SSPAs. TWTAs, eventually, will burn out and have to be replaced and that is a major concern for long mission lifetimes in space where replacement is impossible. In addition,
TWTAs are far less durable than solid-state devices as the materials used to build them are more fragile and likely to break under mechanical shock, vibration, or high temperature variations. The extra bulk in TWTAs, which is required for the size of the TWT itself, stabilizing the components, heat management, and containing the large power supply, make TWTAs rather large compared to SSPAs which is never an advantage on a mission where space is limited.
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Solid-state devices were once less reliable than TWTAs for satellite communications, as
Strauss detailed in 1994.1 However, in the last twenty years (and especially in the last several),
SSPAs have become more efficient, more powerful, smaller, and less costly than ever before.
Their extremely high reliability is their strongest asset; operating a solid-state device within its manufacturer-specified operating conditions renders a mean time to failure exceeding a billion hours (often by orders of magnitude). While they aren’t nearly as powerful as TWTAs can be, they are capable of more than enough output power for satellite communications and, when paired with sufficiently-high-gain antennas, can useful in space beyond Earth orbit where
TWTAs would usually dominate due to their power capabilities. And so, this research and thesis are part of an effort to further develop high-power, efficient solid-state power amplifiers in high- frequency bands for use in spaceflight communications.
The amplifier developed in this research must demonstrate the potential to replace a
TWTA on a satellite mission which essentially comes down to the SSPA having sufficient output power to transmit effectively to earth while maintaining the efficiency and gain flatness over the transmit bandwidth required to transmit the data from the spacecraft. For a given mission, the advantages and disadvantages of TWTAs vs SSPAS have to be weighed. Considering every advantage and disadvantage can take a lot of time. In general, the advantages the SSPAs have outweigh the advantages of the TWTA only if the SSPA can still meet the other requirements for the mission. True, TWTAs are often a safe bet and sacrifices are made on the spacecraft, but if the SSPA can still meet the requirements for data transmission, it’s usually the better choice due to its lower failure probability and smaller size/greater modularity.
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To evaluate whether the SSPA can adequately perform the required tasks (and thus replace a TWTA), we must examine where the SSPA has disadvantages compared to the TWTA.
As mentioned above, the bandwidth and output power of the SSPA are less than the TWTA and the gain flatness is generally better for a TWTA. These are the most critical parameters which could limit the viability of an SSPA. Bandwidth is unlikely to actually be an issue; solid-state
Ka-band devices generally have an appreciable fractional bandwidth (usually over 10% which is several GHz wide); this is enough for tremendous data rates to be achieved and thus it is unlikely that bandwidth of SSPAs will limit their viability despite TWTAs having much wider bandwidth.
Gain flatness can be a concern; the 3-dB bandwidth is likely wide enough but gain variation across this bandwidth may distort signals. Solid-state devices usually don’t have a tremendous amount of gain variation inside the 3-dB bandwidth, but for any device that has them there are mitigation techniques. Digital modulation schemes and adding pre-distortion are simply a matter of including the appropriate firmware without requiring much in terms of additional hardware.
Filtering options also exist which can eliminate undesired gain characteristics, and these filters are usually tunable to account for device-specific variances.
Finally, output power is a major concern. In general, a satellite’s transmitting antenna has sufficient directivity that very high power isn’t necessary for mission success. At lower frequencies, a power amplifier that can put out 10-20 Watts is usually sufficient to ensure satellite mission success. At higher frequencies, it is harder to produce power but also less transmit power is generally needed. A given antenna dimension will have higher directivity at higher frequencies which makes up for a lack of power. Using the 10-20W figure as a benchmark, the SSPA developed during this research was designed with an end-of-life output
16 power target of 10W. A power amplifier that can put out 10W across 1.5 GHz of bandwidth (5% fractional bandwidth) at Ka-band is sure to perform the required function on a spacecraft and, when installed into a transmitter, reduces overall communication system cost and size.
Methodology
The beginning part of the research was to find Ka-band components that are operable in space. Flight-ready parts are expensive because they are produced in low with long lead times and must be capable of surviving the harsh environment of space. The goal was not to build an already-flight-ready power amplifier, but to develop a proof-of-concept unit which represents potential future investment. In order to avoid the costs of using parts which are already space- qualified or qualifying parts which aren’t qualified, NEPP Grade 4 parts were used. A design that operates in Ka-band frequencies would naturally be implemented on a low-dielectric-constant, low-loss substrate material. Because of the high operating frequency, a thinner substrate will perform better than a thicker one because thicker substrates allow multimode propagation more easily than thinner. The primary characteristics which govern the choice of substrate are the dielectric constant εr (or relative permittivity), substrate thickness, and the material loss tangent.
After parts are selected, focus shifted to what type of amplifier would actually be designed and why that type would be selected. Because of the limitations of available parts, the
+40 dBm (10 W) output power goal requires more than one final device be used in combination.
As is standard practice, this power amplifier was designed to match a 50-ohm source impedance and a 50-ohm load impedance. The basic design process involved transmission line design and
17 matching, stability analysis, and gain budgeting. Other concerns which apply to this power amplifier design are specific to the space environment such as corona and multipaction (which are ionization breakdown phenomena) which do not exist in industries that do not operate in vacuum. These details are expounded in Chapter 3.
As part of the design process, every part of this system that could be simulated was simulated in AWR Microwave Office. When the gain lineup was determined, board design and simulation began. In the end, full electromagnetic simulations (section-by-section) of the driver amplifier and the final amplifier were performed and data was taken to compare to the data produced by the eventual build. Each electromagnetic structure in each subassembly was simulated with a high-density mesh with AWR and s-parameter files of each subsystem were generated and plots of the simulations were taken in multiple configurations. Adjustments and tuning were done where necessary to determine the optimum build condition. The software- based simulation process and data analysis will be further detailed in Chapter 4. Chapters 5 and
6, respectively, detail the testing and collected data as well as the analytical comparison of the measured performance with the simulated performance.
Power amplifier performance is dependent on many things. Data transmission quality is affected not only by the amplifier’s characteristics but also on the modulation scheme, encoding, input signal-to-noise ratio, and other factors. However, it is possible to determine with a high degree of confidence the important characteristics of a power amplifier without putting modulated data through it. So, the majority of the testing was able to be performed on a network
18 analyzer utilizing different calibrations, sweep parameters, drive levels, and data formatting. The measurements which best reflect the performance of a power amplifier are as follows:
• Input and output impedance match/return loss
• Power consumption and dissipation
• Output power and gain linearity
• System gain/gain flatness over frequency
• AM/PM (phase modulation as a result of changing amplitude)
• Phase-nonlinearity (the change in signal phase over frequency relative to ideal phase)
• Gain and phase balance (for split output and input devices)
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Chapter 2: Space-Qualifiable Ka-band Components
Component Spaceflight Capability
Let us take a moment for a brief overview of NASA Electronic Parts and Packaging
(NEPP) part grades as specified in EEE-INST-0026.
Grade 1 parts are the highest-grade parts. They are qualified on a lot-by-lot basis and are subject to frequent qualification efforts by the manufacturers in order to retain Grade 1 status for use in spaceflight. After the manufacturing environment has been qualified (which is a process full of requirements not considered here), there are many steps needing to be taken for each part.
Beginning with wafer fabrication, Grade 1 qualification requires that only 1 wafer run may be used in a given part lot due to homogeneity concerns. Each wafer lot must undergo acceptance testing which features government-controlled rework to assure homogeneity. A variety of physical tests are done on a subset of each lot (such as shear testing, bond pulling, and destructive physical analysis) which eliminates some of the lot. Parts must be put through 240- hour burn-ins and are subject to agency-specified failure analysis requirements and variable data tracking. Each lot must also subject certain parts to a 1000-hour life test in strenuous environments (which include thermal stress and radiation) to ensure parts from that lot will be able to survive long mission lifetimes in spaceflight. Grade 1 parts are also subject to package
20 qualification (to ensure radiation tolerance, build quality, etc). Naturally, these and many other screening and qualification measures make Grade 1 parts extremely expensive, subject to low yield rates, and long lead times.
Grade 2 parts are far less controlled than Grade 1. They don’t require single-wafer-runs per lot and lot acceptance testing on each wafer run isn’t required. Wafer rework is still agency- controlled. Lot control is also essentially eliminated as a given lot may be made from different machines, by different operators in different environments as long as the processes are compliant with agency specifications. More parts per lot are required to be analyzed destructively (due to unlimited lot size) but the relative cost per lot is less. Burn-in, failure analysis, and variable data recording are not required for these parts and life tests must only be performed once per year on any lot (not each lot as in Grade 1). Package qualification is only necessary every year as well.
Grade 3 parts are much the same as Grade 2 parts. They are not subject to controlled rework or destructive physical tests (and destructive physical analysis is only required on a few parts from any lot). Grade 4 parts are virtually uncontrolled outside the manufacturer and thus are only subject to manufacturer-developed specifications. Naturally, most spaceflight missions require
Grade 1 parts to be used and thus the cost of parts for these missions is very high compared to parts for terrestrial use. For the development of this SSPA in this research, it was not necessary to use anything beyond Grade 4 parts as long as the parts could be qualified to Grade 1 if they were to be used on a space mission. Use of parts which would fail qualification would not demonstrate the viability of such a design in space and thus would be a research failure.
Space Environmental Effects
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Space presents an extremely harsh environment to electronic devices. This environment is totally unique and is not encountered in any other industry, so special care and screening must be taken to ensure electronic components do not fail or cause failures elsewhere on spacecraft.
The launch environment for spacecraft also presents a set of challenges. Between the launch environment and space environment, conditions that space components must be able to endure include (but are not limited to) the following:
• Vibration – vibration is a natural result of powerful launches and systems must be able to
maintain their structural integrity and (if powered during launch) their performance when
vibrated, and certainly must be able to perform afterwards.
• Shock – Shock events happen primarily when launch vehicle stages separate with
pyrotechnic charges. Systems undergoing powerful shock pulses must maintain their
structural integrity and be able to recover performance in short order.
• Thermal extremes – All systems have to be able to perform adequately at thermal
extremes which generally reach from -35°C to +65°C in acceptance testing.
• Vacuum – high vacuum is a natural condition in space. With no atmosphere, thermal
management becomes a problem. Beyond that, outgassing (which means the gradual loss
of mass/material to evaporation), which happens much more with no atmospheric
pressure, becomes an obstacle to avoid. During pressure changes to vacuum, corona
discharges are possible at critical pressures (which can be devastating to devices) and,
when vacuum is achieved, multipaction can occur in higher-powered devices.
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• Radiation – the natural space environment has three basic types of radiation: non-ionizing
radiation, ionizing radiation, and single-event upsets. Radiation effects on electronic
devices will be explored further in the next section.
Radiation Sources and Effects in Space
Depending on the parameters of the mission and the equipment available to the spacecraft, different radiation tolerances (to radiation-susceptible components) are required. The radiation environment varies due to solar activity, cosmic radiation, distance from Earth, orbital inclination/flight trajectory, and other factors. Radiation doses absorbed are measured in rads; one rad is equal to 0.01 J/kg of absorbing material.
The majority of radiation encountered by satellite missions is made up of electrons and protons trapped by the Earth’s magnetosphere. There is significant electron and proton radiation between 1,000 and 32,000 kilometers in regions known as Van Allen belts. Altitude distribution of electrons and protons vary considerably; protons trapped in the magnetosphere primarily populate lower altitudes than electrons, but the proton energies can exceed 1 GeV (giga-electron- volt) whereas electron energies tend to top out below 10 MeV (mega-electron-volts). Orbits that pass over Earth’s magnetic poles and over the south Atlantic Ocean receive substantial radiation exposure due to the lower altitudes the Van Allen belts reach in the atmosphere. Beyond the high-energy proton and electron flux, there is substantial presence of low-energy (< 100 keV) protons and electrons which drive up the total ionizing dose.
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Solar activity (in particular, solar flares) also cause substantial proton radiation. Alpha particles, electrons, and other heavier particles are emitted as well, but their fluences tend to be far less than that of protons. Solar activity follows a general 11-year cycle with periods of high and low solar activity, but unpredicted flares happen and they have substantial radiation effects.
Worse, even, than high-energy proton flux is Galactic Cosmic Ray (GCR) radiation, which is often termed (in the context of radiation dose) as a Single-Event Upset. GCR radiation includes X- and gamma-ray radiation and heavy nucleus radiation. It is uncommon to see nuclei heavier than iron in these radiation events, but lighter nuclei are quite common. Heavier nuclei have greater inertia than lighter nuclei and despite their relative scarcity, they can be very damaging to electronics.
Radiation Effects on Electronic Components and Mitigation Techniques
In the case of ionizing radiation (electrons, protons, electromagnetic radiation, etc), the radiation energy absorbed by materials generally only affects semiconductors. It is manifested within these devices as new electron-hole pairs which can separate and wander around the devices, becoming stuck in certain areas. These pairs often alter the properties of the devices they enter; naturally, some semiconductors are more resistant structurally to these effects than others. Often, these pairs are able to recombine or be shunted off to the junction contacts and they end up having very little effect on device performance.
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Displacement damage (caused primarily by neutrons and heavy nuclei, but can include ultra-high-energy electrons, gamma rays, etc.) are a little different. Instead of interfering with metal-oxide interfaces and creating unbounded electron-hole pairs, displacement damage literally results in the displacement of atoms from the semiconductor structure which can have catastrophic effects. These effects usually are strongest in minority charge carrying semiconductors, so certain majority charge carrying devices which are susceptible to ionizing radiation are not very susceptible to displacement damage.
Single-event upsets, as mentioned above, are high-energy nuclei depositing energy into semiconductor devices. The charge of the nuclei making contact can be great enough to switch the logic state of a device (on top of its potential ionizing and displacement damage effects).
While these are the rarest events, they can have the most catastrophic effects as they can not only cause physical damage to the device, they can alter data streams with no indication of radiation effects.
Vulnerability to any given dose of radiation is dependent on the material used; the molecular structure of the semiconductor, which depends on the elements themselves, are what determine the electron-hole vulnerabilities. Metal-oxide semiconductors and silicon- or germanium-based semiconductors can face major degradation and even outright failures when hit with only a few krad (kilorads) of radiation. Such components are cheap and easy to manufacture but are very vulnerable; thus, they generally are not usable in space. III-V semiconductors (like Gallium-Arsenide/GaAs) tend to be much more resistant to radiation. In fact, according to radiation testing done by the NASA Jet Propulsion Laboratory (JPL)10, GaAs
25 is among the “hardest” semiconductor materials studied in radiation testing; this includes ionizing radiation, displacement damage and single-event upsets.
Mitigation of radiation effects is an ongoing study. For a spacecraft system designer, concerns about the chemical structure and the physics of radiation effects are often insignificant.
Generally, a system designer will be more concerned with what he can do to avoid negative effects. In the case of ionizing radiation, the vast majority of the ionizing dose (barring extreme high-energy fluences from unforeseen events) can be blocked using conductive shielding; a few tens of mils are usually sufficient to stop the low- and mid-energy ionizing particles. Such shielding is commonly provided by the spacecraft or the chassis of the system, so such radiation effects usually do not greatly influence missions. As far as displacement damage and single- event upsets, the best bet we have is to pick semiconductor devices which have radiation-tolerant characteristics. In particular, GaAs and GaN (gallium nitride) are very radiation-tolerant and
MMICs (monolithic microwave integrated circuits) made from these materials tend to do very well in radiation environments where the total ionizing dose is several hundred krad.
Support Component Selection
To begin this section, let us look at the substrates used in the power amplifier. While several substrates with differing characteristics were considered, Rogers 10-mil RT-Duroid 5880 was selected. It’s low dielectric constant (2.2), low loss tangent (0.0009), excellent thermal properties, and solid mechanical profile make it an excellent choice. It has been proven in spaceflight communications already over several decades and will likely continue to be used for
26 a long while to come. The design went through full electromagnetic simulation using this material as the substrate. However, when fabrication time came, the Rogers factory where the
RT-Duroid 5880 was made was experiencing fabrication issues resulting in unacceptable lead time and expense (and the Rogers material is quite expensive already). Instead, the design was fabricated on Taconic TLY-5 which is an equivalent material at much lower cost with shorter lead times. For flight boards, the Rogers material would be almost guaranteed to be used, but for an EDU, the Taconic material is more than sufficient.
For the input/output terminations, Amphenol 2.92mm (K-connector) end-launch connectors were added. At the output of the final amplifier subassembly, a cable would feed to the 2.92mm Ka-band isolator which would function as the output connector for the entire system; however, there is no real benefit to adding the isolator in the scope of this thesis as an isolator which can handle >10 watts at Ka-band is likely to be very expensive and should be left for flight unit development.
Two digital-step attenuators were considered for this prototype, as well as an analog attenuator. In reality, they are just different variants of the same design family. The
HMC939ALP4E and the HMC941ALP4E are 5-bit digital-step attenuators with approximately 5 dB insertion loss and 30.5 dB and 15.5 dB of dynamic range, respectively; the tradeoff in dynamic range allows 1 dB vs 0.5 dB resolution. Being GaAs MMICs, they are satisfactory for spaceflight as control attenuators before the final amplifier module. Then, the HMC985ALP4KE was considered. Operating off two -5V control pins (tied together), this device achieves nearly
35 dB of analog attenuation control with a low 2.1 dB insertion loss. Also, with no biasing
27 required, it consumes only 10 microamps on its -5V control lines which is negligible. The device can also handle input powers up to 2W continuously which exceeds the output power of the driver device. Ultimately, the HMC985ALP4KE was chosen for the prototype as output power control resolution and very wide dynamic range satisfies the control requirements for this device.
The control range is far greater than the expected output power variance from a Ka-band modulator and the device is not in danger of being damaged by the driver device which has a 1W output power.
Ordinary surface-mount resistors and capacitors were used in the build of the power amplifier module. While there is a preferred parts list for flight components at L-3 Technologies
Cincinnati Electronics, cheap commercial equivalents were used in the building of this. The resistors were used as gate bias voltage dividers and the capacitors served as bypass capacitors on the drain and gate lines on both subassemblies.
Amplifier Devices
Because of the heritage designs and lack of current capability at L3 CE, wire-bonded dies were largely ignored. Dies tend to have the best performance across the board, but their difficult implementation makes them impractical for prototyping and they do not offer enough benefit to develop the capability at L3 CE. One particular device, the Custom MMIC CMD217, performs better than any individual power amplifier device found; its >9 W output power and wide bandwidth (with very flat gain response) makes it an otherwise perfect candidate.
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The search for (reasonably) powerful, wideband, space-ready Ka-band final amplifier devices was fairly short as there simply aren’t that many on the market. Ignoring bare die components, the search effectively was narrowed down to two amplifiers: Qorvo’s TGA2594-HM and its
TGA2595-CP. The former is a 4W (+35 dBm) QFN-24 GaN MMIC. It has good bandwidth and reasonable matching to a 50 Ω termination, but its lower output power disqualified it in favor of the TGA2595-CP. The TGA2595-CP is an 8W (+39 dBm) GaN MMIC. It has excellent bandwidth (its 3-dB operating frequency spanning from below 27 GHz to above 31 GHz) and high output power. This, coupled with its flanged 10-pin package and excellent thermal dissipation capability, made it the clear choice as a final amplifier device.
Having found a satisfactory final amplifier device, it was decided that the driver amplifier would be an Analog Devices HMC1132. This device is a 1W (+30 dBm) GaAs MMIC with over
5 GHz of 3-dB bandwidth. It has the ability, even with the insertion loss of the attenuator, cabling, and transmission line losses, to drive the TGA2595-CP well into saturation; so, it seemed to be the perfect driver for the final amplifier.
These components, when implemented with matched transmission lines, produced excellent bandwidth, gain flatness, and linearity across the entire spectrum of interest. All the critical components (the amplifiers and attenuator) are radiation tolerant and otherwise suited to space environments (given their data from the manufacturers). It can be said with a large degree of confidence that, should these components be used in flight configurations, they would not fail as a result of the ordinary space environment or launch conditions.
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Chapter 3: Analytical Design
Concept of Operation
Power amplifiers generally are designed to take in fairly low-power signals and amplify them to high levels. This usually cannot be accomplished in a single stage because the gain of each stage is low compared to the required gain of the power amplifier module; rather, the amplifier module is broken down into the final amplifier and a number of driver stages. After components were selected, it was determined that only one driver stage was necessary to meet the drive requirements of the final amplifier device.
Due to the limited power of all the solid-state devices found on the market, hitting a 10 W goal with a single final device is impossible at 29 GHz. So, the problem was addressed by designing the amplifier to take an input signal, split it into two balanced 180° out-of-phase signals, then amplify each one equally using two identical final amplifying devices and then recombine them for a greater output power. In order to meet the 10 W goal, the subassemblies must conform to some requirements which are delineated in the form of a gain budget (or link budget). The following tables shows the gain budgets for each subassembly and thus the leftover margin for gain and phase imbalance:
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Final Amplifier Gain Budget
Pin Gain Pout
Part (dBm) (dB) (dBm) Notes
0.5 dB margin remains between
Combination Margin amplitude and phase imbalance
Final Amp Output 2.92mm
Connector 1521-60051 41.0 -0.5 40.5 40 dBm goal
3 dB combination gain and assumed
Final Amp Output Structure 39.0 2.0 41.0 1 dB microstrip losses
Final Amp Device Output of TGA2595-CP when
TGA2595-CP 18.0 21.0 39.0 driven with +18 dBm
Final Amp Input Structure 18.5 -0.5 18.0 0.5 dB assumed microstrip loss
Final Amp Input 2.92mm
Connector 1521-60051 19.0 -0.5 18.5 0.5 dB assumed connector loss
Driver Amplifier Gain Budget
Pin Gain Pout
Part (dBm) (dB) (dBm) Notes
System Interconnect Cable 6" Datasheet specifies max insertion
WM10487-ND 19.9 -0.9 19.0 loss of 0.92 dB up to 40 GHz
Driver Amp Output 2.92mm
Connector 1521-60051 20.4 -0.5 19.9 0.5 dB assumed connector loss
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3 dB splitting loss and assumed 1
Driver Amp Output Structure 24.4 -4.0 20.4 dB microstrip losses
Datasheet specifies typical insertion
HMC985ALP4KE Attenuator 26.5 -2.1 27.5 loss up to 30 GHz of 2.1 dB
Driver Amp Interstage
Structure 27.5 -1.0 26.5 Assumed 1 dB microstrip loss
Datasheet specifies 30.5 dBm Psat,
Driver Amp Device HMC1132 7.5 20.0 27.5 minimum gain of 20 dB
Driver Amp Input Structure 8.0 -0.5 7.5 0.5 dB assumed microstrip loss
System Input 2.92mm 0.5 dB assumed connector loss, 1.5
Connector 1521-60051 8.5 -0.5 8.0 dB margin under +10 dBm input
The assumption here is that the final amplifier output structure combines the signals with identical phase and gain distortion as the driver amplifier’s output structure. Therefore, we flow down this 0.5 dB combination margin to the driver amplifier’s output.
A simulation of a perfect (non-distorted) combination was run using a simple Excel spreadsheet which yields the combination loss (in dB) when two signals of the same magnitude and frequency but varying phase are combined as follows:
퐶표푚푏푖푛푎푡푖표푛 퐿표푠푠 (푑퐵) = 20 ∗ log (A ∗ sin(휑) + B ∗ sin(휑 − 휃))
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A and B are the amplitudes of the respective sine waves and are set equal to each other in this model. The signals are shown to vary in phase and the loss (compared to the ideal combination of the signals) is shown:
Figure 1: Combination Loss Due to Relative Phase Shifts Up To 90 Degrees
Magnitude variation of A and B (in dB) will add linearly, so this was not separately analyzed. From this curve, we can see that the total signal level will drop 0.5 dB due to an input phase variation of 38.75 degrees; this 38.75-degree phase imbalance is assumed to be split between the driver amplifier’s output structure and the final amplifier’s output structure.
Therefore, the driver amplifier’s performance target for phase imbalance is half the 38.75 degrees, or 19.375 degrees. Due to a lack of acceptable splitter/combiner/coupler designs components on the market, the splitting and combining were accomplished with identical ring couplers. The theory of operation for the amplifier used in this research is illustrated in the functional block diagram shown below:
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Figure 2 Ka-band Power Amplifier Concept of Operation
The driver amplifier consists of a single medium-power amplification stage and an analog-control attenuator. This attenuator is manually controlled by an externally-applied voltage
(which, in a flight configuration, would likely be replaced by a digital-to-analog converter driven by the transmitter’s FPGA) in order to vary the drive level the final amplifier receives. After the attenuator is the ring coupler (configured to function as a power splitter) which splits the signal into two balanced 180° out-of-phase signals which are carried out of the amplifier by the
2.92mm K-connectors (chosen for their 40 GHz upper frequency limit). The terminating port of the ring coupler is carried out of the subassembly by a K-connector which is directly attached to a 2.92mm 2W 50 Ω power terminator. In a flight configuration, there would usually be a diamond terminating resistor mounted on the board with sufficient power rating to consume
100% of the amplifier’s power and still meet derating requirements, but the components which
34 are used for this in flight are extremely expensive and are impractical for the scope of this research. The same is true of the final amplifier board which contains an identical ring coupler functioning as a power combiner instead of a splitter.
The final amplifier subassembly consists of two TGA2595-CP devices. Each device’s input is a K-connector and a transmission line and each output feeds the ring coupler between the two devices. The ring coupler has an output port and a terminated port, each served by K- connectors. Again, the final amplifier would include a high-reliability on-board termination in flight but that is impractical for this thesis.
Basic Power Amplifier Design and Background
Power amplifiers are classified based on their modes of operation. There are four basic classifications for analog power amplifiers: A, AB, B, and C. Classes D, E, and others are designated for switching amplifier designs and digital circuits and are not discussed in this thesis.
Essentially, for analog power amplifiers, each classification describes the amount of time (per signal period) the amplifier is in a conducting state. This quantity, known as the conduction angle, is measured in degrees (or radians).
Class A amplifiers are always drawing current from their biasing circuitry and therefore their conduction angle is 360° (100% conduction operation). Because there is no “off time”, there is little frequency distortion or added phase noise compared to other amplifier classes
(which is beneficial for high-frequency operation) and the designs of Class A amplifiers is
35 usually simpler than those in other classes. The primary downside to Class A amplifiers is that they are inefficient (theoretically, they can only operate up to 25% efficiency irrespective of frequency of operation) and therefore always dissipate at least as much power (just to keep the device operating) as they supply to their loads. This is an enormous problem for heat management and is also an issue at high frequencies where efficiency is already difficult to achieve.
Class B amplifiers operate at a conduction angle of 180° (50% conduction operation). For a single amplifying transistor, this is problematic as half the signal is lost. So, generally, Class B amplifiers are used in cascaded designs which operate in opposite and alternating portions of the input signal period. This lineup is generally called “push-pull” operation and can achieve a theoretical efficiency of π/4 (approximately 78.5%). Class B amplifiers tend to suffer from crossover distortion because components are not ideal and one amplifying element is incapable of stopping its conduction at the exact moment the other takes over, and there tend to be slight impedance mismatches in the low-power level portions of the signal.
Between the Class A amplifiers and Class B amplifiers is Class AB; these amplifiers are designed in the push-pull configuration like Class B but each amplifying element conducts for greater than half the signal period. This allows the crossover distortion present in Class B amplifiers to be greatly reduced (or totally eliminated with proper negative feedback and mixing). The theoretical efficiency limit of these is the same of Class B amplifiers but most
Class AB amplifiers are less efficient as they take advantage of conduction crossover. In general,
MMICs tend to be developed for biasing in this class because it offers the greatest versatility.
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Finally, we look at Class C amplifiers. Class C amplifiers are those whose conduction angles are less than 180° (< 50% conduction operation). As one might imagine, the small conduction angle causes high distortion which requires tuned loads in order to recover the original signal waveform. They are more efficient than the other analog amplifiers and, when matched to a tuned load and properly filtered, have minimal distortion products. Tuning of the load is done to match the amplifier at the carrier frequency and distortion products, which increase with distance from the carrier frequency, can generally be filtered out with band-pass filters. Without precise tuning to match the receiver, however, Class C amplifiers prove difficult to implement effectively in bandwidth-efficient modulation schemes and so are not considered in this thesis.
The decision was made to operate in a Class AB configuration; however, the strong bias scheme in the actual implementation will be very close to a pure Class A configuration. The amplifiers themselves are packaged GaN amplifiers and not single-stage transistors so the flexibility of operating class was quite small; however, the multi-stage amplifiers do allow simpler implementation and biasing than a discrete transistor or set of transistors would.
Transmission Lines
The design of transmission lines used in RF circuitry is extremely important; improper design and matching of transmission lines results in unwanted reflections, attenuation, distortion, and unwanted propagation modes. Each transmission line must be designed so that they are
37 matched to the specific amplifying elements they lead to. There are five basic types of microwave transmission lines: coaxial, waveguide, stripline, microstrip, and coplanar waveguide.
Coaxial lines are inefficient at high frequencies and are not discussed in this thesis; high- frequency coaxial cables are used as interconnects between the amplifier assemblies and likely would be in a flight unit as well, but they are not relevant to the design of the assemblies themselves. Waveguides are the most efficient transmission lines but are bulky, expensive, and difficult to implement in full transmitter modules with solid-state devices. They are better suited to be matched with TWTAs and so they are also not discussed in this thesis. Symmetrical striplines support a pure transverse-electromagnetic (TEM) wave propagation mode but cannot be tuned without damaging the transmission line/substrate and cannot be used with surface- mount components because the ground planes on both the top and bottom of the conductor dielectrics prohibit any such action.
Microstrip transmission lines are perhaps the simplest type of transmission line. They consist of a ground plane with a dielectric substrate overlaid on top of it; layered on that is the actual microstrip line itself. There is air or free space above the microstrip line. Essentially, microstrips are dielectric-filled two-parallel-plate waveguides and operate based on the principles of pseudo-transverse electromagnetic wave (pTEM) propagation; that is, they are not pure transverse electromagnetic waves (unlike a radiating antenna’s output). Still, they allow propagation which is extremely close to TEM waves and, for most purposes, a pure TEM wave can be assumed as the mathematical representation is simpler.
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The characteristics of a microstrip transmission line are dependent on the substrate properties and the geometry of the transmission line itself. In particular, we are interested in the characteristic impedance of a microstrip line of a given width. The equations used to determine these characteristics are as follows8:
휂 퐹 2 2 √ 50 = 푍푐 = ln ( + 1 + ( ) ) 2휋√휀푟푒 푈 푈
휀 + 1 휀 − 1 10 −퐴퐵 휀 = 푟 + 푟 (1 + ) 푟푒 2 2 푈
2 4 푈 1 푈 + ( ) 1 푈 3 퐴 = 1 + ln ( 52 ) + ln (1 + ( ) ) 49 푈4 + 0.432 18.7 18.1
휀 − 0.9 0.053 퐵 = 0.564 ( 푟 ) 휀푟 + 3
30.666 0.7528 −( ) 퐹 = 6 + (2휋 − 6)푒 푈
where η = 120π Ω (intrinsic impedance of space), εr = dielectric constant (relative permittivity) of the substrate, εre = effective dielectric constant of the substrate, and U = w/h (width of the substrate divided by the height of the substrate.
By careful inspection, it becomes obvious that the characteristic impedance of a microstrip line Zc depends on the effective dielectric constant and the ratio of the width of the microstrip line to the height of the substrate. To quickly arrive at the optimal ratios, a MATLAB script was written which varied these parameters. The only inputs necessary were the desired
39 characteristic impedance of the microstrip line and the dielectric constant of the substrate in question. The first output of the script gives the width/height ratio at the desired characteristic impedance and the second gives the effective dielectric constant of the substrate under the conditions specified. The substrates considered were Rogers 4003C (εr = 3.38), 4350B (εr =
3.48), and Rogers RT-Duroid 5880 (εr = 2.2). The 5880 material was ultimately chosen, and the results of the MATLAB script written when the 5880 characteristics were entered are shown below:
Figure 3: Zc vs U = W/H for a Microstrip Line on RT 5880
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Figure 4: εre vs U = W/H for a 50 Ω Microstrip Line on RT 5880
The resulting U = W/H ratio on Rogers RT-Duroid 5880 was 3.087:1 At that U = W/H ratio, the effective dielectric constant becomes 1.88 (down from 2.2). So, the ideal 50 Ω microstrip line on this substrate would be 3.087 times as wide as the height of the substrate and the wavelength of signals going through this substrate would be 3.087-1/2 times shorter than in free space (about
56.9% as long as in free space). For the 10-mil substrate chosen for this design, the width of the microstrip line would have to be approximately 30 mils wide, which is quite wide for Ka-band components which tend to have very thin pins. While this in itself does not disqualify microstrip lines from use, microstrip tapers do have different impedances than straight lines and those effects need to be considered in the design of any system.
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Finally, coplanar waveguide (CPWG) transmission lines are very much like microstrip lines. They are composed of a center conductor (which acts as the signal conductor) with a ground conductor on either side of them, all on top of a substrate material. If there is a ground plane present, the transmission line is sometimes deemed a grounded coplanar waveguide
(GCPWG). Because of the presence of the ground planes on either side of the conductor and the plane underneath the substrate, there are infinitely many combinations of conductor widths, gap dimensions, substrate thicknesses, and dielectric constants that can result in a given line impedance. Coplanar waveguide structures are easier to match to any given impedance and have superior electromagnetic radiation limiting. Also, due to the presence of ground pins on either side of the signal pin on many RF devices, the coplanar waveguide can be designed to perfectly fit virtually any pin and spacing and still be matched to 50 Ω. This is a huge benefit when considering the often quite-small size of components at Ka-band. However, the high difficulty in tuning coplanar waveguide transmission lines often makes them impractical for low-volume device production which is usually the case in spaceflight communications. Coplanar waveguides are especially useful when stability and isolation are concerns because radiated fields will be substantially weaker than in other transmission lines and there is a lower probability of oscillation.
While a 50 Ω coplanar-waveguide transmission line is easy enough to design, its implementation in power amplifiers with filters, couplers, splitters, and combiners is challenging and, at Ka-band, the advantages offered by the greater isolation aren’t really necessary. Greater isolation is a big advantage in some lower frequency bands where radiative oscillation is more common but this design not only lacks a chassis which would facilitate radiative oscillation, it is
42 such a high frequency that even if it had one the attenuation through the chassis of waves propagating in a waveguide mode would be substantial. Thus, it was ultimately decided that microstrip lines were the best choice; the tenability, ease of transition, and ease of implementation made it the obvious winner for this design.
Ring Coupler Design and Analysis
A number of different splitter/combiner types were considered for use in this design. A
Wilkinson-style splitter is generally simple to design and implement but it requires a lumped- element resistor of 2*Z0 between the dual input/output ports; this is because a passive three-port network cannot be reciprocal, lossless, and matched simultaneously as noted by Pozar.2 a lumped-element resistor that could handle the necessary power in the case of a load pull test or mismatch is extremely expensive at this frequency, so the Wilkinson-style splitter was not used.
Branchline, Gysel, and rat-race ring couplers all operate on similar principles to each other, but the ring coupler is the only one which provides a 180-degree phase shift option so it was chosen.
The basic design of a ring coupler is illustrated in the image below.7
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Figure 5: General Ring Coupler Design - Pozar’s Microwave Engineering 4th Edition
A ring coupler can be used to split or combine signals either in-phase or 180-degrees out- of-phase. In the case of the 180-degree splitter used here, port 2 serves as the input while ports 1 and 4 are the outputs and port 3 is terminated. As a 180-degree combiner, port 1 serves as the output of the 180-degree out-of-phase signals which are input at ports 2 and 3 while port 1 is terminated.
The circumference of the ring coupler is 1.5λ; on the 10-mil 5880 substrate, λ can be shown to equal approximately 302 mils using the above microstrip equations which results in a coupler with a 452-mil circumference (144-mil diameter). The portions of the coupler which present a characteristic impedance of √2 * Z0 (70.7 Ω) are formed with a curved microstrip line with a width of 17 mils and the Z0 (50 Ω) portions are 30-mils wide. Each port is separated by
λ/4 electrically (75 mils) and set 60 degrees apart mechanically in the layout. During electromagnetic simulations of the coupler (detailed in Chapter 4), the actual dimensions were tuned slightly for optimal performance around the 29 GHz center frequency.
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As mentioned, a serious concern that is present in spaceflight RF communication systems which is not present in terrestrial applications is multipaction. Multipaction (also called the
“multipactor effect”) is an ionization phenomenon which occurs in vacuum when high-strength alternating electric fields cause the metal structures which carry the RF signals to emit electrons which are accelerated by the alternating electric fields. This causes a sort of “electron cloud” to form which releases tremendous heat and can destroy systems in addition to siphoning off the RF energy and causing major interruptions to the signal. Multipaction is dependent on the geometry of the RF structures, the frequency of the waves, and the strength of the electric field between two structures. In particular, the breakdown field strength can be normalized to a potential difference (voltage) based on the product of the frequency and the gap width between the considered RF structures; the plot of breakdown voltage vs frequency-gap product is known as a
Hatch and Williams curve. The reason this concern is raised here is that the ring coupler on the final amplifier subassembly is the structure with the highest susceptibility to multipaction; the potential difference across the ports is higher than at any other point in the power amplifier module. The image below, from page 27 of the ECSS Space Engineering Multipaction Design and Test handbook, shows the Hatch and Williams curve for a parallel-plate geometry which approximates a microstrip geometry.
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Figure 6: Hatch and Williams Curve for Parallel RF Structures9
The frequency-gap product relevant to this ring coupler geometry is approximately 89.9
GHz*mm (29 GHz center frequency and 3.1mm gap) as shown in the coupler image below. This is because the maximum field at point A is 180-degrees out of phase with the field at B, essentially creating an electric field pointing from one point to the other equal to the peak-to- peak value of the wave. At f*d = 89.9, the Hatch and Williams curve above shows a breakdown voltage in excess of 3 kV. Thus, multipaction is not feasible with this geometry and part selection and is of no concern for either the driver amplifier subassembly or the final amplifier subassembly.
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Figure 7: Final Amplifier Ring Coupler Gap
Final Amplifier Design
The success of this research project primarily lies in the final amplifier board’s capabilities; these capabilities also governed the design requirements of the driver amplifier so it is prudent to list the final amplifier design method first. The target power level of this design, as mentioned previously, is 10 watts (+40 dBm) produced at end-of-life. As no individual solid-state device on the market has the ability to produce 10 watts, there arose a need to develop a combined amplifier stage which adds the output power of two devices such that the signal at the
47 output of the device is at a higher power level than either device can produce alone without distorting the signal.
The ring coupler previously discussed was used in the final amplifier design. The layout for the final amplifier devices, the TGA2595-CP, was created using the AWR Microwave Office layout editor according to the pad dimensions recommended by the manufacturer. The input and output transmission lines for each device start at 15 mils wide and taper to 30 mils (50 Ω) over a wavelength (300 mils). The combiner, if lossless, would add the amplifier’s output together netting a 3 dB gain over the individual device levels of +39 dBm. Thus, the ideal output level would be approximately +42 dBm which more than satisfies the 10 W (+40 dBm) design target.
However, the combiner will introduce microstrip loss as will the output connector and transition, so the real output level is expected to be below +42 dBm. As mentioned in the gain budget, the assumed loss of the output connector is about 0.5 dB which would allow for up to 1.5 dB of microstrip loss which is substantially higher than expected. This margin should allow the module to meet the 10 W (+40 dBm) design target if driven with a sufficient RF input level at each input.
This level is dependent on the driver amplifier’s output capability (in both amplitude and relative phase). The AWR Microwave Office layout of the final amplifier subassembly is shown below, as well as a colored 3D representation of the final amplifier subassembly with the final devices in place (the green color represents the solder mask which was not applied for the built boards but would be for flight). The final amplifier measures 4.4”x2.06”.
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Figure 8: Final Amplifier Layout
Figure 9: Final Amplifier 3D Scale Rendering
Driver Amplifier Design
The driver amplifier has three primary functions in this design. First, it must take low- power RF signals and be able to amplify them to a high enough level that the final amplifier subassembly will be saturated when no attenuation is applied. Second, it must split the signal
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(via its ring coupler) so that there are two equal-amplitude 180° signals. Third, it must provide drive level control via its attenuator to operate the final amplifier in saturation or in backoff (that is, a power level below saturation). The splitting function is achieved using the above ring coupler in its splitting configuration.
Device selection and transmission line design needed to be considered together. The 1 W
HMC1132 was chosen as the amplifying device and the HMC985APL4KE attenuator was chosen to control the drive level to the final device. The pads for each device are not the same size, so the interstage between the two devices includes a 10-mil to 15-mil taper along a wavelength (300 mils). The layout of the coupler requires some degree of curvature in the transmission lines so that sharp corners are avoided (which cause undesired radiated losses). The input stage includes a taper from 30-mils wide (50 Ω) to 10-mils wide to match the attenuator pad size. A 30-degree curve at 10-mil width was added so that, after curving back in the interstage, the attenuator would be offset from the centerline of the board to allow another curve
(60 degrees) so that the ring coupler’s input would be fed from a straight microstrip line.
As with the final amplifier subassembly, the AWR Microwave Office layout of the driver amplifier subassembly is shown below, as well as a colored 3D representation of the driver amplifier subassembly with the final devices in place (again, the green color represents the solder mask which was not applied for the built boards but would be for flight). The board measures
2.66”x1.45”.
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Figure 10: Driver Amplifier Board Layout
Figure 11: Driver Amplifier 3D Scale Rendering
Amplifier Stability
One last crucial topic in the design of any amplifier system is the stability of the amplifier in the source and the load planes. The stability of each subassembly is evaluated separately and then the stability of the integrated power amplifier system is assumed based on the source and load plane stability of the subassemblies. The equations used for stability calculations, taken from Pozar7 are as follows:
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1 − |푆11|2 − |푆22|2 + |훥|2 퐾 = > 1 2|푆21푆12|
|훥| = |푆11푆22 − 푆12푆21| < 1
2 1 − |푆11| 푀푢1 = ∗ > 1 |푆22 − 훥푆11| + |푆12푆21|
2 1 − |푆22| 푀푢2 = ∗ > 1 |푆11 − 훥푆22| + |푆12푆21|
The above calculations were put into a spreadsheet with the simulated S-parameters of the subassemblies. The results show that the driver amplifier subassembly is unconditionally stable in both the source plane and the load plane over the frequency range 19.4515 GHz to 40
GHz (where the S-parameter data on the devices ends) and outside that range the device is conditionally stable. The final amplifier subassembly is shown to be unconditionally stable in both the source plane and the load plane across the frequency range 25 GHz to 34 GHz beyond which s-parameter data is not available. Thus, the system overall is stable (as the inputs and outputs of each subassembly are matched to 50 Ω) and can be operated at the maximum available gain.
The plots on the next two pages show the K-factor and the source and load plane stability factors (Mu1 and Mu2, respectively) of the devices. Gmax is shown as well but the calculation was not relevant in this thesis. The factors are all converted to dB because the scale on the plots would be far too large to accurately evaluate stability using the graphs; this means that K, Mu1, and Mu2 simply must be positive instead of being greater than 1 and the vertical scale is much more manageable as a result.
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Figure 12 Driver Amplifier Subassembly Stability Over Frequency
Figure 13 Final Amplifier Subassembly Stability Over Frequency
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Chapter 4: Software-Based Simulation and Data
Scope
In general, part of the design process involves simulating parts of systems to allow the designer to alter their designs in an effort to achieve the optimal design. This sort of in-process simulation is not considered here; rather, only simulation methods and data of the final design are included. That is not to say that the design was performed and then all this simulation took place; rather, it is more efficient for the purposes of this thesis to only examine the simulation efforts which took place at the end of the design process which supported the final build of the amplifier subsystems.
The electromagnetic simulations were performed using the AWR Microwave Office
AXIEM simulator. AXIEM is a 2.5-dimensional method-of-moments-based electromagnetic solver with user-definable layer and mesh characteristics which allow for any geometry with planar electromagnetic wave propagation to be simulated. Other software (namely MATLAB and MathCAD) were used in the design process but those are not detailed in this chapter as they were not used for test or simulation purposes. All simulations performed here used a 0.5-mil mesh resolution. The thickness of the substrate was set to 10 mils with top and bottom copper set
55 to a thickness of 1.4 mils. The dielectric constant was set to 2.2 and the loss tangent was set to
0.0009, both of which are specified by the manufacturer.
Driver Amplifier Subassembly Simulation
Three electromagnetic simulations make up the driver amplifier effort: the input stage, the interstage, and the output stage. S-parameter files for each of the stages were generated and combined with the s-parameter files of the amplifier device and attenuator device from the manufacturer Analog Devices. This combination produced a top-level s-parameter file which represents the driver amplifier subsystem as a whole (not including connectors, tuning, solder, or other potential manufacturing peculiarities).
To begin, the electromagnetic structure for the input stage is shown in the figure below:
Figure 14: Driver Amplifier Input Stage Electromagnetic Simulation Structure
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The input structure here includes the input connection, the input transmission line, and the electromagnetic structures which surround the transmission line as it enters the amplifying device. The darker color shows top-copper layer and it is where ports 1 and 2 are attached. The lighter colors are set to ground potential by being marked as part of the via layer; this is an approximation because, while there are ample vias in the design which anchor these structures, the structures themselves are not solid blocks which disappear into the heavy-backed ground. As these vias are less than λ/8 apart, however, this approximation should make no real difference in the simulation’s accuracy. The s-parameter file was generated by the solver and the results are shown in the figure below:
Figure 15: Driver Amplifier Input Stage Simulated S-Parameters
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These results, of course, are the input return loss and the insertion loss of the input stage, assuming a good 50 Ω match at port 2. Across the bandwidth of interest, the input stage achieves less than 1 dB of insertion loss while maintaining a return loss better than 10 dB. In the real system, the insertion loss will be a bit worse and the return loss a bit better due to connector loss.
In short, the input structure to the driver amplifier subsystem shows a decent match to a 50 Ω system impedance while maintaining fairly low insertion loss which is necessary to ensure sufficient signal levels are presented to the amplifying device.
Next, the interstage structure is shown in the figure below:
Figure 16: Driver Amplifier Interstage Electromagnetic Simulation Structure
As before, the darker section is the actual transmission line (which includes tapering and bending) and the lighter sections are set to the via layer. These lighter sections are the near-side
58 footprints of the amplifying device and the attenuating device. Similarly, port 2 of this transmission line was placed at the attenuator end of the transmission line and port 1 was placed at the amplifier end. The solver-generated s-parameter file was plotted and the results are below:
Figure 17: Driver Amplifier Interstage Simulated S-Parameters
Because of the taper and bending required, the impedance match of this interstage is mediocre which results in a suboptimal insertion loss which is approximately 1 dB at the center frequency. However, there is room on the transmission line for tuning which may improve the match and minimize the line loss.
Lastly, the output stage EM structure is shown below:
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Figure 18: Driver Amplifier Output Stage Electromagnetic Simulation Structure
This four-port structure was built out of polygons and, like the other structures, includes via-layer part footprints and connector footprints. Port 1 is the output of the attenuator, ports 2 and 3 are the split outputs and port 4 is the isolated port which will feature a 50 Ω termination in
60 the physical build. To compensate for the bends and tapering, there is ample room for stubs to be placed on all four transmission line sections and there is even room on the coupler should some tuning effort be necessary. The solver produced a 4-port s-parameter file and some of the results are shown in the figure below:
Figure 19: Driver Amplifier Output Stage Simulated S-Parameters
This figure will take a little bit of dissecting. In pink, we see the input return loss for the output structure. The structure would be well-matched at 30 GHz and while it is not poorly matched across the bandwidth of interest, there is room for improvement with transmission line tuning in the physical build. In purple and light green are the output return losses for ports 2 and
3 of the output structure. Their shapes are very similar and show decent matching across the
61 bandwidth of interest with some room to tune. In dark blue we see the signal level at the port 2 split output relative to the input signal level and in dark green we see the signal level at the port 3 split output relative to the input signal level. These two traces are basically right on top of each other which is extremely important for the proper function of this power amplifier as a whole system. We expect, by design, a minimum of 3 dB of loss (because ideally the signal is split into two equal parts) and this simulation shows approximately 4 dB of loss across the bandwidth of interest. It is no surprise that there is an additional 1 dB of loss due to the length of transmission line present. The red trace shows the signal level at the port 4 isolated output relative to the input signal level; ideally, this signal level would be 0 (negative infinity in dB) but there would naturally be some leakage. This simulation shows more than 30 dB of isolation from the input signal which means this coupler structure was designed properly for terminating signals at that port and splitting signals out ports 2 and 3 without having to dissipate substantial power in its terminating load.
The s-parameter files for each simulation and the manufacturer-provided device s- parameter files were placed into a schematic in AWR Microwave Office. The correct ports were connected to each other in the schematic and a new s-parameter file was generated from the schematic. The resulting s-parameter file yields the plot below:
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Figure 20: Driver Amplifier Subassembly Simulated S-Parameters
The color scheme for this plot is identical to the output structure plot color scheme. The pink trace is the subsystem input return loss. The dark blue and dark green traces show the system gain to each output port and are almost identical traces. The light green and purple traces are the output return losses for each port which are similar in shape and show promise for excellent matching when tuning is performed. The red trace shows the loss from the input of the subsystem to the isolated port which is substantial across the bandwidth of interest; very little power will be dissipated in the terminating load here. The biggest concern here is that the amplifier has approximately 10 dB of gain at the center frequency and the s-parameter file provided by the manufacturer is supposedly representative of a device at the brink of compression which occurs around approximately +6 dBm input power. If this simulation holds
63 true, the device will only have an output power of approximately +16 dBm at each output port which may not be enough to fully saturate the final amplifier subsystem. There are things which can be done to real builds which may show enough power to the final amplifier that +40 dBm (10
W) is achievable, but those techniques will be discussed later. In conclusion, electromagnetic simulation shows decent matching across the bandwidth of interest, decent gain and output power (which may or may not be sufficient depending on the compression of the final device), and excellent gain balance between the output ports.
Final Amplifier Subassembly Simulation
For the final amplifier subsystem, there are only two structures that were simulated using
AXIEM. In reality, there are 3 structures but the input stage for each amplifying device is identical) but inverted and theory of reciprocity dictates that these structures will perform identically. So, to start, the input stage structure is shown in the figure below:
Figure 21: Final Amplifier Input Stage Electromagnetic Simulation Structure 64
As with all the previous structures, the dark sections are ported and represent the top copper whereas the lighter sections are embedded in the via layer. The biggest concern in this structure is the taper may result in an unpredicted input return loss curve when manufactured which may result in unacceptable insertion loss. The length of the taper structure is 200 mils which should serve as an effective wideband impedance transformer between 11 and 44 GHz.
The simulated data is shown in the below figure:
Figure 22: Final Amplifier Input Stage Simulated S-Parameters
Across the bandwidth of interest, the input structure maintains an input return loss better than 14 dB and the worst-case input return loss here is -13.85 dB which occurs at 26 GHz which is well below the intended 28.25 GHz lower end of the desired bandwidth. This shows good
65 matching across the bandwidth which results in a reasonable insertion loss which is only -0.32 dB at its worst. This worst-case loss is inside the bandwidth of interest but the insertion loss curve is very flat so this loss should not have any discernable effect on signals coming into the final amplifier subassembly.
The other structure simulated is the output stage. As mentioned in the analytical design section, the output structure here includes a ring coupler of identical topology to the ring coupler in the driver amplifier subassembly. The output structure here includes the coupler structure, transmission lines, part footprints, connector footprints, the four drain bias lines, and bypass capacitor footprints. The transmission lines and coupler are set in the top copper layer and the rest are set in the via layer. The structure is shown in the figure below:
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Figure 23: Final Amplifier Output Stage Electromagnetic Simulation Structure
The amplifier device outputs are marked as ports 1 and 2 which are the inputs to the structure. The outputs are ports 3 and 4. As mentioned in the analytical design section, the structure is designed so that either port 3 or port 4 could serve as the signal output while the
67 other is terminated. If the input signals are close to 180° out of phase, port 3 will be the output and port 4 will be the isolated port with the 50 Ω terminator. If the signals are nearly in-phase, port 4 will be the output and port 3 will be the isolated port with the 50 Ω terminator. This is all important to note because the s-parameter plots can be deceiving to those unfamiliar to the design. The simulation was run and the s-parameter plot is shown below:
Figure 24: Final Amplifier Output Stage Simulated S-Parameters
In blue we see the input return loss for ports 1 and 2 which is better than 10 dB across the bandwidth of interest. In pink we see the port-to-port isolation between ports 1 and 2; this is an important measurement as it shows how much signal can leak through the coupler into the output of the final amplifying devices. It is important for this number to be fairly low as high levels here
68 can cause device damage and also result in power being wasted instead of being channeled out the subassembly output. The red and brown traces are the isolated port level and summing port level, respectively. This can easily fool someone who looks at the plot but does not consider the actual application; this electromagnetic simulation does not have the ability to simultaneously stimulate ports 1 and 2 with the signal (either in-phase or out-of-phase). All it shows is the relative signal level at ports 3 and 4 referenced to port 1 or port 2. Because it cannot stimulate the structure with an already-split signal, we cannot directly analyze this structure as a combiner.
Rather, we must take the theory of reciprocity into account and treat this structure as a splitter
(much like the driver amplifier subassembly) and acknowledge that when stimulated from the input ports, the signals will combine in some fashion at one output port or the other. To this point, we expect (by design of the splitter alone) a minimum of 3 dB loss from the input port to either output port as well as some quantity of transmission line losses. This is shown clearly in the figure.
The isolated port level varies between -3.5 dB and -4.5 dB referenced to the input and the summed port level varies between -4 dB and -5 dB referenced to the input. This is to be expected as the summing port has an irregular geometry which results in a less ideal match; however, there is ample room for tuning to improve this. The isolated port actually would be a more efficient output port and would serve well in this function if the signals were presented in-phase instead of out-of-phase. To confirm this point, in chapter 7, a revised driver amplifier subsystem is discussed which would better reflect the likely layout in an actual spaceflight transmitter; however, for the purposes of proving the concept, this somewhat more difficult approach was undertaken in this thesis.
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The s-parameter files for each simulation and the manufacturer-provided device s- parameter files were placed into a schematic in AWR Microwave Office. The correct ports were connected to each other in the schematic and a new s-parameter file was generated from the schematic. The resulting s-parameter file yields the plot below:
Figure 25: Final Amplifier Subassembly Simulated S-Parameters
The dark blue and light green traces represent the gain of the subassembly at port 3 referenced to each amplifier input, respectively. As one can see, the traces are virtually identical.
Similarly, the black and brown traces represent the isolated port level referenced from each amplifier input. This number is high, but again, the simulation does not account for the phase
70 balance of the input signals; we can be confident, as evidenced by this virtually identical level from each port, that when combined out-of-phase these signals would effectively cancel each other out as the coupler is designed to do. The pink trace is the input return loss at each port
(identical) and the red trace is the output return loss at the summing port. Ultimately, this simulation shows well over 20 dB of gain across the bandwidth of interest (especially when accounting for the combination gain) and decent matching at input and output to a 50 Ω system impedance.
Top-Level Amplifier Simulation
To evaluate full system performance, the s-parameter files for each subassembly were combined in an AWR Microwave Office schematic. In addition to the system s-parameter files, an s-parameter file for the RFLI26G40GB isolator (provided by the manufacturer RFLambda) was included so that the results properly reflect the actual future build configuration. It is important to note that no loss was built into this schematic to account for cables between the subassemblies or connectors on the subassemblies themselves; thus, this plot represents a sort of best-case target to aim for with the physical build of the amplifier subassemblies. The schematic was simulated and the below figure includes the relevant results:
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Figure 26: Full Power Amplifier Module Simulated S-Parameters
As the legend in the plot denotes, the red trace is the overall system gain. The system appears to show approximately 40 dB of gain across the bandwidth of interest with a peak of
46.49 dB at 27.83 GHz. Depending on the amount of implementation loss, this gain may still be sufficient to produce a 40 dBm (10 W) output with a +6 dBm to +10 dBm drive level. The dark blue trace indicates to level at the isolated port on the final device which is terminated with a 50
Ω load; the peak gain of 18.01 dB is well below the frequency band of interest. The light green trace indicates the level at the driver amplifier’s isolated port which is terminated by a 50 Ω load.
The light green trace shows appreciable loss referenced to the input signal which should result in far less than 1 mW (0 dBm) being dissipated in its load. Depending again on the implementation loss and drive level, it is reasonable to assume that less than 100 mW (+20 dBm) total will be
72 dissipated in the two terminating loads which is good for efficiency. The purple trace shows the output return loss which is primarily governed by the isolator’s output match. The pink trace is the input match which is identical to the input return loss measured in the top-level driver amplifier subassembly simulation. In conclusion, these simulations show that the amplifier as designed has an excellent chance of meeting the +40 dBm (10 W) output power goal and, based on the gain flatness at and near 29 GHz, should also have a chance at passing high-rate modulated data without destroying the data when implemented in a system with a 50 Ω system impedance. As a matter of interest, the figure below shows the top-level simulation without the isolator. The main effect in adding the isolator is introducing a few tenths of a dB in loss and slightly altering the output match to a 50 Ω system impedance.
Figure 27: Full Power Amplifier Module Simulated S-Parameters
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Chapter 5: Prototype Testing and Data
After one of the driver amplifier boards and final amplifier boards were finished being fabricated, it came time to test the devices. During this testing, a standard subassembly test procedure for amplifier devices was modified for these assemblies so that testing could be repeated and benchmarks for additional builds of this device could be met. The first step in testing amplifiers is generally setting a gate bias point at which the desired quiescent current is achieved. After that, RF alignment and testing may begin.
The following two images here show the test setup used for all the measurements:
Figure 28: Power Amplifier Subassemblies Mounted on Heat Sinks
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Figure 29: Power Amplifier Test Setup
Driver Amplifier Subassembly Measured Performance
For the driver amplifier, the manufacturer recommends starting the bias sequence with -
2.5 V at the gate and slowly increasing (towards 0 V) the bias point until a quiescent current between 500 mA and 700 mA is achieved. To set this bias point, a ribbon was set in place of R1 on the board and R2 was left open; this allows the gate to be directly controlled by a power supply. The driver amplifier device (HMC1132) was very sensitive to small changes in gate bias point once the 500 mA level was achieved, so for initial testing the bias was set there. Resistors of values 4.02 kΩ and 997 Ω were placed such that a bias voltage of -0.993 V would result from a -5 V supply being connected to Vg which results in a quiescent current of 520 mA. This bias
75 point results in a sub-maximal quiescent current which simply means the device could deliver a bit more gain and power later on if the bias were set more strongly.
The next step in testing this driver amplifier was performing an RF alignment, which in this case means measuring input and output return loss at the four ports so that optimal performance could be achieved at the center frequency and across the desired 1.5 GHz bandwidth. The network analyzer was calibrated and configured to sweep from 27 GHz to 31
GHz with a power level of -10 dBm. Port 1 of the network analyzer was attached to J1. The bias voltage of -5V was applied to Vg on the boards and Vc (which controls the attenuator) was left open, resulting in maximum attenuation. The remaining three ports were terminated with 50 Ω loads. The amplifying device is specified by the manufacturer to have an input return loss (S11) of 6 dB, so over the 300 mil (1 λ) input transmission line there was certainly room to improve the match. Because the device includes a DC-blocking capacitor at its input, there was no danger to tuning the device with the drain attached but the drain was left off anyway as turning it on didn’t substantially change the match (due to the 40 dB of 50 Ω attenuation presented by the attenuating device). Tuning was performed on the input transmission line using narrow (≤ 25 mil wide) stubs of length approximately λ/4. The resulting input return loss (S11) is shown in the figure below:
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Figure 30: Driver Amplifier Subassembly Measured Input Return Loss at J1
It may seem obvious, but the primary null was tuned to be close to the center frequency of 29 GHz so that minimal signal reflection would occur when a signal is sent into the device at that frequency. The markers show the limits of the bandwidth of interest (1.5 GHz total from
28.25 GHz to 29.75 GHz) and the worst return loss across the band of -10.88 dB is located at the
29.75 GHz marker; over the entire bandwidth the driver amplifier’s input is well-matched to a standard 50 Ω system.
Moving on to the outputs, the previous configuration was kept mostly the same. Port 1 of the network analyzer was attached to J2 of the driver amplifier and port 2 of the network analyzer was attached to J3 of the driver amplifier. The driver amplifier input J1 was terminated,
77 as was the isolated port J4 (which, after measurement, will be its permanent condition). This tuning configuration (where the return loss of J2 and J3 are both visible) is absolutely critical because any tuning on the output transmission lines, the isolated line, and the coupler will have an effect on the output match of both J2 and J3. Stubs were placed on the transmission lines and one on the coupler (which was extremely sensitive to stub tuning) and the resulting output return losses for J2 and J3 are shown in the two figures below:
Figure 31: Driver Amplifier Subassembly Measured Output Return Loss at J2
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Figure 32: Driver Amplifier Subassembly Measured Output Return Loss at J3
The worst-case return loss for the J2 output across the bandwidth is -14.86 dB at 29.75
GHz and the worst-case return loss for the J3 output across the bandwidth is -17.6 dB at 28.25
GHz. While the return losses are not identical to each other, both show excellent matching to 50
Ω system output impedance which is the important factor when tuning output match. Since the tuning was performed with the 50 Ω termination on the isolated port J4, no additional tuning needed to take place on the transmission line there; however, for the sake of completeness, the return loss was measured there as well (with all other ports terminated). The figure below shows the match of the isolated port:
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Figure 33: Driver Amplifier Subassembly Measured Output Return Loss at J4
As in the other plots, the markers show the limits of the bandwidth of interest. It is worth nothing that the isolated port does not perfectly match 50 Ω across the bandwidth and in fact the match is worse than -10 dB in some parts of the bandwidth; this is because the coupler and output transmission lines, especially after being tuned, are not built as ideal structures despite being designed according to ideal transmission line theory. However, the fact that the output match is not perfectly 50 Ω is what allows the isolated port to work so well as the system does not want to see exactly 50 Ω across the entire bandwidth because of the non-ideal manufacturing and tuning applied. Lastly, the port-to-port isolation between the output ports was measured.
This is a critical measurement as any imperfect loading on either output port will result in
80 reflected power back into the system and we have to be sure that power reflected from one side will not affect the other. The figure below shows the J2-J3 port-to-port isolation:
Figure 34: Driver Amplifier Subassembly Measured J2-J3 Isolation
This isolation varies quite a lot over the bandwidth which is expected due to the structure of the ring coupler. Most of the bandwidth has more than 10 dB of isolation but there are a couple of spots where the isolation is not ideal. As long as the driver amplifier sees a good 50 Ω match at each output port it will not matter.
Because of the high frequency, tuning is extremely difficult; the transmission lines are extremely sensitive to any tuning and are strongly responsive to the angle, length, width, and location of tuning stubs as well as the presence and quantity of solder on the transmission lines.
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The above figures represent the result of several hours of tuning effort after which the RF alignment was complete.
After the amplifier had finished undergoing RF alignment it was time to test the amplifier. The amplifier was tested on the network analyzer (calibrated with a power meter to ensure proper input power was delivered) with port 1 attached to the driver amplifier input J1.
S21 (gain) was measured at J2 and J3 separately. The parameters of primary interest for this device are output power, gain balance between the split outputs, and phase balance (the device was designed to split the outputs 180° out of phase). These parameters are most important as they are what allow the final amplifier subsystem to function properly; with poor gain or phase balance the final amplifier will recombine the signals badly resulting in low power and poor data quality and with low driver amplifier output power the final amplifier will not be driven hard enough to reach its fullest power potential. Parameters of secondary interest are gain linearity and compression, phase-nonlinearity, and amplitude-to-phase modulation (AM/PM). These secondary parameters govern data quality which can be more or less important depending on modulation scheme, data rate, and other factors.
Port 1 of the network analyzer was attached to J1 of the driver amplifier. J4 was terminated with its proper load and port 2 of the network analyzer was attached to J2 (with J3 terminated) and J3 (with J2 terminated) when each port was measured. For the first 27-31 GHz sweep, the drive level on the network analyzer was set to +6 dBm. During the first S21 measurement (gain at J2), the gain was found to be a little low compared to the designed level and so the bias point at the amplifier was changed. Instead of applying -5 V to the Vgg pad on
82 the driver board, the power supply was changed to bring -4.5 V to Vgg which, when divided down by the 4.02 kΩ and 997 Ω resistors, supplied -0.89 V to the amplifier gate. The resulting quiescent drain current was approximately 680 mA here, and this bias point is where the remaining data was taken. The figures below show, in order, the power gain (S21) for J2, the power gain (S21) J3, S21 for J2 and J3 overlaid on top of each other, and the gain differential between the two:
Figure 35: Driver Amplifier Subassembly Measured Gain at J2 Output
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Figure 36: Driver Amplifier Subassembly Measured Gain At J3
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Figure 37: Driver Amplifier Subassembly Measured Gain Comparison J2-J3
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Figure 38: Driver Amplifier Subassembly Measured Gain Differential J2-J3
First, it is important to note the actual level coming out of the driver amplifier at each output port. At the center frequency of 29 GHz, J2 displayed 13.59 dB of gain over the +6 dBm input level, resulting in +19.58 dBm output power. J3 displayed a similar 13.41 dB of gain resulting in +19.41 dB of output power. This is lower than the targeted +21 dBm output level, but connector loss and build non-ideality can account for that much loss at this frequency. The peak power level for each output port appears to exceed +22 dBm, but that occurs outside the intended bandwidth. This shows promise for use at slightly different frequencies. In-band, at just over 29
GHz, is a peak at which over +21 dBm is supplied by each port; this again shows promise at slightly different center frequencies than what was intended in this thesis. The primary takeaway from these measurements is that there is quite a bit of power available below 30 GHz and that the
86 device is fairly broadband below 30 GHz as well. It is also important to note the gain flatness of the driver amplifier across this bandwidth; over the 1.5 GHz bandwidth, there is approximately 2 dB peak-to-peak gain flatness. This in itself is not problematic as the gain may be flattened further in the final amplifier subassembly; less than 3 dB of gain variation over the bandwidth of interest was the target for the system as a whole.
The gain balance across the bandwidth of interest is exceptional, as shown in Figure 37 and Figure 38. Within the bandwidth, the worst gain imbalance is 0.669 dB at 28.25 GHz and as the frequency increases the gain imbalance shrinks to virtually negligible levels. Large gain imbalances ultimately mean that power will be dissipated in the terminating loads on the isolated ports of ring coupler splitters and combiners; generally, the output waveform will not suffer degradation but will suffer some power loss as a result of the wasted power in the loads. A larger issue would be phase imbalance. The phase imbalance (or rather, phase differential) of the device’s two output ports is shown in the figure below:
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Figure 39: Driver Amplifier Subassembly Measured Output Phase Differential J2-J3
The targeted worst-case phase imbalance, as determined in Chapter 3, was 24.5° which by itself would correspond to a termination loss of 0.2 dB; here, the worst-case measured phase imbalance is 10.19°. The ideal phase differential for this implementation of a ring coupler splitter would be exactly 180°. However, as this coupler (ideally) is identical to the one in the final amplifier subassembly, a phase imbalance from 180° could be either cancelled out or doubled by the same imbalance on the other coupler, depending on which ports are attached to which.
Beyond that, deviations beyond the worst-case determined phase imbalance would also be cancelled out or doubled in the same fashion. Substantial phase deviations can be problematic as phase deviations directly degrade output waveforms after recombination, so it is important to that
88 the driver amplifier and final amplifier subassemblies are tuned together at top-level to cancel out any of these potential deviations.
Next, power sweeps were performed on the driver amplifier subassembly. Both AM/PM measurements and linearity/compression measurements are measured by sweeping from a low power level to a saturating power level at the input of the device under test. Linearity is important as there will be varying power levels present at the input when modulated data is sent through the amplifier; strongly non-linear devices can distort the signal which will cause higher error-vector-magnitudes and thus higher bit-error-rates. AM/PM is similar but refers to phase modulation as a result of amplitude modulation. Phase differences, again, can be seriously problematic if they are large.
The power sweeps were performed at 29 GHz from -4 dBm input power to +6 dBm input power. To start, the next two figures show the linearity measurements for J2 and J3, respectively:
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Figure 40: Driver Amplifier Measured Compression at J2
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Figure 41: Driver Amplifier Measured Compression at J3
These plots do not show the P1dB exactly, but from visual inspection we can estimate that it occurs at approximately +3.1 dBm input level, which results in an output level of about
+18.1 dBm. The power level at +6 dBm input power is just above +19 dBm for each port which agrees with the gain measurements taken earlier. Moving on, the next two figures show the
AM/PM measurements for J2 and J3 respectively:
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Figure 42: Driver Amplifier Subassembly Measured AM/PM at J2
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Figure 43: Driver Amplifier Subassembly Measured AM/PM at J3
The AM/PM is denoted on each figure. This measurement depends not only on the actual curve but also the power range on which the measurement is taken. Naturally, as you back further and further into linearity, the AM/PM (in degrees per decibel) will decrease and approach
0. So, it was decided that this measurement would occur from +6 dBm down to the moment the amplifier starts to compress which occurs at approximately +0.9 dBm input power. The worst
AM/PM here occurs at J2 and is only 1.1 degrees per decibel; this AM/PM will have minimal effects on data quality. AM/PM tends to increase with frequency and such a low AM/PM figure is encouraging for transmitting quality data at a very high rate, even using a simpler, bandwidth- inefficient coding scheme like BPSK.
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This concludes the measurements taken on the driver amplifier subassembly. The driver amplifier was able to produce almost as much power as was targeted and produced a P1dB greater than +18 dBm. Drawing approximately 800 mA from a +5 V supply the device consumed
4 watts. The device was well-matched to a 50 Ω system impedance at all ports and exhibited enough isolation to assure proper operation when paired with an acceptable load at each output.
The gain and phase balance between the two output ports were both excellent and the gain and phase linearity measurements are encouraging for quality high-rate data transmission. In short, despite being a little bit low on power, the driver amplifier subassembly otherwise performed very well and its performance is likely satisfactory to drive the final subassembly properly and meet the overall system design goals.
Final Amplifier Subassembly Measured Performance
For the final amplifier devices, the manufacturer recommends starting the bias sequence with -5.0 V at the gate and slowly increasing (towards 0 V) the bias point until a quiescent drain current of 560 mA is achieved (for each device). To set this bias point, a ribbon was set in place of the series resistors for each device on the board and the shunt resistors were left open; this allows the gates to be directly controlled by a power supply. Each device was biased separately.
Resistors of values 56.2 Ω and 44.2 Ω were placed such that a bias voltage of -2.193V would result from a -5 V supply being connected to Vg1 which results in a quiescent current of 610 mA for Q1; for Q2, resistors of values 56.2 Ω and 44.2 Ω were placed such that a bias voltage of -
2.197 would result from a -5 V supply being connected to Vg2 which results in a quiescent
94 current of 560 mA. This bias point should allow the full power of the devices to be reached
(assuming sufficient drive level is present).
Next, the final amplifier subassembly underwent input and output return loss tuning. J1 of the subassembly was attached to port 1 of the network analyzer; the drive level was set to -10 dBm and J2, J3, and J4 were all terminated. The input return loss across the band was satisfactory without any stub tuning; the extent of tuning was removal of excess solder using a wick. The plot below shows the S11 measurement taken on J1:
Figure 44: Final Amplifier Subassembly Measured Input Return Loss at J1
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The worst input return loss level across the bandwidth of interest was -10.84 dB at 28.25
GHz and through the rest of the band the return loss was much better. In a similar manner, J2 was connected to port 1 of the network analyzer while J1, J3, and J4 were terminated. The input return loss needed a little bit of improvement on J2, so a narrow stub was placed in the middle of the taper. The S11 measurement is shown in the plot below:
Figure 45: Final Amplifier Subassembly Measured Input Return Loss at J2
The return loss curve here is much flatter across the bandwidth than that of J1. The levels across most of the bandwidth are higher (that is, more signal is reflected) but are still low enough that minimal signal reflection will exist at this input. It is important to note that, while the curves for J1 and J2 are quite differently shaped, the actual difference in level for the signals passing
96 through is negligible and will not have a substantial effect on their ability to be combined at the output.
The output return loss at J3 required a bit more tuning. J1, J2, and J4 were all terminated with 50 Ω loads and J3 was attached to port 1 of the network analyzer. A stub was also placed on the output path to improve the characteristics of the meandering line. During full-module testing, a small copper lump was also placed on the coupler to improve the combination effect which could not be discovered at subassembly testing. Also, a wide stub was placed close to the J4 connector to improve the match into the 50 Ω termination which ultimately improves the isolated port path of the ring coupler combiner; this results in less signal being wasted in the termination and more signal making it out of the subassembly output. So, the plot below shows the output return loss at J3 after full-module tuning which represents the final operating configuration:
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Figure 46: Final Amplifier Subassembly Measured Output Return Loss at J3
This plot shows that the output match of the final amplifier subassembly is absolutely excellent when implemented in a 50 Ω system. The worst return loss across the bandwidth is about -15 dB just above the center frequency. In the same configuration (except with J3 terminated and J4 being measured), the output return loss for the isolated port J4 is shown in the plot below:
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Figure 47: Final Amplifier Subassembly Measured Output Return Loss at J4
The isolated port does not perfectly match 50 Ω across the bandwidth and in fact the match is worse than -10 dB in some parts of the bandwidth; this is because the coupler and output transmission lines, especially after being tuned, are not built as ideal structures despite being designed according to ideal transmission line theory. However, the fact that the output match is not perfectly 50 Ω is what allows the isolated port to work so well as the system does not want to see exactly 50 Ω across the entire bandwidth because of the non-ideal manufacturing and tuning applied. In particular, the stub near J4 which improved output power and the resulting interaction with the imperfect coupler impedance result in a mediocre output match for the terminated port. Ultimately, it does not matter as the full-system measurements are taken in this configuration and this configuration showed itself to be the best after some hours of tuning.
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Lastly, the port-to-port isolation between the output port and the isolated port was measured.
This is a critical measurement as any imperfect loading on either output port will result in reflected power back into the system and we have to be sure that power reflected from one side will not affect the other. This is especially important as the isolated port output match is not ideal for a 50 Ω system, and any potential reflections would manifest in the system output if the isolation is poor. The figure below shows the J3-J4 port-to-port isolation:
Figure 48: Final Amplifier Subassembly Measured J3-J4 Isolation
This plot does not show the markers at the bandwidth limits, but it is obvious that the port-to-port isolation across the whole bandwidth is beyond excellent. Any signal which is reflected off the output or off the terminating load will be more than 30 dB down by the time it
100 makes it to the other port. This demonstrates that any such reflections will have a minimal effect on the performance of the final amplifier (and system as a whole) in this configuration. Due to the design of this system, no further testing could be performed on the final amplifier subassembly and so we will move on to the full system tests and data.
Full-System Measured Performance
As mentioned earlier, the most important measurements for the system as a whole are gain (and gain flatness), output power, and phase non-linearity. The setup for these system measurements is shown in Figure 29 at the beginning of this chapter. Port 1 of the network analyzer was attached to J1 of the driver amplifier subassembly. J4 of the driver amplifier subassembly was terminated with a 50 Ω load. J2 and J3 of the driver amplifier subassembly were connected (respectively) to J2 and J1 of the final amplifier subassembly with six-inch long,
86-mil diameter 2.92 mm cabling. J4 of the final amplifier subassembly was also terminated with a 50 Ω load. Port 2 of the network analyzer was connected through 30 dB of attenuation and twelve inches of 2.92 mm cabling to J3 of the final amplifier subassembly which is the system output. The cabling and attenuation was calibrated out of the measurements so the readings we see represent the system’s actual performance.
To start, the network analyzer sweeps from 27 GHz to 31 GHz at a drive level of +6 dBm.
The plot below shows the S21 measurement for the system across this bandwidth:
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Figure 49: Full Power Amplifier Measured System Gain
Marker 1 is the center frequency 29 GHz, marker 2 is the low end of the bandwidth of interest at 28.25 GHz, and marker 3 is the high end of the bandwidth of interest at 29.75 GHz.
Also, marker 4 shows the minimum gain (within the bandwidth of interest) being 34.21 dB at
28.654 GHz and marker 5 shows the maximum gain (also within the bandwidth of interest) being
35.9 dB at 29.06 GHz. This plot shows that, across the 1500 MHz bandwidth of interest, the worst-case peak-to-peak gain variation is 1.69 dB. The goal for this flatness was to have less than
3 dB of gain variation from the center frequency to the bandwidth extremes, so the amplifier’s performance far exceeds the flatness goal. Gain flatness is especially important across system bandwidth as it directly influences the output waveform when modulated data is passed through the system; in general, the wider the bandwidth is in which the gain is relatively flat, the higher
102 the data rate the system can handle. With such gain flatness across so wide a bandwidth, very high data rates are still achievable in this system even using inefficient modulation schemes like
BPSK.
The minimum gain in the bandwidth of interest correlates to a minimum in-band output power of +40.21 dBm, or 10.5 watts. At the center frequency, the output power measured +41.53 dBm, or 14.2 watts. For interest, the peak in-band output power is +41.9 dBm, or 15.4 watts. The goal for output power at the center frequency was 10 watts (+40 dBm) and, with the 3 dB bandwidth goal of 1500 MHz, a minimum output power goal across the bandwidth of 5 watts
(+37 dBm). The power amplifier system far exceeds the power goals across the entire bandwidth.
Next, the system phase-nonlinearity was measured. Phase non-linearity is measured by measuring the S21 group delay (which effectively determines the electrical length of the power amplifier), then changing the format of the network analyzer to measure S21 phase (instead of magnitude) and adjusting the internal electrical delay to match the group delay taken. Then, markers are placed at the maximum and minimum value to determine the phase-nonlinearity in units of degrees peak-to peak. The next figure is a screenshot taken from the network analyzer which shows the measurement described:
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Figure 50: Full Power Amplifier Measured System Phase-Nonlinearity
Markers 1-3 show the center frequency and the bandwidth extremes, and markers 4 and 5 show the maximum and minimum phase angle when the internal electrical delay is adjusted to match the group delay of the network analyzer. The phase-nonlinearity of this system is 9.3 degrees peak-to-peak over a 1500 MHz bandwidth. This suggests that the system will introduce very little phase error into modulated data signals which is beneficial for transmitting high-rate data. While actual specifications for current transmitters in space cannot be mentioned in this thesis, similar phase-nonlinearity numbers are achieved by much lower-rate data transmitters in lower frequency bands, so this phase-nonlinearity result is encouraging.
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This concludes the full-module testing of the power amplifier. Drawing approximately
800 milliamps from the +5 V supply and 2.2 amps from the +24 V supply, the module consumed
56.8 watts. Its peak output power of 15.4 watts yields an overall system efficiency of exactly
27.1%, which does exceed the initial goal of 22% determined by the quoted efficiency of the final amplifier devices. Initial concerns were raised about the driver amplifier’s output power; there was doubt as to its ability to drive the final amplifier subassembly hard enough to achieve the required output power. However, as shown by the full module testing, the power was shown to be more than adequate. The amplifier did not show any sign of oscillation (which confirms the stability calculations done in Chapter 3). Due to test equipment availability, modulated data was not able to be passed through the power amplifier, but various other measures provided encouragement that high-rate modulated data would be able to pass cleanly without being distorted by the power amplifier’s operation. In short, the performance of the full module exceeded design expectations which is encouraging for the use of SSPAs in this frequency range as replacements for TWTAs in the future.
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Chapter 6: Test Data Analysis and Comparison
Scope
This section of the thesis is intended to analyze and explain the differences in results between the simulations (documented in Chapter 4) and the measured data from the physical build (documented in Chapter 7). At the end of this chapter, ideas for improvements in the design process and implementation will be explored to better account for the discrepancies where present so that future design and modeling efforts will be more likely to closely reflect the eventual physical builds.
Driver Amplifier Subassembly Comparison
To start with, let’s examine the input return loss at the J1 connector of the driver amplifier subassembly. The following figure includes the simulated input return loss as well as the measured input return loss:
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Figure 51: Driver Amplifier Simulated vs Measured Input Return Loss at J1
The two traces follow the same general shape across this frequency band. The rather sharp null near the center frequency in the measured data trace is due to the stub placed on the input transmission line. Stub tuning is generally a fairly high-q-factor tuning method (as it creates good matches proportional to the geometry and location of the stub). The tuning on the input transmission line allowed a better input return loss across the frequency band than the simulation results. In addition to the tuning, the input k-connector is specified by the manufacturer to have anywhere from 0.5 dB to 1.0 dB of insertion loss over the entire Ka-band which, assuming the connector is well-matched to 50 Ω itself, would improve the return loss by
1 to 2 dB over a de-embedded measurement with an RF probe.
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Next, we concern ourselves with the output matching of the driver amplifier subassembly. The first figure below shows the measured output return loss at the J2 connector compared to the simulated output return loss at J2 and the second figure shows the measured output return loss at the J3 connector compared to the simulated return loss at J3:
Figure 52: Driver Amplifier Simulated vs Measured Output Return Loss at J2
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Figure 53: Driver Amplifier Simulated vs Measured Output Return Loss at J3
These figures show a substantial difference in the shape of the return loss curves compared to the simulated structures. While the measured curves are very similar to each other, they are quite different from the simulations which are also quite similar. The presence of solder, connectors, and stub tuning elements changes the shape of the curves. The 50 Ω terminating load on the isolated port of the coupler is of course not a perfect 50 Ω match and the attenuator device at the coupler structure input also would present some degree of mismatch. All these things affect the coupler structure as a whole which causes the shape of the return loss curve to change from the simulated shape. That said, the real build (when tuned, at least) outperformed expectations set by the electromagnetic simulations which is encouraging for future builds.
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Next, briefly, is the output return loss comparison at J4 (the isolated port). This one is not important by itself because the measurement requires the terminating load be removed which is not the final configuration, but it does give insight as to what impedance the coupler likes to see in order to keep the outputs balanced. The shape of the measured return loss curve is very similar to the simulated curve, just shifted up (or down) in frequency by about 2 GHz. This effect is almost certainly due to the tuning stub elements placed in the output structure; the differences here have no significant meaning but are nonetheless interesting to look at.
Figure 54: Driver Amplifier Simulated vs Measured Output Return Loss at J4
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Moving on, the next area of concern is the measured gain at each port. The measured data shown here was taken on the network analyzer with a +6 dBm drive level into the driver amplifier subassembly. As mentioned in Chapter 6, the gain balance between the two ports was exceptional under these conditions. Also, as noted in Chapter 4, the simulated gain at each port is essentially identical to the other. The first figure below is the gain measured at J2 referenced to
J1 compared to the simulated gain and the second figure is the gain at J3 referenced to J1 compared to the simulated gain:
Figure 55: Driver Amplifier Simulated vs Measured Gain at J2
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Figure 56: Driver Amplifier Simulated vs Measured Gain at J3
These figures should seem very similar with only small differences visible without markers placed on the traces. The measured gain is higher than the simulated gain at the center frequency and above which is promising; the peak gain is not as high, but this measurement was taken with the amplifier fairly compressed (as noted in Chapter 5 when linearity measurements were taken).
Lastly, the driver amplifier’s port-to-port isolation (between the J2 and J3 outputs) is compared to the simulated results in the figure below. The measured isolation is better across the majority of the bandwidth due to the stub tuning, but the tub tuning also resulted in some degree of ripple across the bandwidth as well. Still, the worst-case measured level from one port to the
112 other is about -14 dB. If we combine this 14 dB isolation with the typical return loss of either output, we discover that a reflected signal would be a minimum of 29 dB below the output power level of the device. This means any reflected signal off the outputs will have very little if any effect on transmitted data.
Figure 57: Driver Amplifier Simulated vs Measured J2-J3 Isolation
In the end, the simulated and measured results did not wildly vary. There is some variation which can be explained by the tuning methods and manufacturing variation, but the variation does not indicate any shortcoming of the simulation method or the design or build of the driver amplifier subassembly.
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Final Amplifier Subassembly Comparison
Following a similar method, we’ll examine the differences between the final amplifier subassembly simulated and measured results. The following two figures include the simulated input return loss as well as the measured input return loss of the J1 and J2 inputs, respectively:
Figure 58: Final Amplifier Measured vs Simulated Input Return Loss at J1
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Figure 59: Final Amplifier Measured vs Simulated Input Return Loss at J2
The first thing one might notice is that, while the simulated return loss curves for each input port are virtually identical, the measured return loss curves do differ in shape. The J1 input return loss curve is very close to the simulated curve; the input transmission line contains no tuning elements and so it is not surprising that the curves are nearly identical. It so happens that this input stage did not need tuning as a result of device-to-device variability as well as the manufacturing variability inherent in hand-population of a board. On the other input transmission line, there is a tuning stub placed. Before the stub was placed, the return loss curve followed the downward trend with frequency but was higher across the bandwidth; this difference again is attributed to device-to-device variation and the student researcher’s amateur soldering skill.
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Next, we look at the output return loss on the system output J3:
Figure 60: Final Amplifier Measured vs Simulated Output Return Loss at J3
The tuning stubs placed in the output structure had the apparent effect of shifting the return loss curve up in frequency and then changing its shape somewhat. The stubs appear to be optimally placed for lower in the frequency range (meaning there is room for improvement), but the output match is more than sufficient across the bandwidth.
Again, as a matter of interest, the J4 output return loss is shown in the next figure. The power amplifier was not tuned to present a good match to the J4 isolated port, but the best results occurred in the tuned configuration which resulted in this output return loss. The differences can
116 mostly be attributed to all the tuning elements placed in the output structure which, while they didn’t drastically alter the curve, did eliminate a deep null at the lower end of the bandwidth.
Figure 61: Final Amplifier Measured vs Simulated Output Return Loss at J4
The last compared static measurement is the J3-J4 port-to-port isolation. The next figure shows the simulated vs measured isolation. The curves are extremely similar in shape and magnitude but are offset in frequency. This difference is attributed to the tuning elements placed on the output structure. Tuning elements shift the impedance to match 50 Ω at a different frequency than an untuned line; the obvious result here is that the output structure does an excellent job rejecting signals going from one port to the other. This, coupled with the output return losses, means that in the bandwidth of interest any signal reflected off the output will be
117 more than 40 dB lower than the output signal and will have no discernible effect on the output waveform or data.
Figure 62: Final Amplifier Measured vs Simulated J3-J4 Isolation
Top-Level Comparison
Lastly, we shall compare the system gain in the next figure. The gain curve was very flat across the bandwidth of interest and, at +6 dBm input level, results in a minimum output power in the bandwidth of about +41 dBm. The system was simulated using the small-signal models presented by the manufacturers of the components used in the design. Since the input power to the system here was +6 dBm the system is operating several dB into compression (or, rather, fully
118 into saturation). The small-signal models (and the datasheets) for the components did not specify the drive level used in their creation, so we can only assume that the devices were tested well back in the linear region and not near their compression points. Thus, this measured gain, while lower across the whole bandwidth than that of the simulation, is expected to be lower and its flatness across the bandwidth is a good indicator of good tuning and build quality.
Figure 63: Full Power Amplifier Module Measured vs Simulated System Gain
In conclusion, we see that the simulations performed in AWR Microwave Office present a fairly reliable prediction of the performance of the solid-state power amplifier when built.
There are differences which can be explained by the tuning, the build quality, and the simulation method (as well as assumptions made during simulation), but ultimately we can conclude that
119 even at high frequencies, somewhat complex system simulations can give us reliable results which we can trust for innovative designs.
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Chapter 7: Conclusion
The research performed here shows that current technology does support the use of solid- state power amplifiers in space communications and that they are viable replacements for travelling wave tube amplifiers. The minimum performance targets for output power, bandwidth, and power efficiency were 10W, 1.5 GHz, and 22%, respectively. The hardware produced a peak in-band output power of approximately 15.4W at 29.06 GHz (14.9W at the center frequency of
29 GHz); over the 1.5 GHz bandwidth around 29 GHz the device produced a minimum of 10.5W which is well within the 3 dB bandwidth requirement. Producing this, the device consumed a combined 56.8W from its power rails which results in a peak power efficiency of 27.1%. The selected parts are fit for qualification to Grade 1 screening levels as defined by NEPP and are built from materials which are suitable for not only the vacuum of space but also the radiation environment. The amplifier’s design is not susceptible to ionization breakdown (either by multipaction or corona) and so this design should be suitable for most satellite missions which require high-rate data transmission on a Ka-band carrier.
There are a number of potential improvements to be made for this design. In order to achieve better matching and a lesser need for tapering in microstrip lines, the amplifier could be designed on a substrate with a higher dielectric constant or reduced thickness; either will reduce the required line width to match 50 Ω as well as reduce the overall size of the module. Microstrip lines can be made shorter as well in an effort to reduce size. Chassis design with an absorbent lid
121 and feed-throughs for DC power will result in a standalone module. Integrating a waveguide launch into such a chassis instead of using 2.92 mm connectors as the RF interfaces will result in lower loss not only out of the module but also allows the transmitter to be non-co-located with the satellite antenna which would be difficult to achieve using coaxial cables. Other improvements such as designing the driver amplifier to split signals in-phase (and on a smaller footprint with a higher dielectric constant and/or thinner substrate) will allow simpler matching and tuning to be done on the final amplifier as the current 50 Ω termination path would carry the
RF output instead and the current RF output would be fully replaced with an on-board 50 Ω high-power terminating resistor. All of these improvements will result in greater effective transmitted power and reduced size without requiring more advanced device technology to be developed.
This design and its potential improvements demonstrate that current technology is sufficient to produce viable Ka-band solid-state power amplifiers as replacements for travelling- wave-tube amplifiers for high-rate data transmitters on satellite missions. The design concept is extensible into other frequency ranges using other parts for other power levels and is shown to be viable due to its relatively wide build margins (as noted in Chapter 3) and the limited phase and magnitude error demonstrated at 29 GHz. High-rate transmission can be achieved with simple encoding schemes due to the wide bandwidth and there is no longer a need for an external power amplifier (TWTA or otherwise) when such an SSPA is integrated into the transmitter chassis.
This design, or an improvement of this design, will show itself to be ready for a full qualification effort to meet satellite program requirements and eliminate the need for TWTAs on satellite missions.
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References
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[2] TWTA versus SSPA; A 2004 Update of On-Orbit Reliability; IEEE-IVEC May 2005. Weekly, Nicol, Mangus
[3] TWTA versus SSPA; A New Look at Boeing Fleet On-Orbit Reliability Data and Comparison Factors; IEEE-IVEC April 2006. Nicol, Mangus, DePano
[4] TWTA versus SSPA; On-Orbit Reliability of the Boeing Satellite Fleet; IEEE-IMS May 2010. Nicol, Mangus, Grebliunas
[5] Maxtech, Inc. “The SSPA Advantage.” Application Note AP-4, Rev. 6 May 1998.
[6] EEE_INST-002: Instructions for EEE Parts Selection, Screening, Qualification, and Derating; April 2008, Dr. Kusum Sahu
[7] Pozar, David M. Microwave Engineering, 4th Edition. John Wiley & Sons, Inc. Hoboken, New Jersey, 2012. Print.
[8] Hong, Jia-Sheng and Lancaster, M.J. Micrsotrip Filters for RF/Microwave Applications. John Wiley & Sons, Inc. Hoboken, New Jersey, 2001. Print.
[9] ECSS Secretariat. ECSS Space Engineering Multipaction Design and Test. ESA Requirements and Standards Division, Noorwijk, The Netherlands, 2013. Print.
[10] C. Barnes and L. Selva, “Radiation effects in MMIC devices,” in GaAs MMIC Reliability Assurance Guideline for Space Applications, R. Kayali, S. Ponchak, and G. Shaw, Eds. Pasadena, CA, USA: JPL Publication, 1996, pp. 203–243.
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