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A Case Study in Hardware Trojan Design and Implementation Int. J. Inf. Secur. (2011) 10:1–14 DOI 10.1007/s10207-010-0115-0 REGULAR CONTRIBUTION A case study in hardware Trojan design and implementation Alex Baumgarten · Michael Steffen · Matthew Clausman · Joseph Zambreno Published online: 3 September 2010 © Springer-Verlag 2010 Abstract As integrated circuits (ICs) continue to have an functional requirements pass, can one be sure that there is no overwhelming presence in our digital information-dominated additional logic that is hidden from the tests? How much trust world, having trust in their manufacture and distribution is there in the design chain? What if something malicious has mechanisms is crucial. However, with ever-shrinking tran- been added? sistor technologies, the cost of new fabrication facilities is At the Embedded Systems Challenge, part of the 2008 becoming prohibitive, pushing industry to make greater use Computer Security Awareness Week (CSAW) [1] at the Poly- of potentially less reliable foreign sources for their IC sup- technic Institute of NYU, this exact scenario was proposed. ply. The 2008 Computer Security Awareness Week (CSAW) Several student-led teams from around the country assumed Embedded Systems Challenge at the Polytechnic Institute of the role of the hardware hackers that had been able to gain NYU highlighted some of the vulnerabilities of the IC sup- access to the HDL source code for the Alpha. With this ply chain in the form of a hardware hacking challenge. This source code in hand, each team had one month to imple- paper explores the design and implementation of our winning ment as many undetectable hardware Trojans as possible. A entry. hardware Trojan is a malicious modification to the circuitry that compromises the integrity of the original design, usu- Keywords Hardware hacking · Trojans · Security · FPGA ally to the attacker’s benefit. The Alpha device, augmented with Trojans, had to pass a set of functional tests, use the same reference power, maintain the configuration memory 1 Introduction usage, pass a brief code inspection and be undetectable by a general user. With these requirements in mind, our team Consider a hypothetical scenario1 in which a government from Iowa State University designed a wide set of applicable team is tasked with the design and test of a new crypto- Trojans and performed a proof-of-concept implementation graphic device, code-named Alpha. The Alpha device (which using a provided Field-Programmable Gate Array (FPGA) is expected to be in heavy use and hence is of high value to the board. This paper describes our winning efforts in detail. sponsoring government) allows soldiers to transmit messages securely to other soldiers and their command station. Alpha has returned from the fabrication facility and is waiting for 2 Competition details the team’s approval to ship. From a testing and verification perspective, when the highly sensitive nature of the device is The CSAW Embedded Systems Challenge began on Sep- considered, several complex questions arise. How much con- tember 2008, concluding a month later in New York. Each fidence does the team have that the Alpha is ready? Even if team received a BASYS development board [12] contain- ing a Xilinx Spartan FPGA along with basic peripheral I/O. Figure 1 shows a schematic and picture of our experimental A. Baumgarten · M. Steffen · M. Clausman · J. Zambreno (B) Electrical and Computer Engineering, Iowa State University, Ames, IA, USA 1 While seemingly far-fetched, this hypothetical mirrors real-world e-mail: [email protected] events, as is highlighted in Sect. 3. 123 2 A. Baumgarten et al. RS232 (a) (b) Expansion Headers JTAG PS/2 XILINX Spartan 3E VGA USB LEDs Power Seven Segment Display DIP Switches Push Buttons Fig. 1 a Diagram of components used from the BASYS board; b Experimental setup setup. The original design of the Alpha required a PS/2 key- specifications of the project. This description, typically in board connected to the board for input and a VGA monitor a form of a hardware description language (HDL), is the along with a serial connection for output. Four other buttons intellectual property (IP) of the designer. When the design changed the state of the system. Xilinx ISE 10.1 was used stage is complete, the RTL moves into the synthesis stage as the development environment for the mixed-mode HDL as it begins a series of electronic design automation (EDA) code as well as for the generation of the FPGA bitstream steps using software tools from companies such as Cadence, while Modelsim SE 6.3 was used for simulation. Addition- Mentor Graphics, and Synopsys in order to produce a final- ally, our team made use of an oscilloscope, power supply, ized layout schematic (i.e. netlist). These steps begin with multimeter, thermometer, HAM radio, and custom circuits logic synthesis which converts the RTL design into a directed to verify the functionality of each Trojan. acyclic graph (DAG) representation. Logic optimization uses In normal operation of the Alpha device, messages typed complex heuristics to search for graph transformations in in plaintext on the keyboard display on the VGA monitor. order to optimize for a particular metric. Next, mapping heu- Pressing the encrypt button on the board sends the message ristics convert the graph into primitive gate representations. through an AES-128 encryption block with the key selected Placing and routing give each gate a physical location on the by the 5 dip switches.2 Finally, the transmit button sends the IC and establishes their interconnections. After the synthe- encrypted message over the serial port. The message receiver sis is complete, the foundry receives the synthesized design, uses the correct key to decrypt the message. For the pur- a blueprint of the circuit. The foundry can then prepare the pose of this contest, the organizers provided a C program masks and tool the machinery. Finally, the completed ICs are called encVerifier to receive and decrypt the message. For distributed to the end users. scoring the designs, the judges evaluated the completeness In the past, each hardware company could use an in-house, and uniqueness of the Trojans along with their ability to be vertical process for both design and fabrication. However, undetectable to a set of functional tests, deviation in power as transistor feature sizes and time-to-market continued to consumption, deviation in bitstream size, and their ability to shrink, coupled with the demands for lower-power, high pass a brief code inspection. performance ICs, the cost to establish a full-scale foundry became prohibitive (upwards of $4Billion) for many compa- nies. Because of these factors, the IC supply chain flattened, 3 Background and motivation clarifying the roles of the various parties. Hardware IP ven- dors emerged who specialize in designing functional units, 3.1 IC supply chain overview memories, and bus controllers. These vendors license their technology to others for use in their own IC designs. The IC The integrated circuit (IC) supply chain is the process by design companies integrate third-party IP along with their which a conceptual idea transforms into an IC. The pro- own IP to create an IC design. Finally, contract foundries cess starts with the IC designer who creates the register harness economies of scale as they spread the large capital transfer level (RTL) description of the IC according to the required to build the foundry among their clients. The entire supply chain is vulnerable [25], but specific attention must be focused on the HDL and the foundries. 2 There is an obvious cryptographic limitation in using 5 dip switches to select unique 128-bit keys, but conceivably a more elegant model In the same way that software describes what the pro- could be used for obtaining the key in a production environment. gram should do and is vulnerable to malicious descriptions, 123 A case study in hardware Trojan design and implementation 3 the HDL describes the operation of the circuit and is vul- (DOS) where some subset of the functionality fails to nerable to the inclusion of malicious circuitry. An attacker work as intended. who is able to add circuitry to the design by means of the 2. Gaining extra knowledge: Leaking sensitive information HDL has limitless potential and flexibility. Since the attack not originally intended to be leaked from the device. This occurs very early in the process, discerning malicious intent includes allowing a malicious user to capture the plain- becomes very hard to detect. text messages, the key used to encrypt those messages or any other information that would allow that gives the 3.2 Supply chain vulnerabilities malicious user more knowledge about the system then originally intended. The concerns that arise from IC fabrication fit into three basic 3. Exercising additional functionality: Utilizing the device categories: Metering, Theft, and Trust. Each of these catego- for a function in which it is not intended to be utilized. ries broadly addresses the production of extra ICs beyond the In this attack, the device may function correctly, produce purchase order, unauthorized access to information including the correct outputs, and not leak information, but it still the IP, and the tampering of ICs received from the foundry. may be used in a manner not intended by the original The 2008 CSAW competition focused on the issue of trust, specifications. but a discussion of metering and theft rounds out the back- ground. 3.2.2 Metering The second category of concern, metering, deals with the 3.2.1 Trust number of ICs produced and for whom. The concept of water- marking has been applied to several technologies including As the trend of “fabless” semiconductor companies contin- hardware IP [24]. In this case, it is only a partial solution ues to increase, so does the trust placed in the hands of the that identifies the IP and not the IC.
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