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Hardware Trojans – Prevention, Detection, Countermeasures (A Literature Review)

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Hardware Trojans – Prevention, Detection, Countermeasures (A Literature Review) UNCLASSIFIED Hardware Trojans – Prevention, Detection, Countermeasures (A Literature Review) Mark Beaumont, Bradley Hopkins and Tristan Newby Command, Control, Communications and Intelligence Division Defence Science and Technology Organisation DSTO–TN–1012 ABSTRACT A Hardware Trojan is a malicious, undesired, intentional modification of an electronic circuit or design, resulting in the incorrect behaviour of an electronic device when in operation – a back-door that can be inserted into hardware. A Hardware Trojan may be able to defeat any and all security mechanisms (software or hardware-based) and subvert or augment the normal operation of an infected device. This may result in modifications to the functionality or specification of the hardware, the leaking of sensitive information, or a Denial of Service (DoS) attack. Understanding Hardware Trojans is vital when developing next generation de- fensive mechanisms for the development and deployment of electronics in the presence of the Hardware Trojan threat. Research over the past five years has primarily focussed on detecting the presence of Hardware Trojans in infected devices. This report reviews the state-of-the-art in Hardware Trojans, from the threats they pose through to modern prevention, detection and countermeasure techniques. APPROVED FOR PUBLIC RELEASE UNCLASSIFIED DSTO–TN–1012 UNCLASSIFIED Published by DSTO Defence Science and Technology Organisation PO Box 1500 Edinburgh, South Australia 5111, Australia Telephone: (08) 7389 5555 Facsimile: (08) 7389 6567 c Commonwealth of Australia 2011 AR No. 015-008 July, 2011 APPROVED FOR PUBLIC RELEASE ii UNCLASSIFIED UNCLASSIFIED DSTO–TN–1012 Hardware Trojans – Prevention, Detection, Countermeasures (A Literature Review) Executive Summary Electronic systems have proliferated over the past few decades to the point that most aspects of daily life are aided or affected by the automation, control, monitoring, or com- putational power provided by Integrated Circuits (ICs). The ability to trust these ICs to perform their specified operation (and only their specified operation) has always been a security concern and has recently become a more active topic of research. ICs are the building blocks for all modern electronic systems, they form the information backbone of many critical sectors including the financial, military, industrial, and transportation sec- tors. Without trust in these ICs, the systems they support cannot necessarily be trusted to perform as specified and may even be susceptible to attack by a malicious adversary. A Hardware Trojan is a malicious, undesired, intentional modification of an electronic circuit or design, resulting in the undesired behaviour of an electronic device when in operation. It is like a back-door that can be inserted into hardware – a foothold that an adversary can leverage to attack a system. ICs that are “infected” by a Hardware Trojan may experience modifications to their functionality or specification, the leaking of sensitive information, or a Denial of Service (DoS) attack. Hardware Trojan insertion into an IC can occur at any stage during the design and manufacturing process, including the specification, design, verification and manufacturing stages. Hardware Trojans may even be retro-fitted to existing ICs post-manufacture. Maintaining tight control over the IC design life-cycle is costly; the current trend is towards separation of design from manufacture, increasing use of third-party Electronic Design Automation (EDA) tools and third-party Intellectual Property (IP) cores, and outsourcing to contract-design houses. For a country like Australia, and even more so for the small Defence industry, keeping the entire design and manufacturing process in-house is infeasible for all but the smallest Application Specific Integrated Circuit (ASIC) designs. Our reliance on the globalisation of the electronics industry is critical for developing both our commercial and military capa- bilities. The Hardware Trojan threat must therefore be taken seriously and our approach must ensure that we are able to either trust the operation of ICs used or, better still, to safely utilise Commercial-Off-The-Shelf (COTS) electronic devices and ICs regardless of the presence of Hardware Trojans. Understanding Hardware Trojans is vital when developing next generation defensive mechanisms for the development and deployment of electronics in the presence of the Hardware Trojan threat. Research over the past five years has focussed on detecting the presence of Hardware Trojans in infected devices. As part of the Cyber CERP (Corporate Enabling Research Program) work program a literature review of Hardware Trojans was undertaken. This report reviews the state-of-the-art in Hardware Trojans, including the threats they pose and how they are commanded, through to modern prevention, detec- tion and countermeasure techniques. Importantly, there are currently no known catch-all countermeasures that can ensure that a device or system is free from Hardware Trojans, or allow a system to operate in the presence of Hardware Trojans. UNCLASSIFIED iii DSTO–TN–1012 UNCLASSIFIED THIS PAGE IS INTENTIONALLY BLANK iv UNCLASSIFIED UNCLASSIFIED DSTO–TN–1012 Authors Mark R G Beaumont Command Control Communications and Intelligence Division Mark Beaumont was awarded a B.E. (1st class Hons) in Elec- tronic and Computer Engineering in 1998 from the University of Tasmania, and an M.IT. from the University of Adelaide in 2010. He now works within Information Operations Branch. Bradley D Hopkins Command Control Communications and Intelligence Division Bradley Hopkins was awarded a B.E. (Hons) in Electronic and Electrical Engineering in 1997 from the Flinders University of South Australia. He now works within Information Operations Branch. Tristan Newby Command Control Communications and Intelligence Division Tristan Newby was awarded a B.Sc. in Mathematics and Com- puter Science in 1998 from the University of Adelaide, and an M.Sc. from the same university in 2008. He now works within Information Operations Branch. UNCLASSIFIED v DSTO–TN–1012 UNCLASSIFIED THIS PAGE IS INTENTIONALLY BLANK vi UNCLASSIFIED UNCLASSIFIED DSTO–TN–1012 Contents Glossary ix 1 Introduction 1 2 Threats 3 2.1 Insertion Phase and Location ......................... 4 2.2 Hardware Trojan Actions ........................... 5 2.2.1 Modify Functionality ......................... 6 2.2.2 Modify Specification ......................... 6 2.2.3 Leak Information ........................... 7 2.2.4 Denial of Service ........................... 7 2.3 Hardware Trojan Implementations ...................... 7 2.3.1 Illinois Malicious Processor ...................... 8 2.3.2 Cyber Security Awareness Week ................... 8 2.3.3 Malicious Off-chip Leakage Enabled by Side-channels ....... 8 2.3.4 Cryptographic Hardware Trojans .................. 9 2.3.5 Exploiting Semiconductor Properties ................ 9 3 Trigger Mechanisms 10 3.1 Internally Triggered .............................. 10 3.1.1 Combinational Activation ...................... 10 3.1.2 Sequential Activation ......................... 11 3.2 Externally Triggered .............................. 12 3.3 Always On ................................... 12 3.4 Trigger Design Issues .............................. 13 4 Prevention 14 4.1 Prevention at Design .............................. 14 4.2 Prevention at Fabrication ........................... 15 4.3 Prevention at Post-Fabrication ........................ 15 UNCLASSIFIED vii DSTO–TN–1012 UNCLASSIFIED 5 Detection 17 5.1 Destructive ................................... 17 5.2 Non-destructive ................................. 18 5.2.1 Invasive ................................ 19 5.2.2 Non-invasive .............................. 19 5.2.2.1 Runtime .......................... 20 5.2.2.2 Logic Testing ....................... 20 5.2.2.3 Side-Channel Analysis .................. 21 6 Countermeasures 23 6.1 Data Guards .................................. 23 6.1.1 Generic Guards ............................ 23 6.1.2 Specific Bus Guards ......................... 25 6.2 Novel RTL-Level Architectures ........................ 26 6.3 Reconfigurable Architectures ......................... 28 6.4 Replication, Fragmentation, and Voting ................... 29 7 Summary 32 References 33 viii UNCLASSIFIED UNCLASSIFIED DSTO–TN–1012 Glossary AES Advanced Encryption Standard symmetric cryptography algorithm ATA AT Attachment bus standard AFRL Air Force Research Laboratories ALU Arithmetic Logic Unit AMBA Advanced Micro-controller Bus Architecture ASIC Application Specific Integrated Circuit CAD Computer Aided Design CLB Configurable Logic Block CMOS Complementary Metal-Oxide-Semiconductor COTS Commercial-Off-The-Shelf CPU Central Processing Unit CSAW Cyber Security Awareness Week DES Data Encryption Standard symmetric cryptography algorithm DMA Direct Memory Access DoS Denial of Service DSP Digital Signal Processor DARPA Defense Advanced Research Programs Agency EDA Electronic Design Automation EM Electron Migration EMI Electro-Magnetic Interference FPGA Field programmable Gate Array HCI Hot Carrier Injection HDL Hardware Description Language IC Integrated Circuit IO Input/Output IP Intellectual Property JTAG Joint Test Action Group specified IC test interface UNCLASSIFIED ix DSTO–TN–1012 UNCLASSIFIED NBTI Negative Bias Temperature Instability OB Oxide Breakdown PCIe Peripheral Component Interconnect Express RF Radio Frequency RSA An encryption algorithm developed by Rivest, Shamir, and Adleman RTL Register Transfer Level
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