Course Outline • Prerequisites – COMPXXXX Data structures and algorithms • Stacks, queues, hash tables, lists, trees, heaps, . Introduction – COMPXXXX Microprocessor and Interfacing • Assembly programming • Mapping of high level procedural language to assembly language COMP3231/9201/3891/9283 • Interrupts (Extended) Operating Systems – You are expected to be competent programmers!!!! • We will be using the C programming language Kevin Elphinstone – The dominant language for OS implementation. – Need to understand pointers, pointer arithmetic, explicit memory allocation. 2
Why does this fail? Lectures • Common for all courses (3231/3891/9201/9283) void func(int *x, int *y) • Wednesday, 1 3pm, Elec Eng G25 { • Thursday, 1 2pm, Webster Theatre A *x = 1; *y = 2; – Extended OS Thursday 2 3pm Webster 250 • starts in week 2 } – The lecture notes will be available on the course web site void main() • Available prior to lectures, when possible. { • Slide numbers for note taking – The lecture notes and textbook are NOT a substitute for int *a, *b; attending lectures. func(a,b); printf(“%d %d\n”,*a,*b);
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Tutorials Assignments • Start in week 2 • Assignments form a substantial component of your assessment. • A tutorial participation mark will • They are challenging!!!! contribute to your final assessment. – Because operating systems are challenging – Participation means participation, NOT • We will be using OS/161, attendance. – an educational operating system – Comp3891/9283 students excluded – developed by the Systems Group At Harvard – It contains roughly 20,000 lines of code and – Comp9201 optional comments • You will only get participation marks in your enrolled tutorial. 5 6
1 Assignments Assignments • Assignments are in pairs • Don’t under estimate the time needed to do the – Info on how to pair up available soon assignments. • We usually offer advanced versions of the • If you start a couple days before they are due, you assignments will be late. – Available bonus marks are small compared to amount of • To encourage you to start early, effort required. – Bonus 10% of max mark of the assignment for finishing a – Student should do it for the challenge, not the marks. week early – Attempting the advanced component is not a valid excuse – To iron out any potential problems with the spec, 5% bonus for failure to complete the normal component of the for finishing within 48 hours of assignment release. assignment – See course handout for exact details • Extended OS students (COMP3891/9283) are • Read the fine print!!!! expected to attempt the advanced assignments
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Assignments Assignments
• Three assignments • Late penalty – due roughly week 3, 6, 11 – 4% of total assignment value per day • The first one is trivial • Assignment is worth 20% • You get 18, and are 2 days late – It’s a warm up to have you familiarize • Final mark = 18 – (20*0.04*2) = 16 (16.4) yourself with the environment and easy marks. • Assignments are only accepted up to – Do not use it as a gauge for judging the one week late. 8+ days = 0 difficulty of the following assignments.
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Assignments Plagiarism
• To help you with the assignments • We take cheating seriously!!! – We dedicate a tutorial per assignment to • We systematically check for plagiarised code discuss issues related to the assignment – Penalties are generally sufficient to make it difficult – Prepare for them!!!!! to pass
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2 Cheating Statistics Exams
Session 1998/S1 1999/S1 2000/S1 2001/S1 2001/S2 2002/S1 2002/S2 2003/S1 2003/S2 enrolment 178 410 320 300 107 298 156 333 133 • There is NO mid session suspected cheaters 10(6%) 26(6%) 22(7%) 26(9%) 20(19%) 15(5%) ???(?%) 13 (4%) ???(?%) • The final written exam is 2 hours full penalties * * * * 2 6 9 14 10 9 5 2 1 reduced penalties 7 15 7 7 5 4 2 2 9 • Supplementary exams are oral . cheaters failed 4 10 16 16 10 12 5 4 ? cheaters – Supplementaries are available according to suspended 0 0 1 0 0 1 0 0 0 UNSW & school policy, not as a second chance.
*Note: Full penalty 0 FL not applied prior to 2001/S1 13 14
Assessment 3891/9283
• Exam Mark • Class Mark • No tutorial participation component Component Component • Assignment marks scaled to 100 – Max mark of 100 – Max mark of 100 • Based solely on the • 10% tutorial final exam participation • 90% Assignments
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9201 Undergrad Assessment
• Optional tutorial participation, we’ll • The final assessment is the harmonic award the better mark of mean of the exam and class – Tutorial participation included as for component. comp3231 • If E >= 40, – Class marked based solely on the assignments 2EC M = E + C
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3 Postgrads (9201/9283) Assessment • Maximum of a 50/50 weighted harmonic mean and a 20/80 harmonic mean • If E < 40 – Can weight final mark heavily on exam if you can’t commit the time to the assignments – You are rewarded for seriously attempting the assignments 2EC M = min44, • if E >= 40, E + C 2EC 5EC M = max( E+C , E+4C )
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Harmonic Mean (Class Mark = 100 - Exam Mark) Final M ark = 50
100 100
90 90
80 80
70 70 Harm 50/50 60 60 Arith 50/50 Harm 50/50 50 50 Arith 20/80 Harm 20/80
Final Mark Final 40 Harm 20/80 40 30 30
20 20 ExamMark Required to Pass 10 10
0 0 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 Exam Mark Class Mark
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Assessment Textbook
• You need to perform reasonably • Andrew consistently in both exam and class Tanenbaum, components. Modern Operating • Harmonic mean only has significant Systems, 3rd effect with significant variation. Edition, Prentice Hall • Reserve the right to scale, and scale courses individually if required. – Warning: We have not scaled in the past.
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4 References Consultations/Questions
• A. Silberschatz and P.B. Galvin, Operating System Concepts , • Questions should be directed to the forum. th th th 5 , 6 , or 7 edition, Addison Wesley • Admin related queries to Nicholas Fitzroy Dale • William Stallings, Operating Systems: Internals and Design Principles, 4th or 5 th edition, Prentice Hall. [email protected] • A. Tannenbaum, A. Woodhull, Operating Systems--Design and • Personal queries can be directed to me Implementation , 2 nd edition Prentice Hall [email protected] • John O'Gorman, Operating Systems , MacMillan, 2000 • We reserve the right to ignore email sent directly to • Uresh Vahalla, UNIX Internals: The New Frontiers , Prentice us (including tutors) if it should have been directed to Hall, 1996 the forum. • McKusick et al., The Design and Implementation of the 4.4 BSD Operating System , Addison Wesley, 1996 • Consultation Times – TBA
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Course Outline Course Outline
• “the course aims to educate students in • Processes and threads the basic concepts and components of • Concurrency control operating systems, the relevant • Memory Management characteristics of hardware, and the tradeoffs between conflicting objectives • File Systems faced by operating systems in efficiently • I/O and Devices supporting a wide range of • Security applications.” • Scheduling
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Learning Outcomes
• High level understand what is an Introduction to Operating operating system and the role it plays Systems • Appreciate the evolution of operating systems tracks the evolution of Chapter 1 – 1.3 hardware, and that evolution is repeated in each new hardware era.
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5 What is an Operating System?
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Viewing the Operating System as an Abstract Disk Users Machine • Extends the basic hardware with added Memory functionality
• Provides high level abstractions CPU – More programmer friendly – Common core for all applications Network • It hides the details of the hardware Bandwidth – Makes application code portable
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Dated View: the Operating Viewing the Operating System System as the Privileged as a Resource Manager Privileged Mode Component • Responsible for allocating resources to users and processes Operating System • Must ensure – No Starvation – Progress Requests Applications – Allocation is according to some desired policy • First come, first served; Fair share; Weighted fair share; (System Calls) limits (quotas), etc User Mode – Overall, that the system is efficiently used Applications Applications
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6 The Operating System is Why Study Operating Privileged Systems? • Applications should not be able to interfere or bypass • There are many interesting problems in the operating system operating systems. – OS can enforce the “extended machine” • For a complete, top to bottom view of a – OS can enforce its resource allocation policies system. – Prevent applications from interfering with each other • Understand performance implications of application behaviour. • Note: Some Embedded OSs have no privileged component, e.g. PalmOS • Understanding and programming large, – Can implement OS functionality, but cannot enforce it. complex, software systems is a good skill to • Note: Some operating systems implement significant acquire. OS functionality in user mode, e.g. User mode Linux 37 38
Second Generation Machines (A brief) Operating System History • Largely parallels hardware Batch Systems development • IBM 7094 • First Generation machines – 0.35 MIPS, 32K x 36 bit memory – Vacuum tubes – 3.5 million dollars – Plug boards • Programming via wiring • Batching used to more • Users were simultaneously efficiently use the designers, engineers, and hardware programmers – Share machine amongst • “single user” many users • difficult to debug (hardware) – One at a time – No Operating System – Debugging a pain • Drink coffee until jobs finished 39 40
Batch System Issue: Keeping Batch Operating Systems Systems Busy • Reading tapes or punch cards was time • Sometimes called “resident job monitor” consuming • Managed the Hardware • Expensive CPU was idle waiting for input • Simple Job Control Language (JCL) – Load compiler – Compile job – Run job – End job • No resource allocation issues
– “one user” 41 42
7 Third Generation Systems - Multiprogramming Example Multiprogramming • Divided memory among several loaded jobs Memory • While one job is loading, CPU works on another Job 1 • With enough jobs, CPU 100% busy Job 2 • Needs special hardware to isolate memory partitions from each other Job 3 – This hardware was notably absent on early batch systems OS 43 44
Job turn-around time was Time sharing still an issue. • Batch systems were well suited to • Each user had his/her own terminal – Scientific calculations connected to the machine – Data processing • All user’s jobs were multiprogrammed • For programmers, debugging was much – Regularly switch between each job – Do it fast easier on older first gen. machines as the programmer had the machine to • Gives the illusion that the programmer has the machine to himself himself. • Early examples: Compatible Time • Word processing on a batch system? Sharing System (CTSS), MULTICS 45 46
The Advent of the PC An then… • Large Scale Integration (LSI) made small, • Further developments (hardware and fast( ish), cheap computers possible software) resulted in improved techniques, • OSs followed a similar path as with the concepts, and operating systems .. mainframes – CAP, Hydra, Mach, UNIX V6, BSD UNIX, THE, – Simple “single user” systems (DOS) Thoth, Sprite, Accent, UNIX SysV, Linux, EROS, – Multiprogramming without protection, (80286 era, KeyKOS, OS/360, VMS, HPUX, Apollo Domain, Window 3.1, 95, 98, ME, etc , MacOS <= 9) Nemesis, L3, L4, CP/M, DOS, Exo kernel, Angel, Mungi, BE OS, Cache Kernel, Choices, V, Inferno, – “Real” operating systems (UNIX, WinNT, MacOS Grasshopper, MOSIX, Opal, SPIN, VINO, OS9, X etc..) Plan/9, QNX, Synthetix, Tornado, x kernel, VxWorks, Solaris . 47 48
8 Operating System Time Line
Computer Hardware Review
Chapter 1.4
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Learning Outcomes Operating Systems
• Understand the basic components of • Exploit the hardware available computer hardware • Provide a set of high level services that – CPU, buses, memory, devices controllers, represent or are implemented by the DMA, Interrupts, hard disks hardware. • Understand the concepts of memory • Manages the hardware reliably and hierarchy and caching, and how they efficiently affect performance. • Understanding operating systems requires a basic understanding of the underlying hardware 51 52
Basic Computer Elements Basic Computer Elements • CPU – Performs computations – Load data to/from memory via system bus • Device controllers – Control operation of their particular device – Operate in parallel with CPU – Can also load/store to memory (Direct Memory Access, DMA) – Control register appear as memory locations to CPU • Or I/O ports – Signal the CPU with “interrupts” • Memory Controller – Responsible for refreshing dynamic RAM – Arbitrating access between different devices and CPU
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9 The real world is logically similar, A Simple Model of CPU but a little more complex Computation • The fetch execute cycle
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A Simple Model of CPU A Simple Model of CPU Computation Computation • Stack Pointer • The fetch execute cycle CPU Registers CPU Registers • Status Register – Load memory contents from – Condition codes address in program counter • Positive result PC: 0x0300 (PC) PC: 0x0300 • Zero result SP: 0xcbf3 • The instruction SP: 0xcbf3 • Negative result Status – Execute the instruction Status • General Purpose Registers R1 – Increment PC R1 – Holds operands of most – Repeat instructions Rn Rn – Enables programmers to minimise memory references. 57 58
‘Safe’ registers and Privileged-mode Operation CPU Registers instructions • To protect operating system Interrupt Mask • Registers and instructions are safe if execution, two or more CPU Exception Type – Only affect the state of the application itself modes of operation exist MMU regs – Privileged mode (system , Others – They cannot be used to uncontrollably kernel mode) PC: 0x0300 interfere with • All instructions and registers are SP: 0xcbf3 • The operating system available Status • Other applications – User mode R1 • Uses ‘safe’ subset of the – They cannot be used to violate a correctly instruction set – E.g. no disable interrupts Rn implemented operating system policy. instruction
• Only ‘safe’ registers are 59 60 accessible
10 Privileged-mode Operation I/O and Interrupts Address Space • I/O events (keyboard, mouse, incoming network • The accessibility of 0xFFFFFFFF packets) happen at unpredictable times Accessible only • How does the CPU know when to service an I/O addresses within an to event? address space Kernel mode changes depending 0x80000000 on operating mode – To protect kernel code Accessible to and data User and Kernel mode
0x00000000 61 62
Interrupts Interrupt Cycle • An interruption of the normal sequence of execution • Processor checks for interrupts • A suspension of processing caused by an event • If no interrupts, fetch the next instruction external to that processing, and performed in • If an interrupt is pending, divert to the such a way that the processing can be resumed. interrupt handler • Improves processing efficiency – Allows the processor to execute other instructions while an I/O operation is in progress – Avoids unnecessary completion checking (polling)
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Classes of Interrupts Interrupt Handler
• Program exceptions • A software routine that determines the (also called synchronous interrupts ) nature of the interrupt and performs – Arithmetic overflow whatever actions are needed. – Division by zero – Executing an illegal/privileged instruction • Control is transferred to the handler by – Reference outside user’s memory space. hardware . • Asynchronous (external) events • The handler is generally part of the – Timer operating system. – I/O
– Hardware or power failure 65 66
11 Memory Hierarchy Simple Interrupt • Going down the hierarchy Application – Decreasing cost per User Mode bit – Increasing capacity – Increasing access time – Decreasing Kernel Mode frequency of access to the memory by the processor Interrupt • Hopefully Handler • Principle of locality!!!!! 67 68
Cache Memory Hierarchy Word Transfer Block Transfer CPU Cache Main Memory • Rough approximation of memory hierarchy Registers
• Cache is fast memory placed between the CPU and main memory – 1 to a few cycles access time compared to RAM access time of tens – hundreds of cycles • Holds recently used data or instructions to save memory accesses. • Matches slow RAM access time to CPU speed if high hit rate • Is hardware maintained and (mostly) transparent to software • Sizes range from few kB to several MB. • Usually a hierarchy of caches (2–5 levels), on and off chip. • Block transfers can achieve higher transfer bandwidth than single words. – Also assumes probability of using newly fetch data is higher than the probability of reuse ejected data.
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Processor-DRAM Gap (latency) Moving-Head Disk Mechanism Proc 1000 CPU 60%/yr. “Moore’s Law” 100 Processor-Memory Performance Gap: (grows 50% / year) 10 DRAM
Performance DRAM 7%/yr. 1 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 Time 71 72
Slide originally from Dave Patterson, Parcon 98
12 A Strategy: Avoid Waiting for Example Disk Access Times Disk Access • Disk can read/write data relatively fast • Keep a subset of the disk’s data in – 15,000 rpm drive 80 MB/sec memory – 1 KB block is read in 12 microseconds cache • Access time dominated by time to locate the ⇒ Main memory acts as a of disk head over data contents – Rotational latency • Half one rotation is 2 milliseconds – Seek time • Full inside to outside is 8 milliseconds • Track to track .5 milliseconds • 2 milliseconds is 164KB in “lost bandwidth” 73 74
Two-level Memories and Hit Effective Access Time Rates • Given a two level memory, – cache memory and main memory (RAM) – main memory and disk Teff = H × T1 + (1 − H) × (T1 + T2) T what is the effective access time? 1 = access time of memory 1 T2 = access time of memory 2 H = hit rate in memory 1
• Answer: It depends on the hit rate in the Teff = effective access time of system first level.
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Example • Cache memory access time 1ns • Main memory access time 10ns • Hit rate of 95%
9 Teff = 0.95 × 1 × 10− + 9 9 0.05 × (1 × 10− + 10 × 10− ) 9 = 1.5 × 10−
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