Early Evaluation of the Cray XT3 at ORNL Highlights
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Introducing the Cray XMT
Introducing the Cray XMT Petr Konecny Cray Inc. 411 First Avenue South Seattle, Washington 98104 [email protected] May 5th 2007 Abstract Cray recently introduced the Cray XMT system, which builds on the parallel architecture of the Cray XT3 system and the multithreaded architecture of the Cray MTA systems with a Cray-designed multithreaded processor. This paper highlights not only the details of the architecture, but also the application areas it is best suited for. 1 Introduction past two decades the processor speeds have increased several orders of magnitude while memory speeds Cray XMT is the third generation multithreaded ar- increased only slightly. Despite this disparity the chitecture built by Cray Inc. The two previous gen- performance of most applications continued to grow. erations, the MTA-1 and MTA-2 systems [2], were This has been achieved in large part by exploiting lo- fully custom systems that were expensive to man- cality in memory access patterns and by introducing ufacture and support. Developed under code name hierarchical memory systems. The benefit of these Eldorado [4], the Cray XMT uses many parts built multilevel caches is twofold: they lower average la- for other commercial system, thereby, significantly tency of memory operations and they amortize com- lowering system costs while maintaining the sim- munication overheads by transferring larger blocks ple programming model of the two previous genera- of data. tions. Reusing commodity components significantly The presence of multiple levels of caches forces improves price/performance ratio over the two pre- programmers to write code that exploits them, if vious generations. they want to achieve good performance of their ap- Cray XMT leverages the development of the Red plication. -
Cray XD1™ Supercomputer Release 1.3
CRAY XD1 DATASHEET Cray XD1™ Supercomputer Release 1.3 ■ Purpose-built for HPC — delivers exceptional application The Cray XD1 supercomputer combines breakthrough performance interconnect, management and reconfigurable computing ■ Affordable power — designed for a broad range of HPC technologies to meet users’ demands for exceptional workloads and budgets performance, reliability and usability. Designed to meet ■ Linux, 32 and 64-bit x86 compatible — runs a wide variety of ISV the requirements of highly demanding HPC applications applications and open source codes in fields ranging from product design to weather prediction to ■ Simplified system administration — automates configuration and scientific research, the Cray XD1 system is an indispensable management functions tool for engineers and scientists to simulate and analyze ■ Highly reliable — monitors and maintains system health faster, solve more complex problems, and bring solutions ■ Scalable to hundreds of compute nodes — high bandwidth and to market sooner. low latency let applications scale Direct Connected Processor Architecture Cray XD1 System Highlights The Cray XD1 system is based on the Direct Connected Processor (DCP) architecture, harnessing many processors into a single, unified system to deliver new levels of application � � � ���� � � � Compute� � � Processors performance. ���� � Cray’s implementation of the DCP architecture optimizes message-passing applications by 12 AMD Opteron™ 64-bit single directly linking processors to each other through a high performance interconnect fabric, or dual core processors run eliminating shared memory contention and PCI bus bottlenecks. Linux and are organized as six nodes of 2 or 4-way SMPs to deliver up to 106 GFLOPS* per chassis. Matching memory and I/O performance removes bottlenecks and maximizes processor performance. -
Merrimac – High-Performance and Highly-Efficient Scientific Computing with Streams
MERRIMAC – HIGH-PERFORMANCE AND HIGHLY-EFFICIENT SCIENTIFIC COMPUTING WITH STREAMS A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY Mattan Erez May 2007 c Copyright by Mattan Erez 2007 All Rights Reserved ii I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. (William J. Dally) Principal Adviser I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. (Patrick M. Hanrahan) I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. (Mendel Rosenblum) Approved for the University Committee on Graduate Studies. iii iv Abstract Advances in VLSI technology have made the raw ingredients for computation plentiful. Large numbers of fast functional units and large amounts of memory and bandwidth can be made efficient in terms of chip area, cost, and energy, however, high-performance com- puters realize only a small fraction of VLSI’s potential. This dissertation describes the Merrimac streaming supercomputer architecture and system. Merrimac has an integrated view of the applications, software system, compiler, and architecture. We will show how this approach leads to over an order of magnitude gains in performance per unit cost, unit power, and unit floor-space for scientific applications when compared to common scien- tific computers designed around clusters of commodity general-purpose processors. -
Cray XT and Cray XE Y Y System Overview
Crayyy XT and Cray XE System Overview Customer Documentation and Training Overview Topics • System Overview – Cabinets, Chassis, and Blades – Compute and Service Nodes – Components of a Node Opteron Processor SeaStar ASIC • Portals API Design Gemini ASIC • System Networks • Interconnection Topologies 10/18/2010 Cray Private 2 Cray XT System 10/18/2010 Cray Private 3 System Overview Y Z GigE X 10 GigE GigE SMW Fibre Channels RAID Subsystem Compute node Login node Network node Boot /Syslog/Database nodes 10/18/2010 Cray Private I/O and Metadata nodes 4 Cabinet – The cabinet contains three chassis, a blower for cooling, a power distribution unit (PDU), a control system (CRMS), and the compute and service blades (modules) – All components of the system are air cooled A blower in the bottom of the cabinet cools the blades within the cabinet • Other rack-mounted devices within the cabinet have their own internal fans for cooling – The PDU is located behind the blower in the back of the cabinet 10/18/2010 Cray Private 5 Liquid Cooled Cabinets Heat exchanger Heat exchanger (XT5-HE LC only) (LC cabinets only) 48Vdc flexible Cage 2 buses Cage 2 Cage 1 Cage 1 Cage VRMs Cage 0 Cage 0 backplane assembly Cage ID controller Interconnect 01234567 Heat exchanger network cable Cage inlet (LC cabinets only) connection air temp sensor Airflow Heat exchanger (slot 3 rail) conditioner 48Vdc shelf 3 (XT5-HE LC only) 48Vdc shelf 2 L1 controller 48Vdc shelf 1 Blower speed controller (VFD) Blooewer PDU line filter XDP temperature XDP interface & humidity sensor -
Pubtex Output 2006.05.15:1001
Cray XD1™ Release Description Private S–2453–14 © 2006 Cray Inc. All Rights Reserved. Unpublished Private Information. This unpublished work is protected to trade secret, copyright and other laws. Except as permitted by contract or express written permission of Cray Inc., no part of this work or its content may be used, reproduced or disclosed in any form. U.S. GOVERNMENT RESTRICTED RIGHTS NOTICE The Computer Software is delivered as "Commercial Computer Software" as defined in DFARS 48 CFR 252.227-7014. All Computer Software and Computer Software Documentation acquired by or for the U.S. Government is provided with Restricted Rights. Use, duplication or disclosure by the U.S. Government is subject to the restrictions described in FAR 48 CFR 52.227-14 or DFARS 48 CFR 252.227-7014, as applicable. Technical Data acquired by or for the U.S. Government, if any, is provided with Limited Rights. Use, duplication or disclosure by the U.S. Government is subject to the restrictions described in FAR 48 CFR 52.227-14 or DFARS 48 CFR 252.227-7013, as applicable. Autotasking, Cray, Cray Channels, Cray Y-MP, GigaRing, LibSci, UNICOS and UNICOS/mk are federally registered trademarks and Active Manager, CCI, CCMT, CF77, CF90, CFT, CFT2, CFT77, ConCurrent Maintenance Tools, COS, Cray Ada, Cray Animation Theater, Cray APP, Cray Apprentice2, Cray C++ Compiling System, Cray C90, Cray C90D, Cray CF90, Cray EL, Cray Fortran Compiler, Cray J90, Cray J90se, Cray J916, Cray J932, Cray MTA, Cray MTA-2, Cray MTX, Cray NQS, Cray Research, Cray SeaStar, Cray S-MP, -
Cray XT3/XT4 Software
Cray XT3/XT4 Software: Status and Plans David Wallace Cray Inc ABSTRACT: : This presentation will discuss the current status of software and development plans for the CRAY XT3 and XT4 systems. A review of major milestones and accomplishments over the past year will be presented. KEYWORDS: ‘Cray XT3’, ‘Cray XT4’, software, CNL, ‘compute node OS’, Catamount/Qk processors, support for larger system configurations (five 1. Introduction rows and larger), a new version of SuSE Linux and CFS Lustre as well as a host of other new features and fixes to The theme for CUG 2007 is "New Frontiers ," which software deficiencies. Much has been done in terms of reflects upon how the many improvements in High new software releases and adding support for new Performance Computing have significantly facilitated hardware. advances in Technology and Engineering. UNICOS/lc is 2.1 UNICOS/lc Releases moving to new frontiers as well. The first section of this paper will provide a perspective of the major software The last twelve months have been very busy with milestones and accomplishments over the past twelve respect to software releases. Two major releases months. The second section will discuss the current status (UNICOS/lc 1.4 and 1.5) and almost weekly updates have of the software with respect to development, releases and provided a steady stream of new features, enhancements support. The paper will conclude with a view of future and fixes to our customers. UNICOS/lc 1.4 was released software plans. for general availability in June 2006. A total of fourteen minor releases have been released since last June. -
The Gemini Network
The Gemini Network Rev 1.1 Cray Inc. © 2010 Cray Inc. All Rights Reserved. Unpublished Proprietary Information. This unpublished work is protected by trade secret, copyright and other laws. Except as permitted by contract or express written permission of Cray Inc., no part of this work or its content may be used, reproduced or disclosed in any form. Technical Data acquired by or for the U.S. Government, if any, is provided with Limited Rights. Use, duplication or disclosure by the U.S. Government is subject to the restrictions described in FAR 48 CFR 52.227-14 or DFARS 48 CFR 252.227-7013, as applicable. Autotasking, Cray, Cray Channels, Cray Y-MP, UNICOS and UNICOS/mk are federally registered trademarks and Active Manager, CCI, CCMT, CF77, CF90, CFT, CFT2, CFT77, ConCurrent Maintenance Tools, COS, Cray Ada, Cray Animation Theater, Cray APP, Cray Apprentice2, Cray C90, Cray C90D, Cray C++ Compiling System, Cray CF90, Cray EL, Cray Fortran Compiler, Cray J90, Cray J90se, Cray J916, Cray J932, Cray MTA, Cray MTA-2, Cray MTX, Cray NQS, Cray Research, Cray SeaStar, Cray SeaStar2, Cray SeaStar2+, Cray SHMEM, Cray S-MP, Cray SSD-T90, Cray SuperCluster, Cray SV1, Cray SV1ex, Cray SX-5, Cray SX-6, Cray T90, Cray T916, Cray T932, Cray T3D, Cray T3D MC, Cray T3D MCA, Cray T3D SC, Cray T3E, Cray Threadstorm, Cray UNICOS, Cray X1, Cray X1E, Cray X2, Cray XD1, Cray X-MP, Cray XMS, Cray XMT, Cray XR1, Cray XT, Cray XT3, Cray XT4, Cray XT5, Cray XT5h, Cray Y-MP EL, Cray-1, Cray-2, Cray-3, CrayDoc, CrayLink, Cray-MP, CrayPacs, CrayPat, CrayPort, Cray/REELlibrarian, CraySoft, CrayTutor, CRInform, CRI/TurboKiva, CSIM, CVT, Delivering the power…, Dgauss, Docview, EMDS, GigaRing, HEXAR, HSX, IOS, ISP/Superlink, LibSci, MPP Apprentice, ND Series Network Disk Array, Network Queuing Environment, Network Queuing Tools, OLNET, RapidArray, RQS, SEGLDR, SMARTE, SSD, SUPERLINK, System Maintenance and Remote Testing Environment, Trusted UNICOS, TurboKiva, UNICOS MAX, UNICOS/lc, and UNICOS/mp are trademarks of Cray Inc. -
Overview of the Next Generation Cray XMT
Overview of the Next Generation Cray XMT Andrew Kopser and Dennis Vollrath, Cray Inc. ABSTRACT: The next generation of Cray’s multithreaded supercomputer is architecturally very similar to the Cray XMT, but the memory system has been improved significantly and other features have been added to improve reliability, productivity, and performance. This paper begins with a review of the Cray XMT followed by an overview of the next generation Cray XMT implementation. Finally, the new features of the next generation XMT are described in more detail and preliminary performance results are given. KEYWORDS: Cray, XMT, multithreaded, multithreading, architecture 1. Introduction The primary objective when designing the next Cray XMT generation Cray XMT was to increase the DIMM The Cray XMT is a scalable multithreaded computer bandwidth and capacity. It is built using the Cray XT5 built with the Cray Threadstorm processor. This custom infrastructure with DDR2 technology. This change processor is designed to exploit parallelism that is only increases each node’s memory capacity by a factor of available through its unique ability to rapidly context- eight and DIMM bandwidth by a factor of three. switch among many independent hardware execution streams. The Cray XMT excels at large graph problems Reliability and productivity were important goals for that are poorly served by conventional cache-based the next generation Cray XMT as well. A source of microprocessors. frustration, especially for new users of the current Cray XMT, is the issue of hot spots. Since all memory is The Cray XMT is a shared memory machine. The programming model assumes a flat, globally accessible, globally accessible and the application has access to shared address space. -
INNOVATION for HPC AMD Launches Opteron 6300 Series X86 & Announces 64-Bit ARM Strategy
HPC Advisory Council Switzerland Conference 2013 ROBERTO DOGNINI – HEAD OF COMMERCIAL SALES EMEA MARCH 2013 AGENDA AMD & HPC Opteron 6300 Is AMD out of the server game ? What’s changing.... and roadmap... Products Q&A 2 INNOVATION FOR HPC AMD Launches Opteron 6300 Series x86 & Announces 64-bit ARM Strategy AMD Launches Worlds First 16- Core x86 Server Processor 2012 AMD Opteron Cray ORNL “Titan” Powers First x86 2011 Ranks #1 on Top500 PetaFlop Supercomputer AMD Achieves 2010 Sixth # 1 Spot in Last AMD Launches First x86 Dual- Five Years AMD Launches Core Opteron 2009 Opteron processor processor • First 64-bit x86 • Direct-Connect 2008 24 of the 50 Fastest 2007 Supercomputers on Top500 using 2006 AMD Opteron™ 2005 Top500 # 1 & 2 AMD Technology 2004 processors Power 2003 IBM “Roadrunner” Fastest #1 Cray “Jaguar” #2 Supercomputers in 11 Countries Cray/Sandia Cray Introduces “Red Storm” Rank #2 Cray “Jaguar” Reaches Cray XD1 based on Top500 with on AMD #1 on Top500 & AMD AMD Opteron™ Technology Powers 4 of Opteron™ processors The Top 5 Systems processor 3 3 TODAY: NEW AMD OPTERON™ 6300 SERIES PROCESSORS OPTIMIZED FOR HPC TCO AMD Opteron™ 6300 Series Processors Scalable Performance Energy Efficient Cost Effective . Scalability under heavy load – . Up to 40% higher performance . Low acquisition costs maintain SLAs at peak times per watt than previous generation . The right performance at the . Record-breaking Java right price performance1 . Flexible power management 4 AMD OPTERON™ BULLDOZER MODULE Dedicated Shared at the Shared at the Components module level chip level Fetch Decode Int Int FP Scheduler Scheduler Scheduler Core 1 Core 2 bit bit - - FMAC FMAC 128 128 Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline L1 DCache L1 DCache Shared L2 Cache Shared L3 Cache and NB 5 COMPETITIVE PERFORMANCE – 2P SPECFP Perf Per $ 2 x Abu Dhabi 6380 $0.19 2 x SandyBridge E5-2670 $0.16 2 x Abu Dhabi 6386 SE $0.16 2 x SandyBridge E5-2690 $0.12 4 socket... -
Titan Introduction and Timeline Bronson Messer
Titan Introduction and Timeline Presented by: Bronson Messer Scientific Computing Group Oak Ridge Leadership Computing Facility Disclaimer: There is no contract with the vendor. This presentation is the OLCF’s current vision that is awaiting final approval. Subject to change based on contractual and budget constraints. We have increased system performance by 1,000 times since 2004 Hardware scaled from single-core Scaling applications and system software is the biggest through dual-core to quad-core and challenge dual-socket , 12-core SMP nodes • NNSA and DoD have funded much • DOE SciDAC and NSF PetaApps programs are funding of the basic system architecture scalable application work, advancing many apps research • DOE-SC and NSF have funded much of the library and • Cray XT based on Sandia Red Storm applied math as well as tools • IBM BG designed with Livermore • Computational Liaisons key to using deployed systems • Cray X1 designed in collaboration with DoD Cray XT5 Systems 12-core, dual-socket SMP Cray XT4 Cray XT4 Quad-Core 2335 TF and 1030 TF Cray XT3 Cray XT3 Dual-Core 263 TF Single-core Dual-Core 119 TF Cray X1 54 TF 3 TF 26 TF 2005 2006 2007 2008 2009 2 Disclaimer: No contract with vendor is in place Why has clock rate scaling ended? Power = Capacitance * Frequency * Voltage2 + Leakage • Traditionally, as Frequency increased, Voltage decreased, keeping the total power in a reasonable range • But we have run into a wall on voltage • As the voltage gets smaller, the difference between a “one” and “zero” gets smaller. Lower voltages mean more errors. -
Taking the Lead in HPC
Taking the Lead in HPC Cray X1 Cray XD1 Cray Update SuperComputing 2004 Safe Harbor Statement The statements set forth in this presentation include forward-looking statements that involve risk and uncertainties. The Company wished to caution that a number of factors could cause actual results to differ materially from those in the forward-looking statements. These and other factors which could cause actual results to differ materially from those in the forward-looking statements are discussed in the Company’s filings with the Securities and Exchange Commission. SuperComputing 2004 Copyright Cray Inc. 2 Agenda • Introduction & Overview – Jim Rottsolk • Sales Strategy – Peter Ungaro • Purpose Built Systems - Ly Pham • Future Directions – Burton Smith • Closing Comments – Jim Rottsolk A Long and Proud History NASDAQ: CRAY Headquarters: Seattle, WA Marketplace: High Performance Computing Presence: Systems in over 30 countries Employees: Over 800 BuildingBuilding Systems Systems Engineered Engineered for for Performance Performance Seymour Cray Founded Cray Research 1972 The Father of Supercomputing Cray T3E System (1996) Cray X1 Cray-1 System (1976) Cray-X-MP System (1982) Cray Y-MP System (1988) World’s Most Successful MPP 8 of top 10 Fastest First Supercomputer First Multiprocessor Supercomputer First GFLOP Computer First TFLOP Computer Computer in the World SuperComputing 2004 Copyright Cray Inc. 4 2002 to 2003 – Successful Introduction of X1 Market Share growth exceeded all expectations • 2001 Market:2001 $800M • 2002 Market: about $1B -
Tour De Hpcycles
Tour de HPCycles Wu Feng Allan Snavely [email protected] [email protected] Los Alamos National San Diego Laboratory Supercomputing Center Abstract • In honor of Lance Armstrong’s seven consecutive Tour de France cycling victories, we present Tour de HPCycles. While the Tour de France may be known only for the yellow jersey, it also awards a number of other jerseys for cycling excellence. The goal of this panel is to delineate the “winners” of the corresponding jerseys in HPC. Specifically, each panelist will be asked to award each jersey to a specific supercomputer or vendor, and then, to justify their choices. Wu FENG [email protected] 2 The Jerseys • Green Jersey (a.k.a Sprinters Jersey): Fastest consistently in miles/hour. • Polka Dot Jersey (a.k.a Climbers Jersey): Ability to tackle difficult terrain while sustaining as much of peak performance as possible. • White Jersey (a.k.a Young Rider Jersey): Best "under 25 year-old" rider with the lowest total cycling time. • Red Number (Most Combative): Most aggressive and attacking rider. • Team Jersey: Best overall team. • Yellow Jersey (a.k.a Overall Jersey): Best overall supercomputer. Wu FENG [email protected] 3 Panelists • David Bailey, LBNL – Chief Technologist. IEEE Sidney Fernbach Award. • John (Jay) Boisseau, TACC @ UT-Austin – Director. 2003 HPCwire Top People to Watch List. • Bob Ciotti, NASA Ames – Lead for Terascale Systems Group. Columbia. • Candace Culhane, NSA – Program Manager for HPC Research. HECURA Chair. • Douglass Post, DoD HPCMO & CMU SEI – Chief Scientist. Fellow of APS. Wu FENG [email protected] 4 Ground Rules for Panelists • Each panelist gets SEVEN minutes to present his position (or solution).