Control Related Instructions - Jumps Control Related Instructions - Branches

• jr rs ; jump register: PC Å Regs[rs] • beq rs, rt, offset ; branch on equal: if (Regs[rs] = Regs[rt]) then PCÅ [PC]+4+ 14-bit sign extend || offset || 2 zero-bits • jalr rs,rd ; jump and link register: else PCÅ[PC]+4 Regs[rd] Å [PC]+4; PC Å Regs[rs] • bne rs, rt, offset ; branch on not equal: if (Regs[rs] != Regs[rt]) • j jump_target ; jump inside 256 MB region: then PCÅ[PC]+4+ 14-bit sign extend || offset || 2 zero-bits else PCÅ[PC]+4 PC low order 28 bits Å jump_target || 2 zero-bits • bgez rs, offset ; branch on greater or equal zero: if (Regs[rs] ≥ 0) • jal jump_target ; jump inside 256 MB region and link: then PCÅ[PC]+4+ 14-bit sign-extend || offset || 2 zero-bits Regs[31] Å [PC]+4 else PCÅ[PC]+4 PC low order 28 bits Å jump_target || 2 zero-bits Plus: bgtz, blez, bltz g. babic Presentation B 25 g. babic Presentation B 26

Illustration of MIPS Addressing Modes Special Control - Related Instructions

1. Immediate addressing • syscall ; to cause a syscall exception op rs rt Immediate Encoding: 000000 00000000000000000000 001100

2. Register addressing op rs rt rd . . . funct Registers Register • break ; to cause a break exception 3. Base addressing offset op rs rt Address Memory Encoding: 000000 00000000000000000000 001101

Register + Halfword Word • teq rs, rt ; exception if equal: if (Regs[rs] == Regs[rt]) 4. PC-relative addressing op rs rt offsetAddress Memory then trap exception

PC + Word • tlti rs, immediate ; trap exception if less than immediate: if (Regs[rs] < 48-bit sign-extend || immediate

5. Pseudodirect addressing op jump_targetAddress Memory then trap exception

PC Word • eret ; return from exception

Figure 2.24 Plus: several additional conditional trap instructions g. babic Presentation B 27 g. babic Presentation B 28 CPU Modes and Address Spaces Privilege Instructions

There are two processor (CPU) modes of operation: When operating in User Mode, processor has access only to the • Kernel (Supervisor) Mode and CPU and FPU registers, while when operating in Kernel Mode, • User Mode processor has access to the full capabilities of processor The processor is in Kernel Mode when CPU mode bit in Status including CP0 registers. register is set to one. The processor enters Kernel Mode at Privileged instructions can not be executed when the processor power-up, or as result of an , exception, or error. is in User mode, i.e. they can be executed only when the The processor leaves Kernel Mode and enters User Mode processor is in Kernel mode when the CPU mode bit is set to zero (by some instruction). Examples of MIPS privileged instructions: space is divided in two ranges (simplified): • any instruction that accesses Kernel address space, • User address space • mfc0 – move word from CP0 to CPU, – addresses in the range [0 – 7FFFFFFF ] • mtc0 – move word to CP0 from CPU, 16 • lwc0 – load (from memory) word into CP0, • Kernel address space • swc0 – store (into memory) word from CP0. – addresses in the range [8000000016 – FFFFFFFF16]

g. babic Presentation B 29 g. babic Presentation B 30

MIPS Exceptions: A Subset Exceptions by External Causes

There are four sets of causes for an exception. A. Exceptions caused by hardware malfunctioning: • Machine Check: Processor detects internal inconsistency; Reset • Error: on a load or store instruction, or instruction fetch;

B. Exceptions caused by some external causes (to the processor): IRQ 1 • Reset: A asserted on the appropriate pin; • NMI: A rising edge of NMI signal asserted on an appropriate pin; NMI • Hardware : Six hardware interrupt requests can be made via asserting signal on any of 6 external pins. Hardware interrupts can be masked by setting appropriate bits in Status register; g. babic Presentation B 31 g. babic Presentation B 32 MIPS Exceptions: A Subset (continued) MIPS Exception Processing

C. Exceptions that occur as result of instruction problems: When any of the exceptions previously listed occurs, MIPS • Address Error: a reference to a nonexistent memory segment, processor processes the exception in the following 3 steps: or a reference to Kernel address space from User Mode; Step 1. • Reserved Instruction: A undefined opcode field (or privileged instruction in User mode) is executed; • EPC register gets a value equal to either: – address of a faulty instruction if the instruction itself caused • Integer Overflow: An integer instruction results in a 2’s exception (e.g. address error, reserved instruction) or complement overflow; detected hardware malfunctioning (e.g. bus error), • Floating Point Error: FPU signals one of its exceptions, e.g. – address of the next instructions which would have been divide by zero, overflow, and underflow) executed, in all other cases. D. Exceptions caused by executions of special instructions: Additionally, in the case of the address error, BadVAddr • Syscall: A Syscall instruction executed; register gets value of the invalid address. • Break: A Break instruction executed;

• Trap: A condition tested by a trap instruction is true; 33 g. babic Presentation B 34

MIPS Exception Processing (continued) Dual-Mode of CPU Operation

Step 2. (Simplified) • CPU mode bit added to to indicate the •PC Å 8000018016 current CPU mode: 1 (=kernel) or 0 (=user). – next instruction executed is at the location 80000180 16 • When an exception or interrupt or fault occurs CPU hardware • Cause register Å a code of the exception switches to the kernel mode. – Each exception has its code, e.g.: • hardware interrupt = 0 Exception/Interrupt/Fault • illegal memory address (load/fatch or store) = 4 or 5 • bus error (fetch or load/store)= 6 or 7 • syscall instruction execution = 8 kernel user • illegal op-code, i.e. reserved or undefined op-code= 10 set user mode • integer overflow = 12 • Floating point exception = 15 Step 3. Privileged instructions can be executed only in kernel mode. • Processor is now in Kernel mode, i.e. CPU mode bit Å 1;

g. babic Presentation B 35 g. babic Presentation B 36 • Problem for bonus points: • Problem: OS loads the routine at the

• OS loads the exception handling routine at the address 8100 address 8100 000816. What else should be done so this routine is activated each time an exception happens? Your solution 000816. What else should be done so this routine is activated each time an exception happens? Your solution should include should include instructions. instructions.

• Answer by e-mail by Monday 11:00 •Answer:Memory location 8000018016 should contain instruction j 40000216 i.e.

mem location 80000180 Æ 000010 00 0100 0000 0000 0000 0000 0010 j 0 4 0 0 0 0 2

2 • Effect of j instrcuction: PC Å [PC31..28] || [I25..0] || 0

•PC Å 1000 0001 0000 0000 0000 0000 0000 1000 8 1 0 0 0 0 0 8

g. babic Presentation B 37 g. babic Presentation B 38

Comments: -sll instruction is noop instruction -Add srav, srlv, sllv - mention two branch and link instructions - consider adding few fp instructions.

g. babic Presentation B 39