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IBM Redbooks Advanced POWER Virtualization on IBM Eserver p5 Servers: Architecture and Performance Considerations Detailed description of the POWER5 architecture In-depth analysis of Advanced POWER Virtualization features Performance analysis and application tuning Ben Gibbs, Balaji Atyam, Frank Berres, Bruno Blanchard, Lancelot Castillo, Pedro Coelho, Nicolas Guerin, Lei Liu, Cesar Diniz Maciel, Carlos Sosa, Ravikiran Thirumalai ibm.com/redbooks International Technical Support Organization Advanced POWER Virtualization on IBM Eserver p5 Servers: Architecture and Performance Considerations November 2005 SG24-5768-01 Note: Before using this information and the product it supports, read the information in “Notices” on page ix. Second Edition (November 2005) This edition applies to IBM ^ p5 servers that include the POWER5 microprocessor architecture and the IBM AIX 5L Version 5.3 operating system. © Copyright International Business Machines Corporation 2005. All rights reserved. Note to U.S. Government Users Restricted Rights -- Use, duplication or disclosure restricted by GSA ADP Schedule Contract with IBM Corp. Contents Notices . ix Trademarks . x Preface . xi The specialists who wrote this redbook . xii Become a published author . xv Comments welcome. xv Chapter 1. Introduction. 1 1.1 Performance tuning redefined . 3 1.1.1 Understanding performance . 3 1.1.2 Performance considerations . 6 Chapter 2. IBM POWER5 architecture . 9 2.1 Introduction . 10 2.2 Chip design . 12 2.3 POWER5 enhancements . 13 2.4 POWER5 instruction pipelines . 14 2.4.1 Instruction fetching . 15 2.4.2 Branch prediction . 16 2.4.3 Instruction decoding and preprocessing . 17 2.4.4 Group dispatch . 17 2.4.5 Register renaming. 18 2.4.6 Instruction execution . 19 2.5 Caches . 21 2.5.1 Level 2 (L2) cache. 25 2.5.2 Level 3 (L3) cache. 27 2.5.3 Summary of caches on POWER5. 30 2.5.4 Address translation resources. 30 2.6 Timing facilities . 31 2.7 Dynamic power management . 33 2.8 Processor Utilization Resource Register (PURR) . 34 2.9 Large POWER5 SMPs . 36 2.10 Summary . 40 Chapter 3. Simultaneous multithreading . 41 3.1 What is multithreading?. 42 3.2 POWER5 simultaneous multithreading features . 44 3.2.1 Dynamic switching of thread states. 46 © Copyright IBM Corp. 2005. All rights reserved. iii 3.2.2 Snooze and snooze delay. 47 3.3 Controlling priority of threads . 49 3.3.1 Dynamic resource balancing (DRB) . 49 3.3.2 Adjustable thread priorities . 50 3.3.3 Thread priority implementation . 52 3.4 Software considerations . 55 3.4.1 Simultaneous multithreading aware scheduling . 55 3.4.2 Thread priorities on AIX 5L V5.3 . 56 3.4.3 Thread priorities on Linux . 58 3.4.4 Cache effects . 58 3.5 Simultaneous multithreading performance . 59 3.5.1 Engineering and scientific applications . 59 3.5.2 Simultaneous multithreading benchmarks . 61 3.6 Summary . 71 Chapter 4. POWER Hypervisor. 73 4.1 POWER Hypervisor implementation . 76 4.1.1 POWER Hypervisor functions . 79 4.1.2 Micro-Partitioning extensions . 85 4.1.3 POWER Hypervisor design. 87 4.2 Performance considerations . 90 Chapter 5. Micro-Partitioning . 93 5.1 Partitioning on the IBM eServer p5 systems . 94 5.2 Micro-Partitioning implementation . 96 5.2.1 Virtual processor dispatching . 104 5.2.2 Phantom interrupts . 112 5.3 Performance considerations . 115 5.3.1 Micro-Partitioning considerations . 116 5.3.2 Locking considerations . 121 5.3.3 Memory affinity considerations . 126 5.3.4 Idle partition consideration . 127 5.3.5 Application considerations in Micro-Partitioning . 128 5.3.6 Micro-Partitioning planning guidelines . 133 5.4 Summary . 142 Chapter 6. Virtual I/O. 143 6.1 Introduction . 144 6.2 POWER Hypervisor support for virtual I/O . 145 6.2.1 Virtual I/O infrastructure . 147 6.2.2 Types of connections . 149 6.3 The IBM Virtual I/O Server . 152 6.3.1 Providing high availability support. 156 6.4 Virtual Serial Adapter (VSA) . 163 iv Advanced POWER Virtualization on IBM Eserver p5 Servers 6.5 Virtual Ethernet . 164 6.5.1 Virtual LAN . 164 6.5.2 Virtual Ethernet connections . 169 6.5.3 Benefits of virtual Ethernet . 170 6.5.4 Limitations and considerations . 171 6.5.5 POWER Hypervisor switch implementation . 171 6.5.6 Performance considerations . 174 6.5.7 VLAN throughput at different processor entitlements . 176 6.5.8 Comparing throughput of VLAN to physical Ethernet . 178 6.5.9 Comparing CPU utilization . 180 6.5.10 Comparing transaction rate and latency . 182 6.5.11 VLAN performance . 183 6.5.12 VLAN implementation guidelines . 185 6.6 Shared Ethernet Adapter. 186 6.6.1 Shared Ethernet Adapter performance.
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