Volume 3, Issue 2

Our featured article “Design and Verifi cation verifi cation of Low Power Designs,” focuses on the problem of how to verify low- HORIZONS power designs. see page 5 A QUARTERLY PUBLICATION OF MENTOR GRAPHICS Q2 ‘07—VOL. 3, ISSUE 2 Welcome to our super-sized DAC issue of Verifi cation Horizons. Clock Domain Crossing...page 10 By Tom Fitzpatrick, Editor Discusses formal verification of multiple clock and Verifi cation Technologist domains using our CDC solution. Read more Complex Clock Modeling...page 13 Our new VeloceTM emulator assists in verifying In addition to all the fun I get to have at just a bit further. Just as baseball starts with designs with multiple clock domains. Read more work, I’m also the coach of my 9 year-old a set of rules, verifi cation starts (or at least Advancing the AVM...page 16 son’s baseball team. So, it is with somewhat should start) with a Verifi cation Plan that lays Introduce AVM 3.0, which upgrades the mixed emotions that I welcome DAC back to functionality and usability of the AVM. Read more its traditional early-June time slot. In other words, it’s now smack dab in the midst of Processor Driven Testbenches... “In the case of baseball season—a problem we avoided last page 20 Discussing Questa’s use of actual Verifi cation Horizons, year by having DAC in July. The good news is processor code to stimulate the design. Read more success is defi ned that I’ll miss only one game; the bad news in terms of providing Solving the Verification IP Re-Use is it’ll be the last game of the season. Oh well, Paradox...page 23 Resource scheduling at least I’ll make it back in time for the playoffs. interesting, educational capability in Questa. Read more and sometimes enter- I’m reminded of coaching a group of 9 taining articles for Bringing Visibility to Verification and 10 year-olds when I think of the process Management...page 26 How to manage of putting together a publication such as your enjoyment and all of the information now generated. Read more Verifi cation Horizons. This is not, in any way, edifi cation.” to suggest that our contributing authors behave OVL & VSI Article Updates... in any way like children. Rather, I think of it —Tom Fitzpatrick pages 30 & 31 Two brief articles to update more in terms of taking a group of individuals you on the status of some key standards-based and guiding, encouraging and possibly cajoling issues. Read more them into contributing to the success of the out the goals and the processes to follow. Verification for Companies Large team. In the case of Verifi cation Horizons, Then, just as players must hit, throw and and Small...page 32 Helping startup success is defi ned in terms of providing catch to play the game, the job of verifi cation companies entering the world of “advanced interesting, educational and sometimes engineers is to deploy their tools and meth- verification”. Read more entertaining articles for your enjoyment and odologies to do the verifi cation. Progress in baseball is measured by scoring runs. Denali VIP + Mentor AVM...page 37 edifi cation. If I do say so myself, we’ve got Progress in verifi cation is measured via Best-in-Class Functional Verification with a championship-caliber roster for this issue. functional coverage and other metrics. One of SystemVerilog. Read more With apologies to those of you unfamiliar my jobs as coach is to keep score and make with baseball, I’m going to stretch this analogy strategic decisions about where to position A QUARTERLY PUBLICATION OF MENTOR GRAPHICS players in the fi eld, whether to bunt or steal, in large part to contributions from AVM users. We’ve also got two brief articles to update and things of that nature. As a verifi cation This is just one of the advantages of having you on the status of some key standards- manager, you also need to keep score and made the AVM open-source, and I’m sure based issues. The fi rst discusses recent make strategic decisions about where to focus you’ll see more information along these lines advances and activity in the Accellera OVL resources and, ultimately, when to tape-out. in the weeks and months ahead. committee, where they’ve been working From the technology perspective, the In addition to the AVM, Questa also provides towards the release of OVL v2.0. The other two keys to verifi cation are 1) the ability to two unique ways of generating interesting article is an overview of the VSIA Quality IP generate more information about whether the and useful stimulus. In “Considerations for (VSI-QIP) metric, which lets you measure and design conforms to the spec (hopefully while Effective Implementation of Processor Driven ensure the reusability of IP components. minimizing the effort of the verifi cation team), Testbenches,” we discuss Questa’s ability to In our “Partners’ Corner” section, we’re and 2) the ability to manage that information to use actual processor code to stimulate the proud to feature two articles from some of guide the verifi cation process to a successful design, giving you the ability to reuse the code our earliest AVM partners. Our friends at (and quick) conclusion. The more information in simulation and on the actual hardware. XtremeEDA share their experience of helping a that is generated, the more important Combining this stimulus source with existing startup company enter the world of “advanced verifi cation management becomes. You’ll functional coverage and other metrics gives verifi cation” by incrementally adopting pieces notice these themes repeatedly throughout this you a measure of the effectiveness of these of the AVM, laying the groundwork for more issue. “live target” tests, which were previously success in the future. And our friends at Denali Our feature article this time around, “Design unmeasurable when the code was only run tell how they used the AVM to verify their and Verifi cation of Low Power Designs,” on the actual hardware. Similarly, when code PureSpec VIP library, and how that not only focuses on the problem of how to verify low- is found to fail on the hardware in the lab, it improves the quality of PureSpec but also power designs. These verifi cation concerns are can now be run in simulation and debugged makes it easier for you to use in your AVM discussed in the context of the Unifi ed Power much more easily, including single-stepping environment. through the processor code while also having Format (UPF) for specifying power-related So, batter up! I hope you’ll fi nd plenty of full visibility into the behavior of the RTL information. The UPF helps tools like Questa useful information in this issue, and keep in through Questa’s powerful integrated debug model the functional effects of low-power mind the important aspects of verifi cation environment. design techniques, such as clock domains and as you’re wandering through that vast maze clock gating, as well as the management of The next new strategy for stimulus that we call DAC. Remember, it’s all about distinct power islands. This theme is carried generation is discussed in the next article, gathering information about what your design through in our next two articles that discuss which describes our new Questa Algorithmic is doing and how it behaves under the broadest formal verifi cation of multiple clock domains Testbench Synthesis capability. The basics set of scenarios; being able to model those using our CDC solution and introduce our new of this technology were discussed in our scenarios as succinctly and automatically as Veloce emulator, which assists in verifying February issue. This article shows how the possible; and managing all of the information designs with multiple clock domains. Each of resource scheduling capability in Questa so you can answer the two most important these tools provides more information about allows you to take disparate block-level verifi cation questions that everyone asks: the ability of your design to handle these testbenches and automatically coordinate their “Does it work?” and “Are we done?” Then give various low-power strategies. activity at the system level to ensure maximum your mind a chance to unwind and go watch Another form of information required by coverage with minimal engineering time. The some kids play baseball. verifi cation is the ability to model and exercise last of our new technology articles in this issue deals with the problem of how to manage all various scenarios of behavior – what we Respectfully submitted, of the information you’re now able to generate, typically call “stimulus generation.” As one Tom Fitzpatrick as outlined in the previous articles. Questa of the authors of the Advanced Verifi cation Verifi cation Technologist Methodology (AVM), I’m very pleased to 6.3 builds on our Unifi ed Coverage Database introduce AVM 3.0, which upgrades the (UCDB) to provide the ability to correlate all of functionality and usability of the AVM, thanks your coverage and results data back to your original verifi cation plan. 2 www.mentor.com Table of Contents Page 5...Design and Verification of Low Power Designs Verifi cation Horizons is a publication BY MINH CHAU, TEXAS INSTRUMENTS AND STEPHEN BAILEY, MENTOR GRAPHICS of Mentor Graphics Corporation, all rights reserved. Page 10...Clock Domain Crossing Verification Made Easy Editor: Tom Fitzpatrick BY RINDERT SCHUTTEN, 0-IN VERIFICATION PRODUCT MARKETING MANAGER, MENTOR GRAPHICS CORPORATION Program Manager: Rebecca Granquist Page 13...Mentor Graphics addresses complex clock modeling Wilsonville Worldwide Headquarters issues with new VeloceTM emulation technology.

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