Volume 4, Issue 1

Our Partners’ Corner article from our friends at Sibridge Technologies, one of our Questa Vanguard Partners see page 20 A QUARTERLY PUBLICATION OF MENTOR GRAPHICS Q1 ‘08—VOL. 4, ISSUE 1 Welcome back to Verification Horizons! By Tom Fitzpatrick, Editor and Verification Technologist OVM: Open Interoperable Verification...page 5 A more detailed description of some of the key features in the OVM. Read more. Before we get started, I must confess that it’s a bit difficult to concentrate on this Intelligent Testbench Automation issue since I’m still depressed by the Patriots’ Super Bowl loss. But at least I have my job — Now a Reality...page 9 to help take my mind off the pain. Actually, one of my favorite jobs is editing this newsletter, The results of a customer’s test case because I’m always impressed by the quality of the technology I get to share with you. where inFact is compared to their I hope you’ll share my excitement with this issue. established constrained-random Our first article, “OVM: Open Interoperable Verification,” provides a more detailed methodology. Read more. description of some of the key features in the Are You Missing Assertions? OVM that enable, promote, and encourage “...my dad, who was an ...page 12 the development of reusable verification Highlights a unique capability of our 0-In® components and environments. It also provides analog designer, used Formal technology. Read more. an update on the status of the OVM which to tell me “it’s an analog earlier this month received the IEC Design Debugging Synchronization world” to convince me Vision award at DesignCon, and includes a link Failures in Multi-Core Designs that the “digital stuff” where you can find even more detail, an OVM ...page 14 discussion forum, and the OVM source code I was learning would Highlights the challenges inherent in never be sufficient to debugging systems with multiple cores. to download for free! Read more. The product spotlight this issue focuses build everything. As Mark on our inFact™ Intelligent Testbench Twain said, “the older FPGA Design and Verification in Mechatronic Applications...page 16 Automation solution, continuing a series of I’ve gotten, the smarter Provides an introduction to VHDL-AMS, articles introducing and explaining this excit- my father has become.” a superset of VHDL that allows FPGA ing new technology. In “Intelligent Testbench —Tom Fitzpatrick designers the opportunity to model, Automation — Now a Reality, No Longer simulate and verify complete systems Just a Promise,” the inFact team shows the that include non-digital stuff. Read more. results of a customer’s test case in which inFact was compared against their established constrained-random methodology. I won’t spoil the surprise for you, so you’ll have to read the article. But the words “order of magnitude” and “wow” come to mind. “Are You Missing Assertions?” highlights a unique capability of our 0-In® Formal technology, which answers the question: “do I have enough assertions?” The answer is dependent on the interrelationship of the design and its assertions And last but not least, our Partners’ Corner article this — it’s not simply a function of the number of assertions, and it’s quarter comes from our friends at Sibridge Technologies, one more than assertions per line-of-code. The 0-In team has built of our Questa Vanguard Partners. As a fitting “bookend” to our into their tool the ability to properly analyze both the design and introductory article on the OVM, this article describes the smooth the assertions, then quantify the answer using a metric called process Sibridge went through to migrate their existing AVM-based “assertion density.” In addition to providing this metric, the tool Ethernet VIP components to use the OVM. As a member of the points to areas of your design that may need more assertions. OVM design team, I was gratified to see that a real customer Having great assertion coverage without an accompanying found it as easy as we’d designed it to be. measurement of assertion density is akin to being the best ski As the Patriots proved, you can’t win them all. But the Red Sox area in Kansas (a dubious distinction). are still champions, and Spring Training starts in just over a week. Our next product-focused article, “Debugging Synchronization All in all, a Boston sports fan can’t really complain, I suppose. Failures in Multi-Core Designs,” highlights the challenges inherent And on the work side of things, I think you’ll agree that this issue in debugging systems with multiple cores. Since most problems of Verification Horizons shows that Mentor’s winning streak stem from the synchronization between the independent cores, keeps going strong. the ability to isolate these issues is the key to fixing them. The Questa® integrated, multi-core code debugger provides source, variable, memory, and other views for each core in the system, Respectfully submitted, making it straightforward to see exactly what’s happening. When Tom Fitzpatrick you combine these expansive views of the state with Questa’s Verification Technologist ability to replay day-long simulations in a few seconds, suddenly the challenges of debugging such complex systems are no longer as daunting. Back in my college days, my dad, who was an analog designer, used to tell me “it’s an analog world” to convince me that the “digital stuff” I was learning would never be sufficient to build everything. As Mark Twain said, “the older I’ve gotten, the smarter my father has become.” Analog and mixed-signal systems, even for us HDL designers, are becoming more and more prevalent, especially in automotive and aerospace applications. Our technology article this quarter, “FPGA Design and Verification in Mechatronic Applications,” provides an introduction to VHDL-AMS, a superset of VHDL that allows FPGA designers the opportunity to model, simulate and verify complete systems that include non- digital stuff. Bringing these concepts into the HDL world extends proven design and verification methodologies to include these new aspects, as is being done at several companies. 2 Table of Contents Page 5 Verification Horizons is a publication of Mentor Graphics OVM: Open, Interoperable Verification Corporation, all rights reserved. by Tom Fitzpatrick, Mentor Graphics, and Tom Anderson, Cadence Design Systems, Inc. Editor: Tom Fitzpatrick Program Manager: Page 9 Rebecca Granquist Intelligent Testbench Automation— Senior Writer: Now a Reality, No Longer Just a Promise Todd Burkholder Jay O’Donnell, Product Applications Engineer, System-level Engineering Division, Mentor Graphics Wilsonville Worldwide Headquarters 8005 SW Boeckman Rd. Page 12 Wilsonville, OR 97070-7777 Are you missing assertions? Phone: 503-685-7000 by Ramesh Sathianathan, Director of Engineering, Verification, Mentor Graphics To subscribe visit: http://www.mentor.com/products Page 14 /fv/verification_news.cfm Debugging Synchronization Failures in Multi-Core Designs by Jim Kenney –Product Manager, System-level Engineering Division, Mentor Graphics Page 16 FPGA Design and Verification in Mechatronic Applications by Darrell A. Teegarden, Manager, System Modeling and Analysis Business Unit, Mentor Graphics Page 20 Migrating Ethernet VIP to OVM Is a Cinch By Rahul V. Shah, Director, ASIC Engineering Division, Sibridge Technologies 3 ...Open Interoperable Verification provides a more detailed description of some of the key features in the OVM that enable, promote, and encourage the development of reusable verification components and environments. 4 OVM: Open, Interoperable Verification by Tom Fitzpatrick, Mentor Graphics, and Tom Anderson, Cadence Design Systems, Inc. The previous issue of Verification Horizons [Q4’07, (available at: http:// The next aspect of the OVM is the introduction of a phased build www.mentor.com/07horizons) offered a brief introduction to the Open process for all components. In an extension of the AVM’s “construct- Verification Methodology (OVM), a joint development initiative between connect-configure” phasing mechanism for building environments, Mentor Graphics® and Cadence® Design Systems that provides the the OVM adds a few more explicit methods to manage the process first open, interoperable, SystemVerilog verification methodology in the of hierarchical instantiation of components. After construction of the industry. Built on the successful Advanced Verification Methodology top-level test/environment/component, a post_new() phase method is (AVM) from Mentor Graphics and the Universal Reuse Methodology called automatically by the OVM infrastructure. This in turn calls the (URM) from Cadence, the OVM brings the combined power of these two user-defined build() method in which each component instantiates its leading companies together to deliver on the promise of SystemVerilog. children and calls their build() methods in turn. After all components have This article presents more technical details about the OVM and provides been built (i.e., instantiated and allocated) hierarchically, the connect() an update on its status. method is automatically called to connect the components as desired. In the end_of_elaboration() phase, all connection bindings are checked and resolved, so that at the completion of end_of_elaboration(), the OVM KEY CONCEPTS environment is ready to run. The OVM provides a library of base classes, utilities, and other Since very few components would be useful without being able infrastructure to focus your efforts in applying SystemVerilog to the to communicate with other components in the

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