Hardware Evaluation of Estream Candidates
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Hardware Evaluation of eSTREAM Candidates Frank K. G¨urkaynak, Peter Luethi, Nico Bernold, Ren´eBlattmann,Victoria Goode, Marcel Marghitola, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner Integrated Systems Laboratory ETH Zurich 2. February 2006 Table of Contents 1 Overview 2 Methodology 3 Algorithms 4 Efficiency in Hardware 5 Results 6 Conclusions 2 / 28 Department of Information Technology Integrated Systems Laboratory and Electrical Engineering Zurich Algorithms that support only Profile-II Algorithms without any cryptological issues Algorithms which are not likely to get updates Once these are completed, look for additional algorithms that seem easy to implement. Implementing eSTREAM Candidates eSTREAM candidates (34) ABC Achterbahn CryptMT/Fubuki DECIM DICING DRAGON Edon80 F-FCSR Frogbit Grain HC-256 Hermes8 LEX MAG MICKEY Mir-1 MOSQUITO NLS Phelix Polar Bear POMARANCH Py Rabbit Salsa20 SFINKS SOSEMANUK SSS TRBDK3 YAEA Trivium TSC-3 VEST WG Yamb ZK-Crypt 3 / 28 Department of Information Technology Integrated Systems Laboratory and Electrical Engineering Zurich Algorithms without any cryptological issues Algorithms which are not likely to get updates Once these are completed, look for additional algorithms that seem easy to implement. Implementing eSTREAM Candidates eSTREAM candidates (12) ABC Achterbahn CryptMT/Fubuki DECIM DICING DRAGON Edon80 F-FCSR Frogbit Grain HC-256 Hermes8 LEX MAG MICKEY Mir-1 MOSQUITO NLS Phelix Polar Bear POMARANCH Py Rabbit Salsa20 SFINKS SOSEMANUK SSS TRBDK3 YAEA Trivium TSC-3 VEST WG Yamb ZK-Crypt Algorithms that support only Profile-II 3 / 28 Department of Information Technology Integrated Systems Laboratory and Electrical Engineering Zurich Algorithms which are not likely to get updates Once these are completed, look for additional algorithms that seem easy to implement. Implementing eSTREAM Candidates eSTREAM candidates (10) ABC Achterbahn CryptMT/Fubuki DECIM DICING DRAGON Edon80 F-FCSR Frogbit Grain HC-256 Hermes8 LEX MAG MICKEY Mir-1 MOSQUITO NLS Phelix Polar Bear POMARANCH Py Rabbit Salsa20 SFINKS SOSEMANUK SSS TRBDK3 YAEA Trivium TSC-3 VEST WG Yamb ZK-Crypt Algorithms that support only Profile-II Algorithms without any cryptological issues 3 / 28 Department of Information Technology Integrated Systems Laboratory and Electrical Engineering Zurich Once these are completed, look for additional algorithms that seem easy to implement. Implementing eSTREAM Candidates eSTREAM candidates (7) ABC Achterbahn CryptMT/Fubuki DECIM DICING DRAGON Edon80 F-FCSR Frogbit Grain HC-256 Hermes8 LEX MAG MICKEY Mir-1 MOSQUITO NLS Phelix Polar Bear POMARANCH Py Rabbit Salsa20 SFINKS SOSEMANUK SSS TRBDK3 YAEA Trivium TSC-3 VEST WG Yamb ZK-Crypt Algorithms that support only Profile-II Algorithms without any cryptological issues Algorithms which are not likely to get updates 3 / 28 Department of Information Technology Integrated Systems Laboratory and Electrical Engineering Zurich Implementing eSTREAM Candidates eSTREAM candidates (8) ABC Achterbahn CryptMT/Fubuki DECIM DICING DRAGON Edon80 F-FCSR Frogbit Grain HC-256 Hermes8 LEX MAG MICKEY Mir-1 MOSQUITO NLS Phelix Polar Bear POMARANCH Py Rabbit Salsa20 SFINKS SOSEMANUK SSS TRBDK3 YAEA Trivium TSC-3 VEST WG Yamb ZK-Crypt Algorithms that support only Profile-II Algorithms without any cryptological issues Algorithms which are not likely to get updates Once these are completed, look for additional algorithms that seem easy to implement. 3 / 28 Department of Information Technology Integrated Systems Laboratory and Electrical Engineering Zurich Implementing eSTREAM Candidates eSTREAM candidates (8) ABC Achterbahn CryptMT/Fubuki DECIM DICING DRAGON Edon80 F-FCSR Frogbit Grain HC-256 Hermes8 LEX MAG MICKEY Mir-1 MOSQUITO NLS Phelix Polar Bear POMARANCH Py Rabbit Salsa20 SFINKS SOSEMANUK SSS TRBDK3 YAEA Trivium TSC-3 VEST WG Yamb ZK-Crypt Algorithms that support only Profile-II Algorithms without any cryptological issues Algorithms which are not likely to get updates Once these are completed, look for additional algorithms that seem easy to implement. Compare against an AES core running in OFB mode 3 / 28 Department of Information Technology Integrated Systems Laboratory and Electrical Engineering Zurich Implementation platform/technology FPGA (which device?, how are the resources used?), ASIC (which technology?) Project schedule In this project All designs were implemented by a group of 4 students: with equal experience using a standard cell based ASIC design flow within 14 weeks Fair Comparison The following factors may have significant effect on the outcome of a hardware design: The experience of the designer 4 / 28 Department of Information Technology Integrated Systems Laboratory and Electrical Engineering Zurich Project schedule In this project All designs were implemented by a group of 4 students: with equal experience using a standard cell based ASIC design flow within 14 weeks Fair Comparison The following factors may have significant effect on the outcome of a hardware design: The experience of the designer Implementation platform/technology FPGA (which device?, how are the resources used?), ASIC (which technology?) 4 / 28 Department of Information Technology Integrated Systems Laboratory and Electrical Engineering Zurich In this project All designs were implemented by a group of 4 students: with equal experience using a standard cell based ASIC design flow within 14 weeks Fair Comparison The following factors may have significant effect on the outcome of a hardware design: The experience of the designer Implementation platform/technology FPGA (which device?, how are the resources used?), ASIC (which technology?) Project schedule 4 / 28 Department of Information Technology Integrated Systems Laboratory and Electrical Engineering Zurich Fair Comparison The following factors may have significant effect on the outcome of a hardware design: The experience of the designer Implementation platform/technology FPGA (which device?, how are the resources used?), ASIC (which technology?) Project schedule In this project All designs were implemented by a group of 4 students: with equal experience using a standard cell based ASIC design flow within 14 weeks 4 / 28 Department of Information Technology Integrated Systems Laboratory and Electrical Engineering Zurich Guidelines for design The provided C code has been used as a reference All synthesized algorithms include test structures No ROM macros were used Optional MAC support is not included All algorithms accept plaintext and deliver ciphertext Methodology Tools Description: Code written in VHDL Simulation: Mentor Graphics Modelsim 6.0c Logic Synthesis: Synopsys Design Vision-2004.12 Physical Design: Cadence SoC Encounter 4.1-usr4 Technology: UMC 0.25 µm 5-Metal CMOS 5 / 28 Department of Information Technology Integrated Systems Laboratory and Electrical Engineering Zurich Methodology Tools Description: Code written in VHDL Simulation: Mentor Graphics Modelsim 6.0c Logic Synthesis: Synopsys Design Vision-2004.12 Physical Design: Cadence SoC Encounter 4.1-usr4 Technology: UMC 0.25 µm 5-Metal CMOS Guidelines for design The provided C code has been used as a reference All synthesized algorithms include test structures No ROM macros were used Optional MAC support is not included All algorithms accept plaintext and deliver ciphertext 5 / 28 Department of Information Technology Integrated Systems Laboratory and Electrical Engineering Zurich The Team Sherlock Watson Nico Bernold Victoria Goode Ren´eBlattmann Marcel Marghitola 7th semester students of the Information Technologies and Electronics Department of the ETH Zurich. 6 / 28 Department of Information Technology Integrated Systems Laboratory and Electrical Engineering Zurich T Throughput in Gbits/s TpA Throughput per area in Gbits/s·mm2 E Energy per data item mJ/Gbits Performance Metrics Circuit performance will be measured by: A Total circuit area after synthesis in µm2 f Maximum clock rate in MHz P Power consumption in mW Radix Generated output bits per clock cycle 7 / 28 Department of Information Technology Integrated Systems Laboratory and Electrical Engineering Zurich Performance Metrics Circuit performance will be measured by: A Total circuit area after synthesis in µm2 f Maximum clock rate in MHz P Power consumption in mW Radix Generated output bits per clock cycle T Throughput in Gbits/s TpA Throughput per area in Gbits/s·mm2 E Energy per data item mJ/Gbits 7 / 28 Department of Information Technology Integrated Systems Laboratory and Electrical Engineering Zurich IV Key AES 32 128 128 128 Round Key Generator State Register (128 FF) (128 FF) Radix 3.12 32 32 32 32 8 8 8 8 FFs 265 32 32 8 8 8 8 2 A 300k µm Sbox Sbox Sbox Sbox 8 8 8 8 T 0.665 Gb/s Mixcolumns Output Advanced Encryption Standard More experience with implementing AES Highly optimized 32-bit datapath on-the-fly key generation 8 / 28 Department of Information Technology Integrated Systems Laboratory and Electrical Engineering Zurich Key 80 IV 64 Achterbahn 6 1 NLFSR A (22 FF) Filter A Plaintext 7 1 NLFSR B (23 FF) Filter B 7 1 1 Radix 1-16 NLFSR C (25 FF) Filter C 8 1 NLFSR D (26 FF) Filter D 1 8 1 FFs 285 NLFSR E (27 FF) Filter E 9 1 NLFSR F (28 FF) Filter F Combining Function R 2 NLSFR V (64 FF) A 191k-480k µm 1 9 1 NLFSR G (29 FF) Filter G 10 1 Ciphertext T 0.310-1.423 Gb/s NLFSR H (31 FF) Filter H Pro X Very good documentation and reference code X Good performance trade-off Con x Low throughput x Large area 9 / 28 Department of Information Technology Integrated Systems Laboratory and Electrical Engineering Zurich