A CMOS Pixel Sensor with 4-bit Column-Level ADCs for the ILD Vertex Detector L. , F. Morel, Ch. Hu-, Y. Hu Institut Pluridisciplinaire Hubert Curien, 23 rue Loess, 67037 Strasbourg, France

Contact: [email protected] [email protected]

ABSTRACT A 48 × 64 pixels prototype CMOS Pixel Sensor (CPS) integrated with 4-bit column-level, self triggered ADCs for the ILD Vertex Detector (VTX) outer layers was developed and fabricated in a 0.35 µm CMOS process with a pixel pitch of 35 µm. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation. The ADCs accommodating the pixel read out in a rolling shutter mode complete the conversion by performing a multi-bit/step approximation. The design was optimized for power saving at sampling frequency. INTRODUCTION

The ILD vertex detector (VTX) has two options. One of them (VTX-SL) features 5 equidistant single layers, while an alternative option (VTX-DL) features 3 double layers. Sensors equipping the innermost layer in both geometries should exhibit a single point resolution better than 3 µm associated to a very short integration time because of the beamstrahlung background. This requirement motivates an R&D effort concentrating on high read-out speed design. The sensors foreseen for the outer layers have less constrains in term of spatial resolution and read-out speed. A single point resolution of 3-4 µm combined with an integration time shorter than 100 µs are expected to constitute a valuable trade-off. In this case, the design effort focuses on minimizing the power consumption. A larger pixel pitch of 35 µm combined with a 4-bit ADC is proposed, therefore reducing the power consumption and keeping necessary spatial resolution. This work describes the design of prototype sensor (called MIMOSA 31), which is the first CMOS pixel sensor integrating column-level ADCs for the ILD-VTX outer layers. 5 single layers (VTX-SL) 3 double layers (VTX-DL) MIMOSA 31

Ana driver [7:0]  The architecture includes a pixel array of 48 columns of 64 pixels, column-level ADCs and peripheral digital read-out micro-circuit

 The pixels are read out in row by row rolling shutter mode r

e  Each pixel combines in-pixel amplification with a correlated double sampling operation, which has been well used in previous sensors

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 MIMOSA 26 designed for EUDET beam telescope

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a i B  ULTIMATE equipping the STAR-PXL sub-system  The digital read out is implemented with 8 to 1 multiplexer, serializing the outputs of the ADCs

Ref 4-bit Column-parallel ADC Buf  The setting parameters of the sensor are remotely programmable through the JTAG circuits

Latch Memory Buffer  The design efforts are focused on the column-level ADCs Mux 8:1 CTRL FSM_ser JTAG Column-Level ADC

Vref Vref  ADC Architecture  Comparator Offsetcancel Offsetcancel Latch  This ADC is based on a successive approximation register architecture  Output Offset Storage (OOS) stage Offsetcancel Comp Vinp Buf

 This architecture requires 4 cycles to complete one conversion  The buffer is used to improve the Preamp C0 Offsetcancel drive capability of the input Comp  Complete the conversion by performing a multi-bit/step approximation Vinm  The preamplifier is enabled by M9 to  A maximum of 4 bits for signals of small magnitude to only 2bits for large signals Offsetcancel Clk_comp turn off the current when appropriate En_amp Offsetcancel Vref Vref DAC Sample Phase1 Phase2 Phase3 Phase4  The dynamic latch uses a current source M14 to decrease the offset ( ~ 11×× 8 2 mV in post Monte-Carlo simulation) Clk_comp Clk_comp M3 M4 M7 M5 M6 M8

VO- VO+ 10×× VB1 M5 VD/A Comparator ClkADC M7 V VIN- VIN+ M3 M4 in Clk_fsm M1 M2 4 OUT FSM V + V - VIN- VIN+ 011× Sleepmask O O M1 M2 VIN S/H 010× En_amp M9 Offsetcancel Clk_comp V + Comp M6 M8 O RstADC 0011 Clk_comp M13 VB2 M10 Clock 0010 Comp Overthreshold Overthreshold VO- Manager 0001 VB M14 Gen ClkADC Overthreshold 0000 Vthreshold Sleepmask  Clock Manager Case1  Clock-gate the dynamic latch and digital state machine  The auto-zeroing and sampling operations are implemented asynchronously ClkADC (Clk_comp and Clk_fsm) during auto-zeroing Sleepmask  Power dissipation is scaled by clock-gating control between sleep-active conversions Overthreshold  Overthreshold signal is used to power-gate during bit- Clk_fsm cycling. If the first comparison result is high, the 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Clk_comp Overthreshold keeps high. Otherwise, it goes low ClkADC Case2 Auto-zero Bit-Cycle(3:0) Auto-zero Bit-Cycle(3:0) and sleeps the comparator and digital state machine Sample1 Sample2 ClkADC until the next conversion Sleepmask Overthreshold Reference buffer 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Clk_fsm CMOS switches ClkADC controlled by FSM Clk_comp Sleepmask Vref1 Offsetcancel  DAC RstADC  The DAC only generates 8 references, which is V Sample1,2 implemented by a switch multiplexer instead of a out Sleep Conversion Sleep Conversion capacitor network. For a pixel array, it requires 8 Sample1 Sample2 reference buffers to drive the total switched DACs. This approach significantly reduces the area and  S/H Circuit dynamic power consumption. Vref8  Pipelined stage to achieve high conversion speed  Dual CDS architecture to reduce the column offset SIMULATION RESULTS & CONCLUSION  Wide swing OTA Technology 0.35 μm 2P 4M CMOS Read Resolution 4/3/2 C 2nd CDS circuit f Active Area 35 × 545 μm2 M5 M6 Read Sample1 Sample2 CS M9 Input Range 16 mV (single-ended)

Vin C1 M7 M8 Calib Coffset Least Significant Bit (LSB) Voltage 1 mV Vout OTA VB1 VO Sample2 Sample1 Sampling Rate 6.25 MS/s (160 ns/conversion) Vref_ota Read C2 M3 M10 M4 Inactive Power (without hit) 486 μW @ 3V

1st CDS circuit Vref VIN- VIN+ Active Power (with hit) 714 μW @ 3V M1 M2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ClkADC The test of chip is being prepared and the preliminary test results will be shown. This is the Read first CMOS pixel sensor integrating column-level ADCs for the ILD-VTX outer layers. The Calib VB2 M11 Sample1 prototype sensor was designed with specifications of the full scale sensor, and therefore can Sample2 be easily extended in the future. REFERENCES [1] M. Winter et al., “Development of CMOS pixel sensors fully adapted to the ILD vertex detector requirements”, 2011 International Workshop on Future Linear Colliders (LCWS’11), Spain, Sep. 2011. [2] N. Verma and A. P. Chandrakasan, “An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes”, IEEE J. Solid-State Circuit, vol. 42, no. 6, pp. 1196-1205, Jun. 2007.