Arithmetic Circuits-2
• Multipliers – Array multipliers • Shifters – Barrel shifter – Logarithmic shifter
ECE 261 James Morizio 1 Binary Multiplication
M-1 N-1 X = Σ X 2i Y = Σ Y 2i i=0 i i=0 i Multiplicand Multiplier
Product Z = X * Y
N-1 M-1 = Σ (Σ X Y 2i+j ) i=0 j=0 i j Partial products • Product = Sum of partial products
ECE 261 James Morizio 2 Multiplication
1100 : 12 10 0101 : 5 • Example: 10
ECE 261 James Morizio 3 Multiplication
1100 : 12 10 0101 : 5 • Example: 10 1100
ECE 261 James Morizio 4 Multiplication
1100 : 12 10 0101 : 5 • Example: 10 1100 0000
ECE 261 James Morizio 5 Multiplication
1100 : 12 10 0101 : 5 • Example: 10 1100 0000 1100
ECE 261 James Morizio 6 Multiplication
1100 : 12 10 0101 : 5 • Example: 10 1100 0000 1100 0000
ECE 261 James Morizio 7 Multiplication
1100 : 12 10 0101 : 5 • Example: 10 1100 0000 1100 0000
00111100 : 60 10
ECE 261 James Morizio 8 Multiplication
1100 : 12 10 multiplicand 0101 : 5 • Example: 10 multiplier 1100 0000 partial 1100 products 0000
00111100 : 60 10 product
• M x N-bit multiplication – Produce N M-bit partial products – Sum these to produce M+N-bit product
ECE 261 James Morizio 9 The Binary Multiplication
1 0 1 0 1 0 Multiplicand 1 0 1 1 Multiplier
AND operation 1 0 1 0 1 0
1 0 1 0 1 0 Partial Products
0 0 0 0 0 0
+ 1 0 1 0 1 0
1 1 1 0 0 1 1 1 0
ECE 261 James Morizio 10 General Form
• Multiplicand: Y = (yM-1, yM-2, …, y 1, y 0)
• Multiplier: X = (xN-1, xN-2, …, x 1, x 0) M−1 N − 1 NM −− 11 P= y2j x 2 i = xy 2 ij+ • Product: ∑j ∑ i ∑∑ ij j=0 i = 0 ij == 00
y5 y4 y3 y2 y1 y0 multiplicand
x5 x4 x3 x2 x1 x0 multiplier
x0y5 x0y4 x0y3 x0y2 x0y1 x0y0
x1y5 x1y4 x1y3 x1y2 x1y1 x1y0
x2y5 x2y4 x2y3 x2y2 x2y1 x2y0 partial products x3y5 x3y4 x3y3 x3y2 x3y1 x3y0
x4y5 x4y4 x4y3 x4y2 x4y1 x4y0
x5y5 x5y4 x5y3 x5y2 x5y1 x5y0
p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 product
ECE 261 James Morizio 11 Dot Diagram • Each dot represents a bit
x0
partial products multiplier multiplier x
x15
ECE 261 James Morizio 12 The Array Multiplier
x3 x2 x1 x0 y0
x3 x2 x1 x0 Z0 y1
HA FA FA HA
Z1 x3 x2 x1 x0 y2
FA FA FA HA FA: Full adder x x x x Z2 3 2 1 0 y3 HA: Half adder (two inputs) FA FA FA HA Propagation delay = ? Z7 Z6 Z5 Z4 Z3
ECE 261 James Morizio 13 The MxN Array Multiplier — Critical Path
HA FA FA HA
FA FA FA HA Critical Path 1 Critical Path 2 Critical Path 1 & 2
FAFA FA HA
ECE 261 James Morizio 14 Carry-Save Multiplier
HA HA HA HA
HA FA FA FA Carries saved for next HAFA FA FA adder stage
HAFA FA HA Unique critical path
Trade offs?
ECE 261 James Morizio 15 Adder Cells in Array Multiplier
P V V DD DD A Ci
A P S A P
Ci A B B P V V DD DD P A
P Co Ci Ci C A i
P Identical Delays for Carry and Sum
ECE 261 James Morizio 16 Multiplier Floorplan
X3 X2 X1 X0
Y0 Y HA Multiplier Cell 1 C S C S C S C S Z0 FA Multiplier Cell
Y2 C S C S C S C S Z1 Vector Merging Cell
Y 3 C S C S C S C S X and Y signals are broadcasted Z2 through the complete array.
C C C C S S S S
Z7 Z6 Z5 Z4 Z3
ECE 261 James Morizio 17 Multipliers —Summary
• Optimization Goals Different Vs Binary Adder
• Once Again: Identify Critical Path
• Otherpossible techniques - Logarithmic versus Linear (Wallace tree multiplier) - Data encoding (Booth) - Pipelining
ECE 261 James Morizio 18 Comparators
• 0’s detector: A = 00…000 • 1’s detector: A = 11…111 • Equality comparator: A = B • Magnitude comparator: A < B
ECE 261 James Morizio 19 1’s & 0’s Detectors • 1’s detector: N-input AND gate • 0’s detector: NOTs + 1’s detector (N-input NOR)
A7 A 6 A3 A 5 A2 A allzeros 4 allones A A1 3 A A2 0
A1 A0
A7 A6
A5 A4
A3 allones A2
A1 A0
ECE 261 James Morizio 20 Equality Comparator • Check if each bit is equal (XNOR, aka equality gate) • 1’s detect on bitwise equality B[3] A[3] B[2] A[2] A = B B[1] A[1] B[0] A[0]
ECE 261 James Morizio 21 Magnitude Comparator • Compute B-A and look at sign • B-A = B + ~A + 1 • For unsigned numbers, carry out is sign bit A≤ B C B ≥ 3 N A B
A3 B2 A Z 2 A = B B1
A1 B0
A0
ECE 261 James Morizio 22 Shifters
• Logical Shift: – Shifts number left or right and fills with 0’s • 1011 LSR 1 = 0101 1011 LSL1 = 0110 • Arithmetic Shift: – Shifts number left or right. Rt shift sign extends • 1011 ASR1 = 1101 1011 ASL1 = 0110 • Rotate: – Shifts number left or right and fills with lost bits • 1011 ROR1 = 1101 1011 ROL1 = 0111
ECE 261 James Morizio 23 The Binary Shifter
Right nop Left One-bit shifts
Ai Bi
Ai-1 Bi-1
Bit-Slice i
ECE 261 James Morizio 24 Multi-bit Shifters
• Cascade one-bit shifters? • Complex, unwieldy, slow for larger number of shifts • Two other types of shifters – Barrel shifter – Logarithmic shifter
ECE 261 James Morizio 25 The Barrel Shifter
A3 B3 Shift by 0 to
Sh1 3 bits A2 B2
Sh2 : Data Wire A1 : Control Wire B1
Sh3
A0 B0
Sh0 Sh1 Sh2 Sh3
ECE 261 James Morizio 26 The Barrel Shifter
• Area dominated by wiring • Propagation delay is theoretically constant (at most one transmission gate), independent of shifter size, no. of shifts • Reality: Capacitance on buffer input α maximum shift width
ECE 261 James Morizio 27 4x4 barrel shifter
A3
A2
A1
A0
Sh0 Sh1 Sh2 Sh3 Buffer Width barrel ~ 2 p m M pm = metal/poly pitch M = no. of shifts
ECE 261 James Morizio 28 Logarithmic Shifter • Staged approach, e.g. 7 = 1 + 2 + 4, 5 = 1 + 0 + 4
• Shifter with maximum shift width M consists of log 2M stages Sh1 Sh1 Sh2 Sh2 Sh4 Sh4
A3 B3
B A2 2
A1 B1
A0 B0
ECE 261 James Morizio 29 0-7 bit Logarithmic Shifter
A 3 Out3
A 2 Out2
A 1 Out1
A 0 Out0
ECE 261 James Morizio 30 Funnel Shifter
• A funnel shifter can do all six types of shifts • Selects N-bit field Y from 2N-bit input – Shift by k bits (0 ≤ k < N) 2N-1 N-1 0 B C
offset + N-1 offset
Y
ECE 261 James Morizio 31 Funnel Shifter Operation
• Computing N-k requires an adder
ECE 261 James Morizio 32 Funnel Shifter Design 1 • N N-input multiplexers – Use 1-of-N hot select signals for shift amount
– nMOS pass transistor design (V t drops!) k[1:0]
left Inverters & Decoder
s3 s2 s1 s0 Y3
Y2
Z6 Y1
Z5 Y0
Z4 Z3 Z2 Z1 Z0
ECE 261 James Morizio 33 Funnel Shifter Design 2
k1 k0 • Log N stages of 2-input muxes left – No select decoding needed
Z0 Y0
Z1 Y1
Z2 Y2
Z3 Y3
Z4
Z5
Z6
ECE 261 James Morizio 34