Analog Applications Journal

Fourth Quarter, 2015

© Copyright 2015 Texas Instruments Incorporated. All rights reserved. Analog Applications Journal Contents Introduction ...... 3 Automotive Understanding frequency variations in the DCS-Control™ topology ...... 4 The DCS-Control™ topology is an example of an on-time based topology that efficiently provides the low-noise and fast-transient response needed in many automotive applications. This article presents operational details with application examples for this topology to explain the factors that cause frequency variation. Industrial VCM vs. VOUT plots for instrumentation amplifiers with two op amps ...... 8 Common issues with instrumentation amplifiers include distorted output waveforms, incorrect device gain, or ‘stuck’ outputs. This article introduces the VCM vs. VOUT plot and delivers a thorough treatment of the two op-amp topology. The internal node equations are derived and used to plot an internal amplifier’s input common-mode and output-swing limits as a function of the instrumentation amplifier’s common-mode voltage. A software tool that simulates the VCM vs. VOUT plot is also introduced. Common-mode transient immunity for isolated gate drivers...... 13 A gate driver with good common-mode transient immunity (CMTI) supports faster switching speeds. This article gives the background for a general pulse-width modulation (PWM) scheme, the transition loss associated with high switching frequency, and provides isolated gate-driver solutions that can reduce transition time losses. Pushing the envelope with high-performance digital-isolation technology...... 18 Traditional fiber-optic and magnetic isolation solutions can now be replaced with capacitive-based digital and analog devices for reinforced isolation applications. This article discusses key end applications that are driving cutting-edge innovations in isolation technology and benefitting from these innovations. Communications How to reduce current spikes at AC zero-crossing for totem-pole PFC...... 23 The current spikes at AC zero-crossing have prevented the totem-pole PFC from being widely adopted. The causes for current spikes are complicated: turn-on sequence, slow reverse recovery of a MOSFET’s body diode, large COSS of MOSFETs, sudden turn on of the active FET with almost 100% duty cycle, sudden turn on of the sync FET, and so on. Four scenarios for common problems are covered in this article. Then, a solution that significantly reduces current spikes and improves THD is presented with a timing analysis and performance waveforms. Personal Electronics Faster, cooler charging with dual chargers...... 27 Demands for higher charge current and smaller device size have increased the thermal management issues for chargers. This article describes how I-FET dual chargers, either in a parallel or cascade configuration as the application allows, gives better heat distribution for lower IC and case temperatures in addition to faster, cooler charging and longer device run times. TI Worldwide Technical Support ...... 31

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Texas Instruments 2 AAJ 4Q 2015 Analog Applications Journal Introduction

The Analog Applications Journal (AAJ) is a digest of technical analog articles published quarterly by Texas Instruments. Written with design engineers, engineering managers, system designers and technicians in mind, these “how-to” articles offer a basic understanding of how TI analog products can be used to solve various design issues and requirements. Readers will find tutorial information as well as practical engineering designs and detailed mathematical solutions as they relate to the following applications: • Automotive • Industrial • Communications • Enterprise Systems • Personal Electronics

AAJ articles include many helpful hints and rules of thumb to guide readers who are new to engineering, or engineers who are just new to analog, as well as the advanced analog engineer. Where applicable, readers will also find software routines and program structures and learn about design tools. These forward-looking articles provide valuable insights into current and future product solutions. However, this long-running digest also gives readers archival access to many articles about legacy technologies and solutions that are the basis for today’s products. This means the AAJ can be a relevant research tool for a very wide range of analog products, applications and design tools.

Texas Instruments 3 AAJ 4Q 2015 Analog Applications Journal Automotive Understanding frequency variation in the DCS-Control™ topology By Chris Glaser Applications Engineer

Introduction As explained in Reference 1, the timer (tON_MIN) is A common requirement in the automotive market is to responsible for providing a controlled switching frequency avoid interfering with the AM radio band or other sensitive by adjusting the on-time based on VIN and VOUT through electronics, such as sensors. One example for power Equation 1. supplies is setting their switching frequency above ~1.8 MHz VOUT in order to keep all noise at a higher frequency than the t = × 400 ns (1) ON V highest AM radio signals. IN If the frequency is set below the lowest radio signals, The 400-ns value sets the ideal switching frequency to then higher frequency harmonics would be in band and 2.5 MHz when the DCS-Control device is operating with possibly interfere. Most modern power supplies do not use the on-time set by the timer. However, due to circuit an actual oscillator to set their switching frequency, as in losses, propagation delays, and in some specific applica- traditional voltage- or current-mode control. Instead, tion conditions, operation does not always follow the either the on-time or off-time is controlled, which then on-time set by the timer. As a result, the frequency varies. provides a relatively constant operating frequency. The reasons for this variation are grouped together based DCS-Control™ topology is an example of an on-time on the duty cycle, ideally VOUT/VIN, at which the device based topology which efficiently provides the low-noise operates. and fast-transient response needed in many automotive Measured data explains the principles behind the applications. While its switching frequency does vary, this DCS-Control topology’s frequency variation. To better variation is understood, controlled, and usually sufficient explain the concepts, the TPS62130 (catalog version) was for automotive and other frequency-sensitive applications. chosen and it offers two switching frequencies: 2.5 MHz and 1.25 MHz. The 2.5-MHz data exactly matches the Application example TPS62130A-Q1 data because both converters offer the Figure 1 shows the basic block diagram of the 2.5-MHz setting. All data was taken on the evaluation DCS-Control topology used in a typical automotive info- module with a 2.2-µH inductor and two 22-µF output tainment device.[1, 2] capacitors (to overcome the DC bias effect).[3]

Figure 1. Block diagram of the DCS-Control™ topology in the TPS62130A-Q1 converter

Gate Control Driver

Direct Control VOS and Ramp Compensation

– FB Comparator Timer (tON_min) Error Amplifier +

VREF 0.8 V DCS-ControlTM Topology

Texas Instruments 4 AAJ 4Q 2015 Analog Applications Journal Automotive

Moderate duty cycles Figure 2. TPS62130 with a 5-V output In the typical application of converting the 12-V car battery to 5 V for universal serial bus (USB) ports, the 3.0 required duty cycle is not extremely high or low. Frequency variation in this case is very low because the 2.5 on- and off-times are not at their extremes. Figure 2 2.5 MHz_3 A shows the measured switching frequency, on-time, and 2.5 MHz_1 A off-time with a 5-V output voltage, two frequency settings, 2.0 and two different load currents. A moderate duty cycle refers to those input voltages above 9 V for the 2.5-MHz 1.5 setting and above 7 V for the 1.25-MHz setting. 1.25 MHz_3 A Figure 2b shows the reason behind the low levels of 1.0 1.25 MHz_1 A frequency variation. The on-time matches very well to the ideal on-time set by the timer and to Equation 1 for both Switching Frequency (MHz) 0.5 loads and frequency settings. The reasons for the small 0 frequency variation with moderate duty cycles are: over- 5 6 7 8 9 10 11 12 13 14 15 16 17 coming losses and propagation delays. Input Voltage (V) In Figure 2a, the frequency increases with heavier loads due to losses. Higher loads require slightly higher duty (a) Switching frequency cycles to overcome resistive losses in the circuit. Since the on-times are the same for both the 1-A load and 3-A load, 1000 the off-time is decreased to achieve the higher duty cycle 1.25 MHz_3 A_On_Time 900 (Figure 2c). The same on-time and a shorter off-time 1.25 MHz_1 A_On_Time results in a shorter period and higher frequency. 800 1.25 MHz_Ideal Also, the frequency decreases slightly with increasing 2.5 MHz_3 A_On_Time 700 input voltage. Because the on-time decreases with increas- 2.5 MHz_1 A_On_Time ing input voltage, fixed propagation delays in the device 600 2.5 MHz_Ideal

have a more significant effect on the achieved on-time for ime (ns) smaller on-time values. The timer sets the on-time to 500 achieve a certain frequency, but its output signal goes On-T 400 through the control and gate driver (shown in Figure 1) 300 before reaching the power transistors. This path takes some finite amount of time. For example, if a 200-ns 200 on-time is desired and the propagation delay is 20 ns, the 100 actual on-time is 220 ns, which is 10% higher than desired. 5 6 7 8 9 10 11 12 13 14 15 16 17 But, if the input voltage increases and the desired on-time Input Voltage (V) reduces to 100 ns, the same 20-ns delay produces a 20% (b) On-time increase in the actual on-time. This effect is further pronounced for low duty cycles. 600

High duty cycles 550 While a car battery nominally operates at ~12 V, transients from high-current loads, such as starting the engine, can 500 1.25 MHz_1 A_Off_Time 1.25 MHz_3 A_Off_Time reduce the battery voltage. To the power supply this 450 appears as a line transient, which means more advanced 400 regulation is required in some applications. As long as the 350 input voltage does not decrease below the level of the ime (ns) 2.5 MHz_1 A_Off_Time output voltage, the DCS-Control topology maintains 300 2.5 MHz_3 A_Off_Time output regulation during such line and load transients. Off-T 250

200

150

100 5 6 7 8 9 10 11 12 13 14 15 16 17 Input Voltage (V) (c) Off-time

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Figure 3 shows measured data for a 3.3-V output. When the input voltage of the converter drops, the duty cycle Figure 3. TPS62130 with a 3.3-V output increases. At high duty cycles, the switching frequency decreases due to losses and a minimum off-time. High 3.0 duty cycles refers to the left-most portion of Figures 2a and 3a where the switching frequency decreases from its 2.5 nominal value towards zero. 2.5 MHz_3 A High duty cycles demonstrate a minimum off-time in the 2.0 2.5 MHz_1 A topology. Since high duty cycles occur at a lower input voltage and higher output voltage, the energy stored in the 1.5 inductor during the on-time is lower. This outcome is 1.0 because there is much less voltage across the inductor. To 1.25 MHz_3 A maximize efficiency, a minimum off-time is included to 1.25 MHz_1 A 0.5 ensure that sufficient energy is delivered to the output. Switching Frequency (MHz) This is especially helpful in power-save mode, in which a 0 certain amount of energy is delivered so the output stays 4 5 6 7 8 9 10 11 12 13 14 15 16 17 higher for a longer time. This results in a gap between Input Voltage (V) switching pulses and higher efficiency. From Figure 3c, once the minimum off-time is reached (around a 6-V input (a) Switching frequency voltage for the 2.5-MHz setting), the on-time begins to rise from ideal in order to achieve the required increase in 1000 duty cycle that corresponds to the lower input voltage. Figure 2c and Figure 3c show the 120-ns approximate 900 1.25 MHz_3 A_On_Time value of the minimum off-time. 800 1.25 MHz_1 A_On_Time 1.25 MHz_Ideal Furthermore, the minimum off-time is quickly reached 700 at high duty cycles because the input voltage value is 2.5 MHz_3 A_On_Time lower as well. At input voltages below 6 V, the resistance 600 2.5 MHz_1 A_On_Time of the high-side MOSFET (R ) inside the DCS-Control 500 2.5 MHz_Ideal DS(on) ime (ns) device increases, thus creating higher losses and a greater 400 required extension of the duty cycle. For example, 3-A On-T loads show longer on-times than 1-A loads at lower input 300 voltages. 200 Low duty cycles 100 Low duty cycles occur with lower output voltages, such as 0 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 V and 1.8 V. The relatively high 12-V input voltage Input Voltage (V) requires duty cycles of sometimes less than 10%. With respect to the desired 400-ns period, this requires (b) On-time on-times near and even below 40 ns. Such small on-times are challenging for any converter to achieve, or are actu- 700 ally impossible due to absolute minimum on-times. The TPS62130 data sheet notes a typical 80-ns absolute 1.25 MHz_1 A_Off_Time minimum on-time that occurs in these cases. This is the 600 1.25 MHz_3 A_Off_Time primary source of frequency variation at low duty cycles. Fixed propagation delays added to small on-times are 500 another source of variation, as explained before. Figure 4 shows measured data for a 1.8-V output voltage. 400 2.5 MHz_1 A_Off_Time

ime (ns) 2.5 MHz_3 A_Off_Time

Off-T 300

200

100 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Input Voltage (V)

(c) Off-time

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The 2.5-MHz curves in Figure 4b clearly show a minimum on-time in the 80-ns range. This sets an upper boundary Figure 4. TPS62130 with a 1.8-V output on the achievable switching frequency. The 1.25-MHz curves show good frequency variation similar to Figures 2a 3.0 and 3a. Due to smaller on-times with this 1.8-V output, 2.5 MHz_3 A fixed propagation delays cause a sharper downward 2.5 2.5 MHz_1 A frequency shift versus higher output voltages, which result in a lower frequency. 2.0 Additionally, the bumpiness seen in the 2.5-MHz curves (Figure 4a) shows a third impact to the on-time: the 1.5 comparator. During a transient, the comparator extends the on-time past the output of the timer to deliver more 1.0 energy to the output to make the output voltage recover 1.25 MHz_3 A faster. This is a key aspect of a hysteretic converter and Switching Frequency (MHz) 0.5 1.25 MHz_1 A explains the fast transient response of the DCS-Control topology. 0 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 While the 80-ns minimum on-time and the output of the Input Voltage (V) timer do not change much over the input voltage range, the output signal does change due to the changing ripple on (a) Switching frequency the inductor current. There is increased ripple with higher 400 input voltages. Having more ripple across the equivalent 1.25 MHz_3 A_On_Time series resistance (ESR) and equivalent series inductance 350 1.25 MHz_1 A_On_Time (ESL) in the output capacitors creates more signal for the 1.25 MHz_Ideal 300 comparator on which to react, making the system faster. 2.5 MHz_3 A_On_Time Between 12 and 13 V, there is enough signal and the 250 2.5 MHz_1 A_On_Time comparator no longer controls the on-time. The minimum 2.5 MHz_Ideal on-timer controls it. Thus, higher frequency is achieved 200

ime (ns) above this input voltage. 150 One solution to the lower frequency is a two-stage On-T conversion of the 12 V to the load. A two-stage conversion 100 (via 5 V, for example) to very-low output voltages achieves a higher frequency in both stages because of the more 50 moderate on-times of each stage. 0 Finally, the lower switching frequency that occurs with 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 lower output voltages will increase the inductor current Input Voltage (V) ripple, but this ripple is already lowered because of the (b) On-time low output voltage (Equation 2). Lower output voltages have less current ripple to begin with. When following the datasheet recommendations for inductance and switching current capability. High-frequency operation is maintained frequency, this lower switching frequency does not limit for the common applications of USB ports and system rails the output current below the 3-A device rating. with higher voltages.

 V  References 1 OUT  −  ∆I =V × VIN(max) 1. Chris Glaser, “High-efficiency, low-ripple DCS-Control L(max) OUT   (2) offers seamless pulse-width modulation (PWM)/power-save  L(min) × fSW  transitions,” TI Analog Applications Journal, 3Q 2013 Conclusion (SLYT531) 2. Datasheet, “TPS6213xA-Q1 3V to 17-V 3A Step-Down The switching frequency of the DCS-Control topology and Converter with DCS-Control™,” Texas Instruments, other non-oscillator-based control topologies vary with May 2014 changes in the application conditions. Depending on the duty cycle, the on-time and the frequency are affected by 3. TPS62130EVM-505, “Evaluation Module for TPS62130 a losses, the minimum off-time, the absolute minimum 3-A, synchronous, step-down converter in a 3x3-mm, on-time, propagation delays, or the comparator. This 16-pin QFN,” Texas Instruments behavior is understood and expected, and output voltage Related Web sites regulation is maintained. The lower operating frequency provides higher efficiency with no reduction in output Subscribe to the AAJ: www.ti.com/subscribe-aaj

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VCM vs. VOUT plots for instrumentation amplifiers with two op amps By Pete Semig Analog Applications Engineer, Precision Amplifiers

Background Figure 1. VCM vs. VOUT plot for two-op-amp The most common issue found in the TI E2E™ Community instrumentation amplifier for instrumentation amplifiers involves interpreting the datasheet plot for common-mode voltage versus output 15

voltage (VCM vs. VOUT). Misinterpretation or misunder- )

V standing this plot results in forum posts that describe ( 10 VS = ±15 V, G = 5 +15 V distorted output waveforms, incorrect device gain, or 5 + +

‘stuck’ outputs. Verifying that the device is operating oltage VD/2 V V within the limits of the VCM vs. VOUT plot is always the first + O 0 V thing I check when responding to an application issue. D/2 – – Ref

Mode This article introduces the V vs. V plot for an VCM CM OUT –5 –15 V instrumentation amplifier with two operational amplifiers (op amps) and delivers a thorough treatment of this –10 datasheet) amplifier topology. Additionally, the internal node equa- Common- output swing (see Limited by A2 tions are derived and used to plot each internal amplifier’s –15 input common-mode and output-swing limits as a function –15 –10 –5 0 5 10 15 of the instrumentation amplifier’s common-mode voltage. Output Voltage (V) Finally, a software tool that simulates the VCM vs. VOUT plot is introduced. Figure 2. Instrumentation amplifier output The VCM vs. VOUT plot distortion due to V vs. V violation[1] The input common-mode and output-swing limitations of CM OUT all internal amplifiers of an instrumentation amplifier are represented in the VCM vs. VOUT plot. A typical VCM vs. VOUT plot for a two-op-amp instrumen- tation amplifier is shown in Figure 1. The interior of the Input plot defines the linear operating region of the instrumen- tation amplifier because each line in the plot corresponds to either an input or output limitation of one of the two internal amplifiers. The V vs. V plot is specified for a CM OUT Distortion particular supply voltage, reference voltage, and gain as Output shown in Figure 1. Operating outside the boundaries of a VCM vs. VOUT plot causes the device to operate in a non-linear mode as shown in Figure 2. A three-part series article and blog post discuss the VCM vs. VOUT plot for the ubiquitous three-op-amp instrumen- tation amplifier.[1, 2] Two-op-amp instrumentation amplifi- ers are popular because of their low-cost and relatively large VCM vs. VOUT plots.

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Analysis of a two-op-amp instrumentation Figure 3. Topology of a two-op-amp amplifier instrumentation amplifier Figure 3 depicts a typical two-op-amp instrumentation

amplifier connected to an input signal. This topology has V+IN + high input impedance and requires only one resistor, RG, – + V

A O to set the gain, which is the same as the three-op-amp – 1 V topology. D 2 Figure 3 also depicts the definition of common-mode RFA1 R (VCM) and differential-mode (VD) voltages. A differential G amplifier (for example, op amp, difference amplifier, ROA2 instrumentation amplifier) ideally rejects the common- RG mode voltage, VCM. RFA2 RG

However, the signal-path imbalance from V+IN and V–IN

to the output degrades the device’s common-mode rejec- – A+ tion ratio (CMRR), especially over frequency (Figure 4). V–IN 2

+ – This degradation in CMRR is one of the primary reasons V V REF why two-op-amp instrumentation amplifiers typically cost D VCM 2 V less than their three-op-amp counterparts. RR REF The transfer function for the circuit in Figure 3 is given by Equation 1. Notice that the common-mode voltage does not appear in the equation because ideally it is rejected by the instrumentation amplifier. VV= − VG× + VV= × GV+ (1) OI( +NI − NR) EF DREF Figure 4. CMRR of two-op-amp vs. Deriving the transfer function of this topology aids in three-op-amp topologies understanding the VCM vs. VOUT plot. Figure 5 depicts a more traditional drawing of the sche- 100 INA333 (three op amp) matic in Figure 3. In order to determine the contribution 80 of the reference voltage at the output, VO(VREF), apply )

dB 60 superposition by shorting the input sources to ground. ( Amplifier A applies an inverting gain to V based on 2 REF 40 the ratio of RFA2 and RR. Similarly, A1 applies an inverting CMRR INA122 (two op amp) gain to the output voltage of A2 based on the ratio of 20 RFA1 and ROA2. Equation 2 depicts the transfer function 0 for VREF. 10 100 1k 10k 100k Frequency (Hz)  −RFA2  −RFA 1  VO VREF = VREF     R   R  R OA2 (2)  RRFA1× FA 2  = VREF Figure 5. Alternate drawing for Figure 3  RR×   R OOA2  RG RG RG

RFA1

RFA2

RR

– ROA2

VREF –

A+ 2 V–IN A+ 1 VO V+IN VREF

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The gain applied to the instrumentation amplifier’s reference voltage should be 1 V/V. Figure 6. Two-op-amp topology with internal nodes labeled To fulfill this requirement, set RFA1 = RR and RG RFA2 = ROA2 = RF. Figure 6 depicts the RG RG updated two-op-amp topology that results in RR unity gain for the reference voltage.

Furthermore, the internal nodes are labeled RF

RR

for future analysis. – RF

VREF –

Despite just two amplifiers and five resis- A+ 2 V–IN VOA2 A+ 1 VO tors, the circuit in Figure 6 has six gain terms. V +IN VOA1

V

This is because each amplifier applies gain to VREF IA2 – V

V V IA1 three input signals. While it may be obvious D + D + 2 2 – that A2 applies gain to V–IN and VREF, A2 also applies gain to V+IN via the virtual short across the inputs of A1 and RG. Similarly, A1 applies VCM gain to VOA2, V+IN, and V–IN. Equations 3 through 8 depict the six gain terms associated with a two-op-amp instrumentation amplifier. −R −R G = F (3) G = R (6) AV2 R R AV1OA 2 R R F R R G =1 + F (4) G =1 + R (7) AV2 −IN RR|| AV1 +IN RR|| GR GF −R −R G = F (5) G = R (8) AV2 +IN R AV1 −IN R G G

Equations 9 and 10 depict the output voltages of amplifiers A1 and A2. VV= = VG + VG + VG (9) OA1 OI+NA( 1VI + NI) −NA( 1VI − NO) AA2 ()1VOA 2 VV= GV+ GV+ G (10) OA2 +IN ( AV2 +IN ) −IN ( AV2 −IN ) REFA()2VR Substituting Equation 10 for VOA2 in Equation 9 and simplifying yields Equation 11. VV= GG+ GV+ GG+ G + V (11) OI+NA( 1VI + NA2VI+ NA1VOAI 2 ) − NA( 1VI− NA2VI− NA1VOA 2 ) REF The relationship between the gain terms in Equation 11 is shown in Equation 12.

GGAV1 +IN + AV2 +INGAV1OA 2 = −(GAV1 −IN + GGAV2 −IN AV1OA 2 ) (12) R 2R =GG − =1 + R + R AV1 +IN AAV1 −IN R R F G

Finally, using Equations 11 and 12, the transfer function for a Figure 7: Op amp input common-mode and two-op-amp instrumentation amplifier is shown by Equation 13, output-swing ranges depend on supplies[1] which is consistent with Equation 1.

VVOO=AI1 = (VV+NI− − NR) ×GV + EF V+  R 2R  (13) =V × 1+R + R + V D  R R  REF  F G  + VCM VOUT Op amp limitations – Linear operation of an instrumentation amplifier is contingent upon the linear operation of its primary building block; op V– amps. An op amp operates linearly when the input and output signals are within the device’s input common-mode and output- swing ranges, respectively. The supply voltages used to power the op amp (V+ and V–) define these ranges (Figure 7).

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A real-world example of common-mode and output- swing limits is shown in Figure 8. Notice that the common- Figure 8. Op amp VCM and VOUT ranges for 3.3-V supply[1] mode range and output-swing ranges are not necessarily the same. V+ = 3.3 V Two-op-amp node equations OPA333 With a solid understanding of the two-op-amp instrumen- + 50 mV < V < 3.25 V –100 mV < VCM < 3.4 V OUT tation amplifier and op-amp limitations, the next step is to – examine the node equations as indicated in Figure 6. The equations for VOA2 and VOA1 are already given by Equations 10 and 13, respectively. Equations for VIA1 and V– = 0 V VIA2 from Figure 6 are given as: V VV= = V + D (14) information, a combination of examining the device’s limi- IA1 +IN CM 2 tations and measuring the linear operating region can be V used to determine the values. VV= = V − D (15) To move the input common-mode range closer to the IA2 −IN CM 2 negative supply voltage, some instrumentation amplifiers The VCM vs. VOUT plot can vary based on gain and refer- (for example, INA122) level-shift the inputs using preci- ence voltage. Therefore, Equations 10 and 13 through 15 sion transistor buffers.[1] This is particularly useful when must be solved for VO as a function of the gain terms, VCM, operating with a single supply. and VREF. One important relationship that allows for this is Figure 9 depicts a TINA-TI™ simulation that plots obtained by solving Equation 13 for VD, as shown in Equations 17 through 20 for both the maximum and Equation 16. minimum common-mode and output-swing limits for the internal amplifiers of the INA122. The linear operating VVOR− EF VVOD= × GV+REFD → V = (16) region is the interior of all lines. G After making all of the proper substitutions and solving Figure 9. VCM vs. VOUT plot for VO, Equations 17 through 20 capture the linear operat- ing region of a two-op-amp instrumentation amplifier at its 15 output as a function of the gain terms, VCM, VREF, and the common-mode and output limitations of each amplifier (VIA1, VIA2, VOA1, VOA2). 10 V V O_IA1_max V O_OA2_max VG=2 × ×VV − + V (17) O_IA2_max OI_A 1 ()IAC1 MREF 5

VOI_A 2 = −2 ×G × VVIAC2 − MR+ V EF (18) oltage (V) INA122 () V 0 V VV= (19) O_OA1_min OO_AO 1 A1 Mode VO_OA1_max VV=2 − VG+ 2 VV− (20) –5 OO_AC 2 MR AV1OA 2 ( OA2 CM )

Common- In order to operate in a linear region, the voltage at V –10 V O_OA2_min VIA1 must not violate the input common-mode range of VO_IA1_min O_IA2_min A1. Similarly, the voltage at node VOA1 must not violate the output swing limitation of A1. The same holds true for –15 VIA2 and VOA2 for op amp A2. The values of the internal –15 –10 –5 0 5 10 15 op amp limitations are not usually explicitly stated in an Output Voltage (V) instrumentation amplifier’s data sheet. In lieu of such

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Figure 10. VCM vs. VOUT software tool

A software tool was developed to simplify the creation Acknowledgements of VCM vs. VOUT plots for varying gains, reference voltages, The author would like to thank Art Kay at Texas and supply voltages. See Related Web sites an the end of Instruments for developing the VCM vs. VOUT software tool this article for download links. Figure 10 depicts the VCM and Collin Wells for his technical contributions to this article. vs. VOUT plot for the INA122 given standard datasheet conditions. Notice that it compares well with Figure 1 and References Figure 9. The datasheet plot in Figure 1, however, only 1. Peter Semig and Collin Wells, “Instrumentation ampli- depicts the output limitations of A1 and A2, whereas the fier VCM vs. VOUT plots,” Part 1, Part 2 and Part 3, EDN software tool includes the common-mode limitations. Network, December 2014 Finally, note that the software tool can be downloaded to 2. Peter Semig, “How Instrumentation Amplifier V vs. generate V vs. V plots for both two- and three-op- CM CM OUT V plots change with supply and reference voltage,” amp instrumentation amplifiers. OUT TI Precision Hub, January 30, 2015. Summary Related Web sites This article addressed the most misunderstood concept of Software tool: two-op-amp instrumentation amplifiers: the V vs. V CM OUT V vs. V plot generator datasheet plot. A thorough analysis of the two-op-amp CM OUT topology was delivered along with the derivation of the Product information: internal node equations. These equations were used to INA122 INA333 create the VCM vs. VOUT plots. The output from the down- loadable software tool was found to correlate well with the OPA333 plot in the INA122 datasheet. This tool gives designers a Subscribe to the AAJ: simple method for ensuring linear operation of the instru- www.ti.com/subscribe-aaj mentation amplifier in their design.

Texas Instruments 12 AAJ 4Q 2015 Analog Applications Journal Industrial Common-mode transient immunity for isolated gate drivers By Shailendra Baranwal Senior Design Engineer, Isolation Team Introduction solar inverters, uninterruptable power supplies (UPSs), or Isolated gate drivers are widely used for driving insulated- AC applications powered from a battery in automobiles. gate bipolar transistors (IGBTs) and MOSFETs in various The same inverter configuration allows for output-voltage applications such as motor drives, solar inverters and amplitude and frequency control, which is more useful for automobiles. In addition to turning the IGBTs or MOSFETs a motor control. An induction-motor control is a common on and off, these drivers provide galvanic isolation. The example of using an inverter for motor control. device’s switching rate depends on the application and Figure 1 contains a high-level diagram of an AC-to-DC type of the device being used. Switching frequencies of 10 and then DC-to-AC conversion. The system has a three- to 20 kHz are common in IGBTs, however, silicon carbide phase input and controllable three-phase AC output. The (SiC) and gallium-nitride or GaN-based systems can rectifier block converts the AC to DC, and a filter using L1 operate at 50 kHz to 200 kHz. Some advantages for using a and C1 is used to filter out the residual ripple. A key higher switching frequency are smaller filter size, fast parameter for the rectifier is its power factor. The simplest control and lower distortion. However, these advantages form of a rectifier uses diodes. Diode-based rectifiers have come with an increased power loss during transition. very poor power factor and are not suitable for high-power applications. Instead, rectifiers using active power factor Common-mode transient immunity (CMTI) is an impor- [1] tant parameter of a gate driver to consider when operating correction (PFC) are preferred for high-power solutions. it at higher switching frequencies. This article gives back- The inverter consists mainly of Q1 through Q6 IGBTs ground on a general pulse-width modulation (PWM) and the gate-driver circuit. Input to the inverter is the DC scheme, the transition loss associated with high switching supply (VDC) produced by the rectifier. The purpose of frequency, and isolated gate-driver solutions to reduce the inverter is to convert DC to AC voltage. The frequency transition time. and amplitude of the inverter output is controlled by how the IGBTs are switched. In applications such as UPSs or Typical inverter operation solar inverters, a battery supplies power to the inverter. An inverter configuration is used for a DC-to-AC conver- The load can be any general-purpose AC load, or it can sion. These voltage-source inverters (VSIs) can be used connect to the grid. The fundamental structure of the either for general AC voltage-output generation or motor inverter remains the same for many applications. control. Examples of AC voltage-output applications are

Figure 1. Motor control diagram

L1 VDC

Rectifier Microcontroller Q1 Q3 Q5

OUTA Gate Drivers C1 OUTB 6 Motor 3-Phase To OUTC AC Source Q1–Q6 Q2 Q4 Q6

Texas Instruments 13 AAJ 4Q 2015 Analog Applications Journal Industrial

Battery-operated inverters are very common in electric Figure 2. High-level diagram of a vehicles. A microcontroller is used to produce a PWM single-phase inverter waveform to drive the IGBTs and the outputs (OUTA, OUTB and OUTC) switch between 0 V and VDC. An induc- tion motor requires control of voltage and frequency to control its torque and speed. The microcontroller monitors S1 S3 the speed and current in the motor and provides the Filter proper PWM pattern according to user inputs. IGBTs typi- A V + VAB Load cally require gate drivers with isolated outputs because DC – B the output side is switching between 0 V and VDC. The switching frequency of an IGBT-based inverter is typically S2 S4 in the range of 8 to 16 kHz and higher PWM switching frequencies are possible with SiC or GaN IGBTs.[2, 3] In this scenario, gate drivers also need to support faster switching speeds. The inverter can be configured as a single-phase output with only two legs and four switches. Three-phase systems are typically used to get more power. can range from 10 to 200 kHz, depending on the applica- Pulse-width modulation tion and type of switch. In Figure 3a, the duty cycle at PWM or pulse-width modulation is a way to achieve ampli- node A is more than 50% and in Figure 3b, the duty cycle tude control by changing the duty cycle. is less than 50% at node B. This creates a positive voltage Figure 2 shows a simple form of a single-phase inverter. across the load as shown in Figure 3c. In Figure 3d, the duty cycle at node A is less than 50% Input to the inverter is a DC voltage (VDC) and the voltage and more than 50% at node B (Figure 3e),which creates a across the load is VAB = VA – VB. The voltage at node A negative voltage across the load (Figure 3f). switches between VDC and 0 V via switches S1 and S2. The average voltage, VAB, across the load/filter can be Similarly, the voltage at node B switches between VDC and 0 V via switches S3 and S4. Switches S1 and S2 are written as: complementary, as are switches S3 and S4. The maximum VAB = VDC × DA – VDC × DB or VAB = VDC × (DA – DB) (1) output voltage that can be achieved using this system is where D is the duty cycle at node A, and D is duty cycle VDC. An example of switching waveforms at nodes A and B A B without filtering is shown in Figure 3. The switching rate at node B.

Figure 3. Simplified PWM operation with positive and negative output voltages

VDC VDC (a) VA (d) VA 0 V 0 V

VDC VDC (b) VB (e) VB 0 V 0 V

V (f) (c) DC VAB = V–ABV VAB = V–ABV 0 V 0 V

–VDC

Texas Instruments 14 AAJ 4Q 2015 Analog Applications Journal Industrial

Figure 4. A single-phase PWM output waveform

INB INA Ramp

VA

VB

VAB

Controlling the duty cycle, DA and DB, allows control of where VIN is the amplitude of the reference input signal the output voltage, VAB. A sinusoidal single-phase PWM and VRAMP is the amplitude of the triangular wave signal. waveform is obtained by comparing a reference sine wave The fundamental output voltage is mA × VDC × sine (ωt); INA and INB with a high-frequency triangular signal as where ω is the frequency of the reference input signal. shown in Figure 4. The root mean square (rms) of the fundamental signal can The fundamental component of the output has an ampli- be written as: tude that is proportional to the differential reference input mAD× V C (VINA – VINB), and the frequency is the same as the refer- VRMS = (3) ence frequency. This allows the voltage and frequency to 2 be controlled by the reference signal. High-frequency tones are at frequencies 2nfSW ± mfIN, where fSW is the Transition loss in inverters triangular signal frequency, fIN is the reference input The inverter outputs switch between ground and VDC at the frequency, and the n and m multipliers can be 1, 2, 3, etc. PWM frequency, however, the output current is filtered The high-frequency component is filtered by the LC filter, either by the LC filter or motor inductance. Figure 5 or the motor inductance in the case of motor control. shows waveforms for voltage and current in a PWM The ratio between the input signal amplitude and the switching output . Figure 5c shows a DC current with a triangular signal amplitude is called amplitude modulation very small ripple component. The ripple amplitude is ratio, or mA. dependent on the filter size. While this example shows a DC output, the same concept can be extended for a sine- V m = IN (2) wave output. However, the current is a sine wave with a A V RAMP small ripple riding on it.

Figure 5. An inverter’s voltage and current waveforms with an LC filter

S1 VDC

(a) VA S1 S3 S2 0 V Filter S3 A VDC V + VAB Load V DC – (b) B B S4 0 V

S2 S4 ILOAD (c) IRipple 0

Texas Instruments 15 AAJ 4Q 2015 Analog Applications Journal Industrial

The instantaneous output power is VAB × ILOAD, where transition loss, the rise/fall time has to be lower for a VAB is the average DC output, which is dependent on the higher switching frequency. For example, a SiC-based duty cycles at nodes A and B. Assuming that there is no inverter with a 64-kHz switching frequency needs a rise/ phase difference between the voltage and current, the fall time of 50 ns to keep a 1% transition loss. output power for a sinusoidal output is: Gate-drivers for Inverter mAD× V CR × I MS (4) A typical drive of an IGBT-based, voltage-source inverter PVOUTR=MS × IRMS = 2 is shown in Figure 6. This figure shows a single-phase inverter, but it can be extended to a three-phase by The transition time from 0 V to VDC and vice versa of the voltage at node A is finite. The switch’s ON impedance adding one more leg of the bridge. The voltage at outputs is very low when completely on, but higher during transi- OUTA or OUTB switches from VDC– to VDC+. The IGBT tion time. This leads to transition-switching losses. This gate drives are isolated because the output-side ground of loss occurs twice at every PWM cycle. Current through the the driver is switching along with the inverter output while switches during transition is same as the load current the input-side ground is fixed and connected to a chassis. because it is filtered. Transition loss for a single event is The potential differences between GND1 and GND2 of both gate drivers require the drivers to be isolated. The VDC × ILOAD × tRF / 2. gate drivers support high-voltage isolation across the two The total transition loss for a single-phase inverter is grounds along with voltage transition rate at GND2. The P = 2 × 2 × f × I × V × t / 2 LOSS SW LOAD DC RF gate drivers are also selected based on their isolation = 2 × V × I × t × f , DC LOAD RF SW rating and their immunity to the transition on GND2, or where t is the rise/fall time of the voltage. In case of a RF common-mode transient immunity (CMTI). For example, sinusoidal current output, current through the switches is if the DC bus is 1500 V and the transition time of OUTA is an average of the load current: 100 ns, the immunity required by the gate driver is 15 V/ns. The immunity requirement for the driver increases if the 2 2 × IRMS (5) ILOAD = rise/fall time is lower. A voltage-source inverter (VSI) with π a higher switching frequency will have a higher CMTI and the power loss is: requirement. A 1500-V VSI running at 64 kHz and 50-ns rise/fall time requires at least 30-V/ns CMTI. The CMTI 4 2 ×VIDC × RMSR×tFS × f W (6) PLOSS = requirement increases if the transition loss is to be lower. π The gate drivers are specified for CMTI in their data- Ratio of the loss to output power is: sheet. For example, the ISO5851 and ISO5852S both have P 8 × t× f a minimum CMTI of 100 kV/µs. Higher CMTI for a gate LOSS = RF SW (7) driver ensures there is no false fault or false output toggle P π × m OUT A because of the transient noise. Equation 6 suggests that loss is proportional to the The component placement or board design also matters switching frequency. An inverter with a switching for a robustness to transient noise. The parasitic capaci- frequency of 16 kHz and 200-ns rise/fall time will have a tance between one side of the driver to the other side of 1% transition loss, assuming mA = 0.8. To reduce the the driver should be minimized. Using a diagram from the

Figure 6: Single-phase inverter with isolated gate drivers

U1 VDC+ ISO5851DW

R1 V TION GEQ1 Q1 Q3 ISOLA GND1 GND2 OUTA VGEQ2 U2 OUTB V ISO5851DW DC+

Microcontroller R2 TION Q2 Q4 VOUTA

GND ISOLA GND1 GND2 VDC– VDC–

Texas Instruments 16 AAJ 4Q 2015 Analog Applications Journal Industrial

ISO5851 datasheet, Figure 7 shows a Figure 7. Typical application where C1 and C2 can be changed to adjust CMTI typical application diagram. The Ready 10R 15 5 (RDY) and Fault VCCI VCC2 + + (FLT) pins are pulled 3 to 5 V – 0.1 µF 1 µF – 15 V 9,16 3 up by 10-kΩ resistors. GND1 GND2 These resistor values + ISO5851 1 µF – 15 V may need to be lower 10 1,8 IN+ V for noise immunity. + EE2

Transient noise can 1 kΩ DDST 10 kΩ 10 kΩ – 11 2 generate a false fault IN– DESAT or low under-voltage 12 7 lockout (UVLO) RDY CLAMP C2 R signal. This issue can 13 6 G be solved by either FLT OUT C1 reducing the resistor 14 4 values or increasing RST NC the capacitance of C1 220 and C2. pF Digital isolators such as the ISO7810, ISO7821 or ISO7841 also can be used in conjunction with SiC, GaN or IGBT drivers. Digital isolators provide rein- Figure 8. Gate-driver solution using digital isolators forced isolation and a CMTI at a minimum of 100 kV/µs. Figure 8 shows an isolated driver VCC1 VCC2 solution using a digital isolator. The digital V+ isolator can range from a single channel up to + four channels, depending on the application. U1 U2 – The digital isolator has an added benefit of ISO7810/21/41 low propagation delay, low skew and low IN OUT jitter, which are useful in a high-frequency Driver design. VS Conclusion ISOLATION Voltage-source inverters (VSIs) with PWM + GND1 GND2 – topology are a good choice for a motor V– control because the output amplitude and frequency control have a lot of flexibility. A higher switching frequency of PWM VSIs allows for a smaller filter size. The rise/fall times should be lower with high switching frequencies to 3. Jang-Kwon Lim, D. Peftitsis, J. Rabkowski, M. Bakowski, keep the transition loss lower. A gate driver with good H.-P. Nee, “Analysis and Experimental Verification of CMTI supports faster switching speeds. Gate-driver solu- the Influence of Fabrication Process Tolerances and tions from Texas Instruments can support a CMTI Circuit Parasitics on Transient Current Sharing of minimum of 100-kV/µs. Parallel-Connected SiC JFETs,” Power Electronics, IEEE Transactions on, Volume: 29, Issue: 5, May 2014, References pp. 2180 – 2191 1. A. R. Prasad, P. D. Ziogas, and S. Manias, “An active power factor correction technique for three-phase diode Related Web sites rectifiers,” IEEE Trans. Power Electronics, 1991 pp. Product information: 83-92 ISO5851, ISO5852S, ISO7810, ISO7821, ISO7841 2. Dr Scott Allen, “Silicon Carbide MOSFETs for High Subscribe to the AAJ: Powered Modules,” CREE Inc., March 19, 2013 www.ti.com/subscribe-aaj

Texas Instruments 17 AAJ 4Q 2015 Analog Applications Journal Industrial Pushing the envelope with high- performance, digital-isolation technology By Anant Kamath Systems Manager, Isolation, Interface group Introduction Reinforced isolation Isolation is a means of preventing DC and uncontrolled Reinforced isolators are devices that can provide insula- AC currents between two parts of a system, while allow- tion equivalent to two basic isolators in series. By them- ing signal and power transfer between those two parts. selves, reinforced isolators are considered sufficient to Electronic devices and integrated circuits (ICs) used ensure electrical safety against high voltage. However, for isolation are called isolators. Isolation is required reinforced isolators must satisfy increasingly tighter in modern electrical systems for a variety of reasons. performance requirements. Motor-drive applications have Some examples include protecting human operators the most stringent specifications for reinforced isolation and preventing damage to expensive processors in high- because these systems use very high incoming supply voltage systems, breaking the ground loop in communica- ­voltages and they involve interfaces accessible to human tion networks, and communicating to high-side devices operators. The requirements for isolation in motor control in motor-drive or power-converter systems (Figure 1). are defined in safety standards. For example, the IEC Examples of applications that need isolation include 61800-5-1 electrical, thermal and energy safety standard industrial automation systems, motor drives, medical for adjustable speed drives. According to this standard, equipment, solar inverters, power supplies, and electric the requirements on reinforced isolation scale up with an vehicles (EVs). increase in the system voltage which is defined as the Recent advances in isolation technology are enabling root-mean-square (rms) voltage between incoming supply new solutions, reducing system cost, and allowing custom- lines and earth. ers to push the performance envelope of their equipment. To guarantee reinforced insulation for drives with This article discusses key end applications that are driving system voltage greater than 600 VAC, an isolator must cutting-edge innovations in isolation technology and bene- withstand a 5-second temporary overvoltage of at least fitting from these innovations. 4400 VRMS. This isolator also must have a surge voltage

Figure 1. Typical isolation configuration for a power drive system

Isolation High-Voltage Drivers with Isolation Control System Interface Controller Power High-Power Devices Equipment

Isolation Feedback

Texas Instruments 18 AAJ 4Q 2015 Analog Applications Journal Industrial

Figure 2. New motor drive architecture

AC Motor Drive Isolated IGBT Rectifier Diodes Gate Drivers IGBT Module

DC+

AC Power Drive Supply Output DC– M

PWM Signals

DC– DC–

Digital Isolation Link RS-458, CAN, Controller 2 Controller 1 Isolated Current Ethernet and Comms and Voltage Sense Module Micro- controller DC– Micro- DC– processor DC– Encoder

capability of at least 12 kVPK, creepage and clearance of at Examples of creepage and clearance are illustrated in least 14 mm, and a working voltage in the range of 600 VRMS Figure 3. to 1000 VRMS, which depends on the supply line voltages and drive architecture. To make matters more challenging, Figure 3: Pictorial representation of new motor-drive architectures are adding local field- clearance and creepage programmable gate arrays (FPGAs) and controllers to the power board referenced to the DC bus (Figure 2, control- ler 2). This reduces the local isolation requirement on the power board. However, it increases the data rate and bandwidth requirement on one, multichannel integrated, high-speed reinforced link (Figure 2, digital isolation link). Until recently, isolators meeting these isolation require- ments, as well as the timing and data rate requirements, Clearance were not available in the market. The only alternative was fiber-optic isolation. Capacitive reinforced isolation solutions are now avail- able that meet the above requirements for high isolation, wide packages, and high data rates. These solutions are a good fit for motor-drive applications with system voltages beyond 600 VAC. Some optocouplers do meet the high- isolation requirements, but do not meet the data rate or multichannel integration requirements. Additionally, leading magnetic-isolation solutions do not meet the Creepage requirement on working voltage/long-term reliability.

Texas Instruments 19 AAJ 4Q 2015 Analog Applications Journal Industrial

High working voltage waveform is the DC link voltage. For any isolator, its life- Solar and wind energy applications generally use addi- time degrades exponentially with increased voltage stress tional isolation barriers (for example, in the path of the across the barrier. Solar and wind inverter systems target network-communication channel) to achieve reinforced lifetimes in excess of 25 years. It is critical to choose an isolation. Hence, the requirements related to reinforced isolator that meets the working-voltage requirement with a isolation are not as high as in motor-drive applications. liberal margin so that the lifetime of the complete system However, the requirement for high working voltage can is not limited by the isolators. exceed values seen in motor drives. Power plant central- New capacitive isolators achieve a working voltage of ized solar inverters and wind-energy inverters are trending 1500 VRMS (2121 VPK). This voltage is a 50% increase to operate with higher DC bus voltages, extending to 1500 V compared to commonly available devices, which enables and beyond. Higher DC-bus voltages enable higher power higher-voltage and more efficient inverter systems at a ratings without increasing the current levels, which keeps lower cost. Optocouplers have fair isolation and working- copper costs the same. This helps reduce the per-unit cost voltage performance; however, the LEDs they use limit of energy generated. Another bonus of higher voltage is their lifetimes from an electrical-performance point of increased efficiency because the total power output can view. As mentioned earlier, leading polyimide-based, increase with higher voltage, but when current does not magnetic-isolation technologies have low working voltage change, the conduction losses also remain the same. ratings and low long-term insulation reliability, which Higher DC bus voltages directly translate to higher limits their use in high-voltage, solar-inverter applications. working voltages for the isolators used in switching power High common-mode transient immunity transistors in the inverter. In Figure 4, the isolated gate Common-mode transient immunity (CMTI) is the ability of drivers (or any digital isolators paired with discrete gate an isolator to tolerate high-slew-rate voltage transients drivers) continuously see a trapezoidal voltage. These between its two grounds without corrupting signals voltages appear between one side that is connected to passing through it. In electric-vehicle motor drives, as well the inverter output, and the other side is connected to as solar- and wind-energy inverter applications, the earth reference. The peak-to-peak value of this voltage

Figure 4. Block diagram of a centralized solar inverter

DC/AC Conversion with Isolated IGBT Gate Drivers

DC+ Low- EMI Frequency Electric Solar Filter Transformer Grid Panel

PWM Signals

DC–

Isolation Isolation RS-485, System CAN, Controller Ethernet Isolated Current and Voltage Sense Micro- controller

Texas Instruments 20 AAJ 4Q 2015 Analog Applications Journal Industrial isolated gate drivers or isolators passing gate controls to power transistors see large ground transients because one Figure 5. Inverter output switching profile translates to high CMTI for isolators ground is connected to rapidly switching inverter outputs. Figure 5 shows the ground potential difference experi- enced by these gate drivers. In these systems, CMTI is a ~1500 V critical parameter because any bit errors caused by the transients can result in dangerous short-circuit events. Recent application requirements are pushing the need for isolators with higher and higher CMTI. As stated, one requirement is increasing DC bus voltages. A second is dV/dt = 100 kV/µs reducing transition times with faster switching in the power transistors, which improves inverter efficiency. A third is increasing switching frequency, which results in lower-cost and less-bulky magnetics such as inductors, transformers and motors. Availability of reliable silicon- carbide or SiC-based power transistors, which can switch faster and tolerate higher voltages versus traditional Table 1. Creepage requirements depending on working voltage IGBTs, is building on the trend for inverters that switch and package material group faster and more efficiently. Capacitive isolators released in 2014 broke the barrier Minimum Creepage (mm) for 100-kV/µs CMTI. Capacitive isolators and gate drivers Pollution Degree 2 Pollution Degree 3 Working continue to lead the industry with the highest minimum Material Group Material Group Voltage guaranteed CMTI, thus enabling faster, more efficient, and (VRMS) I II III I II III lower-cost inverter designs. 200 2 2.4 4 5 5.6 6.4 High-altitude operation 400 4 5.6 8 10 11.2 12.6 Advanced packaging technology is required for isolators 800 8 11.2 16 20 22 25 used in equipment operating at higher altitudes and in a 1000 10 14.2 20 25 28 32 polluted or high-moisture environments. Improved and wider packages prevent degradation along the package surface and arcing through the air between pins, which Table 2. Multiplication factors for clearances at higher altitudes ensures isolation quality. Isolators used in solar, wind- energy and e-metering applications fall into this category. Multiplication Factor for Altitude Clearances Isolator voltages that continuously operate in heavy pollution can cause package surfaces to degrade and 2000 1 create a conductive path across the isolator. This phenom- 3000 1.14 enon is called tracking. Choosing a higher-quality packag- 4000 1.29 ing mold compound that belongs to a lower material group 5000 1.48 with higher comparative tracking index (CTI) can mini- 6000 1.7 mize this effect for a given package creepage and working voltage. Another approach is to choose a wider package 7000 1.95 with increased creepage to reduce the risk of tracking. Table 1 shows the requirements on creepage distances spacing between pins (more clearance). Table 2 shows the depending on working voltage, the pollution degree, and multiplication factors by which clearance must be the material group of the isolator’s package mold increased at higher altitudes to prevent arcing per IEC compound for reinforced isolation, according to IEC 60664-1. 60664-1. The requirements on creepage increase with Traditionally, conformal coating or potting techniques working voltage and pollution degree, however, selecting a involving deposition of insulating polymer or other mate- lower material group with a higher CTI can reduce the rial over the printed circuit board (PCB) have been used creepage requirement. to reduce the pollution degree around the isolator. This At higher altitudes of 2000 to 5000 meters above sea reduces the requirement on creepage and clearance. level, the air pressure is lower. Therefore, peak over­ However, these methods add cost, are less reliable, and voltages, such as surge or temporary overvoltage, can need additional inspection steps in PCB manufacturing. more readily cause arching between the isolator pins. Wide-body isolators manufactured with high-quality Equipment operating at high altitudes requires greater molding compounds eliminate the need for conformal coating or potting, simplify PCB design, and increase manufacturing reliability.

Texas Instruments 21 AAJ 4Q 2015 Analog Applications Journal Industrial

New isolators use the best quality mold compound References (CTI material group I) and are available in wide packages 1. IEC 61800-5-1 Ed. 2.0, Adjustable speed electrical (14.5 mm creepage/clearance). These isolators can enable power drive systems, safety requirements, electrical, high-altitude designs and tolerate higher pollution without thermal and energy. July 2007 requiring additional steps in PCB manufacturing. 2. Anant S Kamath and Kannan Soundarapandian, “High- Capacitive digital isolators voltage reinforced isolation: Definitions and test meth- Recent advances in capacitive digital isolators place them odologies,” Texas Instruments White Paper, November at the forefront of technology. These new isolators offer 2014 (SLYY063) higher isolation performance, long-term reliability, 3. Anant S Kamath, “Isolation in AC Motor Drives: Under­ increased channel integration, higher data rates and preci- standing the IEC 61800-5-1 Safety Standard,” Texas sion timing performance, better quality package mold Instruments White Paper, November 2015 (SLYY080) compound, wider packages (14.5-mm creepage/clearance), 4. IEC 60664-1 Ed. 2.0, Insulation coordination for equip- and CMTI exceeding 100 kV/µs. Combining these features ment within low-voltage systems, principles, require- enables new applications, reduces system cost, and allows ments and tests, April 2007 end-equipment manufacturers to push the performance envelope of their solutions. Related Web sites Texas Instruments offers the ISO78xx family of rein- Product information: forced digital isolators and the ISO585x and ISO545x ISO7821, ISO7831 ­families of reinforced isolated IGBT gate drivers. These ISO7840, ISO7841, ISO7842 isolators offer features and capabilities that can solve ISO5851, ISO5852S ­difficult isolation problems. These isolators have a working ISO5451, ISO5452 voltage of up to 1500 VRMS, are rated for 40 years, have Subscribe to the AAJ: surge voltage capability of 12.8 kV, and withstand a tempo- www.ti.com/subscribe-aaj rary overvoltage of 5700 VRMS. They offer high data rates of up to 100 Mbps with low skews and part-to-part ­variations and CMTI exceeding 100 kV/us. They also use material group I mold compound and are available in industry-leading wide packages.

Texas Instruments 22 AAJ 4Q 2015 Analog Applications Journal Communications How to reduce current spikes at AC zero-crossing for totem-pole PFC By Bosheng Sun Systems Engineer, High Power Controller Solutions Introduction Power factor correction (PFC) is widely used in AC/DC switch or a sync switch. To further improve efficiency, D1 power supplies with an input power of 75 watts or greater. and D2 are replaced with regular MOSFETs because the PFC forces the input current to follow the input voltage so conduction loss for MOSFETs is lower than for diodes. that any electrical load appears like a resistor. Amongst all The revised structure is shown in Figure 2 where Q1 and the different PFC topologies, the totem-pole PFC[1, 2] has Q2 are regular MOSFETs and are driven at AC frequency. recently received more attention because it uses the least The current flow paths for a totem-pole PFC are shown number of components, has the smallest conduction loss, in Figures 3 and 4. During the positive AC cycle, Q4 is the and has the highest efficiency. Typically, a totem-pole PFC active switch, while Q3 works as a sync FET. The driving cannot operate in continuous-conduction mode (CCM) signals for Q4 and Q3 are complementary: Q4 is controlled because of the slow reverse recovery of the MOSFET’s by D (duty cycle from control loop) and Q3 is controlled body diodes. However, with the advent of the gallium- by 1 – D. When Q4 turns on, the current goes through the nitride (GaN) FET, its diode-free structure makes the AC line, inductor, Q4, Q2, and then back to AC neutral. CCM totem-pole PFC possible. Figure 1 is a totem-pole When Q4 turns off, Q3 turns on, the current goes through PFC structure. the AC line, inductor, Q3, load, Q2, and then back to AC In Figure 1, Q3 and Q4 are GaN FETs. Depending on neutral. Q2 stays on for the whole positive AC half-cycle VAC polarity, they alternatively operate as a PFC active and Q1 remains off.

Figure 1. Totem-pole PFC with GaN Figure 3. Current paths for positive AC cycle FETs and line-rectification diodes

Q1 Q3 D1 Q3 Q3 On, Q4 Off NL

– + VAC VAC Q3 Off, Q4 On Q2 Q4 D2 Q4

Figure 2. Totem-pole PFC with GaN Figure 4. Current paths for negative AC cycle FETs and line-rectification MOSFETs Q3 Off, Q4 On

Q3 On, Q4 Off Q1 Q3 Q1 Q3

NL

+ – V AC VAC Q2 Q4 Q2 Q4

Texas Instruments 23 AAJ 4Q 2015 Analog Applications Journal Communications

During the negative AC cycle, the function of Q4 and Q3 swaps: Q3 becomes the active switch and Q4 works as a Figure 5. Current spike caused by sudden turn on of Q4 sync FET. The driving signal for Q4 and Q3 are still complementary, but Q3 is now controlled by D and Q4 is controlled by 1 – D. When Q3 turns on, the current goes through AC neutral, Q1, Q3, inductor, and then back to AC line. When Q3 turns off, Q4 turns on, the current goes Q1 Q3 through AC neutral, Q1, load, Q4, inductor, and then back to AC line. Q1 stays on for the whole negative AC half- NL cycle and Q2 remains off. + One of the challenges in totem-pole PFCs is that the IL input current has big spikes at the V zero-crossing. The AC Q2 Q4 issue is inherent with totem-pole PFCs and very compli- VDS_Q2 = V OUT cated. In fact, the spikes contain both positive and nega- – tive spikes, and they occur for different reasons. There are several scenarios that can cause current spikes. Scenario 1 Scenario 3 As shown in Figure 5, when the operation mode changes Timing for Q2 turn on is also critical. A short-through can from negative cycle to positive cycle at the AC zero- occur if Q2 turns on before Q4 soft start and if the body crossing, the duty ratio of switch Q3 changes abruptly diode of Q1 does not recover quickly enough. from almost 100% to zero. The duty ratio of switch Q4 Scenario 4 changes abruptly from zero to almost 100%. Because of If Q2 turns on too late, a negative current spike can be the slow reverse recovery of the Q1 body diode and the generated (Figure 6). The high VBUS voltage generates a large COSS of Q2, the VDS voltage of Q2 still equals VOUT reverse inductor current when Q3 is on while Q2 is off. (400 V). Since this high voltage is applied to the inductor This reverse current first turns off the Q2 body diode, when Q4 turns on, a positive current spike is generated. then starts to charge COSS of Q2 and the VDS of Q2 builds This scenario is analyzed in Reference 3 and a Q4 soft- up to a high voltage. Then, when Q4 turns on, the high start method is proposed to solve this issue. voltage (VDS + VIN) that is applied to the inductor results Scenario 2 in high rising current in the inductor. Therefore, the However, even with soft turn on of Q4, there are still inductor’s rising and falling currents are both large magni- excessive current spikes. This is because VAC is very low tude, which achieves a balance that maintains the average right after zero-crossing and is therefore insufficient for current at a small positive value. Now, if Q2 suddenly the inductor current to build up. On the other hand, when turns on at t1, VDS of Q2 will be clamped to zero. When Q4 Q3 turns on with 1 – D, even though its duty is not high, turns on, only VIN is applied to the inductor. Since VIN is the voltage applied to the inductor is high (400-V VOUT). very small, which is insufficient for the inductor to build The resulting high reverse current through the inductor up current high enough, the inductor’s rising current causes a negative current spike. becomes very small. Because the falling current still has a large magnitude, the balance is broken and results in a large negative current spike.

Figure 6. Current spike caused by turning on Q2 too late

iL (Average)

iL 0

VGS_Q4

VGS_Q3

VGS_Q2

t1

Texas Instruments 24 AAJ 4Q 2015 Analog Applications Journal Communications

Reducing current spikes at AC Figure 7. Gate signals timing for proposed method zero-crossing A new control method is provided in this V article to solve the current-spiking issue. In AC this method, Q1, Q2, Q3, and Q4 are turned on with a special sequence and each executes a soft-start mechanism. The driving Q4 Soft Start signals for this new method are shown in Q4 Soft Start V Figure 7: GS_Q4 In this solution, when VAC changes from a V Q3 Soft Start Q3 Soft Start negative to positive cycle, after AC zero- GS_Q3 crossing, Q4 first turns on with a very small VGS_Q2 pulse width. The pulse width then gradually increases to D (the duty cycle generated by VGS_Q1 control loop). By doing a soft-start on Q4, Q1 completely reverse recovers. Now the voltage, All Switches are Off VDS, of Q2 gradually reduces to ground, thus the positive spike caused by scenario 1 is eliminated. Once the Q4 soft-start is complete, the sync FET, Q3, this dead zone. Otherwise, when the PFC turns back on, starts a soft turn-on with a tiny pulse width and gradually the integrator build-up in the loop generates a large PWM increases until the pulse width reaches 1 – D. This elimi- pulse, which can cause a large current spike. nates the negative current spike caused by scenario 2. The same operation principle applies to the AC transi- At the same time when the Q4 soft-start is complete and tion from a positive to a negative cycle. the Q3 soft-start begins, the low frequency switch, Q2, is turned on. Since the body diode of Q1 is already recov- Experiment results ered, there is no short-through issue as mentioned in The method proposed earlier was verified on a 1-kW scenario 3. totem-pole PFC that was controlled with a UCD3138 Also, since Q3 starts with a very small pulse width, it is digital controller from Texas Instruments. Figure 8 is the insufficient for an inductor to build a negative current high current waveform with a traditional control method and enough, and thus eliminates the current spike caused in Figure 9 shows the current waveform with the proposed scenario 4. method. Both were tested with the same conditions. Finally, the zero-crossing detection could be mistrig- Notice how the current spikes are significantly reduced gered by noise. For safety purposes, all the switches are with the proposed method and the current waveform turned off at the end of a positive cycle. This leaves a becomes much smoother at AC zero-crossing. As a result, small dead zone to prevent the input AC from short the total harmonic distortion (THD) is reduced from circuiting. Note that the control loop should freeze during 8.1% to 3.7%.

Figure 8. Current waveform using a Figure 9. Current waveform with the traditional control method proposed control method

V 1 AC 1 VAC (100 V/div) (100 V/div)

3 i 3 L iL (2 A/div) (2 A/div)

Time (2 ms/div) Time (2 ms/div)

Texas Instruments 25 AAJ 4Q 2015 Analog Applications Journal Communications

Conclusion References While totem-pole PFC is attracting more attention, some 1. J. C. Salmon, “Circuit topologies for PWM boost rectifi- design challenges prevent it from being widely adopted. ers operated from 1-phase and 3-phase ac supplies and One inherent issue in a totem-pole PFC is the current using either single or split dc rail voltage outputs,” in spikes at AC zero-crossing. The causes for current spikes Proc. IEEE Applied Power Electronics Conf., Mar. 1995, are complicated: turn-on sequence, slow reverse-recovery pp. 473–479. of MOSFET’s body diode, large COSS of MOSFET, sudden 2. L. Huber, Y. Jang and M. Jovanovic, “Performance turn on of the active FET with almost 100% duty cycle, Evaluation of Bridgeless PFC Boost Rectifiers”, IEEE sudden turn on of the sync FET, and so on. All these Transaction on Power Electronics, Vol. 23, No. 3, May scenarios contribute to spikes. By turning the switches on 2008. with a special sequence, and executing a soft-start mecha- 3. B. Su, J. Zhang and Z. Lu, “Totem-pole Boost Bridgeless nism on both the main and sync FETs, current spikes can PFC rectifier with simple zero-current detection and be significantly reduced and THD is significantly improved. full-range ZVS operating at the boundary of DCM/CCM,” IEEE Trans. Power Electron., vol.26, no.2, Feb. 2011. 4. Z. Ye, A. Agular, Y. Bolurian and B. Daugherty, “GaN FET-Based CCM Totem-Pole Bridgeless PFC,” The 23rd TI Power Supply Design Seminar, 2014. Related Web sites Product information: UCD3138 Subscribe to the AAJ: www.ti.com/subscribe-aaj

Texas Instruments 26 AAJ 4Q 2015 Analog Applications Journal Personal Electronics Faster, cooler charging with dual chargers

By Jeff Falin Applications Engineer, Power Management Battery Management Systems High Power Chargers

As the functionality and related power demands of the rechargeable battery-powered electronics such as smart- Figure 1. Example of I-FET charger efficiency phones and cameras grew, so did their batteries’ capacities 98 in order to extend run time. With higher-power wall adap- bq25892 tors and USB 3.x providing higher currents at 5 V, 9 V and 96 VBAT = 3.8 V VBUS = 5 V 12 V, increasing the charger’s input current limit to accept ) 94

% the additional power gives more charging current for ( faster charging. This also results in more losses that the 92 V = 9 V charger dissipates as heat. Historically, these losses have BUS 90

been distributed through the PCB ground plane by careful Efficiency 88 placement of the external FETs with the charge-controller VBUS = 12 V IC’s. Consumer demand for smaller portable electronics 86 has forced IC manufacturers to develop battery-charger ICs with integrated FETs (I-FETs) and with smaller pack- 84 aging. Including thermal considerations early in the design 0 1 2 3 4 5 6 Charge Current (A) is critical to ensure that these high-current, I-FET char- gers provide the designed charge current without over- heating the PCB. With a 9-V input adapter, a battery charger with 91% Thermal management in portable devices requires efficiency was set to provide a 3-A charging current to a careful PCB layout. For example, removing the heat from 3.8-V charged battery with loses of an IC in a QFN package with an exposed bottom thermal P = 3.8 V × 3 A × (1 / 0.91 – 1), pad requires that the thermal pad be connected to a L which equals 1.13 W in heat. The charger IC was soldered copper ground plane that is not thermally saturated, pref- onto a four-layer, 31-mil thick, FR-4 board with 2-oz erably exposed (as opposed to internal). Too many ICs in copper. The package’s thermal pad was properly soldered close proximity that are trying to use the same heat-sink- down to the top-layer copper ground pour and through ing ground plane can saturate the plane with heat, causing vias-to-ground pours on each of the internal and bottom the ICs to overheat and go into lower-power thermal-­ layers. All of this copper acted as a heat sink. The image in regulation mode, or even shutdown. Figure 2 shows a thermal image for a 4- by 4-mm QFN Additionally, when the ground plane of the printed- package where the temperature rise was 16.1°C at the IC’s circuit board (PCB) is thermally saturated, the device’s top-side case with a 25°C ambient air temperature. In this outside case temperature rises to unacceptable levels. To prevent this, each IC and a section of its adjacent ground plane should be allocated a portion of a thermal budget. Figure 2. Thermal image of single-charger The thermal budget sets a hard limit to the amount of heat operation (VIN = 9 V, VBAT = 3.8 V, ICHRG = 3 A) that a single, small-­footprint, I-FET charger, outputting several amperes of current, can dissipate without raising the device’s case temperature. For a buck charger with integrated FETs, the IC’s effi- ciency is P VI× η = OUT = BATCHRG PIN VIBUSB× US and loss through heat is

 1  PPLI= NO−PPUT =OUT × −1  η  At higher currents, this loss is dominated by the I2R losses across the internal FETs. Figure 1 shows the ­efficiency of a battery charger, such as the bq25890, at different charging currents and input voltages.

Texas Instruments 27 AAJ 4Q 2015 Analog Applications Journal Personal Electronics image, cool is shown as blue/green, warm as yellow, and hotter would show as red to Figure 3: Dual-charger ICs in a parallel configuration white. The PCB tested for Figure 2 contained OTG I no other power dissipating ICs, so the BUS1 copper ground area approximates an infi- V nite heat sink and was not saturated. This BUS SYS state is evidenced by the blue and green Q1 Q2 colors surrounding the yellow hot spot of the IC. Increasing the charging current of this Q3 same charger by 50% to 4.5 A resulted in a I temperature rise of 37°C compared to BUS2 25°C ambient. This temperature rise may be within the thermal budget of some devices, but not others. Q4 Using the same concept of thermal BAT distribution across the PCB as a charge Charger-1 (Charge & Discharge) controller with external FETs, two I-FET charger ICs in parallel, referred to as a dual-charger configuration, can be used. In general, there is no stability issue when VBUS Q1 Q2 (No System connecting the battery-output pins of Connection) multiple chargers in parallel. This is because, while in constant-current (CC) Q3 mode, the charger’s battery pin (BAT) has the characteristics of a high-impedance current source. While in constant-voltage (CV) mode, but well before termination, the battery pin characteristics are like a Q4 + low-impedance voltage regulator. Dual- BAT Battery charger ICs in a parallel configuration are Charger-2 (Charge Only) shown in Figure 3. Charger-1 is configured for charging, however, if the internal battery FET (Q4) that provides a power path has low enough RDS(on), this IC also provides battery discharge through Q4. Charger-2 is configured only for optimization (ICO) to extract maximum adapter power charging. If required, charger-1 exclusively provides a USB without causing loop instability at their mutual VBUS node. On-The-Go (OTG) 5-V power rail at VBUS after charger-2 There­fore, each charger’s current-limit feature should be has been configured for high-impedance mode. Even with set to half the adapter’s maximum output current. Inductor the same termination voltage and current settings, and current ratings may also be reduced by half as well. high regulation accuracy, one charger always attempts to To prevent the VINDPM loop from causing instability and terminate before the other due to the mismatch in each to give charger-1 priority in powering the system, set the charger’s internal reference voltages and currents. If both VINDPM for charger-2 higher than that of charger-1. If the chargers are set to the same termination current, both chargers have an integrated analog-to-digital converter chargers will have difficulty terminating the charge. (ADC) to provide real-time measurements of the charge Therefore, the termination current of one charger (typi- current and the input, system and battery voltages, the cally charger-2) should be set higher than the other (typi- host software must continuously monitor this information, cally charger-1) to allow for a smooth termination. as well as the loop status bits. The host software must When the total required input current is high (for then refresh each charger’s current limit and charge example, ICHARGE > 5 A with a 5-V adapter), the parallel current settings in order to maximize adapter power while configuration is recommended for best thermal distribu- balancing power and thermal loading between the two tion. With both input pins connected, neither charger can chargers. use its control loop for automatic input-current-limit

Texas Instruments 28 AAJ 4Q 2015 Analog Applications Journal Personal Electronics

When the total required input current Figure 4: Dual-charger ICs in a cascade configuration is lower (for example, ICHARGE < 5 A or an adapter change from 9 V to 12 V) and charger-1’s reverse-blocking and current- OTG limiting FET (Q1) has low enough R , DS(on) IVBUS IVBUS1 the cascade configuration shown in Figure 4 may be a better option. VBUS SYS In the cascade configuration, charger-1 controls the total input current for both Q1 Q2 chargers. Host software development is PMID greatly simplified because the VINDPM and ICO features for charger-1 can be fully IVBUS2 Q3 utilized to maximize adapter power extraction. In the event of a large system load transient while in the CV mode, the buck converter for charger-1 could see a higher input current. Therefore, the Q4 inductor for charger-1 needs to be sized BAT to handle the adapter’s full input current. Charger-1 (Charge & Discharge) If members of the same charger family with different I2C addresses are available, say the bq25890 for charger-1 and bq25892 for charger-2, development is VBUS even easier because no additional hard- Q1 Q2 (No System ware is required to switch between the Connection) I2C communication lines of each charger. Q3 Using the same PCB and test setup from Figure 2, the cascade chargers (Figure 4) were set to provide 2.25-A charge current to a 3.8-V battery and were 92% efficient. The heat loss for each charger was only Q4 BAT + PL = 3.8 V × 2.25 A (1/0.92 – 1) = 0.74 W. Battery The top-side case temperature of both Charger-2 (Charge Only) chargers rose above 25°C ambient by only 17°C, as measured by the thermal camera image in Figure 5. This is only 1°C above the single-charger case from Figure 2 for a 50% increase in charge current. Figure 5. Thermal image of dual-charger operation (VIN = 9 V, VBAT = 3.8 V, ICHRG = 4.5 A)

Texas Instruments 29 AAJ 4Q 2015 Analog Applications Journal Personal Electronics

Figure 6 shows the typical charger-termination profile as the charger transitions from constant-current to constant- Figure 6. Dual-charger charge-termination profile voltage regulation. Following the previous recommenda- tion, for a clean termination, charger-2 terminates CC Mode CV Mode charging before charger-1. VBAT (1 V/div) Conclusion IBAT (1 A/div) Charger-2 Most battery-charger ICs have a thermal regulation loop Termination that reduces their charge current in order to protect the ICharger-1 Charge IC from damage due to overheating. As such, PCB thermal 1 (1 A/div) Done management is critical to maximize the charge current (which reduces charge time) into today’s high-capacity 4 ICharger-2 batteries in addition to maintaining practical outside case 3 (1 A/div) temperatures. Thermal management includes assigning CC to CV thermal budgets to all heat-producing ICs, careful IC 2 Transition placement, and heat-sink grounding on the PCB to distrib- ute heat without thermally saturating the copper pours and planes of PCB ground. Using I-FET dual chargers, either in a parallel or cascade configuration as the applica- tion allows, gives better heat distribution for lower IC and case temperatures along with faster, cooler charging and longer device run times. Reference 1. “Dual Battery Charger IC Reference Design (connected in Cascode Configuration),” TI Designs, TIDA-00590 Related Web sites Product information: bq25890 bq25892 bq24715 Subscribe to the AAJ: www.ti.com/subscribe-aaj

Texas Instruments 30 AAJ 4Q 2015 Analog Applications Journal

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