High Speed Serial IOs

Ethernet Peter Thorwartl

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Most widely used Local Area Networking (LAN) technology in the world today Initial system was based on an earlier idea called the Aloha Network Developed in Hawaii in the late 60’s for a radio network among Hawaiian islands Known as Pure Aloha, it shared a common channel Send data anytime and wait for acknowledgement; if not received in a short time, a collision with another transmitting station is assumed After a random back-off time, the station would then resend Due to increasing loads and higher collision rates, utilization was about 18 percent

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Ethernet is a technology that transmits information among computers at speeds of 10 and 100 Mbps as well as 1 and 10 Gbps. Currently, 100-Mbps twisted pair is the most widely used version of Ethernet technology. ALOHAnet, also known as ALOHA, was a pioneering computer networking system developed at the University of Hawaii. It was first deployed in 1970, and while the network itself is no longer used, one of the core concepts in the network is the basis for the almost-universal Ethernet. ALOHA was important because it used a shared medium for transmission. This revealed the need for more modern contention management schemes, such as Carrier Sense Multiple Access with Collision Detect (CSMA/CD), used by Ethernet. Unlike ARPANET, where each node could only talk to a node on the other end, in ALOHA everyone was using the same frequency. This meant that some sort of system was needed to control who could talk at what time. The ALOHA scheme was very simple. Because data was sent via a teletype, the data rate usually did not go beyond 80 characters per second. When two stations tried to talk at the same time, both transmissions were garbled. Then data had to be manually resent. ALOHA proved that it was possible to have a useful network without solving this problem, and this sparked interest in others—most significantly Bob Metcalfe and other researchers working at the Xerox Palo Alto Research Center. This team went on to create the Ethernet protocol.

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Slotted Aloha Further developments resulted in a networking system with transmission slots assigned and a master clock used Channel utilization went up to about 37 percent A new system was developed to deal with increasing loads and collision rates Detected when a collision occurred (Collision Detect) Stations listened for activity before transmitting (Carrier Sense) Supported access to a shared channel by multiple stations (Multiple Access) This system led to Carrier Sense Multiple Access with Collision Detect (CSMA/CD), an Ethernet channel access protocol Sophisticated back-off algorithm for up to 100-percent channel utilization

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The Aloha protocol is an OSI layer 2 protocol for LAN networks with a broadcast topology. The first version of the protocol was basic: If you have data to send, send the data. If the message collides with another transmission, try resending later. What is later? Determining a good back-off scheme for the protocol also determines much of the total efficiency of the protocol, and how deterministic its behavior will be (how predictable will the protocol change as load changes?).

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Robert Metcalfe changed the name of the Aloha network to Ethernet after his first experimental network To make it clear it supported any computer and that it had evolved from the Aloha system “Ether” to describe the physical medium (the cable, for example) which carries the bits to all stations, like “Luminiferous Ether” Original standard published in 1980 using thick coaxial cable Known as the DIX standard (DEC, Intel, and Xerox) In 1985, the IEEE also standardized it under the 802.3 branch Next came media such as thin coaxial, twisted pair, and fiber optics with speeds from 10 Mbps, to 100 Mbps, , and most recently 10-Gigabit Ethernet

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Ethernet was invented at the Xerox Palo Alto Research Center in the 1970s (May 22nd 1973) by Dr. Robert M. Metcalfe. It was designed to support research on the “office of the future,” which included one of the world’s first personal workstations, the Xerox Alto. The first Ethernet system ran at approximately 3 Mbps and was known as “experimental Ethernet.” Formal specifications for Ethernet were published in 1980 by a multi-vendor consortium that created the DEC- Intel-Xerox (DIX) standard. This effort turned the experimental Ethernet into an open, production-quality Ethernet system that operated at 10 Mbps. Ethernet technology was then adopted for standardization by the LAN standards committee of the Institute of Electrical and Electronics Engineers (IEEE 802). From the time of the first Ethernet standard, the specifications and the rights to build Ethernet technology have been made easily available to anyone. This openness, combined with the ease of use and robustness of the Ethernet system, resulted in a large Ethernet market and is another reason Ethernet is so widely implemented in the computer industry. 10-Mbps Ethernet media varieties include the original thick coaxial system, as well as thin coaxial, twisted pair, and fiber optic systems. The most recent Ethernet standard defines the new 100-Mbps Fast Ethernet system, which operates over twisted pair and fiber optic media. The ability to link a wide range of computers using a vendor-neutral network technology is an essential feature for today’s LAN managers. Most LANs must support a wide variety of computers purchased from different vendors—requiring a high degree of network interoperability of the sort that Ethernet provides. The IEEE standard was first published in 1985 with the formal title of “IEEE 802.3 Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications.” The IEEE standard has since been adopted by the International Organization for Standardization (ISO), which makes it a worldwide networking standard.

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There are four basic building blocks which complete an Ethernet system Standard used to carry bits over the system Media Access Control (MAC) Control block for allowing multiple systems to access the Ethernet channel fairly Signaling components Components used to send and receive signals over the Ethernet channel Physical medium The cabling and other hardware used to carry the Ethernet signals among systems on the Ethernet

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Each Ethernet-equipped computer, also known as a station, operates independently of all other stations on the network; that is, there is no central controller. All stations attached to an Ethernet are connected to a shared signaling system, also called the medium. Ethernet signals are transmitted serially, one bit at a time, over the shared signal channel to every attached station. To send data, a station first listens to the channel. When the channel is idle, the station transmits its data in the form of an Ethernet frame, or packet. After each frame transmission, all stations on the network must contend equally for the next frame transmission opportunity. This ensures that access to the network channel is fair and that no single station can lock out the other stations. Access to the shared channel is determined by the Media Access Control (MAC) mechanism embedded in the Ethernet interface located in each station. The MAC is based on the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) protocol.

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PHY would be Back-End Interface an external chip MAC InterfaceInterface

if the RocketIO™ TX Data Transmit TX Ctrl Engine interface is not PHY Flow Pause Req Flow used Contro The ‘Ether’ Pause Value Controll In such cases, MAC will have RX Data Receive standard RX Ctrl Engine interfaces like Medium MDIO Interface Management Independent Interface (MII) and Gigabit Medium Independent Interface (GMII)

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PHY is an external chip if it is a non-RocketIO transceiver interface. In cases where RocketIO are used, it will reside on the FPGA chip (Virtex™-II Pro and Virtex-4 FX FPGAs). The Ether is the medium—it can be a copper wire, twisted pair, or optical fiber. A management interface is optional in some cases and required in other cases.

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Internet Supplier Network

Exterior Router Exterior Router

Perimeter Network

Interior Router Lab Network Internal Network

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Each network segment can work at a different bit rate and with different protocols. Routers store and forward packets and also convert packets of one protocol to another.

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IEEE 802.3 groups 802.3a (1985) 10BASE2 Thin Ethernet 802.3i (1990) 10BASE-T Twisted Pair 802.3j (1993) 10BASE-F Fiber Optic 802.3u (1995) 100BASE-T Fast Ethernet and Auto-Negotiation 802.3x (1997) Full Duplex Standard 802.3z (1998) 1000BASE-X Gigabit Ethernet 802.3ac (1998) VLAN TAG 802.3ab (1999) 1000BASE-T Gigabit Ethernet over Twisted Pair 802.3ac (2000) Link Aggregation 802.3ae (2002) 10 Gbps Ethernet 802.3af (2003) 802.3ak (2004) 10GBASE-CX4

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10BASE2 Thin coaxial cable, 185 m maximum 10BASE-T Term used for any 10-Mb twisted pair media system 10BASE-F Term used for any 10-Mb fiber optic media system 100BASE-T Generic term used for any 100-Mb media system 100BASE-X Term used for any 100-Mb media system based on 4B/5B block encoding systems 100BASE-TX: twisted pair cable 100BASE-FX: fiber optic cable

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The IEEE identifiers include three pieces of information. For example, with 10BASE5, the 10 indicates the media speed of 10 Mbps. BASE indicates baseband, which is a type of signaling. Baseband signaling means that Ethernet signals are the only signals carried over the media system. The third part of the identifier provides a rough indication of segment type or length. For thick coax, 5 indicates the 500-meter maximum length allowed for individual segments of thick coaxial cable. For thin coax, 2 is rounded up from the 185-meter maximum length for individual thin coaxial segments. T and F indicate twisted-pair and fiber optic, respectively, and mean the cable type. When PHY type is used in the identifier, a “-” is used after BASE. When length is used, “-” is not used after BASE. The thick coaxial media segment was the first one defined in the earliest Ethernet specifications. Next came the thin coaxial segment, followed by the twisted pair and fiber optic media segments. The twisted pair segment type is the most widely used today for making network connections to the desktop. 10BASE-FB: Active fiber hubs based on synchronous repeaters for extending a backbone system. 10BASE-FP: Passive hub equipment intended to link workstations with a fiber optic hub. 10BASE-FL: Fiber optic link segment specification that updates and extends the older Fiber Optic Inter Repeater Link (FOIRL) standard 100BASE-T4: Uses four pairs of Category 3 or better twisted pair cable. 100BASE-T2: Uses two pairs of Category 3 or better twisted pair cable.

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1000BASE-X Term used for any 1-Gb media system based on 8B/10B encoding 1000BASE-SX: short-wave laser using a fiber optic cable 1000BASE-LX: long-wave laser using a fiber optic cable 1000BASE-CX: copper wire cable 1000BASE-T Term used for any 1-Gb media system based on 4D-PAM5 block encoding transmitted over a twisted pair cable 4D-PAM5: twisted pair which transmits over four wire pairs. Translates an 8-bit byte of data into simultaneous transmissions of four code symbols (4D); sends over the medium as 5-level Pulse Amplitude Modulated (PAM5) signals

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10GBASE-X Term used for any 10-Gb media system based on a fiber optic cable with a 8B/10B PHY encoding type 10GBASE-R Term used for any 10-Gb media system based on a fiber optic cable with a 64B/66B PHY encoding type 10GBASE-W Term used for any 10-Gb media system based on a fiber optic cable with a 64B/66B and WIS PHY encoding type The WAN Interface Layer (WIS) provides a medium-independent means for the (PCS) to operate over WAN links. It creates 10GBASE-W encoding by encapsulating the encoded data stream from the 10GBASE-R PCS in frames compatible with SONET and SDH transmission formats

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This diagram illustrates the parallelism between an OSI model and a postal service used by an office manager.

SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 12 Located in Austria & Brazil [email protected] Date Oct 23, 2009 OSI Model Layers

Physical layer: hardware; raw bitstream 7. Application Transmits the raw bitstream over a physical cable 6. Presentation Defines cables, cards, and physical aspects Defines Network Interface Card (NIC) attachments to hardware 5. Session

and how the cable is attached to the NIC 4. Transport Defines techniques to transfer the bitstream to the cable Protocols 3. Network IEEE 802, IEEE 802.2, and ISO 2110 ISDN 2. Data Link

Example components 1. Physical Repeater, multiplexer, hubs, oscilloscope, and amplifier

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The OSI model provides a conceptual framework for communication among computers, but the model itself is not a method of communication. Information being transferred from a software application in one computer system to a software application in another must pass through the OSI layers. For example, if a software application in System A has information to transmit to a software application in System B, the application program in System A will pass its information to the application layer (Layer 7) of System A. The application layer then passes the information to the presentation layer (Layer 6), which relays the data to the session layer (Layer 5), and so on down to the physical layer (Layer 1). At the physical layer, the information is placed on the physical network medium and is sent across the medium to System B. The physical layer of System B removes the information from the physical medium, and then its physical layer passes the information up to the data link layer (Layer 2), which passes it to the network layer (Layer 3), and so on, until it reaches the application layer (Layer 7) of System B. Finally, the application layer of System B passes the information to the recipient application program to complete the communication process. Layer 1: Conveys the bitstream (electrical impulse, light, or radio signal) through the network at the electrical and mechanical level. It provides the hardware means for sending and receiving data on a carrier, including defining cables, cards, and physical aspects. Fast Ethernet, RS232, and ATM are protocols with physical layer components.

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Data link layer: reliable transfer across the physical link Turns packets into raw bits and at the receiving end turns bits 7. Application into packets at the transmitter 6. Presentation Handles data frames between the network and physical layers The receiving end packages raw data from the physical layer into 5. Session data frames for delivery to the network layer 4. Transport Responsible for error-free transfer of frames to the other computer via the physical layer 3. Network Defines methods used to transmit and receive data on the 2. Data Link network and the signalling involved to transmit and receive data and the ability to detect signalling errors on the network 1. Physical

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Layer 2: Data packets are encoded and decoded into bits. It furnishes transmission protocol knowledge and management and handles errors in the physical layer, flow control, and frame synchronization. The data link layer is divided into two sublayers: the MAC layer and the Logical Link Control (LLC) layer. The MAC sublayer controls how a computer on the network gains access to the data and permission to transmit it. The LLC layer controls frame synchronization, flow control, and error checking.

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Logical Link Control (LLC) Error correction and flow control 7. Application

Manages link control and defines Service Access Points (SAPs) 6. Presentation Media Access Control (MAC) 5. Session Communicates with the PHY Controls the type of media being used 4. Transport 802.3 CSMA/CD (Ethernet) 3. Network 802.4 Token Bus (ARC net) 802.5 2. Data Link 802.12 Demand Priority 1. Physical Example components Bridge, switch, intelligent hub, and NIC

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Network layer: addressing and routing Translates logical network address and names to their physical 7. Application address (for example, IP address  MAC address) 6. Presentation Responsible for addressing, determining routes for sending, and managing network problems, such as packet switching, 5. Session data congestion, and routing 4. Transport If the router cannot send a data frame as large as the source sends, it compensates by breaking data into smaller units. At 3. Network the receiving end, the network layer reassembles the data 2. Data Link Think of this as layer stamping the addresses on each train car Protocols: IP, ARP, IPX, and NetBEUI 1. Physical Example components Router, frame relay device, and ATM switch

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Layer 3: This layer provides switching and routing technologies—creating logical paths, known as virtual circuits, for transmitting data from node to node. Routing and forwarding are functions of this layer, as well as addressing, internetworking, error handling, congestion control, and packet sequencing.

SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 16 Located in Austria & Brazil [email protected] Date Oct 23, 2009 OSI Model Layers Transport layer: packets, flow control, and error handling Manages flow control of data among parties across the network Divides streams of data into chunks or packets and reassembles 7. Application messages and byte ordering 6. Presentation Error checking to guarantee error-free data delivery Provides acknowledgement of successful transmissions and 5. Session requests retransmission if packets do not arrive error free 4. Transport Responsible for reliable, transparent transfer of data among end points 3. Network Protocols 2. Data Link TCP, ARP, SPX, and UDP Example components 1. Physical Gateway and advanced cable tester router

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Layer 4: This layer provides transparent transfer of data among end systems, or hosts, and is responsible for end- to-end error recovery and flow control. It ensures complete data transfer.

SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 17 Located in Austria & Brazil [email protected] Date Oct 23, 2009 OSI Model Layers Session layer: syncs and sessions Provides for the establishment of communication sessions among applications. It can deal

with authentication and access control, synchronization and data check pointing, for 7. Application example 6. Presentation Presentation layer: translation Responsible for the problems associated with communication 5. Session

among networked systems that use different methods of local 4. Transport data representation. When used, it allows data to be exchanged among machines that store information in different formats 3. Network

Application layer: user interface 2. Data Link

Provides generic application functions, such as mail utilities and file transfers, for example 1. Physical

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Layer 5: This layer establishes, manages, and terminates connections among applications. The session layer sets up, coordinates, and terminates conversations, exchanges, and dialog among the applications at each end. It deals with session and connection coordination. Layer 6: This layer provides independence from differences in data representation (encryption, for example) by translating from application to network format, and vice versa. The presentation layer works to transform data into the form that the application layer can accept. This layer formats and encrypts data to be sent across a network, providing freedom from compatibility problems. It is sometimes called the syntax layer. Layer 7: This layer supports application and end-user processes. Communication partners are identified, is identified, user authentication and privacy are considered, and any constraints on data syntax are identified. Everything at this layer is application specific. This layer provides application services for file transfers, e-mail, and other network software services. Telnet and FTP are applications that exist entirely in the application level. Tiered application architectures are part of this layer.

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UDP, IP, TCP/IPv4Bus Management FIFO, Flow ControlFrame Generation, Stats Gathering, Flow LineControl Coding, Auto-Neg, Sync, 8B/10BSerdes, Clk-rec, CML/PECL Transceiver

PPC PLB Bus MAC P P Fiber/Copper Management Generic GMII PCS TBI M 64 M MDI LX/SX/CX A D 10 User FIFO 8 8 Logic Gen ® 16

OSI Layer 3 and 4 OSI Layer 2 OSI Layer 1 (Network/Transport Layer) (Data Link Layer) (Physical Layer) Software Hardware Hardware

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The above application could fall under a NIC card or switch (line card); that is, the PPC could be replaced with PCI. 1000BASE-X = fiber or copper. PMD = Physical Medium Dependent LX = Long wavelength optical transmission (1300-nm wavelength). Covers both Single-Mode Fiber (SMF) and Multi-Mode Fiber (MMF). In SMF, this is good for 3 km. Although you could assume that you should always use LX, this is not the case. LX lasers cost about three times SX. SX = Short wavelength optical transmission (850-nm wavelength). This is MMF only and is good for approximately 200 m. CX = Single copper media (150-Ohm balanced copper). Xilinx does not support 1000BASE-T. Twisted pair standard uses 3B/4B rather than 8B/10B. PMD = Stratos. The transceiver will be used on the ML3 board. (LVPECL = Low Voltage Positive Emitter- Coupled Logic). CML = Current Mode Logic Note: Xilinx is researching 1-Gb FIFO and has started investigating the PLB PPC bus.

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PHY types for each Ethernet type 10 Mbps Clause 7 10 Mbps Manchester Encoding 100BASE-T4 Clause 23 100 Mbps 8B/6T 100BASE-X Clause 24 100 Mbps 4B/5B 100BASE-T2 Clause 32 100 Mbps PAM5X5 1000BASE-X Clause 36 1000 Mbps 8B/10B 1000BASE-T Clause 40 1000 Mbps 4D-PAM5 10GBASE-X Clause 48 10 Gbps 4 lane 8B/10B 10GBASE-R Clause 49 10 Gbps 64B/66B 10GBASE-W Clause 49 10 Gbps 64B/66B and Clause 50 WIS

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Physical Coding Sublayer (PCS) (1000BASE-X example) The PCS provides a uniform interface to the reconciliation layer of the MAC. It uses 8B/10B coding, where groups of 8 bits are represented by 10-bit code groups. Some code groups represent 8-bit data symbols; others are control symbols It can be used to generate carrier sense and collision detect indications. It also manages the auto-negotiation process by which the NIC communicates with the network to determine the mode of operation (half duplex or full duplex)

Line Coding, Auto-Neg, Sync, 8BSerdes,/10B Clk-rec, CML/PECL Transceiver

P P PCS Fiber/Copper TBI M M MDI A D LX/SX/CX 10

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 21 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Physical Layer Physical Medium Attachment (PMA) The PMA sublayer provides a medium-independent means for the PCS to support various serial, bit-oriented physical media types. This layer serializes code groups for transmission and deserializes bits received from the medium into code groups Physical Medium Dependent (PMD) The PMD sublayer maps the physical medium to the PCS. This layer defines the physical layer signalling used for various media The Medium Dependent Interface (MDI), which is a part of PMD, is the actual physical layer interface. This layer defines the actual physical attachments, such as connectors, for different media types Line Coding, Auto-Neg, Sync, 8B/1Serdes,0B Clk-rec, CML/PECL Transceiver

P P PCS Fiber/Copper TBI M M MDI A D LX/SX/CX 10

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7. Application Example Protocols

TELNET, HTTP, SMTP 6. Presentation File transfer, mail, APIs Software 5. Session Layers Error control, end-to-end transmission, retransmission IETF 4. Transport UDP/TCP, SNMP

IP 3. Network ARP, routing

Gigabit Ethernet MAC Hardware 2. Data Link Framing, error detection, link flow control

Layers Gigabit Ethernet PCS/PMA 1. Physical Line drivers/receivers, Encoder/decoders, timing IEEE802 1000BASE-LX

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Transport layer: Controls errors, transmission, and retransmission. Also drives the simple network manager protocol. (UDP = and TCP = Transmission Control Protocol.) Network layer: IP layer (0x0800). Sets up the Address Resolution Protocol (ARP) and therefore has routing information; that is, building a cache table in each station joining Ethernet addresses to IP addresses. For example: IPv4, which is a 32 bit-address IP protocol (type 0x0806). LLC = Logical Link Control. Multiplexing/demultiplexing: Deciding which protocol is being sent. Can break down which protocol is being used and pass the frame to the correct software; that is, TCP/IP (type encapsulated IP=0x800) or AppleTalk (length encapsulated). It is not part of IEEE802.3 because this layer is part of all LAN systems not just Ethernet; that is, IEEE802.2. This software layer can multiplex and demultiplex length encapsulated data. Sub-Network Access Protocol (SNAP) is a length-type encapsulation used to store Type fields in its Data field. IETF = Internet Engineering Task Force RFC = Request For Comment

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Ethernet frames are the heart of the system. The system moves these frames among computers and stations. A frame consists of: Preamble Used to give the hardware in the system a signal startup time to recognize a frame transmission. Not used in gigabit systems but kept for frame structure similarities The DIX frame consists of 7 0x55 followed by 0xD5 The 802.3 frame consists of 7 0x55 followed by a Start of Frame Delimiter (SFD), which is 0x55D5

8 Bytes 6 Bytes 6 Bytes 2 Bytes 46 to 1500 Bytes 4 Bytes Frame Check Preamble Destination Source Length/ Data Sequence Address Address Type (CRC)

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Destination/source address Unique 48-bit address, made up of a 24-bit Organizationally Unique Identifier (OUI) assigned by the IEEE Standards Association, followed by a unique 24-bit vendor-specific address Also known as the MAC, hardware, or physical address Length/type Used to carry length information; also used to identify what type of high-level network protocol is being carried in the Data field Data Can be between 46 bytes (minimum length) to 1500 bytes. Padding can be used if the length is less than 46 bytes to ensure every Ethernet system “hears” the frame (FCS) Contains the CRC from the sending station to check frame integrity

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The first two fields in the frame carry 48-bit addresses, called the destination and source addresses. IEEE controls the assignment of these addresses by administering a portion of the Address field. The IEEE does this by providing 24-bit identifiers called Organizationally Unique Identifiers (OUIs) because a unique 24-bit identifier is assigned to each organization that wants to build Ethernet interfaces. The organization, in turn, creates 48-bit addresses using the assigned OUI as the first 24 bits of the address. This 48-bit address is also known as the MAC address, hardware address, or physical address. A unique 48-bit address is commonly pre-assigned to each Ethernet interface when it is manufactured, which vastly simplifies the set up and operation of the network. As each Ethernet frame is sent onto the shared signal channel, all Ethernet interfaces look at the first 48-bit field of the frame, which contains the destination address. The interfaces compare the destination address of the frame with their own address. A multicast address allows a single Ethernet frame to be received by a group of stations. Network software can set the Ethernet interface of a station to listen for specific multicast addresses. A single packet sent to the multicast address assigned to that group will then be received by all stations in that group. There is also a special case of the multicast address known as the broadcast address, which is the 48-bit address of all ones. All Ethernet interfaces that see a frame with this destination address will read the frame in and deliver it to the networking software on the computer. The Length/Type field, when its value is greater than 0x05DC (1500), signifies the high-level protocol type. For example, 0x0600 is used for Xerox NS IDP, 0x0601 XNS Address Translation (3 MB only), 0x0800 DOD Internet Protocol (IP), 0x0801 X.75 Internet, 0x0802 NBS Internet, 0x0806 Address Resolution Protocol (ARP), and 0x809B EtherTalk (AppleTalk over Ethernet). The FCS is a polynomial and is computed as: G(x) = X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1

SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 25 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Media Access Control Consists of two modes: half duplex and full duplex Full duplex mode uses the same format but switches off the CSMA/CD protocol because it does not use a shared channel Half duplex follows a set of rules to arbitrate access to a shared channel to which the stations are attached Using a broadcast delivery system, stations will hear a transmission. A station will also listen for an idle channel before transmitting All systems read the frame and accept the frame if it matches its unicast, multicast, or broadcast address; else will stop reading A multicast address is an address recognized by a group of stations. Broadcast, 48 1s, address all stations All stations contend equally for the channel using the CSMA/CD protocol

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Each interface must wait until there is no signal on the channel, after which it can begin transmitting. If some other interface is transmitting there will be a signal on the channel, which is called carrier. All other interfaces must wait until carrier ceases before trying to transmit, and this process is called carrier sense. All Ethernet interfaces are equal in their ability to send frames onto the network. No one has a higher priority than anyone else, and democracy reigns. This is what is meant by multiple access. Because signals take a finite time to travel from one end of an Ethernet system to the other, the first bits of a transmitted frame do not reach all parts of the network simultaneously. Therefore, it is possible for two interfaces to sense that the network is idle and to start transmitting their frames simultaneously. When this occurs, the Ethernet system has a way to sense the collision of signals and to stop the transmission and resend the frames. This is called collision detect. The Carrier Sense Multiple Access with Collision Detect (CSMA/CD) protocol is designed to provide fair access to the shared channel so that all stations have a chance to use the network. After every packet transmission, all stations use the CSMA/CD protocol to determine which station uses the Ethernet channel next. If more than one station transmits on the Ethernet channel at the same moment, then the signals are said to collide. The stations are notified of this event, and instantly reschedule their transmission using a specially designed back-off algorithm. As part of this algorithm, the stations involved each choose a random time interval to schedule the retransmission of the frame, which keeps the stations from making transmission attempts in lock step.

SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 26 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Interframe Gap

The Interframe Gap (IFG) is provided to allow a recovery time between successive frame reception for the Ethernet interfaces This is set for 96 bits—that is, 9.6 ms for 10 Mbps, 960 ns for 100 Mbps, 96 ns for Gigabit, and 9.6 ns for 10-Gigabit Ethernet systems during which the line is idle A station waits for a period equal to the IFG before transmitting its frame If a station wants to transmit successive frames, it will still wait for a period equal to the IFG before it does so

64 Bits 48 Bits 48 Bits 16 Bits 46 to 1500 Bytes 32 Bits 96 Bits 64 Bits 48 Bits 48 Bits 16 Bits 46 to 1500 Bytes 32 Bits

Dest. Source Interframe Gap Dest. Source Preamble L/T Data FCS Preamble L/T Data FCS Address Address (IFG) Address Address

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 27 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Full Duplex Mode

Allows simultaneous communication between pairs of stations using a point-to- point media segment, such as twisted pair or fiber optic, to provide independent transmit and receive paths In theory, full duplex doubles the aggregate capacity of a link. A 1000-Mbps Ethernet system supporting full duplex mode can simultaneously send and receive a total bandwidth of 2000 Mbps

Picture here of full duplex mode

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 28 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Full Duplex Mode

Not limited by timing requirements when sharing a channel in half duplex mode There are exactly two stations connected in the link, each capable of simultaneously sending and receiving frames Ignores carrier sense, multiple access, and collision detect Still waits for an interframe gap between successive frames to ensure that the interfaces at each end can keep up with the frame rate Currently, new systems tend to support full duplex modes of operation—there is no inclusion for half duplex in the 10-Gigabit Ethernet standard

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 29 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Flow Control

With network traffic growing, switching hubs may need to tell stations to stop sending data because of its buffers filling up A number of non-standard control mechanisms were developed for half duplex mode only Full duplex mode optionally supports the MAC control protocol and the PAUSE operation described in the 802.3x Full Duplex Supplement The MAC control system provides a way for the station to receive and act upon a MAC control frame MAC control frames are identified with a type value of 0x8808. These frames are passed to the MAC control block which looks for an operation code (OPCODE) MAC control frames contain OPCODEs within the Data field. They are 46 bytes in length (minimum frame length) and the OPCODE is contained in the first two bytes

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 30 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Flow Control The PAUSE system uses MAC control frames to carry the PAUSE commands in ful l duplex systems A station equipped with MAC control must send a PAUSE frame to the multicast address of 01-80-C2-00-00-01, which is reserved for PAUSE frames or the unicast address of the port on which the frame is received The OPCODE for a PAUSE command is 0x0001 A station receiving a MAC control frame whose first two bytes are 0x0001 knows the frame is being used to implement a PAUSE operation The frame must also contain a 2-byte specified pause period in units (known as Pause Quanta) of 512 bits with a range of 0 through 65535 units MAC Control OPCODE Pause_time 42 bytes Pause OPCODE = 0x0001 pause_time = 0x0002 of Zeros

Preamble Pause Destination Source MAC Control 46-Byte Data Field FCS Address 01-80-C2-00-00-01 Address Type 0x8808

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 31 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Auto-Negotiation

Auto-negotiation is a function of the PCS The need for automatic configuration becomes apparent when installing a station on an Ethernet system. Things to determine are Speed of the Ethernet system Full duplex or half duplex Not always obvious for the user Depending on the system, auto-negotiation can allow Ethernet equipment to automatically select the correct speed and the duplex, relieving the installer of these configuration tasks Allows the system to run at the highest speed offered by a multi-speed Ethernet switching hub Developed in 1995 as part of the Fast Ethernet IEEE standard for twisted pair GMAC fiber optics systems have their own scheme

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I can perform only I can perform both full duplex full and half duplex modes

MAC PCS MDI PCS MAC

I am able to operate at I am able to operate at 100 10/100 Mbps Mbps Designed to work over link segments only; one device at each end Occurs at link initialization when a device is turned on Uses its own, independent signalling system Information transmitted and received is stored in registers, accessed through the Medium Independent Interface Management (MIIM) interface

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Auto-negotiation and management perform clause 37. Without this block, the link will never appear. Auto-negotiation will complete automatically; that is, the auto-negotiation state machine starts at power up (unless bit 12 of the control register is set; that is, auto-negotiation is off). The data sheet contains all the auto-negotiation registers. The auto-negotiation state machine reads reg4 (advertisement register), sends to the link partner, and waits for 10 ms. Auto-negotiation reads data from the link partner, sends an ACK, and waits for an ACK from the link partner. Auto-negotiation then sends the data to Ability reg(5) of the link partner and sets bit 1 of reg 6 (expansion register). The MIIM can now read data from the partner. Note: It is up to the MIIM to set the MAC according to the link partner; that is, if they can only perform full duplex, then they must only send full duplex data. Writing to the advertisement register to say this is not necessary—it is expected. Both devices perform auto-negotiation simultaneously. Therefore, both devices will be transmitting and receiving auto-negotiation register information at the same time. The full duplex and half duplex modes are examples of the auto-negotiation information. Auto-negotiation information must depend on the abilities of both the MAC and PCS sublayers.

SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 33 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Virtual LANs A Virtual LAN (VLAN) is a logical group of switch ports that behave as though they are an independent switching hub Achieved by manipulating frame forwarding software in the switch Switching hub software is designed to forward frames to various ports based on a set of rules and a forwarding database. A vendor can create VLANs by manipulating these rules Vendors supporting VLAN can provide a management interface so you can set which ports belong to which VLAN An 8-port switching hub can be set to have ports 1–4 in one VLAN and ports 5–8 in another. These VLANs act as separate broadcast domains. For example, a multicast sent on one VLAN will not be transmitted to ports on another Therefore, the VLANs behave as though you had split the 8-port switching hub into two independent 4-port switching hubs

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The maximum length of a frame specified in the IEEE 802.3-2002 specification is 1518 bytes for non-VLAN- tagged frames. VLAN-tagged frames can be extended to 1522 bytes.

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VLANs have other capabilities Can be based on the contents of frames instead of just ports Frames will be filtered as they are received on the switching hub. Frames meeting a certain rule criteria (that is, Source Address or Type field) are automatically placed into the corresponding, filter- defined VLAN In this case, a VLAN is used to create a virtual network based on frame traffic meeting certain criteria VLANs can span multiple switching ports

Frame without VLAN Tag Header Preamble Destination Source Length Data FCS Address Address /Type

2-byte Tag Protocol Identifier (0x8100) 2-byte Tag Control Information, VLAN Identifier Destination Source Length Preamble TPID TCI Data FCS Address Address /Type Frame with 4-Byte VLAN Tag Header

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 35 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Jumbo Frames

Jumbo frames are extended Ethernet frames that range in size above the standard 1,518 bytes Although bit error rates have reduced, frame size has remained the same to maintain backward compatibility Increased data ranges, reduced server overhead, and increased throughput Ethernet’s 32-bit CRC is effective for detecting bit errors at frame sizes under 12,000 bytes, thereby drawing a logical upper limit of 12,000 bytes due to the 32-bit CRC Network File System (NFS) transfers data in 8,192-byte blocks. So adding room for headers, an attractive maximum Ethernet frame size for NFS applications is 9,000 bytes

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 36 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Jumbo Frames

There is no standard for jumbo frames—a proprietary system supported by various vendors How can jumbo frames and 1500-byte frames coexist? Two basic approaches On a port-by-port basis, where everything “downstream” from a given port is known to support jumbo frames Use Virtual LANs, where jumbo frames and non-jumbo frame devices are segregated to different VLANs

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 37 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Frames

Standard

VLAN frame

Jumbo frame

Pause frame

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4-byte FCS field Cyclic Redundancy Check (CRC) value Computed on all fields except the Preamble, SFD, FCS, and Extension fields

The Extension field is added only if the frame size is less than that required by CSMA/CD for the collision protocol.

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What is the name of the Ethernet protocol developed for a shared access channel? What Ethernet speeds are available? What is the name of the standardized Ethernet IEEE group? Name some IEEE Ethernet identifiers for each Ethernet speed How many layers comprise the OSI model? Name the layers In what layers does the Ethernet system lie? What makes up the physical layer?

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 39 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Knowledge Check What makes up the Ethernet frame? What makes up the Ethernet address? What is the minimum and maximum data size in a normal-sized frame? Name a function of the Length/Type field What are the two modes of MAC operation? What are the main differences between the two? What are the three addressing methods? Name a method of flow control and how it is identified What is the function of auto-negotiation? What is a VLAN and how is it identified? What is a jumbo frame? What is its logical limit and why?

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 40 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Answers

What is the name of the Ethernet protocol developed for a shared access channel? Carrier Sense Multiple Access with Collision Detect (CSMA/CD) What Ethernet speeds are available? 10 Mbps 100 Mbps 1 Gbps 10 Gbps What is the name of the standardized Ethernet IEEE group? IEEE 802.3

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 41 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Answers Name some IEEE Ethernet identifiers for each Ethernet speed 10BASE-T 100BASE-X 1000BASE-T 10GBASE-X How many layers comprise the OSI model? Seven Name the layers Physical, data link, network, transport, session, presentation, and application In what layers does the Ethernet system lie? Physical and data link layers

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 42 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Answers

What makes up the physical layer? Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD) What makes up the Ethernet frame? Preamble Source/destination address Length/type Data FCS What makes up the Ethernet address? 24-bit Organizationally Unique Identifier (OUI) and a 24-bit vendor-specific address

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 43 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Answers

What is the minimum and maximum data size in a normal-sized frame? 46 to 1500 bytes Name a function of the Length/Type field Length information (the number of valid bytes in the Data field) Identifies what type of high-level network protocol is being carried in the Data field What are the two modes of MAC operation? Half duplex and full duplex What are the two modes of MAC operation? Half duplex and full duplex

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What are the main differences between the two? Half duplex uses a shared channel between systems Full duplex has independent TX and RX channels between point-to-point media segments What are the three addressing methods? Unicast Multicast Broadcast Name a method of flow control and how it is identified PAUSE, MAC control 0x8808, OPCODE 0x0001

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 45 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Answers What is the function of auto-negotiation? Depending on the system, auto-negotiation can automatically configure the link for half or full duplex mode and configure the speed What is a VLAN and how is it identified? Virtual Local Area Network on switching ports 4-byte VLAN tag header What is a jumbo frame? A frame whose data feed is larger than 1500 bytes What is its logical limit and why? 12000 bytes 32-bit CRC becomes ineffective after this point

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 46 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Summary Basics

An Ethernet system consists of the Ethernet frame, Media Access Control, signaling components, and physical medium There are various Ethernet standards and Ethernet type identifiers covering different speeds, physical medium, and limits The OSI model provides a conceptual framework for communication among computers using seven layers of abstractions The Ethernet system lies at the physical and data layers

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 47 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Objectives Hardware Basics

Describe the functionality and use for several common protocols List the available Ethernet interfaces Distinguish among various types of Ethernet hardware

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 48 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Protocols

The formal specifications and conventions that govern and control communication and data exchanges among the communication parties Some commonly used protocols Internet Protocol (IP) Operates at the network layer User Datagram Protocol (UDP) Operates at the transport layer Transmission Control Protocol (TCP) Operates at the transport layer Address Resolution Protocol (ARP) Operates at the network layer Internet Control Message Protocol (ICMP) Operates at the transport layer

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There needs to be a method for determining the Ethernet addresses of other IP-based stations on the network. For several high-level protocols, including TCP/IP, this is done using yet another high-level protocol called the Address Resolution Protocol (ARP). As the ARP request is sent in a broadcast frame, every Ethernet interface on the network reads it in and sends the ARP request to the networking software running on the station. Internet Protocol (IP) is used for host-to-host datagram service in a system of interconnected networks called the catenet. The network connecting devices are called gateways. These gateways communicate among themselves for control purposes via a Gateway-to-Gateway Protocol (GGP). Occasionally, a gateway or destination host will communicate with a source host—for example, to report an error in datagram processing. For such purposes, the Internet Control Message Protocol (ICMP) is used. ICMP uses the basic support of IP as if it were a higher level protocol; however, ICMP is actually an integral part of IP and must be implemented by every IP module. The User Datagram Protocol (UDP) is a connectionless transport layer protocol (Layer 4) that belongs to the Internet Protocol family. UDP is basically an interface between IP and upper-layer processes. UDP protocol ports distinguish multiple applications running on a single device from one another. Unlike TCP, UDP adds no reliability, flow control, or error recovery functions to IP. Because of UDP simplicity, UDP headers contain fewer bytes and consume less network overhead than TCP.

SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 49 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Network Protocols

The data part of the Ethernet frame is actually the high-level network protocol which establishes communications among applications running across the network The most widely used network protocol is Transmission Control Protocol/Internet Protocol (TCP/IP) These high-level protocols are independent of the Ethernet system The Ethernet system is simply the carrier of the protocols and does not care about what the data represents higher up in the OSI model Thus, an Ethernet system can be comprised of many sets of computers running an array of protocols without worry

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A good analogy would be the postal system. You place a private message into an envelope with the address of the recipient and the sender. The post office then delivers the envelope The Data field of the Ethernet frame actually contains both data and address information for the higher- level network protocol

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Fast Ethernet Symbol stream

Physical Layer Encapsulation Ethernet Frame

Data Link Layer Encapsulation IP Packet

Network Layer Encapsulation TCP Segment

Transport Layer Encapsulation

Physical Layer Header Ethernet Header IP Header TCP Header Application Data Ethernet Trailer Physical Layer Trailer

Start-of-Stream Preamble/SFD,Version, TOS, Length,Ports, Byte Addresses Pointers, etc Window, Flags,Application-Specific etc 32-Bit FCS End-of-Stream Delimiter Addresses, Information Delimiter Type Field

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0 4 8 16 19 31 Vers HLen Service Type Total Length

Identification Flags Fragment Offset

Time to Live Protocol Header Checksum

Source IP Address

Destination IP Address

Options (+padding)

Data (Variable Length)

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IP is a datagram-oriented protocol, treating each packet independently, which means that each packet must contain complete addressing information. Also, IP makes no attempt to determine if packets reach their destination or to take corrective action if they do not. Nor does IP provide checksum of the contents of a packet, only the IP header. Version (Bits 0–3): The version number of the IP protocol. Used to verify that the sender, receiver, and any gateways in between are free on the format of the datagram. HLen (Bits 4–7): Datagram header length measured in 32-bit words. All fields except IP options and padding have fixed lengths. A common IP datagram header without options or padding fields has a typical header length of 5 words. Service Type (Bits 8–15): Indicates datagram precedence (bits 8 to 10), type of transport (low delay [bit 11], high throughput [bit 12], and high reliability [bit 13]—used by routing algorithm). Bits 14 and 15 are unused. Total Length (Bits 16–31): The length of IP datagram measured in bytes; includes header and data. Header Checksum: Formed by treating the header as a sequence of 16-bit integers (in network byte order), adding them together by using ones complement, and then taking the ones complement of the result. During computation, the Checksum field is assumed to be zero. Flags: The low-order 2 bits of the 3-bit field control fragmentation. Used for debugging and testing Internet software. The first bit specifies whether datagram is fragmented (1 = do not fragment). Fragment Offset: Specifies the offset in the original datagram, measured in units of 8 bytes, starting at offset zero. Time to Live: Specifies how long in seconds a datagram is allowed to remain on an internet. Whenever a TTL field reaches zero, the gateway discards the datagram and sends an error message back to the source. Protocol: Specifies which protocol was used (TCP/IP, ICMP, or FTP, for example). Options: Not a required field. It is used for network testing. Each option consists of a byte of option code, a byte of length, and data bytes.

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 54 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Ethernet Interfaces

To send Ethernet signals from one station to another, stations are connected together with a standardized media-based system Some are hardware specific Media cables and connectors Others, such as Ethernet interfaces, are common to all media systems As the Ethernet system has evolved, it has developed a set of medium-independent attachments This results in the Ethernet interface controller not needing to know anything about the media system and allows the Ethernet interface to be connected to any type of media system This means that multiple media systems can be developed without requiring any changes in the Ethernet controller interface

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The first medium-independent attachment developed was the Attachment Unit Interface (AUI), supporting 10 Mbps only The Medium Independent Interface (MII), supporting both 10-Mbps and 100-Mbps Ethernet systems, followed The Gigabit Medium Independent Interface (GMII) was developed for 1000-Mbps systems For 10-Gigabit Ethernet systems, 10-Gigabit Medium Independent Interfaces (XGMII) and 10-Gigabit Attachment Unit interfaces (XAUI) have been developed and are being used

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 56 Located in Austria & Brazil [email protected] Date Oct 23, 2009 10/100/1000 Ethernet Interfaces

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 57 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Attachment Unit Interface (AUI)

Each direction of data transfer is serviced with two (making a total of four) balanced circuits: data and control Data and control are independently self-clocked, eliminating the need for separate timing circuits The AUI interface is used to interconnect the Physical Layer Signalling (PLS) to the transceiver Provides the Date Terminal Equipment (DTE) with media independence so that identical PLS, MAC, and MAC clients can be used with any of these media Transmission lengths of up to 50 m

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Designed to make the differences among the various media absolutely transparent to the MAC sublayer Maximizes media independence by cleanly separating the data link and physical layers of the ISO Supports speeds of 10 and 100 Mbps Functionality and timing are identical; the only change is clock speed Provides independent, 4-bit-wide transmit and receive datapaths Provides a simple management interface Capable of driving a limited length of shielded cable Provides for full duplex operation

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MII is an optional set of interfaces that provides a way to link the Ethernet medium access control functions in the network device with the Physical Layer Device (PHY) that sends signals onto the network medium. An MII can optionally support both 10-Mbps and 100-Mbps operation, allowing suitably equipped network devices to connect to both 10BASE-T and 100BASE-T media segments. MII is designed to make the signal differences among the various media segments transparent to the Ethernet chips in the network device. MII converts the line signals received from the various media segments by the transceiver (PHY) into digital format signals that are then provided to the Ethernet chips in the device. The optional MII electronics, and associated 40-pin female connector and MII cable, make it possible to connect a network device to any of several media types—providing maximum flexibility.

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GMII is the interface between the MAC layer and the physical layer Higher Layers Allows any physical layer to be used with the MAC layer and is an extension of the MII used in Logical Link Control Fast Ethernet MAC Control Supports 1000-Mbps (1 Gbps) operation Media Access Control Provides independent, eight-bit-wide transmit and receive datapaths Provides a simple management interface Provides for full duplex operation Designed for a transmission distance of 7 cm

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 60 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Ten-Bit Interface (TBI)

The raw interface to the SERDES Ten-Bit Interface The Ten-Bit Interface (TBI) is defined to provide compatibility 8B/10B among devices designed by Encoder different manufacturers PCS PMA Connects the PCS and PMD 8B/10B RX Elastic sublayers Decoder Buffer Intended for use as a chip-to-chip interface Line Coding, Auto-Neg, Sync, 8B/10BSerdes, Clk-rec, CML/PECL

P P GMII PCS TBI M M A D 10 8

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 61 Located in Austria & Brazil [email protected] Date Oct 23, 2009 10G Ethernet Interfaces

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 62 Located in Austria & Brazil [email protected] Date Oct 23, 2009 XGMII

XGMII provides a simple, inexpensive, and easy-to-implement interconnection between the MAC sublayer and the PHY, supporting 10-Gbps operation 32-bit transmit and receive datapaths The 10-Gigabit Attachment Unit Interface (XAUI) can optionally be used to extend the operational distance of the XGMII with reduced pin count XGMII is designed for a transmission distance of 7 cm

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 63 Located in Austria & Brazil [email protected] Date Oct 23, 2009 XGXS and XAUI

The purpose of the XGMII extender is to extend the operational distance of the XGMII and to reduce the number of interface signals It is comprised of XGMII Extender Sublayer (XGXS) at the RS end XGXS at the PHY end eXtendable Attachment Unit Interface (XAUI) between them Applications include extending the separation between the MAC and PHY components in a 10G system distributed across a circuit board or backplane

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 64 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Ethernet Hardware

Two main types of Ethernet hardware used in an Ethernet system Signaling components which are used to send and receive signals over the physica l medium Transceivers or repeater hubs Ethernet interfaces: MII, GMII, XGMII, AUI, or XAUI Media components which make up the physical medium and carry the Ethernet signals Fiber optic or twisted pair cables or connectors The types of media and signaling components can vary depending on the speed of the system and the types of cable used

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 65 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Internet System

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 66 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Ethernet Repeaters

Extends the range of an Ethernet system by compensating for deterioration of the electrical signal as it propagates along the segments by Enforcing collisions on all segments Restoring the amplitude of the signal Restoring the symmetry of the signal Retiming the signal Extending the fragment Repeaters act within a single collision domain; hence, they are half duplex No MAC, IP, or specialized addressing is used Layer 1 devices

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 67 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Ethernet Switching Hubs

Allow you to build large Ethernet systems that extend beyond the limits of a single collision domain Link Ethernet segments operating at different speed Receive and store a frame on a port operating at one speed and then send the frame on a port at another speed Control the flow of traffic through a system Localize network traffic without sending to all network segments Link LANs together by interchanging frames among them Advantages of Ethernet switches Improved reliability by separating domains Increased bandwidth Transparency to the system Each port on a switch contains a MAC Layer 2 devices

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 68 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Routers

Specialized devices that interconnect the network by switching communications from one line to another at cross points The router then uses a routing algorithm to send the packet across the Internet to the destination computer Used to connect dissimilar networks Handles different protocols Addressing occurs using source and destination IP addresses Layer 3 devices

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 69 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Ethernet Hardware Examples Simple/dumb hub connects multiple segments of the same speed acts as a repeater

Switching hub linking different speed segments creates separate Ethernet LANs

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 70 Located in Austria & Brazil [email protected] Date Oct 23, 2009 TCP Packet Format

0 4 10 16 19 31 Source port Destination port

Sequence number

Acknowledgement number

Data offset Reserved Flags Window

Checksum Urgent Pointer

Options (+padding)

Data (Variable Length)

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Data offset: The number of 32-bit words in the TCP header. This indicates where the data begins. The TCP header (even one including options) is an integral number of 32 bits long. Sequence number: Identifies the position in the sender’s byte stream in the segment. Acknowledgement number: Identifies the number of the byte that the source expects to receive next. Flags: 6-bit field URG: Indicates that the Urgent pointer field is valid. ACK: Indicates that the Acknowledgment field is valid. PSH: Indicates that the segment requests the push of data RST: Indicates that the connection needs to be reset. SYN: Indicates to synchronize the sequence number. FIN: Indicates that the sender has reached the end of its byte stream. Window: The number of data octets, beginning with the one indicated in the Acknowledgment field, which the sender of this segment is willing to accept. Checksum: 16-bit ones complement of the ones complement sum of all 16-bit words in the header and text. If a segment contains an odd number of header and text octets to be checksummed, the last octet is padded on the right with zeros to form a 16-bit word for checksum purposes. The pad is not transmitted as part of the segment. While computing the checksum, the Checksum field itself is replaced with zeros. The checksum also covers a 96-bit pseudo-header conceptually prefixed to the TCP header. This pseudo-header contains the source address, destination address, protocol, and TCP length.

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0 16 31 Source port Destination port

Length Checksum

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Provides connectionless datagram transmission. User Datagram Protocol (UDP) is utilized to send data that does not necessarily need to be very reliable. The UDP packet is encapsulated in an IP packet, which in turn is encapsulated in a Point-to-Point Packet (PPP) packet. Both UDP and IP have checksum octets and the PPP packet has its FCS octets; however this can only guarantee that the data and the destination are correct. There is the possibility that this data does not belong to an expected message sequence but is rather part of another message that just happened to have the same destination. This issue is addressed by the TCP protocol. UDP is a simple-to-implement protocol because it does not require tracking of every packet sent or received and it does not need to initiate or end a transmission. Because of this, it is mainly designed for communications where you either do not care what the response will be or you already know the response. UDP messages are generally faster than TCP, provided that the communication link functions properly. UDP is widely utilized to send Domain Name Search (DNS) requests, exchange chat messages, or access telephone numbers via the Internet. To calculate the UDP checksum, a pseudo-header is added to the UDP header. This includes IP Source Address (4 bytes), IP Destination Address (4 bytes), Protocol (2 bytes), and UDP Length (2 bytes). The checksum is calculated over all the octets of the pseudo-header, UDP header, and data. If the data contains an odd number of octets, a pad zero octet is added to the end of the data. The pseudo-header and the pad are not transmitted with the packet.

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The process for finding an address of a computer in a network uses this format

0 8 16 31 Hardware Type Protocol Type

HLEN PLEN Operation

Sender HA (0–3)

Sender HA (4–5) Sender IP (0-1)

Sender IP (2-3) Target HA (0-1)

Target HA (2-5)

Target IP (0-3)

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Address Resolution Protocol (ARP) is a protocol used by IP, specifically IPv4, to map IP network addresses to the hardware addresses used by a data link protocol. The protocol operates below the network layer as a part of the interface between the OSI network and OSI link layer. It is used when IPv4 is used over Ethernet. Address resolution refers to the process of finding an address of a computer in a network. The address is resolved via a protocol in which a piece of information is sent by a client process executing on the local computer to a server process executing on a remote computer. The information received by the server allows the server to uniquely identify the network system for which the address was required and therefore to provide the required address. The address resolution procedure is completed when the client receives a response from the server containing the required address. An Ethernet network uses two hardware addresses which identify the source and destination of each frame sent by the Ethernet. The destination address (all ones) can also identify a broadcast packet (to be sent to all connected computers). Each interface card is allocated a globally unique 6-byte link address when the factory manufactures the card (stored in a PROM). This is the normal link source address used by an interface. A computer sends all packets which it creates with its own hardware source link address and receives all packets which match the same hardware address in the Destination field or one (or more) pre-selected broadcast/multicast addresses. The Ethernet address is a link layer address and is dependent on the interface card which is used. IP operates at the network layer and is not concerned with the link addresses of individual nodes which are to be used. ARP is therefore used to translate between the two types of address. The ARP client and server processes operate on all computers using IP over Ethernet. The processes are normally implemented as part of the software driver that drives the network interface card.

SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 73 Located in Austria & Brazil [email protected] Date Oct 23, 2009 ARP Process

The address is resolved using a protocol in which a piece of information is sent by a client process executing on the local computer to a server process executing on a remote computer The Ethernet protocol type is 0x0806 Four types of messages are used ARP request ARP reply RARP request RARP reply

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The ARP request message (“who is X.X.X.X tell Y.Y.Y.Y”—where X.X.X.X and Y.Y.Y.Y are IP addresses) is sent using the Ethernet broadcast address and an Ethernet protocol type of value 0x806. Because it is broadcast, it is received by all systems in the same collision domain, ensuring that, if the target of the query is connected to the network, it will receive a copy of the query. Only this system responds. The other systems discard the packet silently. The target system forms an ARP response (“X.X.X.X is hh:hh:hh:hh:hh:hh”—where hh:hh:hh:hh:hh:hh is the Ethernet source address of the computer with the IP address of X.X.X.X). This packet is unicast to the address of the computer sending the query (in this case Y.Y.Y.Y). Because the original request also included the hardware address of the requesting computer, this is already known, and does not require another ARP message to determine this.

SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 74 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Knowledge Check

Name some Ethernet hardware What is the purpose of a repeater? What is the purpose of a switching hub? Name the Ethernet Interfaces for 10-Mbps, 100-Mbps, 1-Gbps, and 10-Gbps Ethernet systems How wide are the data signals for MII, GMII, and XGMII? What signalling is used for AUI and XAUI? What is TBI?

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 75 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Answers Name some Ethernet hardware Repeaters, switching hubs, interfaces, cables, or connectors What is the purpose of a repeater? Enforces collisions on all segments, restoring the amplitude, symmetry, and retiming of a signal Fragment extension What is the purpose of a switching hub? Enables large Ethernet systems, linking LANs together. Links multispeed Ethernet systems and controls the flow of traffic Improved reliability by separating domains Increased bandwidth Transparency to the system

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 76 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Answers What is the purpose of a switching hub? Enables large Ethernet systems, linking LANs together. Links multispeed Ethernet systems and controls the flow of traffic Improved reliability by separating domains Increased bandwidth Transparency to the system Name the Ethernet Interfaces for 10-Mbps, 100-Mbps, 1-Gbps, and 10-Gbps Ethernet systems 10 Mbps: AUI and MII 100 Mbps: MII 1 Gbps: GMII 10 Gbps: XGMII and XAUI

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 77 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Answers

How wide are the data signals for MII, GMII, and XGMII? MII: 4 bits GMII: 8 bits XGMII: 32 bits

What signalling is used for AUI and XAUI? Differential pairs: reduces the pin count

What is TBI? A ten-bit interface, using 8B/10B encoding

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 78 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Summary Hardware Basics The Internet protocols are the most popular open-system protocol suite IP is a network layer protocol that contains addressing information and some control information TCP is a transport layer protocol that provides stream data transfer UDP is a connectionless transport layer protocol There are various interfaces which provide flexibility and varying transparency to the external hardware MII supports 10-Mbps and 100-Mbps data transfer GMII supports 1-Gbps operation XGMII provides a simple, inexpensive, and easy-to-implement interconnection supporting 10-Gbps operation

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 79 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Objectives Physical Layer

Describe the auto-negotiation mechanism State the need for signal encoding and decoding Define ordered sets List various interfaces and describe their functionality Describe how information is coded

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 80 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Auto-Negotiation Auto-negotiation is a mechanism that takes control of the cable when a connection is established to a network device Detects the various modes that exist in the device on the other end of the wire, the link partner, and advertises its own abilities to automatically configure the highest performance mode of interoperation Introduced by National Semiconductor to the IEEE 802.3u 100BASE-T working group in the spring of 1994 Simple, low-cost, flexible, interoperability with the installed base and adaptable to future technologies Two basic cases that auto-negotiation accounts for Auto-negotiation exists at both ends of a twisted pair link Auto-negotiation exists at only one end of a twisted pair link

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Auto-negotiation was introduced by National Semiconductor to the IEEE 802.3u 100BASE-T working group in the spring of 1994 as a result of the need for a mechanism to accommodate multi-speed network devices. Auto-negotiation takes control of the cable when a connection is established to a network device. Auto-negotiation detects the various modes that exist in the device on the other end of the wire, the link partner, and advertises its own abilities to automatically configure the highest-performance mode of interoperation. As a standard technology, this allows simple, automatic connection of devices and supports a variety of modes from a variety of manufacturers. Auto-negotiation acts like a rotary switch that automatically switches to the correct technology, such as 10BASE-T, 100BASE-TX, 100BASE-T4, or a corresponding full duplex mode. After the highest performance common mode is determined, auto-negotiation passes control of the cable to the appropriate technology and becomes transparent until the connection is broken. Auto-negotiation leverages the proven link function of 10BASE-T to provide robust operation over Category 3, 4, or 5 Unshielded Twisted Pair (UTP) . Auto-negotiation is most useful if it exists at both ends of the link because both ends speak the same “language” at start up—allowing a rich set of information to be transferred.

SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 81 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Auto-Negotiation Benefits

The primary benefit is the automatic connection of the highest performance technology available without user intervention If auto-negotiation exists at only one end of a twisted pair link, it determines that the link partner does not support the mechanism Instead of exchanging configuration information, auto-negotiation examines the signal it is receiving The parallel detection function gives the ability to be compatible with any device that does not support auto-negotiation; supports 10BASE-T, 100BASE-TX, or 100BASE-T4 Xilinx cores support 1000BASE-X and SGMII interface auto-negotiation Connection to any other technology via parallel detection other than those listed above is not supported and entertained If auto-negotiation exists on both ends of a twisted pair link, then both ends advertise their abilities to the other and connect at the highest-performance common technology that is shared

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The primary benefit of auto-negotiation is the automatic connection of the highest-performance technology available without any intervention from a user, manager, or management software. If auto-negotiation exists at only one end of a twisted pair link, it determines that the link partner does not support auto- negotiation. Instead of exchanging configuration information, it examines the signal it is receiving. If auto-negotiation determines that the signal matches a technology that the device supports, it automatically connects that technology. This parallel detection function allows auto-negotiation to be compatible with any device that does not support auto- negotiation. Support is available for 10BASE-T, 100BASE-TX, or 100BASE-T4. Connection to any technology via parallel detection is not supported by auto-negotiation. If no common technology exists, auto-negotiation will not make a connection to ensure the preservation of network integrity and minimization of network downtime. In particular, hubs are a primary beneficiary of this feature. For example, if a user connects a 100BASE-T4 device into a 10BASE-T/100BASE-TX switch, the result could be catastrophic for all the users connected through that switch. However, if the hub has auto-negotiation, it would refuse the connection and allow the rest of the network to proceed as usual. In fact, with auto-negotiation in the hub, network users are protected from any connection that the hub cannot recognize or accept. If auto-negotiation exists on both ends of a twisted pair link, then both ends advertise their abilities to the other. Auto- negotiation incorporates a robust handshake that ensures data integrity. The devices compare their abilities and connect at the highest-performance common technology that is shared.

SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 82 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Optional Features Management interface The serial management interface of the Medium Independent Interface (MII) register set provides a mechanism for additional control of auto-negotiation Also provides a means for gathering network status information Next page function The next page function, if supported, provides an additional data exchange capability which allows extensions to the standard and proprietary extensions to exist without affecting interoperability Remote fault indication The basic transport mechanism does not require the detection and advertisement of any particular fault Remote fault indication allows a device that is able to detect faults (wrong cable type or wiring fault, for example) to advertise the presence of the fault to the link partner

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In addition to the basic connection mechanism, auto-negotiation also provides additional optional features. Management interface: The serial management interface of the MII register set provides a mechanism for additional control of auto-negotiation. It also provides a means for gathering network status information. Next page function: After exchanging the base page, which contains the information to make a connection automatically, if both ends of the link indicate support for the next page function, additional data can be exchanged. This allows extensions to the standard and proprietary extensions to exist without affecting interoperability. Remote fault indication: The basic transport mechanism for simple fault information is built into auto-negotiation, but the detection and advertisement of any particular fault is not required. Remote fault indication allows a device that is able to detect faults (wrong cable type or wiring fault, for example) to advertise the presence of the fault to the link partner. Remote fault indication can be used in conjunction with the next page function to transfer more information about the type of fault that occurred.

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A Fast Link Pulse (FLP) burst, composed of 17 to 33 Clock Data link pulses that are identical to the link pulses used in 0 1 15 10BASE-T, is sent to determine whether a link has a

valid connection 100 ns pulses, 62.5 µs nominal spacing FLP bursts occur at the same interval as Normal Link Pulses Clock and data interleaved A pulse may be present at data place if data is 1 (NLPs), 16 ± 8 ms An FLP burst has a nominal duration of 2 ms ± An FLP burst interleaves clock pulses with data pulses to encode a 16-bit word The absence of a pulse within a time window following a clock pulse encodes a logic zero. A pulse within the time window ± following a clock pulse encodes a logic one

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The basic mechanism that auto-negotiation uses to advertise a the abilities of a device is a series of link pulses which encode a 16-bit word, known as a Fast Link Pulse (FLP) burst. An FLP burst is composed of 17 to 33 link pulses that are identical to the link pulses used in 10BASE-T to determine whether a link has a valid connection (sometimes referred to as Normal Link Pulses, or NLPs.) FLP bursts occur at the same interval as NLPs, 16.8 ms. An FLP burst has a nominal duration of 2 ms. An FLP burst interleaves clock pulses with data pulses to encode a 16-bit word. The absence of a pulse within a time window following a clock pulse encodes a logic zero and a pulse within the time window following a clock pulse encodes a logic one. The key to the flexibility and expandability auto-negotiation is the encoding of the 16-bit word. The 16-bit word is referred to as the Link Code Word (LCW). The Selector field, S[4:0], allows 32 different definitions of the Technology Ability field to coexist. The intention is to allow standard technologies to leverage the basic auto-negotiation mechanism. Currently, S[4:0]=< 00001 > is assigned to IEEE 802.3 and S[4:0]=< 00010 > is assigned to IEEE 802.9. Two more codes are reserved for expansion of auto-negotiation. The remaining codes are reserved to be assigned to standard technologies that want to leverage this mechanism, yet fall outside the scope of the currently defined Selector field values. The Technology Ability field, A[7:0], is defined relative to the Selector field value of the Link Code Word. For IEEE 802.3, there are bits defined to advertise.

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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0 0 0 1 R R

Message Type 10BASE-T Half Duplex Next Page Present 10BASE-TX Full Duplex Acknowledgement 100 BASE-T Half Duplex Remote Fault Indicator 100 BASE-TX Full Duplex Flow Control Support 100 BASE-T4 Half Duplex

The local device sends a Link Code Word (LCW) with the ACK bit not set After three consecutive, matching LCWs are received from the link partner, the local device sets the ACK bit in the transmitted LCW to indicate that it has correctly received the link partner’s LCW The local device continues transmitting its LCW Upon receiving three consecutive, matching LCWs from the link partner with the ACK bit set, the local device knows that the link partner has also received the LCW correctly The local device transmits the LCW with the ACK bit set 6–8 additional times to ensure that a complete handshake has occurred Each device compares its abilities and the highest-performance common technology (as determined by priority resolution) is connected to the medium

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To make a connection decision, auto-negotiation must ensure that the link partner receives the LCW correctly and that the link partner’s LCW is received correctly. Auto-negotiation uses the arbitration function to accomplish this task. The local device begins by transmitting its LCW, LCW[LD], with the ACK bit not set. After three consecutive, matching LCWs are received from the link partner, LCW[LP] (ignoring ACK), the local device sets the ACK bit in the transmitted LCW to indicate that it has received the link partner’s LCW correctly. The local device continues transmitting its LCW. Upon receiving three consecutive, matching LCWs from the link partner with the ACK bit set, the local device knows that the link partner has also received the LCW correctly. The local device transmits the LCW with the ACK bit set 6–8 additional times to ensure that a complete handshake has occurred. Now, both the local device and the link partner have exchanged their base LCWs. Each device compares their abilities and the highest-performance common technology (as determined by priority resolution) is connected to the medium.

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Auto-negotiation starts automatically Power-up/reset Upon loss of synchronization Whenever the link partner initiates auto-negotiation Whenever an auto-negotiation restart is requested

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IEEE802.3 Clause 37 describes the 1000BASE-X auto-negotiation function that allows a device to advertise the modes of operation that it supports to a device at the remote end of a link segment (the link partner) and to detect corresponding operational modes that the link partner advertises. Auto-negotiation starts automatically when any of the following conditions are met. Power-up/reset Loss of synchronization Whenever the link partner initiates auto-negotiation Whenever an auto-negotiation restart is requested During auto-negotiation, the contents of the auto-negotiation Advertisement register are transferred to the link partner. This register is writable through the MDIO—therefore enabling software control of the system’s advertised abilities. Information provided in this register includes: Fault condition signaling Duplex mode Flow control capabilities for the attached MAC The advertised abilities of the link partner are simultaneously transferred into the auto-negotiation Link Partner Ability Base register. This register contains the same information as in the auto-negotiation Advertisement register. Under normal conditions, this completes the auto-negotiation information exchange. Completing the cycle is now the responsibility of system management (for example, software running on an embedded PowerPC™ or MicroBlaze processor). The results of auto- negotiation should be read from the auto-negotiation link partner’s Ability base register.

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The PHY performs auto-negotiation with its link partner using the relevant auto-negotiation standard for the chosen medium. This resolves the operational speed and duplex mode with the link partner The PHY then passes the results of the auto-negotiation process with the link partner to the core (in SGMII mode)

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The SGMII-capable PHY has two distinctive sides to auto-negotiation. The PHY performs auto-negotiation with its link partner using the relevant auto-negotiation standard for the chosen medium (BASE-T auto-negotiation is illustrated in the above diagram, using a twisted copper pair as its medium). This resolves the operational speed and duplex mode with the link partner. The PHY then passes the results of the auto-negotiation process with the link partner to the Ethernet 1000BASE-X PCS/PMA or SGMII core (in SGMII mode) by leveraging the 1000BASE-X auto-negotiation specification. This transfers the results of the link partner auto-negotiation across the SGMII and is the only auto-negotiation observed by the core. This SGMII auto-negotiation function leverages the 1000BASE-X PCS/PMA auto- negotiation function but contains two differences: The duration of the link timer of the SGMII auto-negotiation is shrunk from 10 ms to 1.6 ms so that the entire auto-negotiation cycle is much faster. The information exchanged is different and now contains speed resolution in addition to duplex mode.

SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 87 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Layers 1 and 2: Ethernet Hardware

Medium-dependent interface Isolation Magnetics, RJ45, Twisted Pair PHY: separate chip MDI Medium-independent interface Ethernet media access controller

PHY

MII

EMAC

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Adds preamble and Start of Frame Delimiter (SFD) to header Preamble: 10101010 – 7 bytes SFD: 10101011 – 1 byte Performs signal encoding Performs Carrier Sense Multiple Access with Collision Detect (CSMA/CD) Performs auto-negotiation Can be managed by the EMAC via the MDIO port

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NOTES

SFD is D5h. Note that the pattern for preamble and SFD are shown bit reversed because this is how the information is sent.

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The switched version of 10-Mbps, 100-Mbps, or 1000-Mbps Ethernet can al l operate on the same cable as their shared-media versions because their wire speed is the same How can different speed communication take place on the same wire speed grade? Number of transmit pairs Modes: half duplex or full duplex Block encoding: 4B/5B or 8B/10B Line encoding: NRZ, RZ, or NRZI

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The number of transmit pairs are available in standards UTP Cat. 3, 4, 5, and so on.

SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 90 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Technology and Encoding Technology Maximum Segment Length Encoding Topology Bit Rate Method Media (bps) 10BASE5 500 m Manchester Bus 50-ohm coax 10 M 10BASE2 185 m Manchester Bus 50-ohm coax 10 M 10BASE-T 100 m Manchester Star 2 pair UTP cat. 3, 4, 5 10 M 100BASE-FL 2000 m Manchester Star multi-mode fiber* 10 M 100BASE-T2 100 m PAM 5x5 Star 2 pair UTP cat. 3, 4, 5 100 M 100BASE-T4 100 m 8B/6T Star 4 pair UTP cat. 3, 4 ,5 100 M 100BASE-TX 100 m 4B/5B with MLT-3 Star 2 pair UTP cat. 5 100 M 100BASE-FX 412/2000 m 4B/5B with NRZI Star multi-mode fiber* 100 M 1000BASE-T 100 m PAM 5x5 Star 4 pair UTP cat. 5 1000 M 1000BASE-SX 275 m 8B/10B Star multi-mode fiber† 1000 M 1000BASE-LX 316/550 m 8B/10B Star multi-mode fiber‡ 1000 M 1000BASE-CX 25 m 8B/10B Star twinax 1000 M

* Fiber is duplex 62.5/125 µm multi-mode fiber † Maximum segment length is 316/550 m with 50/125 µm multi-mode fiber ‡ Maximum segment length is 316/550 m with 50/125 µm multi-mode fiber or 316/5000 m with 10/125 µm single-mode fiber

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In 100BASE-T4 technology, 8B/6T coding replaces 8-bit data values with six ternary codes, which can have the values –, +, or 0. In 100BASE-T2 technology, two five-level Pulse Amplitude Modulation (PAM) signals are sent over the UTP pairs, with a signaling rate of 12.5 MHz. Each cycle of the signal provides two PAM5x5 level changes, so there are 25 million level changes per UTP pair. Each pair of PAM signals (called A and B) encode a different 4-bit pattern (along with other, special patterns for Idle mode) using combinations of these levels: +2, +1, 0, –1, –2. Therefore, 25 million PAM5x5 pairs × 4 bits per pair = 100 Mbps.

SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 91 Located in Austria & Brazil [email protected] Date Oct 23, 2009 PHY Block Diagram Line Encoding Example

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 92 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Broadcom BCM5461 PHY Block Encoding Example

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10/100/1000BASE-T GMII, RGMII, MII options Support for jumbo packets up to 9 kB JTAG boundary scan support 0.13 micron CMOS Half duplex / full duplex Automatic detection and correction of wiring pair swaps and polarity

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How wide is the TX and RX data on the GMII interface What are the three main available PHY interfaces?

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 94 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Answers

How wide is the TX and RX data on the GMII interface? 8 bits

What are the three main available PHY interfaces? GMII PCS and TBI PCS and PMA

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 95 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Summary

Auto-negotiation is a mechanism that takes control of the cable when a connection is established to a network device It allows the automatic connection of the highest performance technology available without user intervention 8B/10B encoding and decoding provides a sufficient number of transitions which enable clock recovery Various interfaces are possible to connect two Ethernet MAC devices The type of interface to be selected depends on the data transmission rate, distance, and the number of pins available The PHY interface uses differential pair for serial reception from PMD to PMA

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 96 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Objectives Local Link Interface

Contrast the PCS and PMA sublayers in the physical layer of the OSI model Describe the transmit and receiver interfaces of GMAC Explain TX and RX signal functionality and their waveforms under various conditions Identify flow control and the associated control frames List the types of transactions for which the management interface is used

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GMII Virtex™-E (-7) FPGA PCS and TBI PCS and PMA Virtex-II (-4) FPGA Virtex-II FPGA Virtex-II Pro FPGA Virtex-II Pro (-5) FPGA Virtex-II Pro FPGA Virtex-4 FX FPGA Spartan™-IIE (-7) FPGA Spartan-3 FPGA Spartan-3 (-4) FPGA Virtex-4 FPGA Virtex-4 (-10) FPGA

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GMII To PMD GMII block Interface Sublayer Optional TX elastic buffer Opt. TX PCS TX Elastic Engine PCS TX engine Buffer Optional auto-negotiation Opt. Auto- PCS receive engine and synchronization Negotiation RocketIO™ MGT GMII Block

PCS RX RocketIO MGT Optional PCS management Engine & Sync

MDIO Optional PCS Interface Management

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GMII block: Interface between the MAC and the physical layer via independent 8-bit-wide transmit and receive paths. TX elastic buffer (optional): Transfers the GMII transmit signals from GMII_TX_CLK into the main clock domain of the core to be used by the RocketIO™ MGT logic. PCS TX engine: Encodes GMII signals from the MAC TX interface into defined ordered sets for 8B/10B encoding. Auto-negotiation (optional): Information exchange with a link partner defining such things as half or full duplex medium. PCS receive engine and synchronization: Decodes, synchronizes, and defines ordered sets from the 8B/10B decoder into GMII data and control signals. RocketIO MGT: Provides some of the PCS layer functionality, such as 8B/10B encoding/decoding and the PMA SERDES. PCS management block (Optional): The PCS managed register block is accessed through the MDIO interface as if it were an externally connected PHY. This configures the operation of the PCS sublayer, PMA sublayer, and auto- negotiation.

SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 99 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Receiver: Maximum Frame Length

The maximum legal length of a frame specified in IEEE 802.3-2002 is 1518 bytes for non-VLAN-tagged frames. VLAN-tagged frames can be extended to 1522 bytes RX_BAD_FRAME is asserted if the frame exceeds the maximum length when jumbo frame handling is disabled When jumbo frame handling is enabled, frames which are longer than the legal maximum are received in the same way as shorter frames

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 100 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Receiver: Length/Type Field

Enabled (default) Error Checks The following checks are made on all received frames. If either of these checks fails, then the frame is marked as BAD A value in the Length/Type field that is greater than or equal to decimal 46 but less than decimal 1536 is checked against the actual data length received A value in the Length/Type field that is less than decimal 46 is checked to verify that the Data field is padded to exactly 46 bytes Disabled The Length/Type error checks described are not performed. A frame containing only these errors will be marked as GOOD If padding is indicated and client-supplied FCS passing is disabled, then a length value in the Length/Type field will not be used to deassert RX_DATA_VALID Instead, RX_DATA_VALID will be unasserted before the start of the FCS field; thus, any padding will not be stripped from the frame

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The MDIO interface accessed through the MAC management interface Optional processor-independent interface with standard address, data, and control signals Used as is or a wrapper can be applied (not supplied) to interface to common bus architectures The interface is used for Configuration of the MAC core Access to optional statistics counters for use in higher layers Access through the MDIO interface to the management registers is located in the PHY attached to the MAC core

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Depending on the transaction, the interface is accessed differently Configuration transaction Statistics transaction MDIO access transaction

HOST_CLK frequency The management interface clock, HOST_CLK, is configured to derive the MDIO clock, MDC, and is restricted to being at least 10 MHz

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Configuration registers After power up or reset, the client can reconfigure the core parameters from their defaults, such as flow control support Configuration changes can be written at any time Both the receiver and transmitter logic will only respond to configuration changes during interframe gaps unless they are configurable resets which take effect immediately Configuration of the MAC core is performed through a register bank accessed through the management interface

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Statistical gathering During operation, the MAC core collects statistics on the success and failure of various operations, for processing by station management entities further up the protocol stack These statistics are accessed by the host through the optional management interface Each of the statistic registers is 64-bits wide and therefore must be read in a two-cycle transfer

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 105 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Management Interface

MDIO interface The management interface is also used to access the MDIO (MII Management) interface of the MAC core This interface is used to access the Managed Information Block (MIB) of the PHY components attached to the MAC core The MDIO interface supplies a clock, MDC, to the external devices. This clock is derived from the HOST_CLK signal using the value in the Clock Divide[4:0] configuration register The frequency of the MDIO clock is derived from the following equation

f f  HOST _ CLK MDC 1CLOCK _ DIVIDE[4 : 0]2

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MDIO interface The frequency of MDC given by this equation should not exceed 2.5 MHz in order to comply with the IEEE 802.3-2002 specification for this interface To prevent MDC from being out of specification, the Clock Divide[4:0] value powers up at 00000, and while this value is in the register, it is impossible to enable the MDIO interface Access to the MDIO interface is via the management interface For MDIO transactions, the following apply HOST_OPCODE maps to the OPCODE field of the MDIO frame HOST_ADDR maps to the two address fields of the MDIO frame: PHY_ADDR is HOST_ADDR[9:5] and REG_ADDR is HOST_ADDR[4:0]

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HOST_WR_DATA[15:0] maps into the Data field of the MDIO frame when performing a write operation The Data field of the MDIO frame maps into HOST_RD_DATA[15:0] when performing a read operation The MAC core signals to the host that it is ready for an MDIO transaction by asserting HOST_MIIM_RDY A read/write process on the MDIO is initiated by a pulse on HOST_REQ. The pulse is ignored if the interface has a transaction in progress The MAC core then unasserts the HOST_MIIM_RDY signal while the transaction across the MDIO is in progress

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Configuration Vector[63:0] If the optional management interface is omitted from the core, all relevant configuration signals are brought out of the core CONFIGURATION_VECTOR signal Note that these configuration vector signals can be changed by the user at any time With the exception of the reset and the flow control configuration signals, they will not take effect until the current frame has completed transmission or reception The clock heading denotes which clock domain that the configuration signal is registered into before use by the core Driving the signal from this clock domain is not necessary

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NOTES

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MAC FIFOs are included in the example design of a core when the core is generated using the CORE Generator™ software.

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 111 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Knowledge Check What two signals assert to confirm that a good or bad frame has been received by the MAC? How does the receiver use information in the Length/Type field? What must be enabled to receive frames greater than 1518 bytes? Can the receiver accept FCS passing and VLAN frames How are these enabled? Can the MAC be configured to send or receive pause control frames? How is a pause control frame indicated by the transmitter How does the receiver determine that the frame is a MAC control frame?

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What does the pause control frame cause the receiver to do? For what three things can the management interface be used? What are the configuration registers? What happens if the optional management interface is omitted?

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 113 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Answers What is the basic function of the Flow Control block? Controls the flow of data and frames on the transmit path by acting upon control frames passed to the receiver How does the MAC respond to an incoming frame from the client? Asserts TX_ACK after reading the first byte of data What Xilinx family is required to use the GMAC and PCS/PMA interface and why? Virtex™-II Pro and Virtex-4 FX FPGAs because they have MGTs

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 114 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Answers What are the main MAC blocks? TX/RX engine Flow control Client interface Optional PHY interface Management blocks Configuration registers, statistics registers, and MDIO What would the MAC do if it receives a TX_UNDERRUN assertion from the client during a frame transmission? The MAC sends an error code to corrupt the frame What are the two considerations when lowering the interframe gap to fewer than 12 idles and to a minimum of 4 idles? Below the IEEE 802.3 2002 minimum for full duplex Can effect the accuracy of the statistics

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 115 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Answers

To what clock is TX_STATISTICS_VECTOR synchronous? TX_CLK What signals that the data on TX_STATISTICS_VECTOR is valid? TX_STATISTICS_VALID What two signals assert to confirm that a good or bad frame has been received by the MAC? RX_GOOD_FRAME RX_BAD_FRAME How does the receiver use information in the Length/Type field? To check that the length is equal to the length of data in the Data field

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 116 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Answers What two signals assert to confirm that a good or bad frame has been received by the MAC? RX_GOOD_FRAME RX_BAD_FRAME How does the receiver use information in the Length/Type field? To check that the length is equal to the length of data in the Data field What must be enabled to receive frames greater than 1518 bytes? Jumbo frames

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 117 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Answers

How is a pause control frame indicated by the transmitter? PAUSE_REQ

How does the receiver determine that the frame is a MAC control frame? The Length/Type field OPCODE is the PAUSE OPCODE

What does the pause control frame cause the receiver to do? Inhibits frame transmission

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Describe the functionality of hard TEMAC Describe the functionality of PLB TEMAC List some of the configuration parameters State how PLB TEMAC is connected to hard TEMAC

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The Virtex™-4 FX family contains the PowerPC™ processor and TEMAC as IPs in silicon There are two hard TEMACs for each PowerPC processor FX12 and FX20 have one PowerPC processor and two hard TEMACs A wrapper (PLB TEMAC) is required for each hard TEMAC The PLB TEMAC provides connection between the hard TEMAC and the PLB bus of the PowerPC processor Both EMACs are capable of establishing communications at 10/100/1000 Mbps They can be configured for half duplex or full duplex operation Both support media interfaces, including MII, GMII, RGMII, SGMII, and 1000BASE-X

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Two independent EMACs Each EMAC has its own TX/RX statistics, client, and PHY interfaces Both share the host interface that enables configuration of the individual EMAC registers Host interface either connects to a generic host bus or a DCR bus that is hard wired to the PPC405

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 122 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Connecting Hard TEMAC A transparent bus is used to connect the hard TEMAC and the PLB TEMAC The ports on PLB_TEMAC which connect to HARD_TEMAC are grouped into a virtual bus, V4EMACSRC The corresponding signals on HARD_TEMAC are grouped into two virtual buses, V4EMACDST0 and V4EMACDST1, depending on which half of HARD_TEMAC the signals are used When only one half of the hard TEMAC is used, the PLB TEMAC virtual bus should be connected to V4EMACDST0 of the hard TEMAC The shared host signals are left unconnected The PLB TEMAC connected to V4EMACDST0 drives the host interface when both EMACs are used

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TX_CORE_CLK and TX_GMII_MII_CLK are internal clock signals. The clock generation module takes PHYEMAC#GTXCLK and generates EMAC#CLIENTTXCLIENTCLKOUT to run the circuitry in the FPGA fabric connecting to the client side. The CLIENTEMAC#TXCLIENTCLKIN signal runs the client logic and transmit engine inside the Ethernet MAC. This clock signal must be from the FPGA clock drivers (BUFG) of EMAC#CLIENTTXCLIENTCLKOUT. On the physical interface side, when the Ethernet MAC is configured in GMII, MII, or RGMII mode, EMAC#CLIENTTXGMIIMIICLKOUT drives the clock in the FPGA fabric connecting to the GMII/MII/RGMII sublayer. EMAC#CLIENTTXGMIIMIICLKOUT is also fed back into CLIENTEMAC#TXGMIIMIICLKIN. The CLIENTEMAC#TXGMIIMIICLKIN signal runs the MII/GMII/RGMII logic inside the Ethernet MAC. This clock signal must be from the FPGA clock drivers (BUFG) of EMAC#CLIENTTXGMIIMIICLKOUT. When Ethernet MAC is configured in SGMII or 1000BASE-X mode, TX_GMII_MII_CLK is driven by PHYEMAC#GTXCLK, and the CLIENTEMAC#TXGMIIMIICLKIN clock is not used.

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The clock generation module takes the PHYEMAC#RXCLK from the physical interface and generates EMAC#CLIENTRXCLKOUT to run the circuitry in the FPGA fabric connecting to the client side. CLIENTEMAC#RXCLIENTCLKIN runs the client logic and receive engine inside the Ethernet MAC. This clock signal must be from the FPGA clock drivers (BUFG) of EMAC#CLIENTRXCLIENTCLKOUT. When configured in MII, GMII, or RGMII mode, the internal RX_GMII_MII_CLK is derived from PHYEMAC#RXCLK and used to run the MII, GMII, or RGMII sublayer. If the Ethernet MAC is configured in either SGMII or 1000BASE-X PCS/PMA mode, the clock to run the PCS/PMA sublayer is generated from PHYEMAC#GTXCLK.

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The Ethernet MAC can be configured by using hardware or accessing the registers through the host interface in software Three methods Tie off pins in hardware The 80 tie-off pins are loaded into the MAC at power up or when the it is reset Generic host bus using the host interface The HOSTEMAC1SEL signal selects between the host access of EMAC0 or EMAC1 DCR using the host interface The DCR bus bridge in the host interface translates commands carried over the DCR bus into MAC host bus signals

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 126 Located in Austria & Brazil [email protected] Date Oct 23, 2009 PLB TEMAC Overview Features and Limitations Complies with the IEEE 802.3-2000 specification Automatic Pad and FCS field insertion or pass through on transmit Processes transmission and reception of pause packets for flow control Supports receive and transmit of longer VLAN-type frames Programmable interframe gap Provides interrupts for many error and status conditions Optional support of jumbo frames of up to 9 kB in length Hardware selectable DCR or PLB host interface to configuration registers RGMII, GMII, or MII interface to external PHY devices SGMII supported through MGT interface to external copper PHY layer MIIM for access to PHY transceiver registers

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C_DEV_BLK_ID Identification and verification of correct register access capability C_PLB_CLK_PERIOD_PSR The PLB bus clock should be within 42 MHz to 125 MHz for 1-Gbps Ethernet operation C_IPIF_WRFIFO_DEPTH and C_IPIF_RDFIFO_DEPTH Transmit FIFO depth in bits and receive FIFO depth in bits sets RX and TX FIFO memory size to 32 kb,16 kb, 8 kb, 4 kb, and 2 kb, respectively C_MAC_FIFO_DEPTH MAC length and status FIFO depth of 16, 32, or 64 C_BASEADDR and C_HIGHADDR Device base and high address addresses Default values result in error; range must be at least 0x4000

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C_RXFIFO_DEPTH and C_TXFIFO_DEPTH These parameters set the depth (in bits) of the packet FIFOs. The depth of the FIFOs impacts the number of block RAMS used in the system and only has a minor impact on logic resources used. C_DEV_BLK_ID The block ID is reflected as a field in the Module Identification Registers (MIRs). This can be used for identification and verification of correct register access capability. C_MAC_FIFO_DEPTH This parameter is used to select a depth for the transmit status, transmit length, receive status, and receive length registers. These registers are actually FIFOs and the depth represents the maximum number of entries that can be queued before an overflow condition occurs.

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C_TEMAC_INST 0 = instance 0 1 = instance 1 C_TEMAC_BOTH_USED 0 = 1 instance is used 1 = both instances are used

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C_INCLUDE_DEV_MIR Include or exclude the Module ID register C_RX_DRE_TYPE and C_TX_DRE_TYPE Data realignment engines C_INCLUDE_RESET Include or exclude the software reset function C_DMA_TYPE DMA type/interrupt functionality 0 = None 1 = Simple 2 = Scatter/gather

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C_INCLUDE_DEV_MIR This parameter includes or excludes the Module Identification Registers (MIRs) in the IPIF submodule. This includes the device MIR, packet FIFO MIRs, and the DMA MIR if the DMA module is included in the design. This reduces resource utilization in those cases where MIR functionality is not required. C_RX_DRE_TYPE and C_TX_DRE_TYPE These parameters include or exclude the data realignment engines—allowing unaligned source and destination addresses originating from the DMA controller. When these values are set to 0, no data realignment engine functionality is included. When set to 1, the data realignment engine blocks are built entirely out of logic. To save resources in exchange for DSP48s, set these parameters to 2 and the function will be done via DSP48 blocks (two DSP48s are consumed per TX/RX). This feature is only available when C_DMA_TYPE=3.

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When both TEMACs are used, the generic host interface of the hard TEMAC connects to the first instance of the PLB TEMAC.

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Need two instantiations of PLB TEMAC Set C_TEMAC_INST as 0 and 1 in the respective instantiations Set C_TEMAC_BOTH_USED to 1 in both instantiations Need two bus interface connections for hard TEMAC V4EMACDST0 and V4EMACDST1 Set C_EMAC1_PARAMETER to 1 in one hard TEMAC instance Assign PHY interface in both hard TEMAC instance

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The Temac_v1_00_a driver supports the following features Memory-mapped access to host interface registers API for polled frame transfers (FIFO direct-polled mode) API for interrupt-driven frame transfers with or without simple DMA channels (FIFO direct mode) API for interrupt-driven frame transfers with scatter/gather DMA (SGDMA mode) Virtual memory support Unicast receive address filtering Broadcast receive address filtering Full duplex operation

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The Temac_v1_00_a driver supports the following features Automatic source address insertion or overwrite (programmable) Automatic pad and FCS insertion and stripping (programmable) Pause frame (flow control) detection in full duplex mode Programmable interframe gap VLAN frame support Pause frame support Jumbo frame support Data Realignment Engine (DRE)

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The Temac_v1_00_a driver does not support the following features DCR-based access to host interface registers Retrieval of hard statistics counters Multicast receive address filtering MII access to PHY

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 137 Located in Austria & Brazil [email protected] Date Oct 23, 2009 PLB TEMAC API

XStatus XTemac_CfgInitialize (XTemac *InstancePtr, XTemac_Config *CfgPtr, Xuint32 VirtualAddress) XStatus XTemac_Initialize (XTemac *InstancePtr, Xuint16 DeviceID) void XTemac_Reset (XTemac *InstancePtr, int HardCoreAction) XStatus XTemac_Start (XTemac *InstancePtr) void XTemac_Stop (XTemac *InstancePtr) XStatus XTemac_SelfTest (XTemac *InstancePtr)

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Initialization: Initializes a specific XTemac instance/driver. It initializes fields of the instance structure, resets the hardware, applies default options, configures the packet FIFOs, if present, and configures the DMA channels. if present Reset: Performs a graceful reset of the Ethernet MAC. Resets the DMA channels, the FIFOs, the transmitter, and the receiver. All options are placed in their default state. Any frames in the scatter/gather descriptor lists will remain in the lists. The side effect is that after a reset and following a restart of the device, frames that were in the list before the reset may be transmitted or received. The upper layer software is responsible for reconfiguring (if necessary) and restarting the MAC after the reset. Start: Starts the Ethernet controller by enabling the transmitter if XTE_TRANSMIT_ENABLE_ OPTION is set and enabling the receiver if XTE_RECEIVER_ENABLE_OPTION is set. If not polled mode, it starts the SG DMA send and receive channels (if configured) and enables the global device interrupt Stop: Gracefully stops the Ethernet MAC by disabling all interrupts from this device, stopping DMA channels (if configured), and disabling the receiver. Device options currently in effect are not changed. This function disables all interrupts by clearing the global interrupt enable. Self-Test: Performs a self-test on the Ethernet device. The test includes a self-test on the DMA channel, FIFO, and IPIF components. This self-test is destructive. On successful completion, the device is reset and returned to its default configuration. The caller is responsible for reconfiguring the device after the self-test is run and starting it when ready to send and receive frames.

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XStatus XTemac_SetMacAddress (XTemac *InstancePtr, void *AddressPtr) void XTemac_GetMacAddress (XTemac *InstancePtr, void *AddressPtr) XStatus XTemac_MulticastAdd (XTemac *InstancePtr, void *AddressPtr, int Entry) void XTemac_MulticastGet (XTemac *InstancePtr, void *AddressPtr, int Entry) XStatus XTemac_MulticastClear (XTemac *InstancePtr, int Entry) XStatus XTemac_SetMacPauseAddress (XTemac *InstancePtr, void *AddressPtr) void XTemac_GetMacPauseAddress (XTemac *InstancePtr, void *AddressPtr) XStatus XTemac_SetOptions (XTemac *InstancePtr, Xuint32 Options) XStatus XTemac_ClearOptions (XTemac *InstancePtr, Xuint32 Options) Xuint32 XTemac_GetOptions (XTemac *InstancePtr) XStatus XTemac_SendPausePacket (XTemac *InstancePtr, Xuint16 PauseValue) Xuint16 XTemac_GetOperatingSpeed (XTemac *InstancePtr) void XTemac_SetOperatingSpeed (XTemac *InstancePtr, Xuint16 Speed) XStatus XTemac_GetSgmiiStatus (XTemac *InstancePtr, Xuint16 *SpeedPtr) XStatus XTemac_GetRgmiiStatus (XTemac *InstancePtr, Xuint16 *SpeedPtr, Xboolean *IsFullDuplexPtr, Xboolean *IsLinkUpPtr) void XTemac_PhySetMdioDivisor (XTemac *InstancePtr, Xuint8 Divisor)

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 139 Located in Austria & Brazil [email protected] Date Oct 23, 2009 PLB TEMAC API: FIFO

XStatus XTemac_FifoWrite (XTemac *InstancePtr, void *BufPtr, Xuint32 ByteCount, int Eop) XStatus XTemac_FifoSend (XTemac *InstancePtr, Xuint32 TxByteCount) XStatus XTemac_FifoRecv (XTemac *InstancePtr, Xuint32 *ByteCountPtr) XStatus XTemac_FifoRead (XTemac *InstancePtr, void *BufPtr, Xuint32 ByteCount, int Eop) Xuint32 XTemac_FifoGetFreeBytes (XTemac *InstancePtr, Xuint32 Direction) XStatus XTemac_FifoQuerySendStatus (XTemac *InstancePtr, Xuint32 *SendStatusPtr) XStatus XTemac_FifoQueryRecvStatus (XTemac *InstancePtr)

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 140 Located in Austria & Brazil [email protected] Date Oct 23, 2009 PLB TEMAC API: Interrupt XStatus XTemac_SetHandler (XTemac *InstancePtr, Xuint32 HandlerType, void *CallbackFunc, void *CallbackRef) void XTemac_IntrFifoEnable (XTemac *InstancePtr, Xuint32 Direction)void XTemac_IntrFifoDisable (XTemac *InstancePtr, Xuint32 Direction)void XTemac_IntrFifoHandler (void *TemacPtr) void XTemac_IntrSgEnable (XTemac *InstancePtr, Xuint32 Direction)void XTemac_IntrSgDisable (XTemac *InstancePtr, Xuint32 Direction)XStatus XTemac_IntrSgCoalSet (XTemac *InstancePtr, Xuint32 Direction, Xuint16 Threshold, Xuint16 Timer)XStatus XTemac_IntrSgCoalGet (XTemac *InstancePtr, Xuint32 Direction, Xuint16 *ThresholdPtr, Xuint16 *TimerPtr)void XTemac_IntrSgHandler (void *TemacPtr)

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Initialize Status = XTemac_Initialize() Set EMAC address Status = XTemac_SetMacAddress() Set options which are different than defaults Status = XTemac_SetOptions()

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Polled mode frame transmission Set up polled mode by using XTemac_SetOptions() Check for available space by using XTemac_FifoGetFreeBytes() Write frame data into the FIFO by using XTemac_FifoWrite() Initiate transmit by calling XTemac_FifoSend() Check for transmission status by calling XTemac_FifoQuerySendStatus()

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Polled mode frame reception Call XTemac_FifoQueryRecvStatus() until it reports that a frame has been received Call XTemac_FifoRecv() to retrieve the length of the next pending frame Call XTemac_FifoRead() to read the data into your buffer

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Direct interrupt-driven mode transmission Enable transmit interrupts by using XTemac_IntrFifoEnable() Check for available space by using XTemac_FifoGetFreeBytes() Write frame data into the FIFO by using XTemac_FifoWrite() Initiate transmit by calling XTemac_FifoSend()

Note: The FifoSend callback is invoked on transmission success The user’s FifoSend callback handles post-frame transmission application-level work

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Direct interrupt-driven mode reception Enable receive interrupts with XTemac_IntrFifoEnable() Invoke the user’s FifoRecv callback upon arrival of a frame FifoRecv callback must call XTemac_FifoRecv() to retrieve frame length FifoRecv callback then calls XTemac_FifoRead() to copy the frame to a user buffer

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Initialization Reset EMAC TX, RX, and flow control Write 0x80000000 to TXC, RXC1, and FCC

Configuration TX and RX RX RXC1 0x10000000 Enable EMAC RX, no VLAN, no jumbo, strip FCS TX TXC 0x10000000 Enable EMAC TX, no VLAN, no jumbo, no client-supplied FCS

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Configuration address unicast address 0x060504030201 UAW1 0x00000102: EMAC unicast address UAW0 0x03040506: EMAC unicast address

Configuration EMAC mode and receive address mode CFG 0x0x84000000: Enables 1G speed and host interface AFM 0x00000000: EMAC enables address filtering

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TX packet WPFIFO_DATA: Write double TPLR: Transmit length; this starts transmission TSR: Read 0x00000001 value after TX complete is indicated by interrupt

RX packet RSR: Read 0x00000001 value after RX complete is indicated by interrupt RPLR: Read receive length; indicates the number of bytes to read RPFIFO_DATA: Read double

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How can PLB TEMAC be used? How many PLB TEMAC instances are required if one hard TEMAC port is used? How many host configuration ports are required if two hard TEMACs are used? What data rate can hard TEMAC be used for? What parameter is called and needs to be set when both hard TEMAC are used? State the steps involved in performing transmission using polled mode

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 150 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Answers How can PLB TEMAC be used? PLB TEMAC can be connected to hard TEMAC to provide an interface to the processor PLB bus via a “transparent” bus How many PLB TEMAC instances are required if one hard TEMAC port is used? One How many host configuration ports are required if two hard TEMACs are used? One What data rate can hard TEMAC be used for? 10, 100, 1000 Mbps

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SO-LOGIC electronic consulting www.so-logic.net File: 03_so_hssio_ethernet.odp Worldwide Technical Training & Consulting Page 151 Located in Austria & Brazil [email protected] Date Oct 23, 2009 Answers What parameter is called and needs to be set when both hard TEMAC are used? C_EMAC1_PARAMETER State the steps involved in performing transmission using polled mode Set up polled mode by using XTemac_SetOptions() Check for available space by using XTemac_FifoGetFreeBytes() Write frame data into the FIFO by using XTemac_FifoWrite() Initiate transmit by calling XTemac_FifoSend() Check for transmission status by calling XTemac_FifoQuerySendStatus()

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The PLB TEMAC peripheral core provides hard TEMAC connectivity to the processor PLB bus There are two hard TEMACs for each PowerPC™ processor Two instances are required when both hard TEMACs are used Only one host interface is needed even when both hard TEMACs are used

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