Analysis and Design of a High-Frequency RC Oscillator Suitable for Mass Production

Master of Science Thesis in Electrical Engineering Department of Electrical Engineering, Linköping University, 2017

Analysis and design of a high-frequency RC oscillator suitable for mass production

Jianxing Dai Master of Science Thesis in Electrical Engineering

Analysis and design of a high-frequency RC oscillator suitable for mass production

Jianxing Dai

LiTH-ISY-EX--17/5060--SE

Supervisor: Dr. Erik Säll Fingerprint Cards AB Martin Nielsen Lönn isy, Linköpings universitet Examiner: Dr. J Jacob Wikner isy, Linköpings universitet

Division of Integrated Circuits and Systems Department of Electrical Engineering Linköping University SE-581 83 Linköping, Sweden

Oscillators are components providing clock signals. They are widely required by low-cost on-chip applications, such as biometric sensors and SoCs. As part of a sensor, a relaxation oscillator is implemented to provide a clock reference. Lim- ited by the sensor application, a clock reference outside the sensor is not desired. An RC implementation of the oscillator has a balanced accuracy performance with low-cost advantage. Hence an RC relaxation oscillator is chosen to provide the clock inside the sensor. This thesis proposes a current mode relaxation oscillator to achieve low frequency standard deviation across diﬀerent supplies, temperatures and process corners. A comparison between a given relaxation oscillator and the proposed design is made as well. All oscillators in this thesis use 0.18 µm technology and 1.8 V nominal supply. The proposed oscillator manages to achieve a frequency standard deviation across all PVT variations less than 6.5% at 78.4 MHz output frequency with a power dissipation of 461.2 µW. The layout± of the oscillator’s core area takes up 0.003 mm2.

iii

Acknowledgments

I appreciate that Fingerprint Cards AB offers me the opportunity to work on this thesis. The project has been challenging and meaningful. I would like to thank Dr. Erik Säll for being my supervisor at Fingerprints. His suggestion always pointed out a way to solve the issue. Dr. Robert Hägglund, Anders Nordström, Dr. Christer Jansson and Dr. Prakash Harikumar helped me a lot during the project period at Fingerprints as well. Special thanks to Dr. J Jacob Wikner and Martin Nielsen Lönn for being my examiner and supervisor at campus. Dr. J Jacob Wikner’s guidance helped me in different stages of this project. I would also like to thank my office mate Jimmy Johansson, who had worked the whole period with me at Fingerprints. I would like to thank Carl-Fredrik Tengberg for teaching me the Swedish alcohol culture as well as being another thesis student at Fingerprints with me. Finally I would like to thank my parents for supporting me during the past two years.

Linköping, June 2017 Jianxing Dai

Contents

List of Figures x

List of Tables xii

Notation xiii

1 Introduction 1 1.1 Motivation and purpose ...... 1 1.2 Problem statements ...... 3 1.3 Constraints ...... 3 1.4 Methodology ...... 3 1.5 Scope of the dissertation ...... 4

2 Background 5 2.1 Original oscillator ...... 5 2.2 Simulation settings ...... 6 2.3 Simulation results ...... 7 2.4 Speciﬁcations ...... 8

3 Theory 9 3.1 Conventional relaxation oscillator ...... 9 3.2 Original design of the oscillator ...... 10 3.2.1 Bias generation module ...... 12 3.2.2 Comparator ...... 15 3.2.3 Trimming control ...... 17 3.2.4 SR latch ...... 19 3.3 Current mode oscillator ...... 20 3.3.1 Block diagram ...... 20 3.3.2 Circuit schematic ...... 21 3.3.3 Cascode current mirror ...... 21 3.3.4 Current mode comparator ...... 25 3.4 Temperature coeﬃcient ...... 27 3.5 Noise ...... 28

vii viii Contents

3.6 Conclusion ...... 28

4 Method 29 4.1 Testbench ...... 29 4.2 Original oscillator ...... 30 4.2.1 Start-up phenomenon ...... 32 4.2.2 Time delay ...... 33 4.3 Improved oscillator ...... 33 4.3.1 Schematic simulation ...... 35 4.3.2 Limitations ...... 37 4.4 Current mode oscillator ...... 38 4.4.1 Implementation ...... 38 4.4.2 Schematic simulation ...... 39 4.4.3 Layout ...... 41 4.4.4 Post-layout simulation ...... 45

5 Result 47 5.1 Frequency output ...... 48 5.1.1 Temperature dependence ...... 50 5.1.2 Supply voltage dependence ...... 52 5.2 Frequency standard deviation ...... 53 5.3 Noise simulation ...... 56 5.4 Results comparison ...... 58 5.5 Practical issue ...... 59 5.5.1 Trimming range ...... 59 5.5.2 VT variation ...... 60 5.5.3 Extraction variation ...... 61

6 Discussion 63 6.1 Method ...... 63 6.2 Noise ...... 64 6.3 Trimming system ...... 64 6.3.1 Trimming step ...... 65 6.4 External reference ...... 65 6.5 Sizing ...... 65 6.6 Improved performance of the improved oscillator ...... 66 6.7 Improved performance of post-layout simulation ...... 66 6.8 VT dependence ...... 66 6.9 Simulator issue ...... 67

7 Conclusion and future’s work 69 7.1 Future’s work ...... 69

Bibliography 71

A Appendix 77 A.1 Opponent’s questions and respondent’s responses ...... 77 Contents ix

A.2 Change track ...... 80 List of Figures

1.1 The conﬁguration of the original oscillator...... 2

2.1 Distribution of 100-points Monte Carlo simulation at 40 ◦C with 1.98 V supply of the original oscillator...... − ...... 8

3.1 Conventional relaxation oscillator schematic...... 10 3.2 Original design of the oscillator...... 11 3.3 Bias generation module design of the original oscillator...... 14 3.4 Schmitt trigger design of the current oscillator...... 15 3.5 Comparator design of the original oscillator...... 16 3.6 Trimming module design of the original oscillator...... 18 3.7 SR latch design of the oscillators...... 19 3.8 The block diagram of the current mode oscillator...... 20 3.9 The conﬁguration of the proposed current mode oscillator. . . . . 22 3.10 Cascode current mirror design of the oscillator...... 23 3.11 Simpliﬁed model of the cascode current mirror design of the oscillator...... 24 3.12 Current mode comparator design of the proposed oscillator. . . . . 26 3.13 Current comparison circuit’s timing diagram...... 26

4.1 The testbench of the oscillator...... 30 4.2 Delayed enabling signal triggers the oscillation...... 31 4.3 Capacitor voltage in oscillation...... 32 4.4 Comparator internal signals for upper threshold comparison in oscillation...... 34 4.5 Improved design of the oscillator...... 35 4.6 The non-overlapping clock generator in the improved oscillator. . 36 4.7 The ramp capacitor voltage Vrc in oscillation...... 36 4.8 Internal signals of the VthH comparator in the improved oscillator. 37 4.9 The current generated from the bias current generator at nominal condition...... 39 4.10 The capacitor ramp voltages in oscillation state at nominal condition...... 40 4.11 The output signals of the current mode comparator module in oscillation state at nominal condition...... 40

x LIST OF FIGURES xi

4.12 Top level of the proposed oscillator layout...... 41 4.13 The logic module of the proposed oscillator layout...... 42 4.14 The bias module of the proposed oscillator layout...... 43 4.15 The current mode comparator module of the proposed oscillator layout...... 44 4.16 Ramp voltages of the capacitors and output signals of the current mode comparator...... 45

5.1 The original oscillator’s output waveform and frequency settling time...... 48 5.2 The improved oscillator’s output waveform and frequency settling time...... 48 5.3 The schematic simulation results of the proposed oscillator’s output waveform and frequency settling time...... 49 5.4 The post-layout simulation results of the proposed oscillator’s output waveform and frequency settling time...... 50 5.5 Temperature dependences of the implemented oscillators...... 51 5.6 Supply voltage dependences of the implemented oscillators. . . . . 52 5.7 Histogram of 100 samples at 40 ◦C with 1.98 V supply of the original oscillator...... − ...... 53 5.8 Histogram of 100 samples at 40 ◦C with 1.62 V supply of the improved oscillator...... − ...... 54 5.9 Histogram of 100 samples at 40 ◦C with 1.62 V supply of the schematic simulation of the proposed− oscillator...... 54 5.10 Histogram of 100 samples at 40 ◦C with 1.62 V supply of the post- layout simulation of the proposed− oscillator...... 55 5.11 The oscillators’ spectrums...... 56 5.12 The oscillators’ phase noises...... 57 5.13 Trimming range of the implemented oscillators...... 59 5.14 VT variations of the implemented oscillators...... 60 5.15 The output frequencies for diﬀerent extractions of the nominal corner...... 61

6.1 Histogram of 100 samples at 40 ◦C with 1.62 V supply of the original oscillator...... − ...... 68 List of Tables

1.1 Constraints of the design...... 3

2.1 Test settings for oscillators...... 6 2.2 Simulation results of the original oscillator...... 7 2.3 Speciﬁcations of the proposed design...... 8

3.1 Truth table of the SR latch of this design...... 20

5.1 Simulation results comparison between the original oscillator and the improved oscillator...... 49 5.2 Simulation results comparison between the schematic and the layout of the proposed oscillator...... 50 5.3 The comparison between diﬀerent implementations’ Monte Carlo simulation results...... 55 5.4 The noise simulation results’ comparison table...... 57 5.5 Results comparison...... 58 5.6 VT variations caparison...... 61

A.1 Document history...... 80

xii Notation

Abbreviations Abbreviation Description BCG Bias Current Generator CMC Current Mode Comparator cmos Complementary Metal Oxide Semiconductor CS Common Source DFF D-Flip Flop FoM Figure of Merit INT Integrator LSB Least Significant Bit LUT Look-Up Table MC Monte Carlo opamp Operational Amplifier PVT Process, Voltage and Temperature PSS Periodic Steady State RGC Regulated Cascode TCR Temperature Coefficient of Resistance VCC Voltage Current Converter VT Voltage and Temperature

xiii

1 Introduction

In electronics a relaxation oscillator is a nonlinear electronic oscillator circuit that produces a non-sinusoidal repetitive output signal, such as a triangle wave or square wave [1]. The circuit consists of a feedback loop containing a switching device such as a transistor, comparator, op amp, or a negative resistance device like a tunnel diode, that repetitively charges a capacitor or inductor through a resistance until it reaches a threshold level, then discharges it again [2].

The period of the oscillator depends on the time constant of the capacitor or inductor circuit. [3] The active device switches abruptly between charging and discharging modes, and thus produces a discontinuously changing repetitive waveform [2]. This contrasts with the other type of electronic oscillator, the harmonic or linear oscillator, which uses an ampliﬁer with feedback to excite resonant os- cillations in a resonator, producing a sine wave [4].

1.1 Motivation and purpose

There was a given relaxation oscillator using RC architecture to generate square wave clock signal. This oscillator operates with 1.8 V supply voltage and is implemented with 0.18 µm technology. The given oscillator can output a square wave clock of 86 MHz with nominal process corner, 1.8 V supply and 25 ◦C temperature. The given oscillator is shown in Fig. 1.1 and will be further described in Chapter 2 and 3.

1 2 1 Introduction

1.8 V + CMP0

Ibias VthH INV0 − HitHigh S0 ICharge R Q CLK Vrc

S Q CLK S1 CRamp + HitLow

IDischarge

V − thL CMP1 INV1

Ibias

Figure 1.1: The conﬁguration of the original oscillator.

However, to obtain as good performance and robust system as possible, an improved performance is preferable. The oscillator itself can be tuned to operate in the frequency range of 20-100 MHz using digital control signals and this ﬁts the current sensor implementation. The task is to look into oscillator principles to evaluate which circuit structure that is considered most appropriate to imple- ment in order to obtain low frequency variations over a large tuning range.

A frequency variation in this project appears as a deviation to the mean output frequency. The deviation will degrade the supported systems, which are designed to operate at nominal frequency. The designs usually leave a ﬂexible frequency range to operate with, and the frequency standard deviation can be compensated by digital parts of the system.

The frequency variation needs to be within a limited range for the stability of the system operation. As a static variation, frequency variation, or to be precisely, standard deviation could be due to temperature changes, process variations or supply voltage instability.

Noises in the oscillator are appeared to be phase noise, or jitters in time domain. Which are crucial performance parameters of normal oscillator. But due to the application of the oscillator, samples will only be taken when the signal is settled. The settled signals are so stable that the jitters of oscillators will not aﬀect the sampling. Hence the noise performance of the oscillators are not main concern of this thesis. 1.2 Problem statements 3

1.2 Problem statements

This thesis will cover the following questions. • What other kinds of architectures can be used to achieve a relaxation oscillator? • Which component of the design is the main reason for output frequency variation across diﬀerent process, temperature and supply voltage corners? • Which devices of the components are more exposed to process, temperature and supply changes? The questions will be discussed and answered in the following chapters.

1.3 Constraints

This project is aiming to improve the existing design of the relaxation oscillator. Hence the design is limited with process technology, supply voltage, temperature range and output signal type, as shown in Tab. 1.1. The design will be utilized in schematic level and a layout based on the schematic design will be performed. Hence the evaluation will be based on the simulations, which consists of schematic simulation and post-layout simulation.

Table 1.1: Constraints of the design.

Supply voltage (V) 1.62 - 1.98 Temperature ( C) 40 - 85 ◦ − Process technology (nm) 180 Output signal form Square wave Design form Schematic & Layout Results sources Simulations

1.4 Methodology

The methodology includes preliminary literature survey to decide appropriate circuit design and state-of-the-art performance. Based on system specifications, the design parameters of the circuit blocks are derived. The implementations of different modules are carried out subsequently. The design is implemented by combining circuit techniques from different publications as well as adopting modifications of the original design. Simulations are performed with different process corners, supply voltages and temperatures. 4 1 Introduction

1.5 Scope of the dissertation

This thesis is organized as the following structure: • Chapter 2 discusses the design specifications for the oscillator. The original oscillator’s simulation results are listed as well. • Chapter 3 presents the working principles of different components inside the oscillators. This chapter is based on various publications and original oscillator’s circuit design. • Chapter 4 presents the implementations of an improved version of the original oscillator and a new proposal of a relaxation oscillator. • Chapter 5 presents results of the two implemented oscillators and a comparison between different relaxation oscillators. • Chapter 6 presents conclusions and discussions of the results. A wider perspective of this work is also concluded. An appendix of the opponent’s comments and author’s replies is included at the final part of the report. 2 Background

As mentioned in Section 1.1, the thesis is aiming to improve the existing design or propose a new implementation. Thus this chapter focuses on the original design and the speciﬁcations. The simulation results of the original oscillator based on schematic design are listed in this chapter. The worst corner of the frequency standard deviation is shown in histograms. The distribution of the Monte Carlo simulation results are evaluated with the 3σ rule, which is used to measure samples’ deviations to the mean value of test results. To include all simulation results into 3σ range, a standard deviation needs to be adjusted. Hence a wide spread distribution of the simulation results will result in a large standard deviation of the output frequency, which needs to be avoided. The proposed design should be able to easily integrate into the existing system. This requires some key features to be maintained, such as the trimming signal combined with the control code.

2.1 Original oscillator

The original oscillator has the configuration as shown in Fig. 1.1. It consists of two current sources charging and discharging the ramp capacitor CRamp, two comparators connected with inverters and an SR latch as the output logic. It should be noticed that the two bias current mirrors are controlled by trimming codes outside the oscillator. The trimming code changes the amount of the charging and discharging current, consequently adjusts the output frequency. The trimming code ranges from 8 to 7 in decimal, but realized in two’s com- − 5 6 2 Background plement in the oscillator. In the original oscillator, the trimming code is a five bits two’s complement code. The five bits control code requires five branches of current mirrors. They are parallel connected MOSFETs and the numbers of MOSFETs in each branch are determined by 2n. A detailed description of the trimming control module is included in Section 3.2.3.

2.2 Simulation settings

The original oscillator and the proposed oscillator will be evaluated under transient simulations and Monte Carlo simulations. Nominal cases transient simulations provide nominal output frequencies, settling time, duty cycles and current consumptions of the tested oscillators. The Monte Carlo simulations provide the output frequency standard deviations of the oscillators. The supply voltages are provided by ideal DC voltage source. Simulation settings are shown in Tab. 2.1 below. It should be noted that trimming codes differ from each other for different purposes. That is the reason for "depends" in the table. When a tuning range of an oscillator is to be tested, the trimming code will be swept from 8 to 7. When an output frequency is to be tested, the trimming code will be fixed− to 0. The process corner 0 means typical corner. Different combinations of NMOSs and PMOSs corners are named after 1 to 12. The process corner 100 is for the recognition by the MC models. Hence the process corner 100 can be translated as "Monte Carlo model process corner setting".

Table 2.1: Test settings for oscillators.

Simulation Transient Monte Carlo Supply (V) 1.8 1.62, 1.98 Temperature (◦C) 25 -40, 25, 85 Process Corner 0 100 Trimming Code Depends 0

Apart from the VT settings and process corner settings, Monte Carlo simulations have more options than transient simulations. The variation setting is set to "all", which means process variations and mismatches are both simulated during the MC simulations. The sampling method is set to "random". The process variation is covered by the MC simulation model, hence VT variations are suﬃcient for MC corner settings. It should be noticed that the process corner setting for the MC simulations are not enough to cover all process corner variations. Due to the limitations on resources, simulations for all process variations are not feasible. Hence a simpliﬁed MC process corner setting is used to estimate the oscillator’s performances. VT variations with MC simulations can not give identical results to the PVT simulations. 2.3 Simulation results 7

2.3 Simulation results

The given design of the oscillator has the simulation results as shown in Tab. 2.2. As mentioned in Section 2.2, all voltage supplies are ideal. The MC test simulates mismatches and process defects in the tested circuit and the simulation results are collected. Experimentally, the output frequency range in an MC test is larger than a test of all process corner sweep with different supplies and temperatures. Thus the trimming range can be determined through this test as well. The current consumption is measured with transient test. The current is taken within several full clock cycles and averaged to calculate the average current consumption. The taken clock cycles are near the end of the simulation in order to acquire steady state current consumption. The worst corner of the output frequency standard deviation occurs at the scenario of 1.98 V supply, 40 ◦C. The distribution of the 100-points Monte Carlo simulation is shown in Fig.− 2.1. It is clear that the 11.3 MHz standard deviation comes from this wide distribution in frequency domain. The target of the project is to achieve as low as possible frequency standard deviation while fulfilling other specifications.

Table 2.2: Simulation results of the original oscillator.

Current consumption (µA) 112.8 Output frequency tuning 61.0 - 105.9 range (MHz) Output frequency (MHz) 85.68 Output settling time (µs) 2.14 Output duty cycle (%) 46.1 Standard deviation of output 11.3 frequency (MHz) VT variation (MHz) 7.06 Max/Min/Mean values of out- 122.6 / 60.6 / 86.5 put frequency (MHz)

Apart from the frequency standard deviation, the frequency spread in the MC simulation shows a large range at output frequency. This is why a trimming system is required for the oscillator. The trimming system can provide a range to tune the oscillator in order to make the oscillator output frequency at 80 MHz. Since the PVT variations are realized by MC simulation model and the VT settings in this thesis due to the limited resources. These 100-points simulations for each VT combination corner can be seen as close estimations of an oscillator’s performances across PVT variations. 8 2 Background

Figure 2.1: Distribution of 100-points Monte Carlo simulation at 40 ◦C with 1.98 V supply of the original oscillator. −

2.4 Speciﬁcations

Design proposals need to be evaluated in the following perspectives: current consumption, area, start-up time, frequency standard deviation and duty cycle. The speciﬁcations of the proposed designs are shown in Tab. 2.3. It should be noticed that the following speciﬁcation needs to be realized with the trimming code set to 0.

Table 2.3: Speciﬁcations of the proposed design.

Current consumption (µA) 250 ≤ Area (mm2) 0.02 ≤ Start-up time (µs) 2.2 ≤ Frequency standard devia- 6 @ 75 - 85 MHz tion (MHz) ≤ Duty cycle (%) 50 ≈

As a hard requirement, the target of decreasing the frequency standard deviation must be achieved. The other speciﬁcations could be deemed as acceptable when they are around the speciﬁcations. The area estimation of those designs with only schematic levels are done in the Cadence layout tool LayoutXL. The estimation will be done with a utilization ratio of 70%, which could be easily achieved by careful planning and placement. 3 Theory

This chapter will focus on the relaxation oscillator’s working principles, which involve both the oscillator and the sub-modules.

A conventional relaxation oscillator will be described ﬁrst. Then diﬀerent components of the original oscillator design will be elaborated. At last, the key components of the proposed design will be showed.

The original oscillator was designed based on the conventional voltage mode relaxation oscillator. Unlike common relaxation oscillators, the original design achieved an output frequency as high as 85 MHz. The high frequency output inevitably leads to high frequency standard deviation. Thus a current mode relaxation oscillator is proposed in this work, aiming to reduce the frequency standard deviation and keep the output frequency at a range of 75 - 85 MHz.

3.1 Conventional relaxation oscillator

As shown in Fig. 3.1 is a conventional voltage mode relaxation oscillator. The circuit consists of bias currents IBs, a reference voltage VREF, comparators Comp.1,2 capacitors CRAMP1,2 reset switches MNRST1,2, and a control logic circuit. When Q and QB are high and low, MNRST1 and MNRST2 are oﬀ and on, respectively. The CRAMP1 accepts IB and generates ramp voltage of VINT1. The Comp.1 compares VINT1 with VREF. When the VINT1 reaches VREF, the Comp.1 detects it and Q and QB toggle low and high, respectively. By repeating above operation alternately for CRAMP1 and CRAMP2, the circuit generates a clock pulse [5].

9 10 3 Theory

QB Q

Logic

VDD VDD Comp.1 Comp.2 − + + −

IB IB

VINT1 VINT2

+ CRAMP1 − CRAMP2 MNRST1 MNRST2

VREF

Figure 3.1: Conventional relaxation oscillator schematic.

The control logic component is implemented with an SR latch, which is designed to reshape the output waveform from the two comparators as well as controlling the duty cycle of the output signal.

3.2 Original design of the oscillator

As shown in Fig. 3.2 is the oscillator design to be improved. The circuit consists of reference voltages VthH and VthL, bias current IBias, two current mirrors, comparators CMP0,1, capacitor CRamp, switches S0,1 and an SR latch. The bias current Ibias is generated by current mirrors M1 and M2 with opposite direction. Reference voltages are generated by a bias generation module, which provides the reference current for the current mirrors as well. Comparing to the conventional design, this oscillator uses logic signal HitLow to set the SR latch due to the start-up voltage of the Vrc being logic high. Switches S0 and S1 are controlled by the clock signal output of the SR latch. The CLK signal is inverted to drive the switches, which are implemented by CMOS technology, i.e. S0 is implemented by PMOS and S1 is implemented by NMOS. Then the 3.2 Original design of the oscillator 11

two current mirrors generate the bias current IBias to charge and discharge the capacitor to generate a saw-tooth wave. The comparator will output a logic high signal when the positive input is higher than the negative input. The comparator CMP0 will output logic high when VthH is higher than Vrc, and CMP1 will output logic high when Vrc is higher than VthL. These comparators’ output signals will be inverted and work as set and reset signals to the SR latch. A simple expression for the output clock signal can be concluded from Fig. 3.1

1 Tclk = Tclk_high + Tclk_low = (3.1) fclk

CRamp(VthH VthL) T = − (3.2) clk_high I | Charge|

CRamp(VthH VthL) T = − (3.3) clk_low I | Discharge|

1.8 V + CMP0

Ibias VthH INV0 − HitHigh S0 ICharge R Q CLK Vrc

S Q CLK S1 CRamp + HitLow

IDischarge

V − thL CMP1 INV1

Ibias

Figure 3.2: Original design of the oscillator.

This oscillator works in the following sequence: • An enabling signal is switched from logic low to logic high, triggering the bias module of the oscillator to start working. The Vrc is set to logic high initially. • The enabling signal is delayed and delivered to the internal components of 12 3 Theory

the oscillator.

• The CRamp begins to discharge after the trimming control module is acti- vated.

• When the Vrc touches the low threshold voltage VthL, the CMP1 output signal toggles and HitLow changes to logic high, which set the SR latch output Q to logic high.

• The switch S1 turns oﬀ and S0 turns on. The Camp begins to charge after the CLK signal toggling to logic high.

• When the Vrc touches the high threshold voltage VthH, the CMP0 output signal toggles and HitHigh changes to logic high, which reset the SR latch output Q to logic low. Then the oscillator keeps on oscillating until the enabling signal toggles to logic low. Which shuts down the oscillator. The generated clock is used to take samples in the rest part of the circuit. Each sample will be taken at steady state, hence the jitter is not of concern in this application. Samples will be taken at their settled states, while the clock will be used at lower frequency to take the samples. Combining these two features together, clock jitters, or phase noises, of an oscillator is not one of the main pursuits of an oscillator design. 3.2.1 Bias generation module

The circuit has enabling signals E and E, bias currents IbnC and IbnR as the input signals. Enabling signals Eo and Eo, bias current IbIch, bias voltages Vbp1 and Vbp2, reference voltages VthH and VthL are the output signals of this circuit. As shown in Fig. 3.3, The circuit can be divided into two parts. The current mirrors take constant reference currents IbnC and IbnR as reference inputs. The bias voltage generator, which takes IbnC as the reference input, generates the bias voltages for comparators, bias current IbIch and enabling signals Eo and Eo for the rest parts of the oscillator.

The bias current IbIch is the reference current of the current mirrors that control the charging and discharging of the capacitor CRamp in Fig. 3.2. The enabling signals Eo and Eo are designed to have a time delay, which ensures that the comparator reference voltages and other pre-charging components of the oscillator are ready. The time delay is achieved by capacitor charging delay.The capacitor is implemented by connecting the PMOS PMC0 as a MOS capacitor, which needs to be charged and discharged to trigger the Schmitt trigger. As for the capacitor connected MOSFET, The drain, source and bulk of the MOS- FET are connected to gether as one plate of the capacitor. The gate of the MOSFET functions as the other plate of the capacitor. Since the gate oxide is the thinnest dielectric available in an integrated circuit, it is imminently sensible to build capacitors around it. All comprise gate and silicon conducting "plates" separated 3.2 Original design of the oscillator 13 by the gate oxide as dielectric. All are nonlinear capacitors, whose value depends on the voltage across it [6].

The threshold voltage generator, which takes IbnR as reference input, generates the reference voltages for comparators. The circuit uses a resistor R2 to compen- sate the temperature variation in the voltage divider. Similar resistor values of R2 and R1 are taken. As shown in Fig. 3.3, threshold voltages are set by series connected resistors R0 and R1. The two capacitors NMC0 and NMC1 are decoupling capacitors to stabilize the output threshold voltages.

Schmitt trigger

It should be noticed that the ﬁrst stage of the enabling signals delay chain is a Schmitt trigger. It is implemented as shown in Fig. 3.4. A Schmitt trigger is used to avoid unsettled logic level to the inverters. As a analog to digital bistable device, the Schmitt trigger is widely used in multi-vibrators. The Schmitt trigger in this design is an output inverted version of a normal one. As illustrated in [7], design parameters could be attained from

k V V 2 M1 = DD − Hi , (3.4) k V V NM1 Hi − TN k V 2 M0 = Li . (3.5) k V V V PM1 DD − Li − | TP|

The ki in the equations is deﬁned as

1 W k = µC . (3.6) i 2 ox L i

VHi and VLi are the expected threshold voltage of the Schmitt trigger (i.e. starting points of the triggering operations). VTN and VTP are the threshold voltage of NMOSs and PMOSs. kNM0 and kPM0 aﬀect the real triggering points VH and VL. The diﬀerences between the starting points and the transitions are marked as ∆VH and ∆VL. They can be expressed as

VDD VHi VTP ∆VH − − | |, (3.7) ≈ kNM0 + kNM0 kPM0 kM0

VLi VTN ∆VL − . (3.8) ≈ − kPM0 + kPM0 kNM0 kM1

∆VH is deﬁned as ∆VH = VH VHi, while ∆VL = VL VLi. The design parameters for NM0 and PM0 can be derived− from Equation (3.7)− and (3.8). 14 3 Theory NM0 I bnC E E NMe1 NMe0 PM0 1 . V 8 NM1 PMe0 iue3.3: Figure V bp1 PM1 NM2 isVlaeGenerator Voltage Bias isgnrto ouedsg fteoiia oscillator. original the of design module generation Bias PMe1 V bp2 E o I bIch NM3 INV0 INV1 NM4 PMe2 E o NM5 NM6 R2 I Schmitt bnR E E PMC0 NMe3 NMe2 PM2 hehl otg Generator Voltage Threshold NM7 PMe3 NMC0 NMC1 R0 R1 PM3 V V E thL thH 3.2 Original design of the oscillator 15

1.8 V

M0 PM1

PM0

A Y

NM0 1.8 V

NM1 M1

Figure 3.4: Schmitt trigger design of the current oscillator.

3.2.2 Comparator

The comparator in this oscillator is a component that compares two signals at the input ports and generates a logic signals accordingly at the output port. As shown in Fig. 3.5, the comparator consists of a differential amplifier, a common source amplifier and a buffer. The buffer turns the two-stage amplifier output into a logic signal driving the following inverters and the SR latch.

It should be noticed that the comparator aims to output a logic signal. Thus the gain of the first stage of the amplifier needs to be reasonable to avoid wrong operating region for the second stage NMOS. If the voltage difference at the first stage of the amplifier is not amplified larger than the threshold voltage of NM2, the second stage of the amplifier will work in sub-threshold region, which needs to be avoided in the comparator. However, a large gain in the first stage requires a large input pair, which introduces larger parasitic into the connecting node of CRamp consequently, resulting in worse speed performance. The slew rate of the amplifier is critical for the comparator design in this oscillator. 16 3 Theory

Differential Amplifier CS Amplifier Buffer 1.8 V

PM3 PM4

Ibias1 Ibias2

b- i- PM0 PM1 i+ Y

a+ NM2

NM0 NM1 NM3 NM4

Figure 3.5: Comparator design of the original oscillator.

Having PMOS input ﬁrst stage and NMOS input second stage maximizes the transconductance of the drive transistor of the second stage, which is critical when high-frequency operation is important [6]. The transconductance of the second stage can be expressed as

r W g = 2µ C I . (3.9) NM2 n ox L bias2

By choosing PMOSs as the ﬁrst stage input pair implies an NMOS will be the second stage transistor. Physically, the n-channel carrier has a larger mobility than the p-channel carrier. Hence, an n-channel input device has potentially larger conductance than a p-channel input device, resulting in larger gNM2.

The offset voltage of an opamp is composed of two components: the systematic offset and the random offset. The former results from the design of the circuit and is present even when all the matched devices in the circuit are identical. The latter results from mismatches in supposedly identical pairs of devices. The offset voltage VOS can be expressed as shown in [8] 3.2 Original design of the oscillator 17

gNM0 VOS ∆Vt(PM0,PM1) + ∆Vt(NM0,NM1) ≈ gPM0 ∆ W ∆ W Veﬀ(PM0,PM1) L NM0,NM1 L PM0,PM1 + . (3.10) 2 W − W L NM0,NM1 L PM0,PM1

In Equation (3.10), ∆Vt is the threshold mismatch, while ∆Veff is the effective voltage driving the gate. For low noise and random input offset voltage, NM0 and NM1 should have small transconductances comparing to the input PMOS pair and longer channel lengths than the PMOSs [8].

3.2.3 Trimming control

The oscillator output frequency can be controlled by the current Ibias as shown in Fig. 3.2, which charges and discharges the capacitor. The frequency will change according to the changes of the bias current amount. The operating parts of this current mirror array are controlled by a series of switches, which are controlled by the trimming code ranged from 8 to 7 in decimal and implemented in 5-bits two’s complement. This trimming system− is to ensure that the output frequency can be located near the desired frequency when the working condition changes.

The circuit shown in Fig. 3.6 has the input signals E, E, Ib,T < 4 : 0 > and D. The output signal is Ichg. It should be noticed that the signal Ib is the bias generation module’s output signal IbIch. Enabling signal E and E are Eo and Eo from the bias generation module. The control signal D is from the output of the SR latch.

As shown in Fig. 3.6, the circuit can be divide into three parts. The start-up circuit copies the reference current and the current mirror array scales the current with factors of 2n. The logic component inverts the trimming signals T < 4 : 0 > to provide signals for both NMOS arrays and PMOS arrays. The decoupling capacitors PMC0 and NMC0 are set to stabilize the gate voltages of the duplicated current mirrors. The part on the left are controlled by two switches. Each of them pulls up or down the decoupling capacitors’ top plates voltage when the enabling signal E is low. The whole circuit begins to operate when E is high.

The current mirror array consists of NMOS arrays and PMOS arrays in series connection with switches which are controlled by the T < 4 : 0 >, E and E. Apart from the current mirrors, there is a pull-up switch forcing the output node logic high during the start-up phase. These two arrays are connected to the capacitor CRamp in Fig. 3.2 to charge and discharge it. The switches NM14 and PM16 are controlled by the Q signal of the logic module output, which is inverted by INV0.

During the Tclk_high period, PM0-PM5 are responsible for charging the ramp capacitor CRamp in Fig. 3.2. During the Tclk_low period, NM0-NM5 are responsible for discharging the ramp capacitor CRamp. In this way the feedback loop is implemented and the capacitor to be compared is charged and discharged periodically. 18 3 Theory E E E E NMe0 PMe0 1 . V 8 PM15<1:0> PM7<1:0> tr-pCircuit Start-up I b NMC0 PMC0 iue3.6: Figure NM6<1:0> NM13<1:0> PM14<1:0> PM6<1:0> rmigmdl eino h rgnloscillator. original the of design module Trimming NM5<9:0> NM12<9:0> PM13<9:0> PM5<9:0> Logic T2 T2 < < T 4 4 T2 < > > 0 : 4 < 0 : 4 > NM4<15:0> NM1<15:0> PM12<15:0> PM4<15:0> > INV2<4:0> T2 T2 < < 3 3 > > INV1<4:0> urn irrArray Mirror Current NM3<7:0> NM10<7:0> PM11<7:0> PM3<7:0> T2 T2 T2 < < < 2 2 0 : 4 > > > NM2<3:0> NM9<3:0> PM10<3:0> PM2<3:0> T2 T2 < < D 1 1 > > NM1<1:0> NM8<1:0> PM9<1:0> PM1<1:0> INV0 T2 T2 < < 0 0 > > NM0 NM7 NM14 PM16 PM8 PM0 PMe1 I E chg 3.2 Original design of the oscillator 19

3.2.4 SR latch

The traditional way of causing a bistable element to change state is to overpower the feedback loop. The simplest implementation accomplishing this is the well- known SR, or set-reset, flip-flop. This circuit is similar to the cross-coupled inverter pair with NOR gates replacing the inverters. The second input of the NOR gate is connected to the trigger inputs (S and R) that make it possible to force the output Q and Q to a given state. These outputs are complimentary (except for the SR = 11 state). When both S and R are 0, the flip-flop is in a quiescent state and both outputs retain their values. (A NOR gate with one of its inputs being 0 looks like an inverter, and the structure looks like a cross-coupled inverter.) If a positive (or 1) pulse is applied to the S input, the Q output is forced into the 1 state (with Q going to 0) and vice versa: A 1-pulse on R resets the flip-flop, and the Q output goes to 0 [9].

As shown in Fig. 3.7, The design has two extra gates in order to achieve control of the SR latch as well as avoid unsettled logic signal during disable period. The unsettled logic signal will force the gates to consume constant power deciding the logic level. The output signal of the OR gate is the set signal to the latch, and the output signal of the AND gate is the reset signal. The truth table is shown below in Tab. 3.1. When the enabling signal E is logic high, the latch works as it is described. When E is logic low, the latch stays at the set state.

OR0 HitLow S NOR0 E Q

E Q HitHigh R NOR1 AND0

Figure 3.7: SR latch design of the oscillators.

In this oscillator design, we take the Q output as the switches control signal for the trimming control module. Due to the start up voltage of the capacitor CRamp is logic high, hence NM0-NM5 in Fig. 3.6 need to be connected ﬁrst to start the feedback loop. Or else the whole system can not be triggered. This requires the inputs to the SR latch should be SR = 01 when Vrc is logic high. The design meets the start-up requirement as shown in the second row of Tab. 3.1. 20 3 Theory

Table 3.1: Truth table of the SR latch of this design.

E HitLow HitHigh S R Q Q 1 0 0 0 0 latch latch 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 0 any any 1 0 1 0

3.3 Current mode oscillator

The proposed design is based on [5]. The key components will be illustrated in the following sections. The proposed current mode oscillator consists of a current generator, current mode comparators and SR latch. The SR latch is elaborated in Section 3.2.4. Hence theories of the bias current generator and the current mode comparators will be presented.

The current mode comparator can also be called current comparison circuit, which explains its function by words. However, it will be called current mode comparator in this thesis.

3.3.1 Block diagram

As shown in Fig. 3.8, the proposed current mode oscillator has an external reference current input and square wave clock signal outputs, which can be either 80 MHz or 40 MHz.

Ibias1 Ibias2 Q Bias current VC Id1 IRef generator Voltage to Q Integrator Current mode (BCG) current Output with reset comparator Latch F converter logic out Q (INT) (CMC) (VCC) I VC d2 Q

Figure 3.8: The block diagram of the current mode oscillator.

The oscillator consists of bias current generator (BCG), integrator with reset (INT), voltage to current converter (VCC), current mode comparator (CMC) and output logic. The BCG generates bias currents IBias1 and IBias2 are sent to the INT and CMC modules. INT generates ramp voltages VC and VCN. The ramp voltages are then transferred to VCC and converted to currents ID1 and ID2. When the converted current reaches IBias2, the latch toggles the internal logic and generates a clock pulse. Finally the clock pulses are reshaped by the SR latch. A DFF is included in the output logic to divide the output frequency by a factor of two. 3.3 Current mode oscillator 21

3.3.2 Circuit schematic

The conﬁguration of the proposed oscillator is shown in Fig. 3.9. The trimming signals are used to control the current ﬂow in the BCG module. They are marked with arrows cross the MOSFETs. For simplicity, the current mirror delivering the external reference to the regulated cascode current mirror’s input and bias is omitted. This omitted current mirror is implemented with a simple current mirror.

3.3.3 Cascode current mirror

As shown in Fig. 3.10 is the cascode current mirror which delivers the reference current with specified ratio to the current mode comparators. The circuit has IRef as the input signal and Vb as the output signal. A trimming system is introduced to this current mirror. The trimming system comes into effect by controlling the current flow of PM0, achieving a tuning range of 12 times to 27 times of the input reference current. The trimming signal is implemented by 4-bits two’s complement code, corresponding to a range of 8 to 7. − The bias current IBias is equal to the reference current IRef to minimize the systematic error of the current gain [10]. NM0 is controlled by two switches NMe0 and NMe1. NMe0 is in charge of connecting the NM0 gate to the drain node, forcing NM0 into saturation region. NMe1 drags the gate of NM0 to ground when the E signal is logic low, forcing NM0 into cut-off region. NM11 to NM15 are used to make sure the drain nodes’ voltages of NM1 to NM5 are the same as the drain node’s voltage of NM0.

This circuit shows an increased output impedance in comparison to the simple current mirror or opamp, however, the usable output-voltage swing becomes nar- rower. By choosing optimum bias condition, this restriction can be somewhat relaxed [11]. The implemented structure is called a regulated cascode (RGC) current mirror.

Regulated cascode current mirror

To simplify the connection of Fig. 3.10, we can ignore the controlling switches and different ratios of devices. By rearranging the circuit, we can have the regulated cascode current mirror as shown in Fig. 3.11. The bias current is set to be equal to the input current IIn avoid gain error. NM2 and NM3 form a feedback loop which stabilize the drain node of NM1. This structure allows a very high gain without compromising the overall bandwidth [12]. To mitigate the effect of channel length modulation of NM1, its drain-source voltage has been fixed (Vds1 constant) by using a feedback loop consisting of an auxiliary amplifier (NM2 and bias current source) and NM3 as source follower [13]. The feedback mechanism upon which the stabilization is based works even if NM3 is driven into ohmic operating region, which extends the usable range for the output signal [11]. 22 3 Theory T<3:0> V V I DD I bias SS Ref BCG iue3.9: Figure h ofiuaino h rpsdcretmd oscillator. mode current proposed the of configuration The INT0 VCC0 CMC0 Q Latch CMC1 VCC1 Q INT1 Q Q Output logic F out 3.3 Current mode oscillator 23 Bias I NM15 NM14<1:0> NM13<3:0> NM12<7:0> NM11<11:0> NMe5 NM5 NM10 > 0 < T NMe4<1:0> NM4<1:0> > 1 < NM9<1:0> T NM3<3:0> NMe3<3:0> Cascode current mirror design of the oscillator. > 2 < NM8<3:0> T NMe2<7:0> NM2<7:0> Figure 3.10: > 3 < NM7<7:0> T PM0 NM1<11:0> PMe0 NMe0 NMe1 8 V . 1 NM6<11:0> b V E E E Ref I NM0 24 3 Theory

1.8 V

Iout

Ibias

NM3

NM2

Iin

NM0 NM1

Figure 3.11: Simpliﬁed model of the cascode current mirror design of the oscillator.

When we assume that the gate-source voltage of NM1 is constant, Vds1 needs to equal to Vgs1 Vth1 to maximize the voltage swing of the output. When NM2 is in strong inversion,− we can acquire

V = V V = V (3.11) ds1 gs1 − th1 gs2

Vgs2 = Vgt2 + Vth2 (3.12) r 2Ibias Vds1 = + Vth2. (3.13) β2

In the equations, β2 is the transconductance coeﬃcient of NM2. Vgt2 is the eﬀec- tive voltage applying to the MOSFET gate control and calculation of the transistor’s drain-source current.

As shown in Equations (3.11) and (3.12), input voltage Vgs1 of NM1 has to be two Vth higher (if we assume NM1 and NM2 of same sizes) to achieve a possible solution of the equation for Ibias and β2. This limitation needs to be kept for better performance such as temperature-independent operating point [14] or low 1/f noise of the transistors. When NM2 is in weak inversion while NM1 and NM3 are in strong inversions, the equations need to be redrawn due to lower limitation of Vgs2. A current ﬂowing 3.3 Current mode oscillator 25 through a weak inversion transistor has the equation as shown in [15]

VGS I = I e ζVT . (3.14) D 0 ×

Then Equation (3.11) can be redrawn

Ibias Vds1 = Vgs1 Vth1 = Vgs2 = ζVth2 ln( ). (3.15) − × I0

This condition can be fulﬁlled with any Vgs1 larger than Vth if the devices are of the same size.

Output swing limitation of the regulated cascode current mirror structure is that Vds1 has to be no lower than one threshold voltage to maintain the feedback of the MOSFETs. Hence the lower bound for the output voltage is

Vout,min = Vth2 + Vdsat3. (3.16)

In the equation, Vth2 is referred to the threshold voltage of NM2 and Vdsat3 is referred to the drain-source voltage of NM3 when it is in saturation region.

This structure is not fully supply independent due to the slight change in Vgs2. This change occurs because of the variation in the drain current of NM2.

3.3.4 Current mode comparator

As shown in Fig. 3.12 is the current mode comparator. Current mirror is replaced by the ideal current source for simplicity. As stated in Section 3.3, the current mode comparator is taken from [5]. The circuit has the input signals Q to control the switches NMe0 and NMe1, output signal Q to control the symmetric half circuit.

When starting with Q signal high and Q low, bias current Ibias1 charges the capacitor connected MOSFET NMC0 and Ibias2 ﬂows through the resistor R0. With the charge in NMC0 rising, the gate-source voltage Vgs1 of NM0 increases. Hence the current ﬂows through NM0 partially. When the drain-source current Id of NM0 is equal to the bias current Ibias2, the output signal Q switches state and the input signal from the other symmetric half also switches. 26 3 Theory

1.8 V

Ibias1 Ibias2 Q

NM0

NMe1 Q

Q NMe0 R0

NMC0

Figure 3.12: Current mode comparator design of the proposed oscillator.

The timing diagram of one clock cycle is shown in Fig. 3.13.

Q Q

Vgs0

Ibias2

Id0

T/2 t Figure 3.13: Current comparison circuit’s timing diagram.

The operation mentioned above is performed in half clock cycle. During the ﬁrst 3.4 Temperature coeﬃcient 27

half clock cycle, NMC0 is charged by the bias current Ibias1. Hence Vgs0 can be expressed as a function of Tcycle,CNMC0 and Ibias1

Tcycle Ibias1 Q = × , (3.17) 2 Q Vgs0 = , (3.18) CNMC0

Ibias1 Tcycle Vgs0 = × . (3.19) 2CNMC0 By rearranging the equation we can express the output frequency as

1 I f = = bias1 . (3.20) clk T 2V C cycle gs0 × NMC0 This indicates the main sources of the frequency variations. Hence these components require attentions during the layout to minimize the PVT eﬀects on devices.

3.4 Temperature coefﬁcient

The implementations of the resistors in all the designs are p+ polysilicon resistors. A total resistance R can be expressed as shown in [16]

L W R = R + R + R + R 0 . (3.21) C silicide bulk × W interface × W

In Equation (3.21), RC and Rsilicide are the effective contact and silicide resistance, L and W are the length and width of polysilicon resistors, respectively. W0 is a normalization constant (e.g. = 1 µm) to guarantee the right dimensions of the full + equation. As illustrated in [17], in a p polysilicon application, the Rbulk and the Rinterface decreases with the increase of temperature. Detailed affecting factors to the different resistor consisting components are illustrated in [18]. The TCR is dominated by the TCR values of Rbulk and Rinterface, and the total TCR can be expressed as

1 dR TCR = R dT 1 1 ∂R ∂Rinterf ace [( bulk L) + ( W )]. (3.22) ≈ W × R × ∂T × ∂T × 0

+ Clearly, TCR is maily determined by Rbulk and Rinterface of the p polysilicon resistor. 28 3 Theory

3.5 Noise

An ideal oscillator produces a perfectly-periodic output. In reality, however, the noise of the oscillator devices randomly perturbs the zero crossings. A small random phase quantity φn(t) can be used to describe the deviations to the ideal zero crossings. The term φn(t) is called the "phase noise" [19].

Since the phase noise falls at frequencies farther from fclk, it must be specified at a certain "frequency offset," i.e., a certain difference with respect to fclk. A 1-Hz bandwidth of the spectrum at an offset of ∆f is considered, measure the power in this bandwidth, and normalize the result to the "carrier power." The carrier power can be viewed as the peak of the spectrum or as the power of A2/2. ’A’ in the expression is the amplitude of the clock signal [19].

3.6 Conclusion

This chapter described the given oscillator and the proposed oscillator in detail. Some concerns regarding the oscillator stability are explained in order to better understand the simulation results later in Chapter 5. As stated in Section 2.4, the main focus of this thesis is reducing the frequency standard deviation across PVT corners to less than 6 MHz. As stated in [20], comparators in the oscillator contribute to the frequency standard deviation of oscillators. Hence a simple structure of a comparator is pre- ferred. The proposed current mode oscillator uses single MOSFET to function as a comparator. The compared signal is current instead of voltage, which helps to improve the stability of the oscillator. As shown in [5], a current mode oscillator can achieve low frequency standard deviation across PVT corners. 4 Method

The implementations of the designs use 0.18 µm technology. The original oscillator and the improved version are implemented in schematic level. The proposed current mode oscillator is implemented in both schematic and layout. The simulation results of diﬀerent implementations are shown respectively in Chapter 5. During the simulation, the performances of the bias generation module and comparators in the original design limits the possibilities to further improve the original oscillator. Hence a current mode oscillator is proposed and implemented.

4.1 Testbench

The following contents in this chapter involve the implementation and simulation of diﬀerent oscillators. All the oscillators use the same testbench. The noise simulation in chapter 5 picks the high frequency output to analyze the phase noise. The connection of the testbench is shown in Fig. 4.1. The supply source is an ideal DC voltage source and the enabling signal is implemented with DC source as well. The enabling signal generator has a delay time in the DC source setting to simulate the logic low disabling period of the circuit. The reference current is taken from a Verilog-A model which is a bandgap current generator producing 1 µA current. Variations for diﬀerent process corners, temperatures and supply voltages are modeled inside the module. The oscillator has a trimming code generator taken from the Cadence built in library igwLib. The code generator can support up to 8 bits output. However, in these applications a maximum 5 bits are taken as the inputs of the oscillator. The trimming range for both the voltage mode oscillator and the current mode

29 30 4 Method

VDD VSS

Iin iBias Model

CK80 (fclk) Trim CK40

VDD

+ − E

Freq80 Freq40 + CK80, CK40 , − Time to Freq

VDD

+ − Trimming Code Trim

VSS

Figure 4.1: The testbench of the oscillator. oscillator is from 8 to 7, converted to 5 bits or 4 bits two’s complement code respectively. −

At the output stage, a frequency detector from library igwLib is used to determine the frequency of the output waveform. The frequency detector is also used to determine the frequency settling time.

4.2 Original oscillator

The original oscillator has a 10 ns disabling pulse to setup. The bias module and logic module are directly controlled by the outer enabling signal. The logic module is controlled by the outer enabling signal for the reason of canceling oﬀ state current consumption. Middle state signal levels will force the logic components to work constantly, wasting power during the circuit oﬀ period. 4.2 Original oscillator 31

The original oscillator is simulated in schematic level and the simulation results are shown in Chapter 2. All the speciﬁcations for the proposed design are decided based on the original oscillator schematic simulation results. Hence the original oscillator’s post layout simulation will not be carried out.

The oscillator is stimulated to start working when the delayed enabling signal Eo is generated from the bias module. Due to the decaps in diﬀerent modules, different components need to be charged up to start working. Thus the oscillation settles at 2.14 µs, as shown in Fig. 4.2. The Vrc voltage driven by the trimming controlled current mirror starts to oscillate after a long period of capacitor charging.

2 Vrc

1.5 E

1 Voltage [V]

0.5

0 0.51 1.52 2.5 Time [µs]

Figure 4.2: Delayed enabling signal triggers the oscillation.

As shown in Tab. 2.2, the oscillator has a deviation of 11.3 MHz at output frequency 85.7 MHz. The output clock signal will not be used directly. It will be divided by 8 instead to lower the transition time as well as the frequency standard deviation. Hence the requirement on frequency deviation is not that strict at high frequency output. Noise is not a concern in this application for the reason that the samples will only be taken when they are settled. Jitters will not aﬀect the performance. However, noise simulations are included in the later sections as references. Some issues appeared during the simulation and will be discussed in the follow- 32 4 Method

ing sections. These issues are around the capacitor CRamp, involving comparator’s speed and current mirror transistors’ working regions. 4.2.1 Start-up phenomenon One of the problems lies on the capacitor voltage during the oscillation stage. As shown in Fig. 4.3, sharp ramps occur in both the charging and the discharging phases.

Vrc 1

0.8

0.6

Voltage [V] 0.4

0.2

0 2.47 2.475 2.48 2.485 Time [µs]

Figure 4.3: Capacitor voltage in oscillation.

This is due to the start-up phenomenon of the trimming control module. As shown in Fig. 3.3, drain nodes of NM6-NM0 and PM5-PM0 will be the same as their source nodes when switches NM14 or PM16 is in off state. NM14 and PM16 are controlled by the inverted Q signal from the SR latch. One of them will be turned off while the other be turned on. During the off state of the switches, all the connected nodes to the source nodes of these switches are floating. Inevitably, the MOSFETs have to reestablish the correct working region to function as current mirrors after the switches turning on. This phenomenon can be partially resolved by reducing the sizes of the two switches. Smaller switches have less capabilities to handle the current flows, hence the start-up phenomenon can be reduced. However, smaller switches can not root out the start-up phenomenon. The solution is provided in Section 4.3. 4.3 Improved oscillator 33

4.2.2 Time delay Limited by the comparator’s slew rate in different stages, the comparator can not react to the crossing points of Vrc and threshold voltage as fast as in ideal scenario. As shown in Fig. 4.4b, an approximately 1 ns difference between the crossing point and the output of the comparator exists. All the names in the legend correspond to the nodes in Fig. 3.5. This is the reason for the deviation of the triggering point. The variation of comparator’s delay time results in frequency variation with voltage and temperature [20]. It is also showed in the figure that the rising phase of the b- node affects the pulse width going into the SR latch. The variation of the delay time in the comparator combines with the sharp ramp in the capacitor voltage Vrc worsen the frequency standard deviation, resulting in a noisy and unpredictable oscillator.

4.3 Improved oscillator

The improved oscillator focuses on the issues mentioned above. For solving the sharp ramps, a duplicate of the current mirrors inside the trimming module is implemented. The logical path of the circuit is simplified to decrease the components usage, which could lead to uncontrolled PVT variations. As shown in Fig. 4.5, the improved oscillator has two additional current mirrors to keep the MOSFETs staying in the correct working region. The comparator’s inputs are swapped to achieve a simpler connection between different modules of the oscillator. Current supplies to the comparators are increased in order to achieve faster response. The current mirror ratio in the second stage is increased from one to four. The input pair of the comparator is reduced in sizes to achieve faster response as well. The connections of the comparators are modified to simplify the signal path. This leads to slow responses of the comparators, since the rising and falling edges are flipped at original crossing points. Hence a modification to the capacitor value, which is determined by the gate area of the capacitor connected MOSFET, needs to be taken. The capacitor value reduction is combined with the threshold voltage divider modifications. As shown in Fig. 3.3, R0 is increased while R1 is decreased. The MOS capacitor size decreases to adjust the output frequency as well. The control switches of the four current mirrors are controlled by CLK. Both S0 and S2 are implemented by PMOSs while S1 and S3 are implemented by NMOSs. During the S0 off state, S3 will be on to provide a current path to maintain PM5-PM0 in Fig. 3.6 at the correct working region, and the same way applies to NMOSs. The original oscillator uses inverted CLK signal as the control signal for the current mirror switches, while the improved oscillator uses CLK directly to drive the switches of the current mirrors. This means the inverter INV0 in Fig. 3.6 can be 34 4 Method

2 a+ b- Y 1.5 i+ i-

1 Voltage [V]

0.5

2.215 2.22 2.225 2.23 2.235 Time [µs]

(a) Full-cycle’s oscillation.

2 a+ b- Y 1.5 i+ i-

1 Voltage [V]

0.5

2.221 2.222 2.223 2.224 2.225 2.226 2.227 Time [µs]

(b) Zoomed in view.

Figure 4.4: Comparator internal signals for upper threshold comparison in oscillation. 4.3 Improved oscillator 35 skipped. The switches NM14 and PM16 can be directly connected to the SR latch output CLK.

1.8 V

I I CMP0 bias bias VthH −

+ HitHigh S3 S0 ICharge R Q CLK Vrc

S Q CLK S1 S2 CRamp HitLow − IDischarge V + thL CMP1

Ibias Ibias

Figure 4.5: Improved design of the oscillator.

The improved design of the original oscillator is proposed due to the simulation results of an intermediate implementation. By just swapping the inputs, deleting the inverters at the output stages of the comparators and maintaining other components unchanged, the oscillator showed a nominal output frequency at 61 MHz and a frequency standard deviation of 6.8 MHz. 4.3.1 Schematic simulation As shown in Fig. 4.7, the ramp capacitor voltage is improved without any sharp ramps. Trimming control module is modified with extra current mirrors and a non-overlapping control signal generator. The non-overlapping circuit is utilized to avoid transparent window between switches S0, S1 and S2, S3. The non- overlapping signal generator is shown as Fig. 4.6. S0 and S2 are controlled by PhiP while S1 and S3 are controlled by PhiN. The time difference during the rising phase is 128 ps, and 213 ps during the falling phase. As shown in Fig. 4.7, the capacitor voltage exhibits a saw-tooth pattern waveform. This is achieved with the help of the duplicated current mirror in the trimming module. The internal signals of the comparator CMP0 are shown in Fig. 4.8. All the names in the legend correspond to the nodes in Fig. 3.5. It should be noticed that the inputs are swapped to achieve inverted output signals from the comparators. Comparing to the original comparator, the modified comparator shows worse 36 4 Method

INV0 NOR0 INV1 INV2 INV3 INV4 D PhiN

INV5 INV6 INV7 INV8 INV9

PhiP NOR1

Figure 4.6: The non-overlapping clock generator in the improved oscillator.

Vrc 1

0.8

0.6

Voltage [V] 0.4

0.2

0 2.47 2.475 2.48 2.485 Time [µs]

Figure 4.7: The ramp capacitor voltage Vrc in oscillation. 4.3 Improved oscillator 37

2 a+ b- Y 1.5 i+ i-

1 Voltage [V]

0.5

2.425 2.43 2.435 2.44 2.445 Time [µs]

Figure 4.8: Internal signals of the VthH comparator in the improved oscillator. performance in the perspective of output time delay. A simple conclusion could be drawn from the waveform that the slew rate limitation in the rising edge is the reason of the worse time delay. It is clear that the falling edge at the output of the original comparator is steeper than the rising edge of the improved comparator. In the simulation section in Section 5.2, the worsened time delay of the comparator does not worsen the frequency standard deviation. Further discussion will be presented in Section 6.5. 4.3.2 Limitations The improved oscillator exhibits a good frequency standard deviation control when the output frequency is around 60 MHz. The standard deviation is 6.8 MHz at output frequency 61 MHz. However, The frequency standard deviation will rise to 8.5 MHz when the output frequency is increased to 79.2 MHz with smaller capacitor and changed thresholds. In order to find out the theoretical performance limitation of the oscillator, the capacitor connected MOSFET CRamp is replaced by an ideal capacitor in the Ca- dence default library analoglib. The frequency standard deviation drops to 7.8 MHz, which does not meet the specification. A conclusion can be drawn that the frequency standard deviation comes from other modules in the oscillator, most prob- ably from bias generation module. This assumption is confirmed by the noise simulation later. 38 4 Method

The original and improved oscillators are based on the conventional comparator design, which are proved hard to be further improved. This kind of RC oscillator is limited by the comparator and passive components design. Based on capacitor connected MOSFET and p+ polysilicon resistor, a current mode oscillator is proposed and implemented based on the requirement on the frequency standard deviatio.

4.4 Current mode oscillator

A current mode circuit is able to operate faster than a voltage mode circuit [21], and effects of the comparator’s non-idealities can be minimized. The clock frequency changes due to the comparator’s non-idealities such as offset voltage and finite delay time. Therefore, it is difficult to obtain a stable clock frequency when we consider the effects of PVT variations [5]. Hence a current mode oscillator is proposed and implemented in order to minimize the comparators’ variations. Consequently, achieving the specification of low frequency standard deviation at high frequency output. 4.4.1 Implementation The reference current input is generated by a bandgap device, which is not included in the design. Resistors are implemented with poly-silicon and capacitors are implemented with capacitor connected MOSFETs. The capacitor value of NMC0 should consist dominantly of its own parasitic capacitors. This requires that the size of NMC0 should be large enough in comparison to NM0, as shown in Fig. 3.12. This application is designed to have an output frequency of 80 MHz, unlike its prototype in [5], which operates at 32 MHz. Hence the bias currents are modified to satisfy the specification as well as stabilization. Ibias1 :Ibias2 is set to 1 : 2. The CMC module is highly symmetric, hence the devices of this module are required to place close to each other to minimize the mismatches during the layout phase. Analog signal wires are better placed far from fast changing digital signal wires, which disrupt the analog signals during the transmission. The p+ polysilicon resistors’ values are estimated to be 135.6 kΩ with the sizes of 20 segments of 20 µm long and 1 µm wide, spacing between segments 250 nm. Size of NM0 is 2 µm width and 0.4 µm length. The size of NMC0 is 6.9 µm width and length. NMC0 is approximately 60 times larger than NM0 in area, which makes the capacitor is dominantly decided by NMC0. Switches in the CMC module for Q and Q signals are 1 µm wide and 0.5 µm long. Reset switches have sizes of 0.5 µm widths and lengths. For the bias generation module, all the NMOSs and PMOSs in the current mirrors have the sizes of 2 µm width and 2 µm length. Switches in the bias module are 1 µm wide and 1 µm long. 4.4 Current mode oscillator 39

Inverters in the design are implemented with a pair of NMOS and PMOS. The size of NMOS is 460 nm width and 180 nm length, while the size of PMOS is 985 nm width and 180 nm length. Other digital components are shown later in the layout part.

4.4.2 Schematic simulation When the oscillator works at nominal corner, the trimming code is set to 0, which means the control code to the BCG is 0000. The expected current output from the BCG is 20 µA. As shown in Fig. 4.9, the BCG module outputs a current of 20 µA when the oscillator has a stable oscillation.

-5 A] µ -10

Current [ -15

-20

-25 0123 4 Time [µs]

Figure 4.9: The current generated from the bias current generator at nominal condition.

As shown in Fig. 4.10, the gate voltages of VCC change periodically with the switches toggle on and off. This shows that the current mode comparator works as expected. The VC in the figure indicates the gate voltage of VCC1 in Fig. 3.9 and VC is corresponding to the gate voltage of VCC0. At the same time, the switches’ control signals Q and Q are shown in Fig. 4.11. They are both output signals of CMC module and internal driving signals. To maintain the oscillation stable, the switches’ sizes are of great concern. A too small switch can result in the termination of the oscillation due to the unfinished 40 4 Method

1 VC

VC 0.8

0.6

Voltage [V] 0.4

0.2

0 2 2.005 2.01 2.015 2.02 2.025 Time [µs]

Figure 4.10: The capacitor ramp voltages in oscillation state at nominal condition.

Q Q 1.5

1 Voltage [V]

0.5

0 2 2.005 2.01 2.015 2.02 2.025 Time [µs]

Figure 4.11: The output signals of the current mode comparator module in oscillation state at nominal condition. 4.4 Current mode oscillator 41 charging/discharging.

4.4.3 Layout The layout implementation has a restriction on the metal layer usage. Only two metal layer could be used in the sub-modules’ implementations. A third metal layer can only be used for power delivery purpose at the top level of the oscillator. Hence interconnections of diﬀerent components will take larger space with this restriction.

Figure 4.12: Top level of the proposed oscillator layout.

As shown in Fig. 4.12 is the layout of the proposed current mode oscillator. The bottom part is the resistors in the CMC module. The two resistors take approx- 42 4 Method imately 1/2 of the whole area. The second largest component is the BCG module, which takes an area of 1200 µm2. The oscillator takes up an overall area of 3185 µm2. The proposed oscillator’s layout consists of three components: bias current generator, current mode comparator and output logic. The BCG module is placed at the upper left corner of the layout. The CMC module locates at the bottom while the output logic stays at the upper right corner. These placements help to keep the components close to each other while leaving enough spaces for the interconnections. The surrounding substrate contact rings of the three components ensure a common substrate is shared by diﬀerent parts of the oscillator. A common substrate provides a stable ground to the oscillator. For signal guarding purpose, extra layers of substrate contacts can be added. Output logic The logic module is shown in Fig. 4.13. It consists of a modiﬁed SR latch and a DFF, which is used to dived the frequency by two. The DFF has a active low reset, which is to ensure a close-to-zero disabling period current consumption.

Figure 4.13: The logic module of the proposed oscillator layout.

The output logic module is placed on top of the CMC module. Hence the Q, Q and E signal can easily get inside the module through the right edge of the CMC module. All the basic cells consisting the logic components were done with only metal 1. Hence only the contact metal edges to the existing metal edges need to be taken care of. The power supply goes inside the module at the left part, aligned with the CMC module power supply position. The output clock signals use metal 2 to be trans- 4.4 Current mode oscillator 43 ferred out of the module. Bias current generator The BCG module is shown in Fig. 4.14. Due to the limitation of the metal layers’ usage, the PMOS used for propagating the bias voltage has to connect to the NMOSs with metal2 at the top part of the BCG module to avoid conﬂicts with the control signals.

Figure 4.14: The bias module of the proposed oscillator layout.

The NMOSs are placed three parts in a group. As shown in Fig. 3.10, NM1, NM7 and NM11 are placed close to each other to minimize the metal wire length of interconnections. The close placement of the NMOSs also saves area usage. In order to have the layout in a square shape, one set of the NMOSs are placed as 44 4 Method an L shape. Whole module is mainly divided into two half, leaving a middle gap for the Vb output to the CMC module. The switches’ control signals reach into the BCG module through the middle gap as well. The enabling signal is required by other modules of the oscillator, hence a metal 2 free path is left at the bottom part of the BCG module to reach the CMC module. The ground and gate interconnections then have to go alongside the NMOSs instead of using metal 2 to connect directly. Current mode comparator The CMC module is shown in Fig. 4.15. The circuit is designed to be symmetric, hence the placements of two halves are close to each other to minimize the mismatches. For keeping the oscillator in a square like shape, the CMC module was done in L shape with two resistors at the bottom part, away from the main block and separated by a guard ring.

Figure 4.15: The current mode comparator module of the proposed oscillator layout.

The critical nodes are the Q, Q, gate of VCC0 and gate of VCC1. They need to be symmetric to minimize devices’ mismatches. Hence the capacitors ,VCCs and 4.4 Current mode oscillator 45 their supplies are placed close to each other.

The metal wire interconnections between the resistors and the rest part of the CMC have a limited resistance value. However, the resistance in the interconnections are much smaller than the resistors themselves. Thus this placement of the resistors will not aﬀect the performance much.

The Vb input port is designed to be at the top part of the CMC module. The propagation to diﬀerent PMOSs’ gate are done by placing them side by side, in order to connect the gates to one node.

The enabling signal coming from the BCG module crosses the middle gap between the MOSFETs and the resistors to reach into the CMC module. This is done by metal 2 mainly, though altering to metal 1 to avoid conﬂict with the power rail.

4.4.4 Post-layout simulation

The simulation results of the layout showed a 20 µA current output from the BCG in an oscillation state. The capacitor connected MOSFETs ramp voltages and Q signals are shown in Fig. 4.16.

VC V 1.5 C Q

1 Voltage [V]

0.5

0 2 2.005 2.01 2.015 2.02 2.025 Time [µs]

Figure 4.16: Ramp voltages of the capacitors and output signals of the current mode comparator. 46 4 Method

The waveform indicates the layout of the proposed current mode oscillator can work as expected. The capacitors’ voltages VC and VC are charged and discharged periodically. 5 Result

This chapter consists of noise simulation results of different oscillator, frequency standard deviations and VT dependeces. A comparison between different oscillators’ implementations is made. Further discussions are made in Chapter 6. This chapter first shows the nominal output frequencies and current consumptions of different implementations. Then proceeding to VT dependences and frequency standard deviation with MC simulations. Thirdly, a comparison between the noise simulations are included for readers who are interested in those performance parameters. Finally, a table of comparisons between different implementations in different performance parameters is shown. Practical issues regarding the given application are also shown. Apart from the key performances of the oscillators, some practical issues are also of interests to be recorded. The extraction variations and the VT variations are the two main parts. Different extractions of the layout exhibit a bit different output frequencies. They should be confirmed to have a relationship of fcworst < ftypical < fcbest. Or else further investigations need to be made. The simulations performed at nominal corner have the following settings: • Supply voltage: 1.8 V,

• Room temperature: 25 ◦C, • Process corner: typical. The current consumption measurement is described in Section 2.1, performed with transient simulation. An average value at the ending part of the simulation is acuired for the oscillator current consumption.

47 48 5 Result

5.1 Frequency output

The output frequency of the original oscillator and its settling time are 85.68 MHz and 2.14 µs, as shown in Fig. 5.1a and Fig. 5.1b. The simulation is terminated by an external timer to save simulation time and computing resources. The improved oscillator has the output frequency and settling time shown in Fig. 5.2a and Fig. 5.2b. Since the output frequency will be divided by 8 when it is applying to the rest part of the circuit, a range of 75 85 MHz is acceptable. −

100 CK80 Freq80 2 80

1.5 60

1 40 Voltage [V]

0.5 Frequency [MHz] 20

0 0

2.4 2.42 2.44 2.46 2.48 0 0.51 1.52 2.5 Time [µs] Time [µs] (a) The logic module output. (b) The frequency settling.

Figure 5.1: The original oscillator’s output waveform and frequency settling time.

100 CK80 Freq80 2 80

1.5 60

1 40 Voltage [V]

0.5 Frequency [MHz] 20

0 0

2.4 2.42 2.44 2.46 2.48 0 0.51 1.52 2.5 Time [µs] Time [µs] (a) The logic module output. (b) The frequency settling.

Figure 5.2: The improved oscillator’s output waveform and frequency settling time.

As shown in Tab. 5.1, the simulation results of the original oscillator and the improved oscillator are included in the table. It should be noticed that the simulation results are collected from nominal corner simulations. 5.1 Frequency output 49

The proposed current mode oscillator is implemented both in schematic and layout, hence the comparison between an ideal behaviour model and a parasitic included model is of interest. The frequency output and settling time of schematic and layout are shown in Fig. 5.3a, Fig. 5.3b, Fig. 5.4a and Fig. 5.4b. In the following table Tab. 5.2, a comparison of key speciﬁcations is shown. The simulations are in nominal corner, the same as for Tab. 5.1.

Table 5.1: Simulation results comparison between the original oscillator and the improved oscillator.

Speciﬁcation Original Improved High frequency output (MHz) 85.63 76.47 High frequency settling (µs) 2.14 2.10 Duty cycle (%) 46.12 47.47 Current consumption (µA) 112.7 185.4 Power consumption (µW) 202.9 333.7

100 CK80 Freq80 2 80

1.5 60

1 40 Voltage [V]

0.5 Frequency [MHz] 20

0 0

2.4 2.42 2.44 2.46 2.48 0 0.51 1.52 2.5 Time [µs] Time [µs] (a) The logic module output. (b) The frequency settling.

Figure 5.3: The schematic simulation results of the proposed oscillator’s output waveform and frequency settling time. 50 5 Result

100 CK80 Freq80 2 80

1.5 60

1 40 Voltage [V]

0.5 Frequency [MHz] 20

0 0

2.4 2.42 2.44 2.46 2.48 0 0.51 1.52 2.5 Time [µs] Time [µs] (a) The logic module output. (b) The frequency settling.

Figure 5.4: The post-layout simulation results of the proposed oscillator’s output waveform and frequency settling time.

Table 5.2: Simulation results comparison between the schematic and the layout of the proposed oscillator.

Speciﬁcation Schematic Layout High frequency output (MHz) 81.64 77.63 High frequency settling (ns) 438.9 455.1 Duty cycle (%) 49.57 49.26 Current consumption (µA) 251.1 256.2 Power consumption (µW) 452.0 461.2

Different implementations of the proposed oscillator do not have great differences between the results. The drop on the output frequency is expected due to the coupled extraction of the layout. This extraction will introduce parasitic resistance and capacitance to various nodes of the circuit. Further discussion will be performed in Section 6.6. From Tab. 5.1 and Tab. 5.2, results show that the settling time of the proposed oscillator is largely decreased. At the same time, the output frequency of the proposed design stays within the range of 75 - 85 MHz. Due to the fact that the oscillators are implemented to improve the frequency standard deviation, the nominal output frequency drop shown in Tab. 5.1 is not a concern as long as it stays within the specification range. 5.1.1 Temperature dependence The temperature dependences are shown in Fig. 5.5. The temperature range is from 40 ◦C to 85 ◦C,starting from -40 ◦C to 85 ◦C, step size 5 ◦C, with a fixed 1.8 V− supply and process corner setting to typical. The temperature dependences of the oscillators show different trends with dif- 5.1 Frequency output 51

87 77

86.5 76.8

86 76.6

85.5 76.4

85 76.2

Frequency [MHz] 84.5 Frequency [MHz] 76

84 75.8

83.5 75.6 -40 -200 20 40 60 80 100 -40 -200 20 40 60 80 100 Temperature [◦C] Temperature [◦C] (a) The original oscillator. (b) The improved oscillator.

85 81

84 80

83 79

82 78

81 77 Frequency [MHz] Frequency [MHz]

80 76

79 75 -40 -200 20 40 60 80 100 -40 -200 20 40 60 80 100 Temperature [◦C] Temperature [◦C] (c) The schematic simulation of the pro- (d) The post-layout simulation of the posed oscillator. proposed oscillator.

Figure 5.5: Temperature dependences of the implemented oscillators. 52 5 Result ferent implementations. The original oscillator has a clear positive correlation to the temperature. All the proposed oscillator’s implementations show negative temperature dependeces, while the improved oscillator behaves unstable to determine a correlation to the temperature changes. The ﬂuctuation in the improved oscillator simulation result will be further discussed in Chapter 6.

5.1.2 Supply voltage dependence

The supply voltage dependences are shown in Fig. 5.6. The tested voltages are 1.62 V, 1.8 V and 1.92 V with a ﬁxed 25 ◦C temperature and process corner set to typical.

88 77.5

87 77

86 76.5 85 Frequency [MHz] Frequency [MHz] 76 84

83 75.5 1.6 1.7 1.8 1.92 1.6 1.7 1.8 1.92 Voltage [V] Voltage [V] (a) The original oscillator. (b) The improved oscillator.

83 79

82.5 78.5

82 78 81.5 Frequency [MHz] Frequency [MHz] 77.5 81

80.5 77 1.6 1.7 1.8 1.92 1.6 1.7 1.8 1.92 Voltage [V] Voltage [V] (c) The schematic simulation of the pro- (d) The post-layout simulation of the posed oscillator. proposed oscillator.

Figure 5.6: Supply voltage dependences of the implemented oscillators.

The original oscillator exhibits a positive correlation to the supply voltage, while the other three implementations are negative correlated to the supply voltages’ change. Further discussions about the supply dependence are made in Chapter 6. Diﬀerent implementations’ VT dependences are listed and compared in Section 5.4. 5.2 Frequency standard deviation 53

5.2 Frequency standard deviation

The frequency standard deviation is simulated through 100-run Monte Carlo simulation. The simulation aims to simulate the mismatches and process defects in the circuit. The MC simulation settings covered a range of expected working conditions. The VT variations are simulated through this MC test. The setting consists of 6 corners, which are the combination of 1.62 V and 1.98 V supply, 40 C, − ◦ 25 ◦C and 85 ◦C temperatures. The process corner is set to 100 which will be recognized by the MC model. The MC model will randomly generate diﬀerent process parameters for diﬀerent transistors. The worst corner of the frequency standard deviation of the original oscillator is shown in Fig. 5.7. The worst corners of the improved oscillator, the schematic simulation result of the proposed oscillator and the post-layout simulation result of the proposed oscillator are shown in Fig. 5.8, Fig. 5.9 and Fig. 5.10.

Figure 5.7: Histogram of 100 samples at 40 ◦C with 1.98 V supply of the original oscillator. − 54 5 Result

Figure 5.8: Histogram of 100 samples at 40 ◦C with 1.62 V supply of the improved oscillator. −

Figure 5.9: Histogram of 100 samples at 40 ◦C with 1.62 V supply of the schematic simulation of the proposed oscillator.− 5.2 Frequency standard deviation 55

Figure 5.10: Histogram of 100 samples at 40 ◦C with 1.62 V supply of the post-layout simulation of the proposed oscillator.−

A comparison between the four implementations is shown in Tab. 5.3. It should be noticed that the simulations are performed with trimming code set to 0, which is supposed to be the 80 MHz output of the oscillator.

Table 5.3: The comparison between diﬀerent implementations’ Monte Carlo simulation results.

Proposed oscillator Performance parameters Original Improved Schematic Layout Mean value of the fre- 86.5 76.8 82.4 78.4 quency (MHz) Standard deviation of the 11.28 8.55 5.40 4.97 frequency (MHz) Mean value of the settling 2.18 2.14 0.44 0.46 time (µs) Standard deviation of the 181.9 214.1 24.1 23.7 settling time (ns) Mean value of the duty cy- 46.32 47.82 49.96 49.14 cle (%) Standard deviation of the 1.61 1.76 0.041 0.58 duty cycle (%) Mean value of the current 114.1 185.0 249.2 254.6 consumption (µA) Standard deviation of 10.6 16.7 21.4 20.9 the current consumption (µA) 56 5 Result

From the distributions of diﬀerent implementations, more samples fall around the µfclk in the proposed oscillator than the original oscillator. In the simulation of the extracted layout of the proposed oscillator, the best standard deviation is achieved by having most of the results fall within one σ range of the MC test. It is clear that a wide spread distribution of simulation results leads to large standard deviation.

5.3 Noise simulation

Noise analysis is performed with PSS simulation. The phase noise of an oscillator is calculated based on the PSS simulation result at a range of 10 kHz 10 MHz. The spectrum of the simulated oscillator are shown in Fig. 5.11a and Fig.− 5.11b. For the convenience of the PSS simulation stability, the output logic is simpliﬁed to a single SR latch. This helps to stabilized the beat frequency guessing during the simulation.

1.4 1.4

1.2 1.2

1 1

0.8 0.8

0.6 0.6 Magnitude [V] Magnitude [V] 0.4 0.4

0.2 0.2

0 0 0 0.51 1.52 0 0.51 1.52 Frequency [GHz] Frequency [GHz] (a) The original oscillator. (b) The schematic simulation of the proposed oscillator.

Figure 5.11: The oscillators’ spectrums.

Any circuit that does not have a stable periodic steady-state cannot be analyzed by the Spectre RF simulator because oscillator noise analysis is performed by linearizing around a waveform that is assumed to be strictly periodic. Hence the oversampling factor needs to be set to 2 due to the fact that the oscillators are non-linear oscillator. Or else the beat frequency simulation can not be stabilized. From Fig. 5.11, clear square waves of the two implementations can bee seen out of the spectrums. A square wave signal in frequency domain ideally has only odd- integer harmonics. That means the oscillators have harmonics at base frequency, three times of the base frequency, ﬁve times of the base frequency, etc. However as shown in Fig. 5.11a, even-integer harmonics also exist, which reduce the power of the desired clock signal. The proposed oscillator, on the contrast, has low odd-integer harmonics, keeping the power of the desired clock signal. These phenomena are veriﬁed by the phase noise simulations. 5.3 Noise simulation 57

The phase noise simulation results are shown in Fig. 5.12a and Fig. 5.12b. The phase noise simulations are based on the PSS simulation results and performed with pnoise simulation panel. Sweep type is set to logarithmic 10 points per decade. Noise type is set to timeaverage, which is single-sided spectrum and harmonic-referred noise analysis, with contribution type USB. It should be noticed that all simulations are carried at nominal corner.

-20 -20

-40 -40

-60 -60

-80 -80

-100 -100 Phase Noise [dBc/Hz] Phase Noise [dBc/Hz]

-120 -120

-140 -140 104 105 106 107 104 105 106 107 Frequency [Hz] Frequency [Hz] (a) The original oscillator. (b) The schematic simulation of the proposed oscillator.

Figure 5.12: The oscillators’ phase noises.

Different components contribute to the phase noise with different types of noises and in different amounts. As shown in Tab. 5.4, an integrated noise is calculated with a range of 10 kHz 10 MHz. It should be noticed that all the transistor names are adjusted to be− the same as shown in Fig. 3.3 and Fig. 3.10.

Table 5.4: The noise simulation results’ comparison table.

Original Proposed NM7 / 27.38% NM0 / 28.82% Top noise contributor Flicker noise Flicker noise Noise amount of the top con- 0.41 0.063 tributor (V2) NM0 / 10.57% NM6 / 26.36% Second top noise contributor Drain-source resistance Flicker noise thermal noise Noise amount of the second top 0.40 0.023 contributor (V2) Total summarized noise (V2) 1.51 0.22

Further noise discussions are made in Chapter 6. The application of the oscillator requires nothing from the noise perspective. Hence the simulating theory and the simulation results are listed together in the results part of the report. 58 5 Result

5.4 Results comparison

A comparison is made between the implementations of the oscillator in Tab. 5.5. It should be noticed that the area measuring of the improved oscillator and the schematic of the proposed oscillator is estimated by the LayoutXL interface. They are 0.01 mm2 and 0.005 mm2 respectively, using an utilization ratio of 70% to generate the area estimation. Thus the layout of the proposed oscillator achieved smaller area consumption comparing to the estimation. The VT dependeces are evaluated by the following equation

max (fVT,max fclk), (fclk fVT,min) fVT/fclk = − − 100% (5.1) ± fclk ×

The equation gives a VT variations range comparing to the nominal output frequency in percentage.

Table 5.5: Results comparison.

Proposed oscillator [22] [5] Original Improved Schematic Layout Type Relaxation oscillator Technology (nm) 350 180 Area (mm2) 0.08 0.09 0.01 - - 0.003 VDD (V) 1.8 - 3.0 1.6 - 2.0 1.62 - 1.98 T(◦C) -20 - 100 -20 - 125 -40 - 85 fclk (MHz) 30 32.6 85.6 76.5 81.6 77.6 Start-up time (µs) 2.5 1 2.14 2.10 0.44 0.46 Power (µW) 180 300.6 202.9 333.7 452.0 461.2 FoM (µW/MHz) 3.33 9.22 2.37 4.36 5.54 5.94 f /f (%) 2.4 0.69 2.53 1.18 0.94 1.22 V clk ± ± ± ± ± ± f /f (%) 0.6 0.38 2.43 0.78 2.79 2.98 T clk ± ± ± ± ± ± σfclk /µfclk (%) 2.7 2.57 13.04 11.13 6.55 6.34 External signal No No Bandgap reference current

From Tab. 5.5, different key parameters and performances of various implementations of the relaxation oscillators are listed. The figure of merit (FoM) of the oscillator is defined as

Power Consumption FoM = . (5.2) Output Frequency

Hence the unit of FoM in this table is µW/MHz, which are the units’ combination of the output frequency and the power consumption. As shown in Tab. 5.5, the proposed oscillator provide a descent FoM performance. The low frequency standard deviation of [5] is in exchange of the power consumption per mega Hertz, 5.5 Practical issue 59 which is the highest 9.22 µW/MHz. Results of the original oscillator, improved oscillator and proposed oscillator are collected from Cadence’s simulations, while [5] and [22] are measured on manufactured chips.

5.5 Practical issue

Apart from the frequency standard deviation, settling time, duty cycle and current consumption, some other aspects of the oscillator are crucial to a mass production product.

5.5.1 Trimming range The trimming range of the implemented oscillators are shown in Fig. 5.13. The simulations are performed at nominal corner with a trimming code from 8 to 7 in decimal. The trimming codes are converted to two’s complement code− and then connected to the oscillator.

110 90

85 100

80 90 75 80 70 Frequency [MHz] Frequency [MHz]

70 65

60 60 -8 -6 -4 -202 4 6 -8 -6 -4 -202 4 6 Trim Code Trim Code (a) The original oscillator. (b) The improved oscillator.

110 100

100 90

90 80 80 70 70 Frequency [MHz] Frequency [MHz]

60 60

50 50 -8 -6 -4 -202 4 6 -8 -6 -4 -202 4 6 Trim Code Trim Code (c) The schematic simulation of the pro- (d) The post-layout simulation of the posed oscillator. proposed oscillator.

Figure 5.13: Trimming range of the implemented oscillators. 60 5 Result

As shown in Fig. 5.13a, the trimmed output signal has a smooth line on the frequency performance, showing a step size approximately 3 MHz per trimming step. The post-post-layout simulation shows a straight line as well. However, deviated points exists on the frequency behaviour line, meaning small diﬀerences on diﬀerent trimming codes exist. The step size of the proposed oscillator post- post-layout simulation is approximately 2.5 MHz. 5.5.2 VT variation The VT variation tests are done at nominal corner with a combination of two temperatures and two supply voltages, 40 ◦C, 85 ◦C, 1.62 V and 1.98 V. The process corner is set to typical for this test.− A comparison between the simulation results is shown in Tab. 5.6.

90 77.5

88 77

86 76.5

84 76 Frequency [MHz] Frequency [MHz]

82 75.5

80 75 -40 -200 20 40 60 80 -40 -200 20 40 60 80 Temperature [◦C] Temperature [◦C] (a) The original oscillator. (b) The improved oscillator.

85 81

84 80

83 79

82 78

81 77 Frequency [MHz] Frequency [MHz] 80 76

79 75

78 74 -40 -200 20 40 60 80 -40 -200 20 40 60 80 Temperature [◦C] Temperature [◦C] (c) The schematic simulation of the pro- (d) The post-layout simulation of the posed oscillator. proposed oscillator.

Figure 5.14: VT variations of the implemented oscillators.

The VT variations are tested with extreme working conditions in order to reduce the simulation time. Theoretically, the four extreme combinations of the supply voltages and the temperatures provide a reference variation range around a given trimming code. Hence the VT variation tests are of interest. Further discussions will be made in Chapter 6. 5.5 Practical issue 61

Table 5.6: VT variations caparison.

Implementations Max. variation (MHz) Original 7.05 Improved 1.58 Proposed schematic 6.43 Proposed layout 6.37

5.5.3 Extraction variation A comparison between the diﬀerent extractions of the nominal corner is shown in Fig. 5.15. The simulations are performed with three layout extractions, cbest, cworst and typical extraction.

77.9

cbest 77.8

77.7 typical

77.6 Frequency [MHz]

77.5 cworst

77.4

Figure 5.15: The output frequencies for diﬀerent extractions of the nominal corner.

The extraction is done as the RC coupled extraction, with reference node set to VSS. The temperature is set to 25 ◦C. RC filters in the extraction setup are MinR=0.001, MinC=0.01 fF 0.1%. The extraction scenarios cbest, cworst and typical are predefined extraction options. Choosing the RC coupled extraction aims to simulate as many parasitic effects as possible inside the oscillator. The coupled option will auto create the parasitic 62 5 Result resistors and capacitors between different layers. Unlike decoupled extraction, which only create the parasitic between different layers and ground. In the decoupled extraction, cross-talk problems caused by coupling parasitic caps cannot be detected. The differences between different extractions are ignored considering the output frequencies are approximately 400 times the difference. Hence all post-layout simulations are performed with the typical extraction of the layout. 6 Discussion

This chapter consis ts of discussions related to the methods and results of the implemented oscillator. Design considerations and brief conclusions are parts of the chapter as well. Issues occurred during the project work will be mentioned as reminders when a reproduction of the work is needed.

6.1 Method

This project consists of several stages. The given oscillator was analyzed first to understand basic principles of a relaxation oscillator. The trimming system, as the special component of the given oscillator, needed to be kept in the proposed design in order to cooperate with the existing application. Improvements based on the given oscillator were then done. Failing to achieve the frequency standard deviation specification, the improved version of the given oscillator was discarded. While trying to simplify the comparator structure and targeting low frequency standard deviation, a reference using current mode oscillator with low frequency standard deviation was found on IEEE library. Hence the proposed oscillator followed the current mode oscillator design to fulfill the frequency standard deviation specification. Post-layout simulations proved that the proposed oscillator based on [5] improved output frequency standard deviation, but not as promising as the reference. This is due to the output frequency difference between this project and the reference. At last, the proposed current mode oscillator managed to achieve most of the specifications, with a bit higher current consumption.

63 64 6 Discussion

The proposed current mode oscillator has small area consumption while main- tains stable output frequency across all PVT corners. The simulations of the proposed oscillator are based on the typical scenario coupled RC extraction with accuracy of MinR=0.001, MinC=0.01 fF 0.1%. The post-layout simulation results based on this extraction are the most accurate performance parameters one can acquire before the design is actually manufactured. The MC simulations can have more points per run to acquire higher accuracy in the output frequency distributions. However, the original designer of the given oscillator claims that 100-points MC simulations are good enough to simulate the oscillator output frequency spreading. Hence I followed the initial setup of the MC simulations. Later on, a 100-points MC simulation with 6 points to be covered takes half a day to ﬁnish the simulation, proving itself to be a time consuming simulation. The 100-points simulation is a trade oﬀ between simulation time and accuracy.

6.2 Noise

Although the noise performance is not of concern in this application, making sure the sources of the noises is helpful for later work. For conventional oscillators, the main noise sources are current sources and comparators. Although there are oscillators with first order lag oscillation, comparators still remain as a significant noise source. The only way to reduce their noise is to apply huge power (for thermal noise) and large size (for flicker noise) to comparators; however, huge power does not match with low-power applications and large size of gates increases the ratio of gate parasitic capacitors including Cox which is sensitive to voltage and temperature. Of course, large parasitic capacitors of comparators result in more power dissipation of oscillation [20]. The proposed current mode oscillator improves the noise performance comparing to the original oscillator. As shown in Tab. 5.4, the top two noise contributors changes from two input NMOSs flicker noises to one input NMOS flicker noise and its drain-source resistance thermal noise. The noise amount of proposed oscillator integrated within a range of 10 kHz - 10 MHz decreases 85% of the original amount.

6.3 Trimming system

The oscillator uses a trimming system to ensure that PVT variations can be compensated. A look-up table (LUT) is created to record the trimming codes for different process corners. These codes are recorded at nominal corner. Unlike [5], the trimming system controls the current instead of capacitors or resistors. Hence the comparison to [5] does not use the after trimming result. Different oscillators are tested with fixed trimming code zero for the reason of ensuring the oscillator output frequencies to be at 80 MHz. A trimming code zero 6.4 External reference 65 is located at the middle point of the trimming range. By forcing the oscillators to output frequency at 80 MHz, the trimming range can cover the frequency spread shown in MC simulations.

It is due to this trimming system that the improvements to the oscillator focus on the standard deviation. Because the process variations have been compensated by using LUT to optimize the trimming code using. This is also the reason for the MC settings cover the VT variations and process defects are simulated by MC model instead of introducing all process corners into MC simulations.

6.3.1 Trimming step

Step size of the trimming range is determined by the VT variations of the oscillator in nominal process corner. The trimming step must be no larger than the VT scattering range around certain process corner, or else the trimming system can not fulﬁll its duty to adjust the output frequency accordingly.

As shown in Section 5.5.1, a similar trimming step size is achieved due to the similarities of the trimming systems adopted in the implementations. Current changes for one LSB diﬀerence are similar in the proposed oscillator and the original structure. For the VT variations, the proposed oscillator has smaller VT variation comparing to the original oscillator. This is veriﬁed by the smaller value of fV and fT of the proposed oscillator.

6.4 External reference

To ensure the oscillator can be integrated to the existing system, an external reference current is kept. This external reference current generator is modeled as a Verilog-A component. When counting the settling time of the output frequency, the start-up time of the external reference does not count in. This is the reason why the oscillator designs have no start-up component for the BCG module.

6.5 Sizing

Size diﬀerences between the MOS capacitor and surrounding transistors is crucial to the oscillator dessign. Since the capacitors are implemented by MOS capacitors in these designs, the capacitor MOSFETs sizes need to be large enough to avoid the parasitic eﬀects from the connected transistors.

A larger transistor has better stability over VT variations. On the other hand, the current consumption, response speed and parasitic become worse as a trade oﬀ. Hence a balance between diﬀerent requirements needs to be achieved. 66 6 Discussion

6.6 Improved performance of the improved oscillator

The frequency standard deviation of the improved oscillator decreased approximately 3 MHz as shown in Tab. 5.3. Since the MC test contains VT variations and process mismatches, the results indicate that the original comparators are more aﬀected by the VT variations than the improved ones.

As illustrated in Section 4.2, start-up phenomenon is the main cause for the high frequency standard deviation of the original oscillator. Extra simulation shows that with modiﬁed trimming control module and original comparators’ connections, a frequency standard deviation of 7.75 MHz can be achieved. Which is better than the improved oscillator’s 8.55 MHz frequency standard deviation.

More improvements can be made to the original bias generation module to limit the current mirror eﬀects to the oscillator. The time limit prohibits further inves- tigation to the original oscillator.

6.7 Improved performance of post-layout simulation

After the MC simulation of extracted layout, results show a better outcome than the schematic one. This can be concluded to the lower output frequency of the extracted view of the proposed oscillator. The introduction of the coupled parasitic components lower the output frequency. Consequently, the standard deviation is reduced by the coupled extraction. The nominal corner output frequency of the post layout simulation drops 4 MHz and standard deviation reduces 0.5 MHz with the MC test. This reduction of the standard deviation is hence expected.

6.8 VT dependence

The capacitor is implemented by connecting the drain, source and bulk of a MOS- FET together as bottom plate of the capacitor, leaving the gate as the top plate. A capacitor connected this way has a voltage dependence. The capacitor’s value increases when the supply increases. Theoretically, the oscillators will have slower charging while in higher supply voltage. However, the start up phenomenon in the original oscillator cancels this eﬀect by a sharp ramp in the beginning of the charging phase. This is achieved by the sacriﬁce of the duty cycle.

The resistors are placed as described in Section 3.2.1 and 3.3.2. Thanks to the large sizes of the voltage divider in the original oscillator, the temperature eﬀect is minimized. The R2 resistor in Fig. 3.3 compensates the temperature variation by making the drain node of NMe2 a temperature varying node. Which results in the drain node of PM3 becoming temperature varying as well. Similar sizes of R2 and R1 ensure the varying resistances will not aﬀect the threshold voltages. As shown in Fig. 3.3, VthL can be expressed as a function of R0, R1 and VthH 6.9 Simulator issue 67

R0 V = V . (6.1) thL R0 + R1 × thH Hence a positive correlation appears between the output frequency and the temperature. It is clear that changes on the voltage divider in the bias module will break this balanced resistor performance. Therefore, the improved oscillator shows ﬂuctuation in the temperature dependence waveform. However, resistor in the proposed current mode oscillator is in charge of the Q signal voltage level. A negative temperature coeﬃcient results in lower gate voltages to the symmetric half. Consequently, the current mode comparator damps currents slower and the whole circuit output frequency decreases. Thus a negative correlation between the output frequency and the temperature is achieved in the proposed current mode oscillator.

6.9 Simulator issue

During the project period, there were several times of routinely update to the Cadence simulator MMSIM. The frequency standard deviation simulation result of the original oscillator was initially 15.6 MHz. Based on this result the speci- ﬁcation was set to 8 MHz accordingly. However, after one update the frequency standard deviation of the original oscillator changed to 11.3 MHz, resulting in a change on the speciﬁcation to 6 MHz. After checking the distribution of the worst scenario simulation results, the histogram showed some abnormal samples outside the 3σ range, which leaded to this 15.6 MHz standard deviation. The histogram of the distribution is shown in Fig. 6.1. The ADEXL testbench setting for the original oscillator had issues after the update as well. The transient simulation terminated earlier than the expected time, leaving the expressions of the output setup unable to resolve the data properly. Thus the testbench was reestablished in an Assembler template to simulate the original oscillator. 68 6 Discussion

Figure 6.1: Histogram of 100 samples at 40 ◦C with 1.62 V supply of the original oscillator. − 7 Conclusion and future’s work

Based on the problem statements in Section 1.2, this thesis presented two designs of the oscillator. The circuit blocks are designed and implemented in a CMOS process. Design considerations for the various circuits and their performance specifications were illustrated in Chapter 2-5 and the following conclusions are drawn. Chapter 2 showed the simulation results of the original oscillator. Based on the simulations results the specifications for the project are proposed. Chapter 3 elaborated the theories behind different blocks of the oscillator. The working method of the proposed current mode oscillator is defined. Chapter 4 illustrated the implementation of the two oscillators. Chapter 5 presented the results of different implementations of the oscillators and comparisons between different performance specifications were made. A layout of a low frequency standard deviation relaxation oscillator was designed and simulated. This current mode oscillator achieves an FoM of 5.94 µW/MHz, σ/µ of 6.34%. This project successfully proposed and designed an oscillator which meets all the specifications. The proposed current mode oscillator achieves low frequency standard deviation at a high frequency output with small area usage.

7.1 Future’s work

This proposed oscillator can be integrated into, for example, a sensor, which can help improve mobile payment in the modern society. Biometric characteristics can be never forgotten comparing to PIN code. A stable oscillator helps to achieve fast recognition and speed up the purchase. A biometric sensor always requires a stable and power saving oscillator.

69 70 7 Conclusion and future’s work

More works can be done to the enabling signal control switches’ implementations and bias current generation module. A transmission gate switch or a self biased current generator with opposite temperature coeﬃcients could be good solution to the proposed current mode oscillator. Extra add-on to the original oscillator is an accessible solution as well, such as self-clocked oﬀset-cancellation [23], voltage averaging feedback [20]. Bibliography

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Appendix

A Appendix

A.1 Opponent’s questions and respondent’s responses

• Q1: If the oscillator should operate in only the range of 75-85 MHz, What is the reason to have a wide tunable frequency range? A1: The tuning range is to cover unexpected output frequencies, which are shown in MC simulations as shown in Tab. 2.2. • Q2: The original design consumed 112.6 µA, but the new "budget" were set to 250 µA. Maybe a table with simulations with the original design with the trimming code set so that the oscillator are provided with this maximum current could be used as a reference? A2: Unfortunately, comparison needs to be made with same trimming codes instead of with same current consumptions. An explanations are added in Section 6.3. One feasible way is to increase the current supply in the original oscillator while keeping the trimming codes fixed to zero. • Q3: At page 49 in table 5.1, the results for the original and improved oscillator is presented. The improved design consumes just above 50% more power when operating at a frequency of about 10MHz lower than the original. Is this still considered an improvement? A3: Yes, the improvement is firstly considered in a standard deviation perspective. The current consumption and the nominal output frequency are less concerned as long as they are within the specifications. An expanded descriptions are added to Section 5.1.

77 78 A Appendix

• Q4: At page 33 you state some new values for the capacitor and resistor of the improved implementation. How did you come up with these values? A4: They are decided by sweeping tests in transient simulations and the values are shown by the schematic window. • Q5: At page 35 there is a schematic of the improved design with comparators flipped, inverters removed and two additional current sources. Did you perform any intermediate simulations, meaning simulating on only the comparator flip and removal of the inverters without adding the current sources? A5: Yes, the intermediate simulations showed that the nominal output frequency dropped to 61 MHz, which was out of the specification range. An MC test was also performed and the results showed that the frequency standard deviation was 6.8 MHz. Extra descriptions are added in Section 4.3. • Q6: At page 31, you say that the standard deviation of high frequencies is not important since the generated signal should be divided by 8. Does this mean that it should actually produce a signal between 9.375 to 10.625 MHz? This is not explained why, and What is the reason for not designing an oscillator to produce this lower frequency directly instead if this is the case? A6: Firstly, the high frequency is desired by the customer. Secondly, a high frequency oscillator consumes less area comparing to a low frequency oscillator. The low frequency oscillator requires large passive components, which take large area of the layout. Finally, this high frequency can be changed to low frequency quite easily by using DFFs, leaving more control spaces to the designers.

• Q7: At page 55 is a table with the results of the different designs. They were all simulated at different mean frequencies. Did you try to set the trimming code so that they were simulated at frequencies more close to each other? A7: The purpose of the simulations on page 55 is to check the frequency standard deviations of different implementations with fixed trimming codes. Setting different trimming codes will deviate the middle point of the trimming range. Explanations are added in Section 6.3. • Q8: At page 57 you say that the oscillator does not require anything from a noise perspective. How come that the oscillator is not affected from noise? A8: The original designer claimed that the oscillator would only take samples when the inputs are so stable that even jitters could not affect the results. I followed his instruction of the oscillator application. Explanations are added in Section 3.2. • Q9: At page 58, two other work are used as a reference. Both of them are running at around 30MHz. Did you find any other work that were operating at the same frequency that your oscillator are? A.1 Opponent’s questions and respondent’s responses 79

A9: No. During my searching of the reference articles, I did not find any relaxation oscillators operating at 80 MHz. • Q10: At page 66, some comments are made on an update of the simulation software. Did you find out what caused this change? A10: No, I failed to find out the reasons. • Q11: How time consuming were the simulations? If it took a lot of time have you any idea on how to maybe reduce this time for future reference? A11: One MC simulations usually takes half a day to finish. A normal transient simulations usually takes two minutes. Hence MC simulations can be performed during the night time and other tests during the daytime. By doing so, out of office hours can also be made use of. Resource limitations are mentioned in Section 2.2. • Q12: At page 64 you state that it is mainly due to the fact that the oscillator has a tunable frequency with the trimming codes that is the reason for the standard deviation in frequency, but at page 65 you say that the start-up phenomenon is the main cause for this. Which one is true and how did you compare the two when determining which of the areas (start up or trimming) that you should pay more attention to? A12: The trimming system just provides an output range to cover unexpected output frequencies. The start-up phenomenon is the true cause of the large standard deviation. This misunderstanding is due to the wrongly constructed sentences in the discussion chapter. Section 6.3 has been revised. 80 A Appendix

A.2 Change track

Table A.1: Document history.

Version Date Changes Performed by Reviewed P1A 2017-05-30 First draft. Jianxing Dai Dr. J Jacob Wikner Abstract revised. Jianxing Dai, P2A 2017-06-12 Discussion chapter expanded. Dr. J Jacob Wikner Carl-Fredrik Tengberg Appendix added. P2B 2017-06-14 Appendix revised. Jianxing Dai Dr. J Jacob Wikner P3A 2017-06-15 Acknowledgments added. Jianxing Dai Dr. J Jacob Wikner