Exceptions/Interrupts and Concurrency Administrivia System

Administrivia

• HW #5 • Projects Outline • System/Machine Organization • Executing a program Exceptions/Interrupts and Concurrency • Exceptions and Interrupts: What are exceptions and interrupts How are exceptions handled • Kernel mode execution Computer Science 104 • Back to Exceptions - the details: Additions to the MIPS ISA to support exceptions Additions to the control to support exceptions. • Concurrency • Synchronization and Atomic Sequences Reading : 4.9, B-7

System Organization What Does an Operating System Do?

exceptions • Service Provider interrupts Processor exports commonly needed facilities with standard interfaces simplifies programs Cache portability • Executive Memory Bus I/O Bridge resource manager for greatest good Core Chip Set • Custodian of the Machine I/O Bus monitors hardware, intervenes to resolve exceptional conditions Memory • Cop Disk Graphics Network Controller Controller Interface protects you from others The memory Disk Disk Graphics Network hierarchy

Executing a Program An Execution Context

• Thread of control (program counter) • The state of the CPU associated with a thread of multiple threads/programs running control (process) • Basic steps for program execution general purpose registers (integer and floating point) fetch instruction from Memory[PC], status registers (e.g., condition codes, HI/LO) execute the instruction, program counter, stack pointer increment PC • Need to be able to switch between contexts • At boot-time, begin with PC at well-known location timeslicing : sharing the machine among many processes loads the Kernel better utilization of machine (overlap I/O of one process with computation of another) Memory PC R1 R2 R3 440 different modes (Kernel v.s. user) 100 4 440 6 4 100 ld $1, ($2) 104 4 440 10 add $1, $3, $3 Text • Maintained by operating system Time 104 108 4 440 10 10 108 st ($2), $3

440 4 Data

• Save current execution context • Unnatural change in control flow Save registers and program counter • warning: varying terminology information about the context (e.g., ready, blocked) “exception” sometimes refers to all cases • Restore other context “Trap” software trap, hardware trap • Need data structures in kernel to support this process control block • Exception is potential problem with program • Why do we context switch? condition occurs within the processor Timeslicing: HW clock tick segmentation fault I/O begin and/or end bus error • How do we know these events occur? divide by 0 Don’t want my bug to crash the entire machine • Interrupts ... page fault (virtual memory…)

Interrupts and Exceptions Handling an Exception/Interrupt • Invoke specific kernel routine • Interrupt is external event User Program based on type of interrupt ld devices: disk, network, keyboard, etc. Interrupt Handler interrupt/exception handler add clock for timeslicing st • Must determine what caused div These are useful events, must do something when they occur. RETT interrupt beq could use software to examine ld each device • Trap is user-requested exception sub PC = interrupt_handler bne operating system call (syscall) • Vectored Interrupts PC = interrupt_table[i] • Kernel initializes table at boot time • Similar mechanism is used to • Clear the interrupt handle interrupts, • May return from interrupt exceptions, traps (RETT ) to different process (e.g, context switch)

Execution Mode A System Call (syscall)

• What if interrupt occurs while in interrupt handler? User Program Kernel • Special Instruction to change Problem : Could lose information for one interrupt ld modes and invoke service clear of interrupt #1, clears both #1 and #2 add Trap read/write I/O device Solution : disable interrupts st Handler create new process TA 6 RETT • Disabling interrupts is a protected operation beq • Invokes specific kernel routine based on argument Only the kernel can execute it ld sub user vs. kernel mode Service • kernel defined interface bne mode bit in CPU status register Routines • May return from trap to different • Other protected operations process (e.g, context switch) installing interrupt handlers • RETT, instruction to return to manipulating CPU state (saving/restoring status registers) user process • Changing modes interrupts system calls (syscall instruction)

1. Machine must save the address of the offending • 3 types of exceptions in our current implementation instruction in the EPC (Exception Program Counter) undefined instruction 2. Then transfer control to the Operating System (OS) arithmetic overflow at some specified address unaligned access 3. OS performs some action in response • Which Event caused Exception? Option 1 (used by MIPS): Cause register contains reason 4. OS terminates program or returns (eventually) using Option 2 Vectored interrupts: cause is part of the address. EPC » addresses separated by 32 instructions could return to different program (context switch) » E.g., • Exceptions are like an “unscheduled procedure call” Exception Type Exception Vector Address to a fixed location! Undefined instruction C0 00 00 00 Arithmetic overflow C0 00 00 20 Unaligned Access C0 00 00 40 » Jump to appropriate address

Additions to MIPS ISA Additions to MIPS ISA

• EPC: a 32-bit register used to hold the address of the • Control signals to write EPC, Cause, BadVAddr, and affected instruction Status • Cause: a register used to record the cause of the • Need to write exception address into PC exception. increase mux to add input for interrupt handler address In the MIPS architecture this register is 32 bits, though some bits are currently unused. • May have to undo PC = PC + 4 • BadVAddr: register contains memory address at if EPC points to offending instruction (not its successor) which memory reference occurred PC = PC - 4 when memory access exception occurs • Status: interrupt mask and enable bits

Details of MIPS Status register Details of Cause register 15 8 5 4 3 2 1 0 15 10 5 2 Status Cause Mask k e k e k e Pending Code old prev current • Pending interrupt 5 hardware levels: bit set if • Mask = 1 bit for each of 5 hardware and 3 software interrupt occurs but not yet serviced interrupt levels handles cases when more than one interrupt occurs at same time, or records interrupt requests when interrupts disabled 1 enables interrupts, 0 disables interrupts • Exception Code encodes reasons for interrupt • k = kernel/user 0 (INT) => external interrupt 0 => was in the kernel when interrupt occurred 4 (ADDRL) => address error exception (load or instr fetch) 1 => was running user mode 5 (ADDRS) => address error exception (store) • e = interrupt enable 6 (IBUS) => bus error on instruction fetch 0 means disabled, 1 means enabled 7 (DBUS) => bus error on data fetch • Interrupt handler runs in kernel mode with interrupts 8 (Syscall) => Syscall exception disabled 9 (BKPT) => Breakpoint exception When interrupt occurs, 6 LSB shifted left 2 bits, setting 2 LSB to 0 10 (RI) => Reserved Instruction exception 12 (OVF) => Arithmetic overflow exception

• Undefined Instruction • Some problems could occur in the way the Detect unknown opcode. exceptions are handled. • Arithmetic overflow • Example: logic in the ALU to detect overflow You do not want a arithmetic overflow instruction to write to the Overflow is provided as an output from the ALU. This signal is used destination register in the modified finite state machine to specify an additional possible next state for state 7 (state 13) • When we get to virtual memory we will see that • Unaligned access certain classes of exceptions must prevent the instruction from changing the machine state. Circuit to check addresses E.g., lw address must have 2 least significant bits == 0 • This gets complex and potentially limits performance => this is why exceptions are hard

Exception Summary Concurrency

• Multiple things happening simultaneously • Control is hard part of computer design logically or physically We have simple control Real systems have much more complex control • Causes Interrupts • Exceptions are the hard part of control Voluntary context switch (system call/trap) • Need to find convenient place to detect exceptions Hyperthreading / Shared memory multiprocessor PC and invoke the operating system • Things get more difficult with pipelining and the P P P P notion of precise exceptions No modifications to machine state from this or any following instructions

Memory

The Trouble with Concurrency Solution: Atomic Sequence of Instructions

• Two threads (T1,T2) in one address space or two T1 T2 count processes in the kernel begin atomic ld (count) • One counter (profile bcopy) add switch begin atomic T1 T2 count st (count+1) count+1 Time wait ld (count) ld r2, count add r1, r2, r3 end atomic add st count, r1 Private stack switch switch per thread for ld (count) ld (count) ld r2, count locals add add add r1, r2, r3 st (count+2) count+2 st (count+1) st count, r1 Time end atomic count+1 switch Shared Data • Atomic Sequence st (count+1) count+1 count Appears to execute to completion without any intervening operations

• Could provide direct support in HW T1 T2 count Atomic increment LOCK(ctr_lock) Insert node into sorted list?? ld (count) add • Just provide low level primitives to construct atomic switch sequences LOCK(ctr_lock) st (count+1) count+1 Time wait called synchronization primitives UNLOCK(ctr_lock) LOCK(counter->lock); // begin atomic switch counter->value = counter->value + 1; ld (count) add UNLOCK(counter->lock); // end atomic st (count+2) count+2 All updates to counter->value must be “protected” by Lock/Unlock UNLOCK(ctr_lock) • test&set (x) instruction: returns previous value of x and sets x to “1” LOCK(x) => while (test&set(x)); LOCK(x) => while (test&set(x)); UNLOCK(x) => x = 0; UNLOCK(x) => x = 0;

Alternative Solutions Transactions Failure Success • Disable interrupts T1 T2 count T1 T2 count begin trans begin trans No context switching ld (count) ld (count) Only works for single threaded systems (not on hyperthreading or add add multicore) switch st (count+1) count+1 begin trans end trans ld (count) Time switch • Transactions add begin trans st (count+1) ld (count) Mark begin and end of transaction count+1 add If no conflict during transaction great switch st (count+1) st (count+1) If conflict, then need to make it look like the instructions never count+2 end trans count+1 executed and start over count+1 end trans end trans Need support to either 1) undo operations or 2) delay updating state until transaction is guaranteed to be atomic Conflict: Neither transaction can complete Both will restart, eventually one completes without a conflicting Access (e.g., runs and completes without a context switch)

Summary Reminders • Operating System • Projects • Threads of Control • Up Next: Virtual Memory Execution context context switches • Kernel vs. User Mode Mode bit; privileged instructions • Interrupts and Exceptions what are they? handling exceptions extending the architecture implementing control • Concurrency • Synchronization and Atomic Sequences