DOCSLIB.ORG

Pulsonix Change Notes Version 7.0 Build 4573 : 04-Aug-2011

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Pulsonix Change Notes Version 7.0 Build 4573 : 04-Aug-2011 Pulsonix Change Notes These notes list the main functional changes and problem fixes in each release of the software. They are listed in order, latest first. Version 7.0 Build 4573 : 04•Aug•2011 Functional changes Scripting Added an optional second parameter to Message function. This is an integer value that allows you to specify flags indicating the type of message box. See release notes for more details. Added new function GetCurrentVariantName to retrieve the name of the currently selected variant. Problems Fixed CAM/Plot Gerber • Inserted user report was not updated with the correct variant when producing a plot for a specific variant. Gerber • No pads visible on Windows Verification Plot of Gerber outputs. Gerber • Embedded view on plot was showing the current design variant, not the variant of the plot. PDF Plot • Inserted user report was not refreshed for plot variant. Output • Program sometimes quit trying to produce plots Export IDF • Area board cutouts were not output to IDF with the board. STEP • STEP preview of board did not understanding environment variables in the paths to the models. STEP • A component with a Z offset was not mirroring correctly. STEP • Area Board cutouts were not being output. STEP • Mirrored component positioned badly for this model. STEP • Subsequent model positions were being rotated when they should not. STEP • Component board cutouts were not treated as notch when touching the board edge. STEP • Specific model was rotated 180 degrees out. STEP • Some mirrored components were not output in the correct positions. STEP • Had more model positioning problems. File Save • Program quit after saving and closing particular designs. Import Cadstar • Program quit attempting to import a particular Cadstar CPA file. Cadstar • Did not handle an undefined ROUTECODE in a CPA file. DxDesigner • Pins were ending up with the wrong pin numbers after ViewDraw import. DXF • Importing DXF into a PCB documentation symbol was not offering layers in the grid. Eagle • Was not translating shapes on "tDocu" and "bDocu" layers separately. Integra • Importing a particular Integra design caused the program to exit. Integra • Duplicate styles were being created. Pads • Rounded rectangular pads were being imported as rectangles. PCAD • Component with duplicate attributes was being created from a PDIF file. Protel • Problems importing some specific Protel designs. Visula • Import of a .PAF file created two top & bottom electrical layers. Visula • Was adding areas with no layer assigned. Interaction Edit Track • Program quit when track hugging with a large gap and getting near to an area board cutout . Move • Had problems moving a segment of a differential paired track with "Preserve Attached Segments" enabled. Hierarchy Add Block • Adding a specific block to a new schematic caused a design corruption. Save To Block • Was causing duplicate unused net names. Edit Block Symbol • Corruption was being caused by editing a particular block generated symbol Properties Footprints • The variants tab was incorrectly appearing for symbols and footprints if the tech file has variants. Components • Change Part Representation put gates into the bin which caused them to be disconnected. Components • Changing a component to one with less pins can produce broken differential pair entry. Pulsonix Database Connection Properties • Changing a part through Properties, Variant, caused duplicate attributes. Technology Spacings • Could not paste values into the spacing grid. Nets • Adding two net names introduced a design corruption. General • Edit boxes were not scrolling. Colours • Loading s particular colour file was disabling Back Annotation. Tools Apply layout Pattern • Comp Names were not placed correctly to match the pattern. Copper Pour • Poured over items on other nets due to very shallow arcs in the board outline. Copper Pour • Flooded over a ring of track in a specific design. Design Rule Check • Doing all net checks on a particular design caused the program to quit. Design Rule Check • Was incorrectly flagging spacing violations within an area. Electrical Rules Check • Reported spurious “Pintype” errors between the same pins of a variant component. Optimise Nets • Was leaving many ground connections because it did not think they are inside the board. Reload From Library • Net names were not preserved during reload, this was inconsistent with Change Part. Reload From Library • Reloading a design•level associated part did not reload its attributes. Router • There was a problem with restoring from routers results for single sided boards with wires. Scripting • Added optional second parameter to Message function, and new function GetCurrentVariantName. Scripting • RunReport command produced a report but it only had a header line and no data. Scripting • Could not retrieve a component attribute. Scripting • CamPlot.Run was returning an error because the output filename had not been set up. Scripting • Run Script dialog was not environment variable aware. Synchronise Designs • Was causing a PCB design corruption. Synchronise Designs • Program quit attempting to synchronise two particular designs. Version 7.0 Build 4572 : 02•Jun•2011 Functional changes Library Toolkit New library toolkit command “SETPARTATTRIBUTE” has been added. Problems Fixed CAM/Plot Plot Preview • Was using yellow for the board outline. Drill Ident • Some drill symbols were coming out wrong. Gerber • Area marked as a board cutout was not included in a plot of a documentation layer. Gerber • Incorrect output was produced for specific user•defined pads. Gerber • Target shaped pads were being flashed instead of drawn. PDF Plot • Plotting a page more than once to a PDF document caused the program to quit. Power Plane • Incorrect pad size was used for drilled out pads on power plane layers. Power Plane • Pads outside of a spacing rule area on the power plane layer got wrong isolating gap. Export ODB++ • Failed to complete the generation process for a particular design. ODB++ • New drill symbol shapes and drawn drill symbols were not handled correctly. ODB++ • Some pads were output with the wrong angle to the component layer. STEP • Boards with cutouts were not being imported. STEP • Built•in standoff of 0.5mm caused auto•generated components to be the wrong height in STEP output. STEP • Did not deal correctly with pad style offsets. STEP • If a component was mirrored its offsets were not mirrored. STEP • Program quit importing a specific STEP board. STEP • Program quit without warning on attempting to preview a bad model. STEP • Arcs in a board outline were being imported with the wrong direction. STEP • Some cutouts were not imported at their correct size. STEP • Some mirrored and rotated components were not being positioned correctly in STEP output. STEP • Was writing copper to a STEP file with the wrong outline size. STEP • Z offsetting of models was not being applied correctly for mirrored components. File Save • Some designs were saved as corrupt due to unnecessary component copper net names. Import DxDesigner • Program quit importing a specific schematic design. DXF • Arcs and circles were misplaced importing a particular file. Eagle • Import was aborted reading specific data. Eagle • Was failing to import some keepout areas. Easy•PC • Did not handle pad styles with slots. Integra • Illegal cutout in the TXF file was causing the program to exit in the Copper Pour stage of Import. PADS • Was incorrectly importing designs containing layers with no layer class. PCAD • ASCII file generated from CAM350 did not read in. Interaction Auto Weld • Net names could disappear when welding a schematic pad to an open end of a connection. Dimensions • Altering a shape was moving some attached dimensions in unexpected ways. Edit Track • Was incorrectly adding a connection in the middle of a differential paired track. Edit Track • Differential paired tracks were crossing over when you finish the edit. Edit Track • Via was disappearing after adding a track even though via still needed. Library Tools Close • Gave no error message if library was write•protected when closing a library item with the "X" button. Footprint Edit • Modifying a footprint after using "Save Copy As" could cause the library to be overwritten. Part Edit • Using "Save Copy As" on a part design could overwrite a library. Reports • RTF report did not handle PCB only components. Toolkit • Additional library toolkit command SETPARTATTRIBUTE added. Toolkit • Using the FINDPART command on a part that had no gates caused the program to quit. Licensing Network Licensing • Check for MAX (permit cap) did not take into account connected clients that had been released. Network Licensing • Client socket was sometimes not closed after an early return of a license loan. Network Licensing • License Server could exit on attempting to connect NLServer Monitor Network Licensing • Some operations could book out an unlimited pin license when not working on a PCB design. Network Licensing • Was always giving message about getting a Design Rule Check license. Pulsonix Database Connection Check/Update • Components were updated with strange values for many 'empty' fields. Properties Component • Changing a component variant details using the apply button could corrupt the component. Component • Did not handle changing a component to an alternate footprint with bond pads. Component • Program aborted whilst changing component variant instance. Reports Report Maker • Incorrect 'Top Height' value was reported for a component in one variant. Technology Report • Program quit attempting to produce a technology report on a particular design. Technology Colour Files • Board colour was not correct after reading colour files saved in earlier versions. Colour Files • Loading colour files into a PCB was be a lot slower than it should be. Attribute Names • Did not allow attribute name context to be changed if attribute was in use. Nets • Exchanging two net names in a particular design caused the program to exit. Tools Apply Layout Pattern • Could not get full pattern match between two groups. Apply Layout Pattern • Did not copy unattached protected vias. Auto Insert Testpoint – Incorrectly placed test points resulting in track to via errors.
Load more

Recommended publications
  • Aras Innovator - Connectors Support Matrix
    Aras Innovator - Connectors Support Matrix MCAD Tools Autocad Autodesk Inventor CATIA V5 Dassault CATIA V6 SolidWorks Creo PTC Creo Direct NX Siemens Solid Edge PDM/PLM Autodesk Vault Altium Vault Enovia Dassault SmarTeam SolidWorks PDM Pro Oracle Agile PTC Windchill SAP PLM Siemens Teamcenter SAP PLM ERP IBM DOORS ORACLE ERP ERP SAP ERP V6 ERP HANNA QAD QAD/Mfg Dynamics NAV Microsoft Dynamics GP Dynamics AX Oracle Netsuite BIM Tools Revit AutoDesk 1 January 2021 Aras Innovator - Connectors Support Matrix ECAD Tools AutoCAD Electrical (Autodesk) Electrical CAD AutoDesk AutoCAD Electrical (Autodesk) Electrical Librarian SolidWorks (Dassault) Electrical Dassault SolidWorks (Dassault) Electrical Librarian Designer Electronic Board Layout CAD Designer Electronic Schematic CAD Designer Electronic Librarian Altium Nexus Server Agent Nexus Electronic Librarian Concord Electronic Librarian Concord PCB Electronic Librarian Xpedition Capture (Mentor Graphic) Electronic Schematic CAD PADS Standard Electronic Schematic CAD Xpedition Electronic Board Layout CAD PADS Standard Electronic Board Layout CAD Xpedition & PADS Professional Electronic Librarian PADS Standard Electronic Librarian Mentor PADS Professional Electronic Schematic CAD PADS Professional Electronic Board Layout CAD Capital Electrical Capital Electrical Librarian EDM Server Agent EDM Librarian Allegro HDL Electronic Schematic CAD OrCAD Capture CIS Electronic Schematic CAD Cadence Allegro & OrCAD Electronic Board Layout CAD Allegro HDL Electronic Librarian OrCAD Electronic Librarian Zuken E3.series (Zuken) Electrical Wiring Layout CAD Elcad Electrical CAD Elcad Electrical Librarian Aucotec Engineering Base Electrical CAD Engineering Base Electrical Librarian EPLAN Electric Electrical CAD EPLAN EPLAN Electric Electrical Librarian Pulsonix Electronic Board Layout CAD Pulsonix Pulsonix Electronic Schematic Layout CAD Pulsonix Electronic Librarian 2 January 2021.
    [Show full text]
  • LH1546ADF Datasheet (PDF)
    LH1546ADF, LH1546ADFTR www.vishay.com Vishay Semiconductors 1 Form A Solid-State Relay (Normally Open) FEATURES • Isolation test voltage 5300 VRMS • Typical RON 22 Ω A 1 4 S1 • Load voltage 350 V • Load current 120 mA C 2 3 S2 • Clean bounce free switching • Current limit protection • Low power consumption • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 DESCRIPTION APPLICATIONS The LH1546AD is a single channel solid state relay in a • General telecom switching 4 pin SMD package. It is a SPST normally open switch (1 Form A) that replaces electromechanical relays in many • Metering applications. It is constructed using a GaAlAs LED for • Security equipment actuation control and MOSFET switches for the output. • Instrumentation In addition, it employs current-limiting circuitry to provide • Industrial controls overvoltage protection. • Battery management systems • Automatic test equipment AGENCY APPROVALS • UL1577, file no. E52744 ORDERING INFORMATION SMD LH1546A##TR PART NUMBER ELECTR. PACKAGE TAPE AND VARIATION CONFIG. REEL > 0.1 mm PACKAGE UL SMD-4, tubes LH1546ADF SMD-4, tape and reel LH1546ADFTR Rev. 1.8, 05-Jul-2018 1 Document Number: 83836 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 LH1546ADF, LH1546ADFTR www.vishay.com Vishay Semiconductors ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C, unless otherwise specified) PARAMETER CONDITION SYMBOL VALUE UNIT INPUT IRED continuous forward current IF 50 mA IRED reverse voltage VR 5V Input power dissipation Pdiss 80 mW OUTPUT DC or peak AC load voltage VL 350 V Continuous DC load current at 25 °C, I 120 mA bidirectional L SSR output power dissipation Pdiss 550 mW SSR Ambient temperature range Tamb -40 to +85 °C Storage temperature range Tstg -40 to +150 °C Soldering temperature t = 10 s max.
    [Show full text]
  • Electronic Design Automation Tools Part 2 by Christopher Henderson This Article Provides an Overview of the Electronic Design Automation (EDA) Design Tools
    Issue 126 December 2019 Electronic Design Automation Tools Part 2 By Christopher Henderson This article provides an overview of the Electronic Design Automation (EDA) design tools. The EDA industry is an interesting ecosystem and bears discussing, so that the design engineer can Page 1 Electronic Design understand the environment. Automation Tools In last month’s feature article we discussed the three major EDA Part 2 tool suppliers: Cadence Design Systems, Synopsys, and Mentor Graphics, which is now owned by Siemens. Here in Part II we will Page 5 Technical Tidbit briefly discuss interoperability issues between the three major platforms. We’ll also discuss other suppliers developing tools in this area. Finally, we’ll discuss the use case and the strengths and Page 8 Ask the Experts weaknesses of the tool suites. Each of the three major EDA firms creates products that work well within their own portfolio, but what about across the three major Page 10 Spotlight providers? What if you want to create designs using tools from across two or more of the providers? This is a major challenge because it requires that one work with different formats for different files, which Page 13 Upcoming Courses requires translators, scripts and additional programs. What would be most useful is a good interoperability standard, and the good news is that there is one. It is called OpenAccess and is supported and promoted by the Silicon Integration Initiative. OpenAccess actually had its start as the result of a lawsuit against Cadence. Users sued Cadence, claiming that their internal format gave them a controlling monopoly in the design area, and a judge agreed with them.
    [Show full text]
  • 233-203 PCB Terminal Block; Push-Button; 0.5 Mm²; Pin Spacing 2.5 Mm; 3-Pole; CAGE CLAMP®; 0,50 Mm²; Gray
    Data sheet | Item number: 233-203 PCB terminal block; push-button; 0.5 mm²; Pin spacing 2.5 mm; 3-pole; CAGE CLAMP®; 0,50 mm²; gray www.wago.com/233-203 Color: L = (pole no. x pin spacing) + 2.3 mm SubjectItem description to changes. Please also observe the further product documentation! WAGO Kontakttechnik GmbH & Co. KG Do you have any questions about our products? Hansastr. 27 We are always happy to take your call at +49 (571) 887-44222. 32423 Minden Phone: +49571 887-0 | Fax: +49571 887-169 Email: [email protected] | Web: www.wago.com 03.07.2020 Page 1/8 Data sheet | Item number: 233-203 www.wago.com/233-203 Item description Compact PCB terminal strips with CAGE CLAMP® connection and screwdriver actuation parallel or perpendicular to conductor entry Double solder pins for high mechanical Custom color combinations Data Electrical data Ratings per IEC/EN 60664-1 Ratings per IEC/EN 60664-1 Nominal voltage (III/3) 63 V Rated surge voltage (III/3) 2.5 kV Rated voltage (III/2) 160 V Rated surge voltage (III/2) 2.5 kV Nominal voltage (II/2) 320 V Rated surge voltage (II/2) 2.5 kV Rated current 6 A Legend (ratings) (III / 2) ≙ Overvoltage category III / Pollution degree 2 Approvals per UL 1059 Rated voltage UL (Use Group B) 150 V Rated current UL (Use Group B) 4 A Approvals per CSA Rated voltage CSA (Use Group B) 150 V Rated current CSA (Use Group B) 4 A Connection data Connection technology CAGE CLAMP® Actuation type Push-button Solid conductor 0,08 … 0,5 mm² / 28 … 20 AWG Fine-stranded conductor 0,08 … 0,5 mm² / 28 … 20 AWG Fine-stranded conductor; with insulated ferrule 0,25 mm² Fine-stranded conductor; with uninsulated ferrule 0,25 mm² SubjectStrip length to changes.
    [Show full text]
  • Release Notes: Desktop Edition
    Release Notes: Desktop Edition AutoVue 19.2c2: November 30, 2007 Installation • Please make sure you have AutoVue 19.2c1 installed before upgrading to AutoVue 19.2c2. Note: If you have an older version of AutoVue installed (e.g. AutoVue 19.2), please uninstall it before installing AutoVue 19.2c1 and upgrading to AutoVue 19.2c2. MCAD Formats • Added font substitution for missing native fonts: • CATIA 4 and CATIA 5 • Pro/ENGINEER • Unigraphics • Added support for Unigraphics NX5. • Performed bugs fixes for Unigraphics and CATIA 5. EDA Formats • Added font substitution for missing native fonts: • Altium Protel • OrCAD Layout • Cadence Allegro Layout • Cadence Allegro IPF • Cadence Allegro Extract • Mentor Board Station • Mentor PADS • Zuken CADSTAR • P-CAD • PDIF AEC Formats • Added font substitution for missing native fonts: • AutoCAD • MicroStation 7 and MicroStation 8 • Performed bug fixes for AutoCAD. Release Notes - AutoVue Desktop Edition - 1 - November 30, 2007 AutoVue 19.2c1: September 30, 2007 Packaging and Licensing • Introduced separate installers for the following product packages: • AutoVue Office • AutoVue 2D, AutoVue 2D Professional • AutoVue 3D Professional-SME, AutoVue 3D Advanced, AutoVue 3D Professional Advanced • AutoVue EDA Professional • AutoVue Electro-Mechanical Professional • AutoVue DEMO • Customers are no longer required to enter license keys to install and run the product. • To install 19.2c1, users are required to first uninstall 19.2. MCAD Formats • General bug fixes for CATIA 5 EDA Formats • Performed maintenance and bug fixes for Allegro files. General • Enabled interface for customized resource resolution DLL to give integrators more flexibility on how to locate external resources. Sample source code and DLL is located in the integrat\VisualC\reslocate directory.
    [Show full text]
  • Pulsonix Users Guide Pulsonix Users Guide 3
    Pulsonix Design System Users Guide 2 Pulsonix Users Guide Pulsonix Users Guide 3 Copyright Notice Copyright ã WestDev Ltd. 2001-2018 Pulsonix is a Trademark of WestDev Ltd. All rights reserved. E&OE Copyright in the whole and every part of this software and manual belongs to WestDev Ltd. and may not be used, sold, transferred, copied or reproduced in whole or in part in any manner or in any media to any person, without the prior written consent of WestDev Ltd. If you use this manual you do so at your own risk and on the understanding that neither WestDev Ltd. nor associated companies shall be liable for any loss or damage of any kind. WestDev Ltd. does not warrant that the software package will function properly in every hardware software environment. Although WestDev Ltd. has tested the software and reviewed the documentation, WestDev Ltd. makes no warranty or representation, either express or implied, with respect to this software or documentation, their quality, performance, merchantability, or fitness for a particular purpose. This software and documentation are licensed 'as is', and you the licensee, by making use thereof, are assuming the entire risk as to their quality and performance. In no event will WestDev Ltd. be liable for direct, indirect, special, incidental, or consequential damage arising out of the use or inability to use the software or documentation, even if advised of the possibility of such damages. WestDev Ltd. reserves the right to alter, modify, correct and upgrade our software programs and publications without notice and without incurring liability. Microsoft, Windows, Windows NT and Intellimouse are either registered trademarks or trademarks of Microsoft Corporation.
    [Show full text]
  • Pulsonix PCB Design
    Pulsonix PCB Design Effortless PCB Layouts Pulsonix PCB Layout Construction Lines Pulsonix provides an expert design environment to get your boards Unique to Pulsonix, construction lines provide user-definable 'guide' produced fast with as little effort as possible.With unparalleled ease lines within your design. Use construction lines to create complex of use, Pulsonix provides a feature-rich toolset to get the job done board outlines or design items and to align irregular shapes.With efficiently. Everything in Pulsonix is logical, easy to setup and easy to their own layer, colour and style, construction lines are valuable for all use. Even complex design constraint rules can be easily defined using 2D creation without the need to import complex shapes from highly accessible dialogs. outside of your PCB design environment. Technology files for fast start-up True Mixed Technology Support Just like templates used for other desktop products, Pulsonix has a Technology is supported for standard plated through holes, surface unique system of technology files for fast start-up. Customise and mount devices/technologies, blind and buried vias and laser/plasma pre-define items such as Design rules, Layers, Materials, Spacing rules drilled micro-vias. Pads with slots or non-round holes are easily and Copper/Thermal rules as well as styles for text, tracks, pads, lines achieved using standard pad style definitions or custom pad shapes. to name a few. Company standards can be created in one file then used and shared by all Pulsonix users.Technology files can be created and updated as you design to create a master file containing all your design settings.
    [Show full text]
  • CADSTAR FPGA TRAINING Agenda
    CADSTAR FPGA TRAINING Agenda 1. ALDEC Corporate Overview 2. Introduction to Active-HDL 3. Design Entry Methods 4. Efficient Design Management 5. Design Verification – Running Simulation 6. Design Verification- Debugging 7. Synthesis and Implementation in Flow Manager 8. Using the PCB interface Corporate Overview Aldec Focus - Background • Founded 1984 – Dr. Stanley Hyduke • Privately held, profitable and 100% product revenue funded • Leading EDA Technology – VHDL and Verilog Simulation – SystemVerilog – SystemC Co-Verification – Server Farm Manager – IP Cores – Hardware assisted Acceleration/Emulation and Prototyping • Over 30,000 active licenses worldwide • Several key Patents in Verification Technology • Office Locations: – Direct Sales and Support • United States • Japan • Canada • France • ROW – Distribution Channel Corporate Milestones Technology Focus Design Creation • Text, block diagram and state diagram entry • Automatic testbench generation • Automatically created parameterized blocks • Variety of IP cores Verification • Multiple language support (VHDL, [System]Verilog, C++, SystemC) • Assertions (OpenVera, PSL, SystemVerilog) • Direct compilation and common kernel simulation • Co-simulation Interfaces(VHPI/VPI, Matlab/Simulink, SWIFT, …) Technology Focus – cont. Hardware Validation • Hardware assisted acceleration of HDL simulation • Emulation and ASIC prototyping • Hardware / software co-simulation (Embedded Systems, SoC) Niche Solution • Actel CoreMP7 Designs Co-verification (ARM7) • DO-254 Verification Solution • Actel RTAX-S/SL
    [Show full text]
  • Pulsonix Design System V11.0 Update Notes
    Pulsonix Design System V11.0 Update Notes 2 Pulsonix Version 11.0 Update Notes Copyright Notice Copyright ã WestDev Ltd. 2000-2021 Pulsonix is a Trademark of WestDev Ltd. All rights reserved. E&OE Copyright in the whole and every part of this software and manual belongs to WestDev Ltd. and may not be used, sold, transferred, copied or reproduced in whole or in part in any manner or in any media to any person, without the prior written consent of WestDev Ltd. If you use this manual you do so at your own risk and on the understanding that neither WestDev Ltd. nor associated companies shall be liable for any loss or damage of any kind. WestDev Ltd. does not warrant that the software package will function properly in every hardware software environment. Although WestDev Ltd. has tested the software and reviewed the documentation, WestDev Ltd. makes no warranty or representation, either express or implied, with respect to this software or documentation, their quality, performance, merchantability, or fitness for a particular purpose. This software and documentation are licensed 'as is', and you the licensee, by making use thereof, are assuming the entire risk as to their quality and performance. In no event will WestDev Ltd. be liable for direct, indirect, special, incidental, or consequential damage arising out of the use or inability to use the software or documentation, even if advised of the possibility of such damages. WestDev Ltd. reserves the right to alter, modify, correct and upgrade our software programs and publications without notice and without incurring liability.
    [Show full text]
  • Integrated Schematic and PCB Design
    Integrated Schematic and PCB ™ Design - CADSTAR Basic TOP FEATURES AND BENEFITS Introduction CADSTAR Basic is Zuken’s integrated schematic and PCB design solution that provides layout specialists with a comprehensive toolset for integrated 3D MCAD/ • 3D-MCAD/ECAD integration with IDF ECAD design. interface. CADSTAR is an intuitive Windows based program that is easy-to-use, fast and • Variant Manager allows one design to reduces design errors, helping you deliver effective designs in less time. cover many application requirements or With industrial-strength technology from Zuken, one of the longest established target markets. suppliers in EDA, it has the breadth of capability and power you need to address today’s demanding design challenges. • Shorter time-to-market with the intuitive Fluent™ GUI, configurable CADSTAR provides extensive functionality and performance at an affordable price. menus, toolbars and macros. One third of the world’s PCBs are designed using Zuken tools - why not join them? • A scalable design solution that offers total flexibility to design simple or complex PCBs. • Faster, more efficient design with block reuse and intelligent copy/paste to extract the maximum value from your design archive. • Can be integrated with your corporate MRP/ERP via the ODBC-compliant database parts library. • Unparalleled interactive and automatic placement and routing with on-line DRC. • Outstanding performance, completion and manufacturability. • Complete range of manufacturing formats. CADSTAR Basic - Comprehensive integrated schematic and PCB design toolset incorporating integrated 3D MCAD/ECAD design. zuken.com/cadstar A Familiar, Customisable, Powerful G.U.I. Integrated System Design Founded on the Microsoft® Office Fluent™ user interface, CADSTAR’s true connective data structure ensures that familiar to millions of PC users worldwide, the CADSTAR copy and paste intelligently re-assigns net names and G.U.I.
    [Show full text]
  • Tradeoffs in Multicomputer Architecture
    The Meerkat Multicomputer: Tradeoffs in Multicomputer Architecture by Robert C. Bedichek A dissertation submitted in partial ful®llment of the requirements for the degree of Doctor of Philosophy University of Washington 1994 Approved by (Co-Chairperson of Supervisory Committee) (Co-Chairperson of Supervisory Committee) Program Authorized to Offer Degree Date In presenting this dissertation in partial ful®llment of the requirements for the Doctoral degree at the University of Washington, I agree that the Library shall make its copies freely available for inspection. I further agree that extensive copying of this dissertation is allowable only for scholarly purposes, consistent with ªfair useº as prescribed in the U.S. Copyright Law. Requests for copying or reproduction of this dissertation may be referred to University Micro®lms, 1490 Eisenhower Place, P.O. Box 975, Ann Arbor, MI 48106, to whom the author has granted ªthe right to reproduce and sell (a) copies of the manuscript in microform and/or (b) printed copies of the manuscript made from microform.º Signature Date University of Washington Abstract The Meerkat Multicomputer: Tradeoffs in Multicomputer Architecture by Robert C. Bedichek Co-Chairpersons of Supervisory Committee: Professor Henry M. Levy Professor Edward D. Lazowska Department of Computer Science and Engineering A central problem preventing the wide application of distributed memory multicomputers has been their high price, especially for small installations. High prices are due to long design times, support for scaling to thousands of nodes, and high production costs. This thesis demonstrates a new approach that combines some carefully chosen restrictions on scaling with a software-intensive methodology.
    [Show full text]
  • Altium Designer Feature Set Summary
    Altium Designer Feature Set Summary Updated March 2013 Altium Designer is available in license options that maximize your choices and make accessing Altium Designer flexible. Whether you are part of a large design team or a consulting engineer operating on your own, Altium Designer presents everything you need to innovate, be competitive and design new products in new ways. Altium Designer 2013 lets designers create a product from concept to manufacture, in a single design environment, embracing hardware, software and programmable hardware (FPGAs). If your design team has engineers who don’t do board implementation but are capturing and verifying the design, implementing systems on FPGAs and specifying the board, choose Altium Designer SE. Altium Designer Altium Designer Altium Designer Altium Designer Feature Description 2013 Viewer 2013 SD 2013 SE 2013 Software integration platform, consistent GUI provided for all supporting editors and viewers, Design DXP Platform Insight for design document preview, design release management, design compiler, file management, P P P version control interface and scripting engine Schematic – Viewer Open, view and print schematic documents and libraries P P P P PCB – Viewer Open, view and print PCB documents, additionally view and navigate 3D PCBs P P P P CAM File – Viewer Open CAM and mechanical files P P P P All schematic and schematic library editing capabilities (except in PCB Projects and Free Documents), Schematic – Soft Design Editing P netlist generation P P VHDL simulation engine, integrated
    [Show full text]