V-6

ADVANCED ONE MICRON BICMOS TECHNOLOGY FOR HIGH SPEED 256K SRAMS

B. Bastani, C. Lage, L. Wong, J. Small, R. Lahri, L. Bouknight, T. Bowman, J. Manoliu, P. Tuntasood BiCMOS Integration, Unit Process Development, Device Physics, and Design Groups

Fairchild

Puyallup, WA 98373 INTRODUCTION for a high density interconnect technology and The MOS technology produces the most straight near planar metal-l topography. A sandwiched forward and the highest density memory array for Al-Si-Cu barrier metallurgy produces a reliable SRAM technology. The ECL process, however, dom- and hillock-free interconnect system. The same inates the high performance arena at the cost of metallurgy is used for the second layer metal. power dissipation and density. A well orchestra- Fig. 2 shows a SEM cross section of the 256K ted combination of these two technologies with memory array where compacted bird's beak, poly 1, proper design methodology results in high speed poly 2, and the metal-2 layer on a planarized memories and logic products with specific per- surface are featured. tormance targets that neither technology could DEVICE CHARACTERISTICS deliver alone (l)-(3). It is for such applica- a) MOSFET tions that BiCMOS technology provides the opti- The impurity profiles for N- and P- channel mum solution. In this paper an advanced one MOSFET are illustrated in Fig. 3. The P- buried micron BiCMOS technology optimized for a high layer shunts the MOSFET parasitic source-drain speed 256K SRAM is described. optimi- lateral bipolar transistor. As a result, the im- zations for MOSFET and bipolar devices are pre- pact-ionization induced breakdown for even sub- sented herein. Ring oscillators, memory array half micron N-MOSFET, is highly suppressed. The and functional subcircuits have been fabricated punchthrough voltage versus the effective chan- to verify the performance of the technology. nel length for the illustrated profiles are TECHNOLOGY given in Fig. 4. A minimum effective channel The one micron BiCMOS process is an optimized length of .6pm for N- channel and .7pm for P- 16 mask, double poly Si, double metal sequence. channel are representative of this process. Figure 1 illustrates a cross section of the de- b) BIPOLAR TRANSISTOR vice. Tables I and II outline the processing se- Two approaches were investigated for the bipolar quence and key technology features respectively. transistor involving As and P dopants to form Self-aligned twin buried layer initially defines the poly emitter. The phosphorous disadvantage the N-channel, P-channel, and bipolar device is a deeper emitter junction (0.22pm) compared areas. The P- buried layer results in improved to arsenic (0.12pm). The P advantage, however, isolation spacing, N-MOSFET performance, and is a lower emitter interfacial series resistance soft error immunity. The N+ buried layer is of 90 0112 as opposed to 250 o-p2. Typical poly formed by As implantation. The lower activation emitter bipolar characteristics are shown in temperature required for As compared to more Fig. 5. Flat hfe characteristics over 4 decades conventional Sb doping reduces collector side- of collector current and excellent ICEO behavior wall capacitance and allows higher performance are evidenced. bipolar to be achieved. c) RING OSCILLATOR A 1.5 micron intrinsic reduced pressure epi is CMOS, ECL and BiCMOS ring oscillators under grown on top of the twin buried layers. Self- various loading conditions were used to bench- aligned twin N- and P- wells are formed in this mark the technology. Table III shows gate delays thin epi layer. Active regions are formed by an under unloaded and loaded conditions. optimized LOCOS process resulting in less than RELIABILITY 0.3pm bird's beaks. Electromigration: MTTF in excess of 200 years LDD MOSFET devices are fabricated with 200 A were achieved for the barrier metallurgy at M-1 gate oxide. A processing sequence of LDD im- design rules. plant, HTO spacer oxide formation, N+ S/D and Soft Error: A 3X reduction in charge collection anneal, bipolar base implant, and P+ S/D implant was achieved at N+ nodes as a result of P+ bur- complete the MOSFET and partial bipolar trans- ied layer. sitor formations. 256K SRAM The emitter window for the bipolar transistor is A symmetric.96p2 NMOS with a poly- opened in the HTO interpoly dielectric prior to silicon load is used for the static RAM array. poly 2 deposition. The butting contact in the Extensive use of ECL circuitry provides the memory array is also formed in this process basis for a high speed design. The 256K SRAM is step: Various bipolar optimization approaches organized in a 16K modular format. Fig. 6 shows have been exercised at the emitter formation in a die layout photograph of a 16K SRAM. order to reduce poly emitter interface resis- SUMMARY tance, base resistance and junction capacitances. One micron BiCMOS technology for high speed 256K LPCVD BPSG glass technology is utilized to mini- SEAM is developed. Advanced lithography and pro- mize thermal process history in the formation of cessing techniques support high density CMOS device interconnects. Low temperature reflow design with ECL performance. This technology is characteristics of an optimized BPSG film provide also extended to logic applications.

41 ThBLE I PROCESS SEQUENCE OUTLINE TABLE XX KEY TECHNOLOGY FEATURES o tswin buried layer o interpoly contact/emitter o 16 masks o 0.8pm resol. 5X stepper o twin well o poly 2 o optimized LOCOS o 0.9±m isolation spacing o LOCOS isolation o emitter/ implant o 200 A gate oxide o LDRAIN = l.l"'m o poly 1 o contact o double poly Si o 2.2pm poly pitch o LDD o metal-1 o double metal o 2.5pm metal-1 pitch o n+ S/D implant o via o l.lXl.llxm contacts o l.lXl.lum vias o base o metal-2 TABLE III GATE DELAYS

______o p_ S/D implant o topside passivation Unloaded 0.5 pf ______CMOS 165ps 540ps ECL 250ps 320ps BiCQIOS 28ODs 380ps REFERENCES 1) N. Nishio, et al; ICCD 1984 ==vNe== 2) A. Watanabe, et al; IEDM 1985 N* ,, GUEES3) A.R. Alvarez, et al;IEDM 1984 *..FIGURES

P L.".. *_ "'"^.."i i) Schematic device cross-section "WnG I Memory array cross-section ..\ c 2) SEN FIG I 3) N- and P-channel impurity profiles 4) tiOSFET punchthrough vs LEFF 5)Poly-emirter bipolar characteristics 6) Layout photograph of 16K die 1 MOSFET 1.5 t1I i.2 1 0.9 I 0.6 ra rI I-^" 0.3 4 .' S Pi:11 .S' LA I 0 -0.3 I I I -0.6 I II 1 I I I .0., I I I I I I FIG31 ti: -1.2 04 I 1,-I I F0 I 3.. -1.9 . . 0 ..9 9.I 5.9 u.s t. t.5 t. 0.3 0O 0.9 1.2 IiS 1.6 2.1 2.4 PEmCltN CHANE LENGJ

Ie-09 GUMhEL PLOT IE-01 250.05.00 HFE

d.od. 25. /d 1. d4=odvldle ,di,.OC 'C 'B- FIG5

IE-i2I *E1t. FIG6 . aOi o5 -1. 500 IE-09 IC C A) VE . ISO/div ( V) d.cod./dIv

FIG2- -% _* _ _ 0~~~~~~~~~~~~~ _~~~~~~~'#e

42