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Building an IEEE-1394 Communication Module for Your

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Building an IEEE-1394 Communication Module for Your by Romualdo Santamaria (Editor’s note – This is a continua- tion of the article “De-Mystifying IEEE-1394: an inside-out look at 1394 the final payload destination address of 1394 software layers and the soft- There are two methods of 1394 data the message is indicated in the packet ware interaction between them” communication: asynchronous and header for all write actions. In the case that appeared in the January 2001 isochronous. Asynchronous is the of a read request, the header of the mes- CompactPCI Systems Magazine) scheme that implements bus-like trans- sage contains the memory location actions. The transactions are read, write, address where data was retrieved. and lock (lock is the “compare and As computer systems get faster and swap” transaction). The asynchronous Asynchronous transactions are based on faster, we are seeing increased levels of communication scheme does not have a request response. For example, if node performance. Calculation power is no any time restrictions, which means that A wishes to read data from a certain longer an issue. In fact, the key prob- while the delivery time of a message is memory space in node B, node A sends lem is the transport of data between the not guaranteed, the physical delivery of a read request to node B. In the header acquisition devices and the computer the message is. of the read request packet, node A spec- systems. ifies the address where the data may be All 1394 messages are prefixed by a retrieved and how much data may be A variety of communication systems header, which is where the nodes find returned, the response destination are available on the market, but when the information they need to execute the address and a label to match the request you compare price, performance, and transaction. Every message on the 1394 and response actions. availability, the choice is obvious. bus is broadcast to all other nodes. Upon IEEE-1394 is a high-speed serial bus receipt of a message, the destination Isochronous communication uses chan- designed for mass-market applications. address contained in the message nel-based communication. This means This communication system is very header is compared with the node that a node sending isochronoous mes- well adapted for mass-market prod- address by the link layer. If the destina- sages will broadcast the messages using ucts, industrial control, data acquisi- tion address matches the receiver node a channel number as a message discrim- tion and even aerospace purposes. The address or the broadcast address, the inator. The nodes wishing to receive the 1394 serial bus is designed to trans- packet is accepted. Otherwise, it is information just have to accept the port data at bandwidths of 100, 200, rejected. incoming messages with the desired and 400 Mbits/sec. With functionality channel number. comparable to buses like the PCI or In the event where the message is VME, this serial communication accepted or rejected because an com- In order to initiate isochronous commu- scheme also boasts streaming capabili- munication error, the receiving node nication, there must be one node in the ties and the ability to connect up to 63 acknowledges receiving the packet to system to synchronize the bus. This devices within a distance of 4.5m the sender. This gives the sender the node is called the cycle master. Every between nodes. Devices can be simple chance to react if an error has occurred. 125ms, this node broadcasts a packet 1394 nodes such as digital cameras, known as a cycle start packet. After hard drives or printers, or much more For every packet received using the receiving this packet, the nodes wishing complex devices such as PCI or VME asynchronous communication scheme to send isochronous information are buses equipped with microprocessors (with the exception of broadcast com- allowed to do so until all the nodes have and peripherals. The design considera- munications), an acknowledgement sent all their isochronous data. Only tions for a simple 1394 node used for message is sent from the receiver to the one instance of each channel is allowed data acquisition or control will be cov- sender. This acknowledgement message per 125ms isochronous cycle. This ered in this article. We begin with an indicates either that the message has enables one talker and several listeners explanation of the 1394 bus and some successfully reached its destination or per channel, with the maximum number of the chipsets found on the market, that it must be retried. of channels being 64. then explain how to choose a chipset and review the various required soft- Another important element of the asyn- To achieve isochronous communication, ware layers. chronous communication scheme is that the talker must request a channel num- Copyright 2001 CompactPCI Systems Reprinted from CompactPCI Systems / July-August 2001 ber and have the appropriate bandwidth with two ports, the end user will be lim- Software layer allocated. Once the reservation has been ited to a daisy chain topology. Devices The software layer is a vital component made, the node can begin sending with more than two ports offer a more of the system, so be sure to make an isochronous messages. The isochronous flexible tree topology. informed decision when selecting the communication scheme does not include 1394 modules that will be supported by an acknowledgement message sent by Link layer interface your device. the receiver. The packet delivery is not There are three types of link layer guaranteed; however, the bus timing and adapters for the host bus interface: PCI For the purposes of this article, only the bandwidth allocation are. interfaces, generic bus interfaces, and transaction layer for the asynchronous generic bus interfaces with a direct responder will be implemented (mean- The acquisition cadence in most data embedded connection to the 1394 bus. ing that the module will be slaves on the acquisition systems is fixed and must bus for all asynchronous transactions). be guaranteed. In keeping with this We will be using the TSB12LV32, a requirement, we will use isochronous generic bus interface with a direct CSR is the minimum set of control and communication to transmit the acquired embedded connection to the 1394 bus, status registers. ROM can be defined as data and asynchronous communication known as the Data Mover bus. the room used to identify the acquisition to control the acquisition module. module and specify the functionalities The TSB12LV32 is a general purpose that are supported. Chipset link layer composed of a generic pro- Our implementation will feature a TSB- cessor bus connected to a micro-con- In order to simplify the design, the cycle 12LV32 link layer and a TSB41LV03 troller host. The processor receives both manager, isochronous resource manager physical layer microchip from Texas asynchronous and isochronous traffic and bus manager will not be supported. Instruments. and transmits the asynchronous packets through the generic bus. All the packets Global system functionality Physical layer interface being transmitted via the processor are When initializing a simple node, it is It is important to define your future treated by the software, which is well possible to work with a minimal trans- requirements when choosing a physical adapted to control the data acquisition action layer, CSR, and ROM. As for the layer chip. If you only require a band- system (the control messages are not application running on the node, we width of 100 Mbits/sec, there is no need time-sensitive). only have to map the data acquisition for a 400 Mbits/sec physical layer. ports on the 1394 bus when configuring However, when taking a closer look We have chosen the Data Mover port to the transaction layer. The host computer at the pricing for these chips shows demonstrate the acquisition of high- simply sends a read request to the node that the 400 Mbits/sec physical layer speed data, as we don’t want the process at the address of the acquisition when- chips are less expensive, more readily to be delayed by the processor due to ever it requires data. The node will then available and most importantly, have software running on the board. return a response packet with the fewer bugs because they are newer. requested data. Furthermore, all service is based on The Data Mover port works in a very these newer parts. simple manner. Being a unidirectional This very simple acquisition node can port, the processor initializes the direc- be implemented using a tiny 8-bit Also don’t forget to consider the total tion of the port and the headers of the micro-controller with the addition of a bandwidth of the system when making packets on the link layer registers. Once 1394 link and physical layers. a decision. If you are already using most completed, the Data Mover is ready to of the bus’ bandwidth, and you need to transmit data on the 1394 bus. To obtain high-speed data acquisition at add more 1394 nodes, you won’t go a regular cadence, the Data Mover can very far at 100 Mbits/sec! The data acquisition hardware tells the be used to grab data and send it via Data Mover when the data packets are isochronous communication. This only There is a wide variety of chips on the ready to be transmitted. With the help of requires a small modification to the market and physical layers with 1, 2, 3, various handshake hardware signals, the node. We will map the Data Mover reg- or 6 ports. link layer requests the arbitration of the isters on the 1394 bus, thereby giving bus then sends the header information, the host complete control of the trans- Selecting the appropriate chip depends and fetches the packet’s data coming mitting isochronous channel.
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