Computer Architecture Binary data
S. Coudert R. Pacalet
Telecom Paris
2021-09-23
1 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Outline
1 Introduction 2 Processing binary data
3 Addresses and address spaces
2 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Section 1
Introduction
3 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Buses: sets of wires Memory data: sets of memory cells Ordered bit sets represent numbers in binary form
Electric potential difference with reference Two main voltage levels: ground, power supply • Ground (reference, zero volt): 0 / false • Power supply (e.g. ≈ one volt): 1 / true o Intermediate or unstable voltages also exists
From bits to numbers
Digital world is binary
From voltage to bits Wires/memory elements carry/store voltages
4 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Buses: sets of wires Memory data: sets of memory cells Ordered bit sets represent numbers in binary form
Two main voltage levels: ground, power supply • Ground (reference, zero volt): 0 / false • Power supply (e.g. ≈ one volt): 1 / true o Intermediate or unstable voltages also exists
From bits to numbers
Digital world is binary
From voltage to bits Wires/memory elements carry/store voltages Electric potential difference with reference
4 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Buses: sets of wires Memory data: sets of memory cells Ordered bit sets represent numbers in binary form
o Intermediate or unstable voltages also exists
From bits to numbers
Digital world is binary
From voltage to bits Wires/memory elements carry/store voltages Electric potential difference with reference Two main voltage levels: ground, power supply • Ground (reference, zero volt): 0 / false • Power supply (e.g. ≈ one volt): 1 / true
4 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Buses: sets of wires Memory data: sets of memory cells Ordered bit sets represent numbers in binary form
From bits to numbers
Digital world is binary
From voltage to bits Wires/memory elements carry/store voltages Electric potential difference with reference Two main voltage levels: ground, power supply • Ground (reference, zero volt): 0 / false • Power supply (e.g. ≈ one volt): 1 / true o Intermediate or unstable voltages also exists
4 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Memory data: sets of memory cells Ordered bit sets represent numbers in binary form
Digital world is binary
From voltage to bits Wires/memory elements carry/store voltages Electric potential difference with reference Two main voltage levels: ground, power supply • Ground (reference, zero volt): 0 / false • Power supply (e.g. ≈ one volt): 1 / true o Intermediate or unstable voltages also exists
From bits to numbers Buses: sets of wires
4 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Ordered bit sets represent numbers in binary form
Digital world is binary
From voltage to bits Wires/memory elements carry/store voltages Electric potential difference with reference Two main voltage levels: ground, power supply • Ground (reference, zero volt): 0 / false • Power supply (e.g. ≈ one volt): 1 / true o Intermediate or unstable voltages also exists
From bits to numbers Buses: sets of wires Memory data: sets of memory cells
4 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Digital world is binary
From voltage to bits Wires/memory elements carry/store voltages Electric potential difference with reference Two main voltage levels: ground, power supply • Ground (reference, zero volt): 0 / false • Power supply (e.g. ≈ one volt): 1 / true o Intermediate or unstable voltages also exists
From bits to numbers Buses: sets of wires Memory data: sets of memory cells Ordered bit sets represent numbers in binary form
4 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Become familiar with them Widely used in computer science
Digital world is binary
Goals of this lecture Discover low level and more abstract binary representations
5 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Widely used in computer science
Digital world is binary
Goals of this lecture Discover low level and more abstract binary representations Become familiar with them
5 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Digital world is binary
Goals of this lecture Discover low level and more abstract binary representations Become familiar with them Widely used in computer science
5 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Pi=k−1 i ⇒ Dk−1...D1D0 denotes number i=0 Di × N o Non-ambiguous interpretation requires knowledge of base
Usually 0, . . . , 9 for first ten symbols, then A, B. . . if needed Let D0, ..., Dk−1 be k symbols in base N
Unsigned numbers
From strings to numbers Base N: N symbols α, β... associated to values zero, one. . .
6 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Pi=k−1 i ⇒ Dk−1...D1D0 denotes number i=0 Di × N o Non-ambiguous interpretation requires knowledge of base
Let D0, ..., Dk−1 be k symbols in base N
Unsigned numbers
From strings to numbers Base N: N symbols α, β... associated to values zero, one. . . Usually 0, . . . , 9 for first ten symbols, then A, B. . . if needed
6 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Pi=k−1 i ⇒ Dk−1...D1D0 denotes number i=0 Di × N o Non-ambiguous interpretation requires knowledge of base
Unsigned numbers
From strings to numbers Base N: N symbols α, β... associated to values zero, one. . . Usually 0, . . . , 9 for first ten symbols, then A, B. . . if needed Let D0, ..., Dk−1 be k symbols in base N
6 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data o Non-ambiguous interpretation requires knowledge of base
Unsigned numbers
From strings to numbers Base N: N symbols α, β... associated to values zero, one. . . Usually 0, . . . , 9 for first ten symbols, then A, B. . . if needed Let D0, ..., Dk−1 be k symbols in base N Pi=k−1 i ⇒ Dk−1...D1D0 denotes number i=0 Di × N
6 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Unsigned numbers
From strings to numbers Base N: N symbols α, β... associated to values zero, one. . . Usually 0, . . . , 9 for first ten symbols, then A, B. . . if needed Let D0, ..., Dk−1 be k symbols in base N Pi=k−1 i ⇒ Dk−1...D1D0 denotes number i=0 Di × N o Non-ambiguous interpretation requires knowledge of base
6 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Base eleven (symbols 0, 1. . . , 9, A) 2 1 0 34211 = 3 × 1011 + 4 × 1011 + 2 × 1011 2 1 = 3 × 1110 + 4 × 1110 + 2 = 3 × 12110 + 4 × 1110 + 2 = 40910 Base two (bits 0, 1) 02 = 010, 12 = 110, 102 = 210, 112 = 310, 1002 = 410, 1012 = 510... ɳ Decimal value of 3426?
Unsigned numbers
Example Base ten (digits 0, 1. . . , 9) 2 1 0 34210 = 3 × 10 + 4 × 10 + 2 × 10 = 3 × 100 + 4 × 10 + 2
7 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Base two (bits 0, 1) 02 = 010, 12 = 110, 102 = 210, 112 = 310, 1002 = 410, 1012 = 510... ɳ Decimal value of 3426?
Unsigned numbers
Example Base ten (digits 0, 1. . . , 9) 2 1 0 34210 = 3 × 10 + 4 × 10 + 2 × 10 = 3 × 100 + 4 × 10 + 2 Base eleven (symbols 0, 1. . . , 9, A) 2 1 0 34211 = 3 × 1011 + 4 × 1011 + 2 × 1011 2 1 = 3 × 1110 + 4 × 1110 + 2 = 3 × 12110 + 4 × 1110 + 2 = 40910
7 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ɳ Decimal value of 3426?
Unsigned numbers
Example Base ten (digits 0, 1. . . , 9) 2 1 0 34210 = 3 × 10 + 4 × 10 + 2 × 10 = 3 × 100 + 4 × 10 + 2 Base eleven (symbols 0, 1. . . , 9, A) 2 1 0 34211 = 3 × 1011 + 4 × 1011 + 2 × 1011 2 1 = 3 × 1110 + 4 × 1110 + 2 = 3 × 12110 + 4 × 1110 + 2 = 40910 Base two (bits 0, 1) 02 = 010, 12 = 110, 102 = 210, 112 = 310, 1002 = 410, 1012 = 510...
7 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Unsigned numbers
Example Base ten (digits 0, 1. . . , 9) 2 1 0 34210 = 3 × 10 + 4 × 10 + 2 × 10 = 3 × 100 + 4 × 10 + 2 Base eleven (symbols 0, 1. . . , 9, A) 2 1 0 34211 = 3 × 1011 + 4 × 1011 + 2 × 1011 2 1 = 3 × 1110 + 4 × 1110 + 2 = 3 × 12110 + 4 × 1110 + 2 = 40910 Base two (bits 0, 1) 02 = 010, 12 = 110, 102 = 210, 112 = 310, 1002 = 410, 1012 = 510... ɳ Decimal value of 3426?
7 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Negate not simple: flip all bits (one’s complement), add 1 Addition and subtraction simple (no tests) Multiplication a bit more complicated
Negate ultra-simple: flip sign bit Addition/subtraction not simple (tests, need of both) Multiplication simple k Pi=k−2 i Two’s complement: −2 × Dk−1 + i=0 Di × 2
Signed numbers
Two main representations Dk−1 Pi=k−2 i Sign and magnitude: (−1) × i=0 Di × 2
8 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Negate not simple: flip all bits (one’s complement), add 1 Addition and subtraction simple (no tests) Multiplication a bit more complicated
Addition/subtraction not simple (tests, need of both) Multiplication simple k Pi=k−2 i Two’s complement: −2 × Dk−1 + i=0 Di × 2
Signed numbers
Two main representations Dk−1 Pi=k−2 i Sign and magnitude: (−1) × i=0 Di × 2 Negate ultra-simple: flip sign bit
8 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Negate not simple: flip all bits (one’s complement), add 1 Addition and subtraction simple (no tests) Multiplication a bit more complicated
Multiplication simple k Pi=k−2 i Two’s complement: −2 × Dk−1 + i=0 Di × 2
Signed numbers
Two main representations Dk−1 Pi=k−2 i Sign and magnitude: (−1) × i=0 Di × 2 Negate ultra-simple: flip sign bit Addition/subtraction not simple (tests, need of both)
8 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Negate not simple: flip all bits (one’s complement), add 1 Addition and subtraction simple (no tests) Multiplication a bit more complicated
k Pi=k−2 i Two’s complement: −2 × Dk−1 + i=0 Di × 2
Signed numbers
Two main representations Dk−1 Pi=k−2 i Sign and magnitude: (−1) × i=0 Di × 2 Negate ultra-simple: flip sign bit Addition/subtraction not simple (tests, need of both) Multiplication simple
8 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Negate not simple: flip all bits (one’s complement), add 1 Addition and subtraction simple (no tests) Multiplication a bit more complicated
Signed numbers
Two main representations Dk−1 Pi=k−2 i Sign and magnitude: (−1) × i=0 Di × 2 Negate ultra-simple: flip sign bit Addition/subtraction not simple (tests, need of both) Multiplication simple k Pi=k−2 i Two’s complement: −2 × Dk−1 + i=0 Di × 2
8 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Addition and subtraction simple (no tests) Multiplication a bit more complicated
Signed numbers
Two main representations Dk−1 Pi=k−2 i Sign and magnitude: (−1) × i=0 Di × 2 Negate ultra-simple: flip sign bit Addition/subtraction not simple (tests, need of both) Multiplication simple k Pi=k−2 i Two’s complement: −2 × Dk−1 + i=0 Di × 2 Negate not simple: flip all bits (one’s complement), add 1
8 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Multiplication a bit more complicated
Signed numbers
Two main representations Dk−1 Pi=k−2 i Sign and magnitude: (−1) × i=0 Di × 2 Negate ultra-simple: flip sign bit Addition/subtraction not simple (tests, need of both) Multiplication simple k Pi=k−2 i Two’s complement: −2 × Dk−1 + i=0 Di × 2 Negate not simple: flip all bits (one’s complement), add 1 Addition and subtraction simple (no tests)
8 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Signed numbers
Two main representations Dk−1 Pi=k−2 i Sign and magnitude: (−1) × i=0 Di × 2 Negate ultra-simple: flip sign bit Addition/subtraction not simple (tests, need of both) Multiplication simple k Pi=k−2 i Two’s complement: −2 × Dk−1 + i=0 Di × 2 Negate not simple: flip all bits (one’s complement), add 1 Addition and subtraction simple (no tests) Multiplication a bit more complicated
8 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ɳ Imagine the ten’s complement ɳ What is the set of representable 4-bits integers? ɳ −310 and 910 on 4 bits ɳ −310 and 910 on 8 bits ɳ How to extend from n bits to n+k bits? ɳ Explain addition and subtraction
Exercise: Two’s complement
Check your understanding of two’s complement ɳ Prove the two’s complement negate
9 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ɳ What is the set of representable 4-bits integers? ɳ −310 and 910 on 4 bits ɳ −310 and 910 on 8 bits ɳ How to extend from n bits to n+k bits? ɳ Explain addition and subtraction
Exercise: Two’s complement
Check your understanding of two’s complement ɳ Prove the two’s complement negate ɳ Imagine the ten’s complement
9 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ɳ −310 and 910 on 4 bits ɳ −310 and 910 on 8 bits ɳ How to extend from n bits to n+k bits? ɳ Explain addition and subtraction
Exercise: Two’s complement
Check your understanding of two’s complement ɳ Prove the two’s complement negate ɳ Imagine the ten’s complement ɳ What is the set of representable 4-bits integers?
9 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ɳ −310 and 910 on 8 bits ɳ How to extend from n bits to n+k bits? ɳ Explain addition and subtraction
Exercise: Two’s complement
Check your understanding of two’s complement ɳ Prove the two’s complement negate ɳ Imagine the ten’s complement ɳ What is the set of representable 4-bits integers? ɳ −310 and 910 on 4 bits
9 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ɳ How to extend from n bits to n+k bits? ɳ Explain addition and subtraction
Exercise: Two’s complement
Check your understanding of two’s complement ɳ Prove the two’s complement negate ɳ Imagine the ten’s complement ɳ What is the set of representable 4-bits integers? ɳ −310 and 910 on 4 bits ɳ −310 and 910 on 8 bits
9 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ɳ Explain addition and subtraction
Exercise: Two’s complement
Check your understanding of two’s complement ɳ Prove the two’s complement negate ɳ Imagine the ten’s complement ɳ What is the set of representable 4-bits integers? ɳ −310 and 910 on 4 bits ɳ −310 and 910 on 8 bits ɳ How to extend from n bits to n+k bits?
9 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Exercise: Two’s complement
Check your understanding of two’s complement ɳ Prove the two’s complement negate ɳ Imagine the ten’s complement ɳ What is the set of representable 4-bits integers? ɳ −310 and 910 on 4 bits ɳ −310 and 910 on 8 bits ɳ How to extend from n bits to n+k bits? ɳ Explain addition and subtraction
9 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ɳ 4th bit (from right) in 8 bit memory cell containing 9710? Ë 01100001 Not really human-readable 2134: 100001010110, 69497: 10000111101111001
• Hexadecimal, 16 symbols: 0, . . . , 9, A, B, C, D, E, F (A16 = 1010, ..., F16 = 1510) • Frequent notation (C language): 0xA3F690D • Octal, 8 symbols: 0, . . . , 7. Notation: 042075
Translating to/from base 2 difficult 9: 1001, 14: 1110, 237: 11101101 ɳ 4th bit (from right) in 8 bit memory cell containing 9710? ɳ Use base two?
Frequent trade-offs
Notations
Human readable or close to hardware (binary)? ɳ Simply use base ten and avoid headache?
10 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ɳ 4th bit (from right) in 8 bit memory cell containing 9710? Ë 01100001 Not really human-readable 2134: 100001010110, 69497: 10000111101111001
• Hexadecimal, 16 symbols: 0, . . . , 9, A, B, C, D, E, F (A16 = 1010, ..., F16 = 1510) • Frequent notation (C language): 0xA3F690D • Octal, 8 symbols: 0, . . . , 7. Notation: 042075
9: 1001, 14: 1110, 237: 11101101 ɳ 4th bit (from right) in 8 bit memory cell containing 9710? ɳ Use base two?
Frequent trade-offs
Notations
Human readable or close to hardware (binary)? ɳ Simply use base ten and avoid headache? Translating to/from base 2 difficult
10 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ɳ 4th bit (from right) in 8 bit memory cell containing 9710? Ë 01100001 Not really human-readable 2134: 100001010110, 69497: 10000111101111001
• Hexadecimal, 16 symbols: 0, . . . , 9, A, B, C, D, E, F (A16 = 1010, ..., F16 = 1510) • Frequent notation (C language): 0xA3F690D • Octal, 8 symbols: 0, . . . , 7. Notation: 042075
ɳ 4th bit (from right) in 8 bit memory cell containing 9710? ɳ Use base two?
Frequent trade-offs
Notations
Human readable or close to hardware (binary)? ɳ Simply use base ten and avoid headache? Translating to/from base 2 difficult 9: 1001, 14: 1110, 237: 11101101
10 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ɳ 4th bit (from right) in 8 bit memory cell containing 9710? Ë 01100001 Not really human-readable 2134: 100001010110, 69497: 10000111101111001
• Hexadecimal, 16 symbols: 0, . . . , 9, A, B, C, D, E, F (A16 = 1010, ..., F16 = 1510) • Frequent notation (C language): 0xA3F690D • Octal, 8 symbols: 0, . . . , 7. Notation: 042075
ɳ Use base two?
Frequent trade-offs
Notations
Human readable or close to hardware (binary)? ɳ Simply use base ten and avoid headache? Translating to/from base 2 difficult 9: 1001, 14: 1110, 237: 11101101 ɳ 4th bit (from right) in 8 bit memory cell containing 9710?
10 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data • Hexadecimal, 16 symbols: 0, . . . , 9, A, B, C, D, E, F (A16 = 1010, ..., F16 = 1510) • Frequent notation (C language): 0xA3F690D • Octal, 8 symbols: 0, . . . , 7. Notation: 042075
ɳ 4th bit (from right) in 8 bit memory cell containing 9710? Ë 01100001 Not really human-readable 2134: 100001010110, 69497: 10000111101111001 Frequent trade-offs
Notations
Human readable or close to hardware (binary)? ɳ Simply use base ten and avoid headache? Translating to/from base 2 difficult 9: 1001, 14: 1110, 237: 11101101 ɳ 4th bit (from right) in 8 bit memory cell containing 9710? ɳ Use base two?
10 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data • Hexadecimal, 16 symbols: 0, . . . , 9, A, B, C, D, E, F (A16 = 1010, ..., F16 = 1510) • Frequent notation (C language): 0xA3F690D • Octal, 8 symbols: 0, . . . , 7. Notation: 042075
Ë 01100001 Not really human-readable 2134: 100001010110, 69497: 10000111101111001 Frequent trade-offs
Notations
Human readable or close to hardware (binary)? ɳ Simply use base ten and avoid headache? Translating to/from base 2 difficult 9: 1001, 14: 1110, 237: 11101101 ɳ 4th bit (from right) in 8 bit memory cell containing 9710? ɳ Use base two? ɳ 4th bit (from right) in 8 bit memory cell containing 9710?
10 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data • Hexadecimal, 16 symbols: 0, . . . , 9, A, B, C, D, E, F (A16 = 1010, ..., F16 = 1510) • Frequent notation (C language): 0xA3F690D • Octal, 8 symbols: 0, . . . , 7. Notation: 042075
Not really human-readable 2134: 100001010110, 69497: 10000111101111001 Frequent trade-offs
Notations
Human readable or close to hardware (binary)? ɳ Simply use base ten and avoid headache? Translating to/from base 2 difficult 9: 1001, 14: 1110, 237: 11101101 ɳ 4th bit (from right) in 8 bit memory cell containing 9710? ɳ Use base two? ɳ 4th bit (from right) in 8 bit memory cell containing 9710? Ë 01100001
10 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data • Hexadecimal, 16 symbols: 0, . . . , 9, A, B, C, D, E, F (A16 = 1010, ..., F16 = 1510) • Frequent notation (C language): 0xA3F690D • Octal, 8 symbols: 0, . . . , 7. Notation: 042075
2134: 100001010110, 69497: 10000111101111001 Frequent trade-offs
Notations
Human readable or close to hardware (binary)? ɳ Simply use base ten and avoid headache? Translating to/from base 2 difficult 9: 1001, 14: 1110, 237: 11101101 ɳ 4th bit (from right) in 8 bit memory cell containing 9710? ɳ Use base two? ɳ 4th bit (from right) in 8 bit memory cell containing 9710? Ë 01100001 Not really human-readable
10 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data • Hexadecimal, 16 symbols: 0, . . . , 9, A, B, C, D, E, F (A16 = 1010, ..., F16 = 1510) • Frequent notation (C language): 0xA3F690D • Octal, 8 symbols: 0, . . . , 7. Notation: 042075
Frequent trade-offs
Notations
Human readable or close to hardware (binary)? ɳ Simply use base ten and avoid headache? Translating to/from base 2 difficult 9: 1001, 14: 1110, 237: 11101101 ɳ 4th bit (from right) in 8 bit memory cell containing 9710? ɳ Use base two? ɳ 4th bit (from right) in 8 bit memory cell containing 9710? Ë 01100001 Not really human-readable 2134: 100001010110, 69497: 10000111101111001
10 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data • Hexadecimal, 16 symbols: 0, . . . , 9, A, B, C, D, E, F (A16 = 1010, ..., F16 = 1510) • Frequent notation (C language): 0xA3F690D • Octal, 8 symbols: 0, . . . , 7. Notation: 042075
Notations
Human readable or close to hardware (binary)? ɳ Simply use base ten and avoid headache? Translating to/from base 2 difficult 9: 1001, 14: 1110, 237: 11101101 ɳ 4th bit (from right) in 8 bit memory cell containing 9710? ɳ Use base two? ɳ 4th bit (from right) in 8 bit memory cell containing 9710? Ë 01100001 Not really human-readable 2134: 100001010110, 69497: 10000111101111001 Frequent trade-offs
10 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data • Frequent notation (C language): 0xA3F690D • Octal, 8 symbols: 0, . . . , 7. Notation: 042075
Notations
Human readable or close to hardware (binary)? ɳ Simply use base ten and avoid headache? Translating to/from base 2 difficult 9: 1001, 14: 1110, 237: 11101101 ɳ 4th bit (from right) in 8 bit memory cell containing 9710? ɳ Use base two? ɳ 4th bit (from right) in 8 bit memory cell containing 9710? Ë 01100001 Not really human-readable 2134: 100001010110, 69497: 10000111101111001 Frequent trade-offs • Hexadecimal, 16 symbols: 0, . . . , 9, A, B, C, D, E, F (A16 = 1010, ..., F16 = 1510)
10 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data • Octal, 8 symbols: 0, . . . , 7. Notation: 042075
Notations
Human readable or close to hardware (binary)? ɳ Simply use base ten and avoid headache? Translating to/from base 2 difficult 9: 1001, 14: 1110, 237: 11101101 ɳ 4th bit (from right) in 8 bit memory cell containing 9710? ɳ Use base two? ɳ 4th bit (from right) in 8 bit memory cell containing 9710? Ë 01100001 Not really human-readable 2134: 100001010110, 69497: 10000111101111001 Frequent trade-offs • Hexadecimal, 16 symbols: 0, . . . , 9, A, B, C, D, E, F (A16 = 1010, ..., F16 = 1510) • Frequent notation (C language): 0xA3F690D
10 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Notations
Human readable or close to hardware (binary)? ɳ Simply use base ten and avoid headache? Translating to/from base 2 difficult 9: 1001, 14: 1110, 237: 11101101 ɳ 4th bit (from right) in 8 bit memory cell containing 9710? ɳ Use base two? ɳ 4th bit (from right) in 8 bit memory cell containing 9710? Ë 01100001 Not really human-readable 2134: 100001010110, 69497: 10000111101111001 Frequent trade-offs • Hexadecimal, 16 symbols: 0, . . . , 9, A, B, C, D, E, F (A16 = 1010, ..., F16 = 1510) • Frequent notation (C language): 0xA3F690D • Octal, 8 symbols: 0, . . . , 7. Notation: 042075
10 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Octal Relevant for 3-bits groups, e.g. Unix-like permissions Octal 7 5 1 Binary 1 1 1 1 0 1 0 0 1 Text r w x r - x - - x owner group user
Summary Octal 1 7 2 4 Binary 0 0 1 1 1 1 0 1 0 1 0 0 Hexadecimal 3 D 4
Hexadecimal and octal
Hexadecimal Compact: one symbol = 4 bits 8 × 4 = 32 D 8 F 3 7 B 0 9 0 1 1 1
17th bit from left
11 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Summary Octal 1 7 2 4 Binary 0 0 1 1 1 1 0 1 0 1 0 0 Hexadecimal 3 D 4
Hexadecimal and octal
Hexadecimal Octal Compact: one symbol = 4 bits Relevant for 3-bits groups, 8 × 4 = 32 e.g. Unix-like permissions D 8 F 3 7 B 0 9 Octal 7 5 1 0 1 1 1 Binary 1 1 1 1 0 1 0 0 1 Text r w x r - x - - x 17th bit from left owner group user
11 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Hexadecimal and octal
Hexadecimal Octal Compact: one symbol = 4 bits Relevant for 3-bits groups, 8 × 4 = 32 e.g. Unix-like permissions D 8 F 3 7 B 0 9 Octal 7 5 1 0 1 1 1 Binary 1 1 1 1 0 1 0 0 1 Text r w x r - x - - x 17th bit from left owner group user
Summary Octal 1 7 2 4 Binary 0 0 1 1 1 1 0 1 0 1 0 0 Hexadecimal 3 D 4
11 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Coefficients of greatest/smallest power of two By convention binary numbers usually: • Written MSB left, down to LSB right (as humans expect) • Indexed k-1 (MSB) down to 0 (LSB) o This is just a convention, other notations possible Examples 7 0 0 0 1 1 1 1 0 1 high half low half 0 7 1 0 1 1 1 1 0 0 low half high half
Vocabulary
MSB/LSB Most/Least Significant Bit (MSB/LSB)
12 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data By convention binary numbers usually: • Written MSB left, down to LSB right (as humans expect) • Indexed k-1 (MSB) down to 0 (LSB) o This is just a convention, other notations possible Examples 7 0 0 0 1 1 1 1 0 1 high half low half 0 7 1 0 1 1 1 1 0 0 low half high half
Vocabulary
MSB/LSB Most/Least Significant Bit (MSB/LSB) Coefficients of greatest/smallest power of two
12 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data o This is just a convention, other notations possible Examples 7 0 0 0 1 1 1 1 0 1 high half low half 0 7 1 0 1 1 1 1 0 0 low half high half
Vocabulary
MSB/LSB Most/Least Significant Bit (MSB/LSB) Coefficients of greatest/smallest power of two By convention binary numbers usually: • Written MSB left, down to LSB right (as humans expect) • Indexed k-1 (MSB) down to 0 (LSB)
12 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Examples 7 0 0 0 1 1 1 1 0 1 high half low half 0 7 1 0 1 1 1 1 0 0 low half high half
Vocabulary
MSB/LSB Most/Least Significant Bit (MSB/LSB) Coefficients of greatest/smallest power of two By convention binary numbers usually: • Written MSB left, down to LSB right (as humans expect) • Indexed k-1 (MSB) down to 0 (LSB) o This is just a convention, other notations possible
12 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Vocabulary
MSB/LSB Most/Least Significant Bit (MSB/LSB) Coefficients of greatest/smallest power of two By convention binary numbers usually: • Written MSB left, down to LSB right (as humans expect) • Indexed k-1 (MSB) down to 0 (LSB) o This is just a convention, other notations possible Examples 7 0 0 0 1 1 1 1 0 1 high half low half 0 7 1 0 1 1 1 1 0 0 low half high half
12 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Big endian: MSB first (at lowest address) Little endian: LSB first (at lowest address) Example: 0xEB2EF18A in 8-bits memory 31 24 23 16 15 8 7 0 bits (LSB: 0) big EB 2E F1 8A a a + 1 a + 2 a + 3 addresses
7 0 15 8 23 16 31 24 bits (LSB: 0) little 8A F1 2E EB a a + 1 a + 2 a + 3 addresses
Vocabulary
Endianness Memory data at several consecutive addresses
13 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Little endian: LSB first (at lowest address) Example: 0xEB2EF18A in 8-bits memory 31 24 23 16 15 8 7 0 bits (LSB: 0) big EB 2E F1 8A a a + 1 a + 2 a + 3 addresses
7 0 15 8 23 16 31 24 bits (LSB: 0) little 8A F1 2E EB a a + 1 a + 2 a + 3 addresses
Vocabulary
Endianness Memory data at several consecutive addresses Big endian: MSB first (at lowest address)
13 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Example: 0xEB2EF18A in 8-bits memory 31 24 23 16 15 8 7 0 bits (LSB: 0) big EB 2E F1 8A a a + 1 a + 2 a + 3 addresses
7 0 15 8 23 16 31 24 bits (LSB: 0) little 8A F1 2E EB a a + 1 a + 2 a + 3 addresses
Vocabulary
Endianness Memory data at several consecutive addresses Big endian: MSB first (at lowest address) Little endian: LSB first (at lowest address)
13 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Vocabulary
Endianness Memory data at several consecutive addresses Big endian: MSB first (at lowest address) Little endian: LSB first (at lowest address) Example: 0xEB2EF18A in 8-bits memory 31 24 23 16 15 8 7 0 bits (LSB: 0) big EB 2E F1 8A a a + 1 a + 2 a + 3 addresses
7 0 15 8 23 16 31 24 bits (LSB: 0) little 8A F1 2E EB a a + 1 a + 2 a + 3 addresses
13 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ɳ 8710 in bases two, eight, sixteen ɳ F 30616 in base two ɳ F 30816 in base eight ɳ 01100010101011102 in bases eight, sixteen ɳ bit #5 in 8-bits memory cell containing 12310?
Exercise: Number representations
Check your understanding of number representations
ɳ 3010 in base three
14 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ɳ F 30616 in base two ɳ F 30816 in base eight ɳ 01100010101011102 in bases eight, sixteen ɳ bit #5 in 8-bits memory cell containing 12310?
Exercise: Number representations
Check your understanding of number representations
ɳ 3010 in base three ɳ 8710 in bases two, eight, sixteen
14 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ɳ F 30816 in base eight ɳ 01100010101011102 in bases eight, sixteen ɳ bit #5 in 8-bits memory cell containing 12310?
Exercise: Number representations
Check your understanding of number representations
ɳ 3010 in base three ɳ 8710 in bases two, eight, sixteen ɳ F 30616 in base two
14 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ɳ 01100010101011102 in bases eight, sixteen ɳ bit #5 in 8-bits memory cell containing 12310?
Exercise: Number representations
Check your understanding of number representations
ɳ 3010 in base three ɳ 8710 in bases two, eight, sixteen ɳ F 30616 in base two ɳ F 30816 in base eight
14 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ɳ bit #5 in 8-bits memory cell containing 12310?
Exercise: Number representations
Check your understanding of number representations
ɳ 3010 in base three ɳ 8710 in bases two, eight, sixteen ɳ F 30616 in base two ɳ F 30816 in base eight ɳ 01100010101011102 in bases eight, sixteen
14 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Exercise: Number representations
Check your understanding of number representations
ɳ 3010 in base three ɳ 8710 in bases two, eight, sixteen ɳ F 30616 in base two ɳ F 30816 in base eight ɳ 01100010101011102 in bases eight, sixteen ɳ bit #5 in 8-bits memory cell containing 12310?
14 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Section 2
Processing binary data
15 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Bitwise boolean operations
Instruction sets usually contain bitwise operations
x 10111010 y 01011101 not x 01000101 x and y 00011000 x or y 11111111 x xor y 11100111 x shl 2 (shift x left by two positions) 11101000 x shr 2 (shift x right by two positions) 00101110
16 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Bitwise boolean operations
Straightforward hardware implementation
17 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data 8-bit configuration register at address 0xFA01 If bit #i set pin #i output, else input
8-pin Input/Output port
216 − 1 output pins 0 4 1 5 0xFA01 MSB 0 1 0 0 1 0 1 1 LSB 2 6 3 7
address space input pins 0
Bitwise boolean operations, example of use
8-bits CPU with 8 registers R0...R7
Load
18 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data If bit #i set pin #i output, else input
Bitwise boolean operations, example of use
8-bits CPU with 8 registers R0...R7
Load
8-pin Input/Output port 8-bit configuration register at address 0xFA01
216 − 1 output pins 0 4 1 5 0xFA01 MSB 0 1 0 0 1 0 1 1 LSB 2 6 3 7
address space input pins 0
18 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Bitwise boolean operations, example of use
8-bits CPU with 8 registers R0...R7
Load
8-pin Input/Output port 8-bit configuration register at address 0xFA01 If bit #i set pin #i output, else input 216 − 1 output pins 0 4 1 5 0xFA01 MSB 0 1 0 0 1 0 1 1 LSB 2 6 3 7
address space input pins 0
18 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ɳ Configure pin #7 as input ɳ Configure: • pins #2 and #7 as inputs • pin #4 as output • using only one load and one store ɳ Invert all pin states without not instruction?
Check your understanding of bitwise operations
Exercise: Bitwise operations
Configure pin #5 as output, other pins unmodified Load R1 0xFA01 Ori R2 R1 b00100000 // (0x20) Store R2 0xFA01
19 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ɳ Configure: • pins #2 and #7 as inputs • pin #4 as output • using only one load and one store ɳ Invert all pin states without not instruction?
Exercise: Bitwise operations
Configure pin #5 as output, other pins unmodified Load R1 0xFA01 Ori R2 R1 b00100000 // (0x20) Store R2 0xFA01
Check your understanding of bitwise operations ɳ Configure pin #7 as input
19 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ɳ Invert all pin states without not instruction?
Exercise: Bitwise operations
Configure pin #5 as output, other pins unmodified Load R1 0xFA01 Ori R2 R1 b00100000 // (0x20) Store R2 0xFA01
Check your understanding of bitwise operations ɳ Configure pin #7 as input ɳ Configure: • pins #2 and #7 as inputs • pin #4 as output • using only one load and one store
19 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Exercise: Bitwise operations
Configure pin #5 as output, other pins unmodified Load R1 0xFA01 Ori R2 R1 b00100000 // (0x20) Store R2 0xFA01
Check your understanding of bitwise operations ɳ Configure pin #7 as input ɳ Configure: • pins #2 and #7 as inputs • pin #4 as output • using only one load and one store ɳ Invert all pin states without not instruction?
19 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Section 3
Addresses and address spaces
20 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data CPU communication: addressed read/write (data or instructions) Memory mapping: hardware map addresses to devices • Memories • Device registers • ... Addresses can be unmapped
Memory mapping
2n − 1 n-bits addresses CPU ROM (RO memory) Address space: address from 0 to 2n − 1 RAM 2 (RW memory)
timer (RW registers) USB (RW registers) unmapped
RAM 1 (RW memory) keyboard (RO registers) 0
21 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Memory mapping: hardware map addresses to devices • Memories • Device registers • ... Addresses can be unmapped
Memory mapping
2n − 1 n-bits addresses CPU ROM (RO memory) Address space: address from 0 to 2n − 1 RAM 2 (RW memory) CPU communication: addressed read/write (data timer (RW registers) USB (RW registers) or instructions) unmapped
RAM 1 (RW memory) keyboard (RO registers) 0
21 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Addresses can be unmapped
Memory mapping
2n − 1 n-bits addresses CPU ROM (RO memory) Address space: address from 0 to 2n − 1 RAM 2 (RW memory) CPU communication: addressed read/write (data timer (RW registers) USB (RW registers) or instructions) Memory mapping: hardware unmapped map addresses to devices • RAM 1 (RW memory) Memories • Device registers keyboard (RO registers) • ... 0
21 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Memory mapping
2n − 1 n-bits addresses CPU ROM (RO memory) Address space: address from 0 to 2n − 1 RAM 2 (RW memory) CPU communication: addressed read/write (data timer (RW registers) USB (RW registers) or instructions) Memory mapping: hardware unmapped map addresses to devices • RAM 1 (RW memory) Memories • Device registers keyboard (RO registers) • ... 0 Addresses can be unmapped
21 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ROM: read only (RO) Devices interface registers • Can be RO, RW or write-only • Can store commands, data, status,. . . • Can have side-effects ⇒ Different programming uses
Memory mapping
2n − 1 Read-write effect vary ROM (RO memory) RAM: read and write (RW)
RAM 2 (RW memory)
timer (RW registers) USB (RW registers) unmapped
RAM 1 (RW memory) keyboard (RO registers) 0
21 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Devices interface registers • Can be RO, RW or write-only • Can store commands, data, status,. . . • Can have side-effects ⇒ Different programming uses
Memory mapping
2n − 1 Read-write effect vary ROM (RO memory) RAM: read and write (RW) ROM: read only (RO) RAM 2 (RW memory)
timer (RW registers) USB (RW registers) unmapped
RAM 1 (RW memory) keyboard (RO registers) 0
21 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data ⇒ Different programming uses
Memory mapping
2n − 1 Read-write effect vary ROM (RO memory) RAM: read and write (RW) ROM: read only (RO) RAM 2 (RW memory) Devices interface registers • Can be RO, RW or timer (RW registers) write-only USB (RW registers) • Can store commands, unmapped data, status,. . . • Can have side-effects RAM 1 (RW memory) keyboard (RO registers) 0
21 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Memory mapping
2n − 1 Read-write effect vary ROM (RO memory) RAM: read and write (RW) ROM: read only (RO) RAM 2 (RW memory) Devices interface registers • Can be RO, RW or timer (RW registers) write-only USB (RW registers) • Can store commands, unmapped data, status,. . . • Can have side-effects RAM 1 (RW memory) ⇒ Different programming uses keyboard (RO registers) 0
21 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Example: Leon’s memory mapping
Typical Leon-based architecture
22 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Example: Leon’s memory mapping (AHB)
AHB bus
23 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Example: Leon’s memory mapping (APB)
APB bus memory mapping 24 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Addresses breakdown on AHB bus: • Bits 31. . . 28: select AHB Slave • Bits 27. . . 0: offset in subspace Addresses breakdown on APB bus: • Bits 27. . . 6 or 27. . . 4: select APB Slave • Bits 5. . . 0 or 3. . . 0: offset in subspace Components not always use complete subspace Component address bus can be narrower than system bus
Remarks on Mapping
Components have dedicated subspaces Power of two addresses and sizes
25 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Addresses breakdown on APB bus: • Bits 27. . . 6 or 27. . . 4: select APB Slave • Bits 5. . . 0 or 3. . . 0: offset in subspace Components not always use complete subspace Component address bus can be narrower than system bus
Remarks on Mapping
Components have dedicated subspaces Power of two addresses and sizes Addresses breakdown on AHB bus: • Bits 31. . . 28: select AHB Slave • Bits 27. . . 0: offset in subspace
25 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Components not always use complete subspace Component address bus can be narrower than system bus
Remarks on Mapping
Components have dedicated subspaces Power of two addresses and sizes Addresses breakdown on AHB bus: • Bits 31. . . 28: select AHB Slave • Bits 27. . . 0: offset in subspace Addresses breakdown on APB bus: • Bits 27. . . 6 or 27. . . 4: select APB Slave • Bits 5. . . 0 or 3. . . 0: offset in subspace
25 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Component address bus can be narrower than system bus
Remarks on Mapping
Components have dedicated subspaces Power of two addresses and sizes Addresses breakdown on AHB bus: • Bits 31. . . 28: select AHB Slave • Bits 27. . . 0: offset in subspace Addresses breakdown on APB bus: • Bits 27. . . 6 or 27. . . 4: select APB Slave • Bits 5. . . 0 or 3. . . 0: offset in subspace Components not always use complete subspace
25 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Remarks on Mapping
Components have dedicated subspaces Power of two addresses and sizes Addresses breakdown on AHB bus: • Bits 31. . . 28: select AHB Slave • Bits 27. . . 0: offset in subspace Addresses breakdown on APB bus: • Bits 27. . . 6 or 27. . . 4: select APB Slave • Bits 5. . . 0 or 3. . . 0: offset in subspace Components not always use complete subspace Component address bus can be narrower than system bus
25 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Powers of 2 allow simple addresses decoding • MSB: subspace identifier • LSB: offset in subspace Example: 64 addresses (n = 6 address bits) • One subspace: k = 0, 64 cells per subspace • Two subspaces: k = 1, 32 cells per subspace • ... • 64 subspaces: k = 6, single cell per subspace k bits, 2k subspaces n − k bits, 2n−k cells per subspace subspace offset n-bits addresses, 2n cells
Addresses and subspaces
Address space can split into subspaces Addresses viewed as subspace identifier + offset in subspace
26 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Example: 64 addresses (n = 6 address bits) • One subspace: k = 0, 64 cells per subspace • Two subspaces: k = 1, 32 cells per subspace • ... • 64 subspaces: k = 6, single cell per subspace k bits, 2k subspaces n − k bits, 2n−k cells per subspace subspace offset n-bits addresses, 2n cells
Addresses and subspaces
Address space can split into subspaces Addresses viewed as subspace identifier + offset in subspace Powers of 2 allow simple addresses decoding • MSB: subspace identifier • LSB: offset in subspace
26 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Addresses and subspaces
Address space can split into subspaces Addresses viewed as subspace identifier + offset in subspace Powers of 2 allow simple addresses decoding • MSB: subspace identifier • LSB: offset in subspace Example: 64 addresses (n = 6 address bits) • One subspace: k = 0, 64 cells per subspace • Two subspaces: k = 1, 32 cells per subspace • ... • 64 subspaces: k = 6, single cell per subspace k bits, 2k subspaces n − k bits, 2n−k cells per subspace subspace offset n-bits addresses, 2n cells
26 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Addresses and subspaces
0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1
One layout, several views Subspaces are more logical concepts than physical ones
27 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Exercise: Simple implementation example
Check your understanding of address subspaces ɳ Modify diagram such that device 2 has 64-addresses subspace
device 3
device 2 3 wires only, device 1 uses 8 (or less) addresses, some addresses are unmapped device 1
device 0 Chip select wires
address bus decoder
up to 8 targets
28 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Two extra LSBs allow byte addressing
Addresses refinement
Example: 4-byte words addressing Add LSBs to addresses for finer addressing granularity
011011 011011 0 1
29 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Addresses refinement
Example: 4-byte words addressing Add LSBs to addresses for finer addressing granularity Two extra LSBs allow byte addressing
011011 011011 0 1
29 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Address fields
Memory
subspace offset
...... Memory
address 1 BYTE 1 BYTE ...
1 BYTE 1 BYTE Example: a memory with 2−byte cells
30 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Address fields
Memory
byte
...... Memory
address 1 BYTE 1 BYTE
byte address MUX ... 1 BYTE
1 BYTE 1 BYTE
Byte addressing is possible by adding one bit to addresses This extra bit is not present on memory address bus. It is handled by some extra logic between CPU and memory.
31 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Let ω be a number of addressing units u Address a is ω-aligned iff a mod ω = 0 Relation with previous slides • ω = subspace size • a ω-aligned iff base address of a subspace • ω usually power of 2 and ω-aligned addresses end with trailing zeros For a memory capable of byte addressing (u = byte), 4-bytes aligned addresses (ω = 4) are 0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018... ω-aligned addresses
02 ω × ω 3 × ω 4 × ω 5 × ω ω bytes ω bytes ω bytes ω bytes ω bytes... Memory
Addresses alignment
ω-aligned addresses Let u be the addressing unit (byte, half-word. . . )
32 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Address a is ω-aligned iff a mod ω = 0 Relation with previous slides • ω = subspace size • a ω-aligned iff base address of a subspace • ω usually power of 2 and ω-aligned addresses end with trailing zeros For a memory capable of byte addressing (u = byte), 4-bytes aligned addresses (ω = 4) are 0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018... ω-aligned addresses
02 ω × ω 3 × ω 4 × ω 5 × ω ω bytes ω bytes ω bytes ω bytes ω bytes... Memory
Addresses alignment
ω-aligned addresses Let u be the addressing unit (byte, half-word. . . ) Let ω be a number of addressing units u
32 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Relation with previous slides • ω = subspace size • a ω-aligned iff base address of a subspace • ω usually power of 2 and ω-aligned addresses end with trailing zeros For a memory capable of byte addressing (u = byte), 4-bytes aligned addresses (ω = 4) are 0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018... ω-aligned addresses
02 ω × ω 3 × ω 4 × ω 5 × ω ω bytes ω bytes ω bytes ω bytes ω bytes... Memory
Addresses alignment
ω-aligned addresses Let u be the addressing unit (byte, half-word. . . ) Let ω be a number of addressing units u Address a is ω-aligned iff a mod ω = 0
32 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data For a memory capable of byte addressing (u = byte), 4-bytes aligned addresses (ω = 4) are 0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018... ω-aligned addresses
02 ω × ω 3 × ω 4 × ω 5 × ω ω bytes ω bytes ω bytes ω bytes ω bytes... Memory
Addresses alignment
ω-aligned addresses Let u be the addressing unit (byte, half-word. . . ) Let ω be a number of addressing units u Address a is ω-aligned iff a mod ω = 0 Relation with previous slides • ω = subspace size • a ω-aligned iff base address of a subspace • ω usually power of 2 and ω-aligned addresses end with trailing zeros
32 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Addresses alignment
ω-aligned addresses Let u be the addressing unit (byte, half-word. . . ) Let ω be a number of addressing units u Address a is ω-aligned iff a mod ω = 0 Relation with previous slides • ω = subspace size • a ω-aligned iff base address of a subspace • ω usually power of 2 and ω-aligned addresses end with trailing zeros For a memory capable of byte addressing (u = byte), 4-bytes aligned addresses (ω = 4) are 0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018... ω-aligned addresses
02 ω × ω 3 × ω 4 × ω 5 × ω ω bytes ω bytes ω bytes ω bytes ω bytes... Memory
32 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data 32-bits (word) CPU Instruction Load
Addresses alignment
Example specification Addressing unit: byte
33 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Instruction Load
Addresses alignment
Example specification Addressing unit: byte 32-bits (word) CPU
33 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Specification says: undefined behaviour if MemAddr not word-aligned MemAddr must be word-aligned Addresses used in load instruction must be multiple of 4 MemAddr must end with 2 trailing zeroes
Addresses alignment
Example specification Addressing unit: byte 32-bits (word) CPU Instruction Load
33 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data MemAddr must be word-aligned Addresses used in load instruction must be multiple of 4 MemAddr must end with 2 trailing zeroes
Addresses alignment
Example specification Addressing unit: byte 32-bits (word) CPU Instruction Load
33 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Addresses used in load instruction must be multiple of 4 MemAddr must end with 2 trailing zeroes
Addresses alignment
Example specification Addressing unit: byte 32-bits (word) CPU Instruction Load
33 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data MemAddr must end with 2 trailing zeroes
Addresses alignment
Example specification Addressing unit: byte 32-bits (word) CPU Instruction Load
33 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Addresses alignment
Example specification Addressing unit: byte 32-bits (word) CPU Instruction Load
33 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Step between addresses of consecutive 4-bytes words in memory is 4 This lecture presents general concepts, ideas Depending on context vocabulary changes • Subspaces can be words, pages, blocks. . . • Subspaces can be split in sub-subspaces. . . • Addresses can be split in more than two fields. . .
Byte-based addressing
In most cases addressing unit is byte (history) Memory cells generally contain several bytes (2-bytes half-words, 4-bytes words, 8-bytes double-words)
34 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data This lecture presents general concepts, ideas Depending on context vocabulary changes • Subspaces can be words, pages, blocks. . . • Subspaces can be split in sub-subspaces. . . • Addresses can be split in more than two fields. . .
Byte-based addressing
In most cases addressing unit is byte (history) Memory cells generally contain several bytes (2-bytes half-words, 4-bytes words, 8-bytes double-words) Step between addresses of consecutive 4-bytes words in memory is 4
34 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Depending on context vocabulary changes • Subspaces can be words, pages, blocks. . . • Subspaces can be split in sub-subspaces. . . • Addresses can be split in more than two fields. . .
Byte-based addressing
In most cases addressing unit is byte (history) Memory cells generally contain several bytes (2-bytes half-words, 4-bytes words, 8-bytes double-words) Step between addresses of consecutive 4-bytes words in memory is 4 This lecture presents general concepts, ideas
34 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Byte-based addressing
In most cases addressing unit is byte (history) Memory cells generally contain several bytes (2-bytes half-words, 4-bytes words, 8-bytes double-words) Step between addresses of consecutive 4-bytes words in memory is 4 This lecture presents general concepts, ideas Depending on context vocabulary changes • Subspaces can be words, pages, blocks. . . • Subspaces can be split in sub-subspaces. . . • Addresses can be split in more than two fields. . .
34 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Conclusion
Bibliography Computer Organisation & Design, D.A. Patterson and L. Hennessy, Morgan Kaufmann, USA Computer Architecture, A Quantitative approach, D.A. Patterson and L. Hennessy, Morgan Kaufmann, USA And a lot more in the library. . .
Questions?
35 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data