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Implementing an Adder/Subtractor Circuit, 3 The University of Toledo EECS:6660:0xxField Programmable Gate Arrays s11l2_fpga.fm - 1 Dr. A.D. Johnson Lab Assignment #2 Due Thursday, April 7 2011 I MPLEMENTING AN A DDER/S UBTRACTOR CIRCUIT 1. OBJECTIVES - learning the VHDL implementation process using Parameterized Language Templates, - getting familiar with the organization of Altera’s Library of Parameterized Modules”, - learning the VHDL implementation process for the "adder/subtractor" functions, - learning how to convert the counter output to the 7-segment display codes, - learning how to connect the counter output to the 7-segment displays on the DE2 demo board, - learning how to use the constraints file to map the circuit signals to the FPGA pins. 2. NE-1026 P RELAB A SSIGNMENT Use the NE-1026 Computer Lab to log on to your Engineering College Computing ( ECC ) account and complete the Prelab Assignment. For the later work on Lab Assignment #2 use the NE-2036 FPGA Lab and log on to your FPGA Lab accounts. The work on this prelab assignment will require information from the “terasic” DE2 FPGA protoboard’s manual, DE2_User_Manual, which is available on the Engineering College Computing ( ECC ) file server, /eng/applications/altera/DE2_System_v1.6/DE2_User_Manual Prelab Assignment Report is a prerequisit for the work in the FPGA Lab; it is due at the beginning time of the FPGA Lab session. All results of the Prelab Assignment work must be accounted for in the text of the Prelab Assignment Report. 2.1 CREATING THE D IRECTORY FOR P RELAB A SSIGNMENT#2 After logging on to your ECC general account, open a Terminal window by executing: RMB → Background → Tools → Terminal In the opened terminal window execute: bash cd ~/fpga/lab mkdir lab2 cd lab2 which has created a directory named ~/fpga/lab/lab2, and made it the working directory in which the rest of this prelab assignment ought to be completed. 2.2 C OPYING THE FILE DE2_ PIN_ASSIGNMENTS.CSV FROM THE ECC S ERVER When working with the DE2 demo board, all toggle-switches, push-buttons, LEDs, and seven-segment display pin assignments are already fixed by the connections on the board. Their list is stored in the file DE2_pin_assignments.csv which is located at /eng/applications/altera/DE2_System_v1.6/DE2_lab_exercises/ 3/31/11 The University of Toledo EECS:6660:0xxField Programmable Gate Arrays s11l2_fpga.fm - 2 Dr. A.D. Johnson and can be imported into a project from there (see p18 of intro_vhdl). The pin assignment process can be completely avoided when names of the I/O signals connected to the components on DE2 board have been assigned in the way shown in Figure 2.1, and when the file DE2_pin_assignments.csv has been included into the project files. To copy the DE2 pin assignments file execute, scp /eng/applications/altera/DE2_System_v1.6/DE2_tutorials/ DE2_pin_assignments.csv . 2.3 Studying and Using the Altera VHDL Templates Altera maintains a Library of Parameterized Moduls written in VHDL for most commonly used hardware modules. A module named counters can be found in it and used as a starting point for preparing some VHDL code needed in this Lab Assignment. The way to accessing the module is described below. Assuming that execution of commands in Sections 2.1 through 2.3 has been followed, execute quartus and create the project adder_subtractor_vhdl then select from the Quartus II window, Tools ® MegaWizard Plug-in Manager after which follow the steps described starting on page 7 of the non-interactive tutorial located on the ECC Server at /eng/applications/altera/DE2_System_v1.6/DE2_tutorials/tut_lpms_vhdl.pdf which will make it possible for you to create the adder/subtractor VHDL code, for the ADD_SUB module in the circuit of Figure 2.1. 2.4 VHDL C ODE FOR THE EXPERIMENT Prepare the file named main_lab2.vhd which contans your own VHDL code with a description of the logic circuit architecture shown in Figure 2.1. Components described by behavioral source code should provide for the following functions: 1. implementing two UP/DOWN-counting eight-bit binary counters with asynchronous RESET input, shown in Figure 2.1, 2. implementing an adder/subtractor circuit, 3. implementing a hex to 7-segment decoder. Hint#2: Push-buttons KEY0, KEY1 and KEY2 on the DE2 board provide a debounced, active-low signal. The structural part of the code contained in the file named main_lab2.vhd should provide for the following functions: 1. designate the names of the input signals to the counters exactly as shown in Figure 2.1; 2. connect the output signals of each counter to: - the corresponding input of the adder/subtractor module, 3/31/11 The University of Toledo EECS:6660:0xxField Programmable Gate Arrays s11l2_fpga.fm - 3 Dr. A.D. Johnson HEX2LED Q2(7:4) BIN8 HEX5(6:0) Q2(7:0) HEX SEG KEY(2) CNT Q U1D0 HEX2LED RES Q2(3:0) HEX SEG HEX4(6:0) LEDR(0) SW(0) ADD_SUB HEX2LED AS(7:4) A AS(7:0) HEX SEG HEX1(6:0) S_D B C_B C HEX2LED A0S1 AS(3:0) LEDR(1) HEX SEG HEX0(6:0) SW(1) HEX2LED BIN8 Q1(7:4) HEX SEG HEX7(6:0) KEY(1) CNT Q1(7:0) U1D0 Q HEX2LED KEY(0) RES Q1(3:0) HEX SEG HEX6(6:0) LEDR(7) Figure 2.1 Architecture of the logic circuit for experimentation with the adder/subtractor module. - the corresponding inputs of hexadecimal to seven segment code converters; 3. designate the output signals of the six HEX2LED converters exactly as shown in Figure 2.1, Hint#3 Names of the I/O signals connected to the components on DE2 board of which there exist multiple instances, like toggle-switches, push-buttons, LEDs, seven-segment displays, must be assigned in the following way: (a) in the top module’s port statement as, SW: in STANDARD_LOGIC_VECTOR (3 downto 0), (b). when used individually, they must be referred to as SW(0), ..., SW(3). 4. To simplify the simulation process, create a Test Bench module by, - use the test bench template to create the top module testb_lab2.vhd, - write a behavioral VHDL source code which will generate the sequences of all input signals to the architecture in Figure 2.1, - import the prepared code into the “User Defined Section “ of the testb_lab2.vhd file. 2.5 Simulating the prepared VHDL code Simulation can be performed by following the Xilinx ISE flow, or by following the QuartusII design flow which both use the simulation tool ModelSim, or by invoking the stand-alone ModelSim. which will require executing, tcsh 3/31/11 The University of Toledo EECS:6660:0xxField Programmable Gate Arrays s11l2_fpga.fm - 4 Dr. A.D. Johnson . /eng/applications/mentor/s1026_06.csh vsim When simulation shows the expected functioning of the architecture shown in Figure 2.1, consider your VHDL source code prepared for the experimentation described in Section 4. For the Prelab report, take snapshots of the wave forms around the signal transition time points which indicate the proper functioning of signals. This step completes the Prelab Assignment. 3. NE-2036 FPGA Lab Equipment Equipment to be used for Lab Assignment#2 includes: - “terasic” demo board DE2, with an Altera Cyclon II FPGA, shown in Figure 3.1, - an x86 platform running under the Linux version CentOS5, - asymmetric USB cable, - 9V power supply for the demo board DE2. Figure 3.1View of the “terasic” demo board DE2, with an Altera Cyclone II FPGA on it. 4. NE-2036 FPGA Lab Assignment At the beginning of the Lab session, and before anything else should be attempted, a number of connections must be established between the FPGA board and other external equipment. These actions 3/31/11 The University of Toledo EECS:6660:0xxField Programmable Gate Arrays s11l2_fpga.fm - 5 Dr. A.D. Johnson are described in sections 4.1 through 4.2. In the sequel, the sections 4.4 through 4.7 describe the interaction with the FPGA vendor software which leads to the programming of the FPGA, and enables the experimenting with the protoboard circuitry. 4.1 DE2 Connections A small number of connections ought to be established before proceding to other tasks. 4.1-1 USB Connections The USB cable must be connected between: - the mini USB connector which is located next to the power jack on the DE2 FPGA board, - a USB connector on the computer. 4.1-2 Power Supply Connections DE2 FPGA proto board is powered by its own external power supply unit which should be connected as follows: - power supply’s 9V DC cord plugged into the DC power jack on the DE2 demo board, - power supply’s 120V AC cable into the power strip. The power is turned ON by pressing the red-button switch on the DE2 demo board. 4.1-3 Selecting the Configuration Mode The configuration mode/procedure is determined by the setting of the RUN/PROG toggle-switch: - for JTAG mode, which loads configuration data directly into the FPGA, set the RUN/PROG switch into position, RUN - for AS (Active Serial) mode, which loads configuration data into the configuration storage device named EPCS16, set the RUN/PROG switch into position, PROG. 4.2 Setting up the Quaqrtus II Software Environment To log in to a class account in the FPGA Lab, use the computer to which a DE2 FPGA board is connected. Then set up the environment which supports the application software by entering the following information user id: s11sxx passwd: fpga99 and executing the following commands in the given order: yppaswd: <new password> mkdir lab cd lab 4.3 Copying the Prepared Project Files from the ECC Environment The copying procedure will be as follows: scp -r <student_id>@ne1026215.eng.utoledo.edu:fpga/lab/lab2 .
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