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Jchongthesis.Pdf (4.148Mb) Activity Recognition Processing in a Self-Contained Wearable System by Justin B. Chong Thesis submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of Master of Science in Computer Engineering Dr. Thomas L. Martin, Chair Dr. Mark T. Jones, Dr. Thurmon E. Lockhart Sept 12, 2008 Blacksburg, Virginia Keywords: E-Textiles, Activity Recognition, Singular Value Decomposition Copyright 2008, Justin B. Chong Activity Recognition Processing in a Self-Contained Wearable System Justin B. Chong (ABSTRACT) Electronic textiles provide an effective platform to contain wearable computing elements, espe- cially components geared towards the application of activity recognition. An activity recogni- tion system built into a wearable textile substrate can be utilized in a variety of areas including health monitoring, military applications, entertainment, and fashion. Many of the activity recognition and motion capture systems previously developed have several drawbacks and lim- itations with regard to their respective designs and implementations. Some such systems are often times expensive, not conducive to mass production, and may be difficult to calibrate. An effective system must also be scalable and should be deployable in a variety of environ- ments and contexts. This thesis presents the design and implementation of a self-contained motion sensing wearable electronic textile system with an emphasis toward the application of activity recognition. The system is developed with scalability and deployability in mind, and as such, utilizes a two-tier hierarchical model combined with a network infrastructure and wireless connectivity. An example prototype system, in the form of a jumpsuit garment, is presented and is constructed from relatively inexpensive components and materials. Acknowledgements The work shown in this thesis would not have been accomplished without the help and support of a lot of people. For those who are not mentioned specifically, thank you. I would like to thank my advisor Dr. Tom Martin for all of the guidance, advice, jokes, and most importantly the opportunities he has given me throughout my graduate and under- graduate career. I would like to thank Dr. Mark Jones for his guidance, for serving on my committee, and for being the one to introduce me to the field of embedded systems. I would also like to thank Dr. Thurmon Lockhart for serving on my committee. I would like to thank my roommate Syed Imtiaz Haider for being an excellent sounding board for ideas and for being a great friend. And above all, I would like to dedicate this thesis work to my parents Teri and Yong Chong. I want to thank my mother for her continual support and words of encouragement, and I want to thank my father for being my inspiration to pursue this field of work and education. This material is based upon work supported by the National Science Foundation under Grant No. CCR-0219809, CNS-0447741, and CNS-0454195. Any opinions, findings and conclusions or recommendations expressed in this material are those of the author(s) and do iii not necessarily reflect the views of the National Science Foundation (NSF). iv Contents 1 Introduction 1 1.1 Motivation . 1 1.2 Contributions . 2 1.3 Thesis Organization . 2 2 Background 4 2.1 Electronic Textiles and Wearable Computing . 4 2.2 Previous Electronic Textile Research at Virginia Tech . 6 2.3 Sensor Based Activity Recognition . 7 3 System Overview 9 3.1 Design Hierarchy and Data Flow . 9 3.2 Two-Tier Model . 12 3.2.1 Tier 1 . 12 3.2.2 Tier 2 . 12 v 4 Hardware Development 14 4.1 Tier 1 Acceleration Modules . 15 4.1.1 Acceleration Sensors . 15 4.1.2 Piezo-Electric Material . 16 4.1.3 Power Regulation . 17 4.1.4 Breadboard Prototype . 19 4.1.5 Miniaturized Tier 1 Prototype . 21 4.2 Tier 2 Processing Element . 22 4.2.1 Gumstix Motherboard . 23 4.2.2 Network Interface Module . 23 4.3 Interconnections and Textile Substrate . 25 5 Software Development 29 5.1 Tier 1 Firmware . 29 5.1.1 Event-Driven Software Model . 30 5.1.2 Optimized Software Model . 33 5.2 Tier 2 Software . 33 5.2.1 Operating System . 35 5.2.2 Application Code . 36 6 Communication 40 vi 6.1 I2C ......................................... 40 6.2 Serial . 44 6.3 Bluetooth . 44 7 Results 46 7.1 Individual Acceleration Module Accuracy . 46 7.1.1 Avoidance of Slow VDD Rise Time . 47 7.1.2 Accelerometer and Gyroscope Output . 47 7.2 Activity Recognition Application Performance . 49 7.2.1 Jumpsuit Prototype Validation . 51 7.2.2 CPU Utilization . 52 7.3 Network Communication Performance . 53 7.3.1 Theoretical Network Bandwidth Utilization . 53 7.3.2 Experimental Sample Rate Sustainability . 59 7.3.3 Deviation From Expected Results . 62 7.3.4 Comparison of Software Approaches . 68 8 Conclusions 70 8.1 Contributions . 70 8.2 Future Work . 71 Bibliography 73 vii A Gumstix Tutorials 77 A.1 How To Connect to the Gumstix . 77 A.1.1 Connecting Via Serial Port . 77 A.1.2 Connecting Via Bluetooth . 78 A.2 OpenEmbedded Build Environment Setup . 79 A.3 Flashing the OpenEmbedded Filesystem Image to the Gumstix . 84 A.4 Developing Applications for Gumstix OpenEmbedded . 88 A.5 Setting up Bluetooth on the Verdex 400xm-bt Gumstix . 90 B Atmel Tutorials 94 B.1 Programming an Atmel Microcontroller . 94 B.2 Fixing the slow or skewed clock on the Atmel Atmega8l . 96 C VTProf Tutorial 98 C.1 Using VTprof to Profile your C/C++ Source Code . 98 D Miscellaneous 102 D.1 Soldering Tips and Tricks . 102 D.1.1 General Soldering Tips . 102 D.1.2 SMD Soldering Techniques . 103 D.1.3 SMD With Leads Soldering Techniques . 104 D.1.4 BGA Soldering Techniques . 104 viii D.1.5 QFN Soldering Techniques . 106 D.2 How to Tile Boards Into a Merged Panel Using Gerbermerge . 109 D.3 Capacitance Estimation . 113 ix List of Figures 3.1 Two Tiered Model . 10 3.2 Nodes Distributed Across Human Body . 11 4.1 Piezo-Electric Material . 17 4.2 Piezo-Electric Noise . 18 4.3 Linear Voltage Regulator Circuit . 19 4.4 Breadboard Prototype . 20 4.5 Gyronator Test Platform . 20 4.6 Acceleration Module (Front) . 21 4.7 Acceleration Module (Back) . 22 4.8 Product Feature Matrix . 23 4.9 Gumstix Verdex 400xm-bt . 24 4.10 I2C to UART Daughter Card/Gumstix Assembly . 24 4.11 Ribbon Cable Prototype . 26 4.12 USB to Ribbon Cable Converter Board . 26 x 4.13 USB to IDC Converter Board . 27 4.14 IDC Attached to Wire Bus . 27 4.15 Perpendicular Bus Jumpering Via IDC Connector . 28 5.1 Stub Baseline Execution Flow . 31 5.2 Event Data Structure . 32 5.3 Optimized Model Execution Flow . 34 5.4 Sample Gprof and VTProf Output . 39 6.1 Example I2C Transaction . 42 6.2 Raw Payload Packet . 43 6.3 Raw VTEDP Packet . 44 7.1 PMOS Power Transistor Configuration . 48 7.2 Switching Accelerometer On and Off Via PMOS Transistor . 48 7.3 2 g Swing Level Test . 49 7.4 Hand Held Oscillation Test . 50 7.5 Acceleration Module Placement . 51 7.6 Jumpsuit Prototype . 52 7.7 Recognize Application Output (Marching in Place) . 53 7.8 Logic Analyzer Capture Waveform for a 19 Byte Packet . 55 7.9 Logic Analyzer Capture Waveform for a 10 Byte Packet . 56 xi 7.10 Theoretical Maximum Global Sample Rates . 59 7.11 Experimental Maximum Sustainable Global Sample Rates (Event-Driven) . 61 7.12 Experimental Maximum Sustainable Global Sample Rates (Optimized) . 61 7.13 Logic Analyzer Capture of Arbitration Detection . 65 7.14 Logic Analyzer Capture of NACK . 66 7.15 Logic Analyzer Capture of Multiple Arbitrations . 67 7.16 Comparison of Event-Driven and Optimized Software Models . 69 A.1 Download Monitor Screen . 86 B.1 Permissions Setup Output . 95 C.1 Example Code . 100 C.2 Profile Report.
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