Implementation of an Advanced Barrel Shifter on Reconfigurable Hardware Logic

International Journal of Innovative and Emerging Research in Engineering Volume 2, Issue 4, 2015

International Journal of Innovative and Emerging Research in Engineering e-ISSN: 2394 – 3343 p-ISSN: 2394 – 5494

Aashish Pandeya, Malvika Shekhawata, Anamika Yadava, Prof. Sushma Wadarb, Prof.Avinash Patilb aStudent of Electronics & Telecommunication Engg., AIT, pune, India. bAssistant Professor of Electronics & Telecommunication Engg., AIT, pune, India. ABSTRACT: A Barrel shifter is a combinational circuit which is used for shifting and rotating multiple bits in a single cycle. Presently Barrel Shifter is not present in the lower version of microcontrollers like PIC 16 series. This paper focuses on the implementation of the advanced barrel Shifter design in the PIC 16 series (8 bit). The proposed design constitutes of advanced 8 bit barrel shifter using 2:1 mux which can perform logical shift, arithmetic shift and rotate operations. The design is implemented on the SPARTAN 3 FPGA kit. Keywords: Barrel Shifter, Rotator, Opcode, mux, FPGA, RISC.

I. INTRODUCTION A Barrel Shifter is a combinational circuit which shifts and rotates data left and right logically and arithmetically. As the technology advanced, Barrel shifters were implemented in the higher versions of PIC series for faster processing and data handling. With our proposed design we are trying to implement Barrel shifter in the lower version of PIC microcontrollers i.e. PIC 16 series which is of 8 bit. SPARTAN 3 FPGA kit which is a RISC (Reduced Instruction Set Computer) processor core is used for implementation. SPARTAN 3 kit is used because it is one of the perfect platform to experiment with new designs [1] . From a simple logic circuit to an embedded processor core can be easily implemented. Also it is compatible with Xilinx which is used for simulation and testing of the proposed design [1].

II. SYSTEM BLOCK DIAGRAM Barrel shifter is implemented in the execution unit as shown in Figure 1. The Opcodes are fetched and decoded from the instruction and given to the execution unit. Execution unit comprises of the ALU (Arithmetic and Logic unit), Barrel Shifter and Logic Unit. The following table explains the operation assigned to each Opcode and desired output to the input A (87654321).

Figure1. System block diagram

International Journal of Innovative and Emerging Research in Engineering Volume 2, Issue 4, 2015

Table 1: Assigned Opcodes

3-bit Opcode Operation S.No Y (output) Left rotate Arithmetic

1. 1 1 0 0 0 0 shift right logical 0 0 0 8 7 6 5 4

2. 1 1 0 0 0 1 shift right arithmetic 8 8 8 8 7 6 5 4

3. 1 1 0 0 1 X rotate right 3 2 1 8 7 6 5 4

4. 1 1 0 1 0 0 shift left logical 5 4 3 2 1 0 0 0

5. 1 1 0 1 0 1 shift left arithmetic 5 4 3 2 1 0 0 0

6. 1 1 0 1 1 X rotate left 5 4 3 2 1 8 7 6

III. BARREL SHIFTER DESIGN A. USING 8:1 MUX The conventional 8 bit barrel shifter consists of eight 8:1 mux. Each mux consists of 3 select lines which are having common connection. The shifting operation is decided by input given to the select lines in Barrel Shifter. These three select lines correspond to total of 8 shift patterns based on the input provided. For example if the select lines combination is 010 then the output will be shifter by 2 bit. This is a one stage design with all the multiplexers placed vertically. The design is shown in the Figure 2

Figure 2: Barrel shifter design using 8:1 mux

B. USING 2:1 MUX The design using 2:1 mux incorporates twenty four 2:1 mux. Multiplexers are arranged in three stages with three select lines. One select line at each stage. The shifting operation is decided by the input given to the select lines [3] . At first stage 4 bit shifting is done. If second stage is enabled 2 bit shifting will be done and if third stage is also activated then the input will be shifted by 1 bit. With this design the Barrel Shifter obtains a complete 8 bit shift if required by providing input to select line as 111.The design is shown in Figure 3.

International Journal of Innovative and Emerging Research in Engineering Volume 2, Issue 4, 2015

Figure 3: Barrel shifter design using 2:1 mux

C. COMPARISON On comparing the barrel shifter design using 2:1 mux and 8:1 mux following results were obtained: a. The hardware utilization of barrel shifter using 2:1 mux is much reduced; because of this reason area occupied by the design is reduced comparatively to the straight design. The delay is bit increased because of the increased stages. This may not be a big issue because the time difference is very less. b. The simulation results show the actual delay of shifting operation. The timing delays information is been extracted.The delays vary from technology to technology. We are using SPARTAN-3 FPGA technology for simulation. From this we can find out the area, speed and power. But our main issue which we are dealing with is the area and the speed. On simulating we find that the delay is little more of approximately 0.7 ns in 2:1 mux design (3 stage). c. The difference between 8-bit barrel shifter with 8-bit mux and 8-bit barrel shifter with 2-bit mux is the number of stages that the design consists and the hardware utilization that is area occupied by the design. With 2-bit mux, the design consist three stages. Each stage consist eight 2-bit multiplexers, so in total 24 multiplexers are been used in the design. d. The design of 8-bit barrel shifter with 2-bit multiplexer is implemented and compared with another one. Even though the delay is 0.7ns of 3-stages which is more than the other design ,the remaining resources are best optimized to the previous design. For larger design implementation, the designer may consider on the area utilization. The proposed design has taken only 24 LUTs and 14 slices for 8-bit barrel shifter. Finally the design is occupy less area and achieve the same speed.

III. PROPOSED DESIGN The proposed design can perform shifting and rotation of n specified no of bits. It can perform both arithmetic and logical shifting. A multiplexer is added in the initial stage to select arithmetic or logical shift. It selects ‘0’ for logical right shifting and ‘1’ for arithmetic right shifting.

International Journal of Innovative and Emerging Research in Engineering Volume 2, Issue 4, 2015

Figure 4. Proposed design of Barrel Shifter

We have chosen the RISC PROCESSOR since multiple instructions can be completed in one machine cycle, which allows the processor to handle several instructions at the same time through its pipeline [1] . There are four stages – fetch, decode, decode check and execute. The T state generation result is shown in the figure 5.

Figure 5. T State Generation

IV. TESTS AND RESULTS

A. 4 BIT RIGHT SHIFT The input given is ‘ 11000001’ and we have successfully obtained the output as ‘00001100’. The simulation results are shown in Figure 5.

Figure 6. The Simulation Result of an 4 Bit Right Shift Operation.

B. 4 BIT ARITHMETIC SHIFT The input given is ‘11000001’ and we have successfully obtained the output as ‘1111100’. The simulation results are shown in Figure 6.

International Journal of Innovative and Emerging Research in Engineering Volume 2, Issue 4, 2015

Figure 7. The Simulation Result of 4 Bit Right Arithmetic Shifts.

C. 4 BIT ROTATE The input given is ‘11000000’ and we have successfully obtained output as ‘00001100’. The simulation results are shown in Figure 7.

Figure 8. The Simulation Result of 4 Bit Rotation Operation

V. CONCLUSIONS With the help of the proposed design now we can implement barrel shifter in the lower versions of PIC16 series (8 bit). Also we can perform arithmetic, logical shifting and rotation operation very effectively. Problem of shifting to higher version of PIC because of absence of one of the important module of Barrel Shifter in lower versions is avoided by implementing it in PIC 16 series (8 bit) and hence helps us in cost reduction of design as well.

ACKNOWLEDGMENT We are grateful to Prof. Sushma Wadar and Prof Avinash Patil for their kind and helpful research assistance. We would also like to thank our library staff and the excellent facility provided by them and the friends who have helped us a lot in finalizing the project within the limited time frame.

REFERENCES

[1] Spartan 3 Board , Available from https://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD. [2] Kiseon Cho and Minkyu Song, “Design Methodology of 32-bit Arithmetic Logic Unit with an Adaptive Leaf Cell Based Layout Technique” VLSI Design, 2002 Vol. 14 (3), pp. 527-536. [3] Saurabh Kotiyal, Himanshu Thapliyal and Nagarajan Ranganathan, “Design of A Reversible Bidirectional Barrel Shifter”, 11th IEEE International Conference on Nanotechnology Portland Marriott August 15-18, 2011, Portland, Oregon, USA [4] M. Seckora, "Barrel shifter or multiply/divide IC structure," u.s. Patent 5,465,222,November 1995. [5] Pillmeier, Matthew Rudolf, “Barrel Shifter Design, Optimization, and Analysis”. [6] Wikipedia , Google.