Proceedings of SPIT-IEEE Colloquium and Internatio nal Conference, Mumbai, India Vol. 2, 150
VLSI Implementation of a Barrel Shifter
Priyanka Mandal, Siddhant Malani, Yogesh Gudepkar, Suparas Singhi and P.M.Palsodkar
Abstract—A Barrel Shifter is a multiplexer based digital circuit. Several microprocessors incorporate it as a part of their ALU to provide fast shift operations. This paper deals with the design of Barrel Shifter using VLSI Technology. Four modules have been designed which consist of an inverter which forms an integral part of 2:1 Multiplexer and 4:1 Multiplexer and also used as control inputs, an AND gate used for arithmetic shifting, a 2:1 MUX used for collecting the falling bits and a 4:1 MUX needed to shift the data words left or right. There are three stages of 4:1 MUX with smaller 2:1 MUX preceding it in every stage. The modules have been designed in Schematic-edit and they have been simulated in Waveform-edit.
I. INTRODUCTION
A Barrel Shifter is a digital circuit that can shift a data word by a specified number of bits. It can perform shifting of N-bit Fig: Block Diagram of 8 Bit Barrel Shifter data in a single cycle. A N-bit Barrel Shifter can shift data left Consider a four-bit barrel shifter, with inputs A, B, C & D. or right by N-1 bits. In general, a Barrel Shifter can implement The shifter can cycle through the order of the bits ABCD i.e. it arithmetic shifting, logical shifting and rotation functions [10]. can 'shift' all of the outputs up to three positions to the right The signals for the input/output, and shift functions for a N-bit and thus make any cyclic combination of A, B, C and D. This barrel shifter are given as follows: makes a barrel shifter a vital component in microprocessor (along with the ALU) [11]. Data In = (2x(N-1)) Bit II. METHODOLOGY Shift Amount = (log2N) Bit Data Out = (N) Bit The design and simulation of the layout for N-bit Barrel
The principal distinction between a barrel shifter and an Shifter is carried out by using VLSI technology . The ordinary shifter is the amount of bits being shifted at one time. functionality of the shifter includes arithmetic shifting, logical A common shifter will usually shift only one bit per cycle shifting, and rotation. The design is divided into smaller whereas a barrel shifter can shift many bits per cycle. It can be sections so that it becomes easy to build and test each function implemented as a sequence of multiplexers. The number of of the circuit separately for each section. The first stage shifts the word bit by 4 bits, the second by 2 multiplexers required is [nlog2(n)] , for a n bit word. Four common word size and the number of multiplexers needed are bits and the third by 1 bit shifting a total of 7 bits. A total of listed below: twenty four 4:1 multiplexers (8 for each stage) are used for designing purpose [09]. The Multiplexers at each stage would shift the bits 16-bit — 16log 2 (16) = 16 x 4 = 64 according to the shift amount. Arithmetic shifting is needed and so AND gate is connected to the last four inputs in the 8-bit — 8log 2 (8) = 8 x 3 = 24 first stage. The AND gate would copy the MSB (most significant bit) and shift it in according to the shift amount. For example if MSB is "one", it would be shifted in 4 times if
the shift amount is 4 (only right shifting carries the MSB). Mr.P.M.Palsodkar is working as lecturer in department of ECE, G.H.Raisoni College of Engineering, Nagpur , Maharashtra In Barrel Shifter, when shifting logically, the bits shifted (e-mail:[email protected]) "fall off" at the ends of the multiplexers. To rotate the bits, we P.Mandal, S.Malani, Y.Gudepkar & S.Singhi are Final year student of need to "catch" these bits which are being lost. To do this, a 2- G.H.Raisoni College of Engineering.(e-mail: [email protected] ,[email protected]., [email protected] & to-1 multiplexer is implemented in the circuit for every lost [email protected] ). bit. Thus, the design requires twelve 2:1 multiplexers [10].
Proceedings of SPIT-IEEE Colloquium and Internatio nal Conference, Mumbai, India Vol. 2, 151
III. DESIGN APPROACH 1) CMOS Inverter
W=1u
L=1u
V=5.0 OUT IN
W=1u
L=1u
Fig III.2.b: Layout of CMOS AND Gate
Fig III.1.a: Schematic of CMOS Inverter The AND gate is implemented using two N-MOS structure in series, two P-MOS structure in parallel and one Inverter [1]. We have implemented AND gate by inverting the output of NAND gate. The Inputs are given to the gates of both N-MOS and P-MOS & output of NAND gate is fed as input to the inverter. VDD and Ground are connected to Source and Drain of MOS structures respectively [3].
3) CMOS 2:1 Multiplexer
IN L=1u W=1u L=1u W=1u V=5.0
Fig III.1.b: Layout of CMOS Inverter L=1u W=1u
B W=1u L=1u
The inverter is implemented using P-MOS & N-MOS in OUT series where IN corresponds to Input Bit and OUT L=1u W=1u
A W=1u L=1u corresponds to Output bit [1], [3].
2) CMOS AND Gate
Fig III.3.a: Schematic of 2:1 Multiplexer
W=1u
L=1u
L=1u
W=1u
W=1u
W=1u L=1u
L=1u A OUT
W=1u
L=1u W=1u
L=1u
B V=5.0
Fig III.2.a: Schematic of CMOS AND Gate Fig III.3.b: Layout of 2:1 Multiplexer
Proceedings of SPIT-IEEE Colloquium and Internatio nal Conference, Mumbai, India Vol. 2, 152
In digital circuit design, the selector wires are of digital The Boolean expression obeyed by the 4:1 Mux is as value. In the case of a 2:1 multiplexer, a logic value of 0 follows: would connect B to the output while a logic value of 1 would Z = AS1’S2’ + BS1’S2 + CS1S2’ + DS1S2 connect A to the output. In larger multiplexers, the number of When S1 and S2 are both zero then input A will be selector pins is equal to n where n is the number of inputs. selected. Similarly B will be selected when S1 is zero and S2 A 2:1 multiplexer obeys the following a Boolean is one & so on. expression: Z = (AS +BS’) IV. SIMULATION RESULT Where A and B are the two inputs, S is the selector input, 1) CMOS Inverter and Z is the output [ 13]. INV
v( OUT) 5.0 4.5 The implementation of 2:1 MUX uses 2 Transmission 4.0 3.5 V(out) Gates. A & B are the input bits, IN corresponds to the control 3.0 2.5 signal. The output is obtained depending upon the control 2.0 1.5 Voltage (V) Voltage signal. 1.0 0.5
0.0 0 50 1 00 150 200 Time (ns)
INV 4) CMOS 4:1 Multiplexer v( IN) 5.0 4.5 4.0 3.5 3.0 S1 2.5 V(in) 2.0
1.5 Voltage (V) Voltage L=1u W=1u L=1u W=1u 1.0
V=5.0 0.5
W=1u
L=1u
0.0
0 50 1 00 150 200 L=1u W=1u
A W=1u L=1u Time (ns) S2 W=1u L=1u Fig IV.1.a: Schematic Result for CMOS Inverter L=1u W=1u
A1 W=1u L=1u L=1u W=1u W=1u L=1u In the simulation we can see that when input is High output OUT
L=1u W=1u obtained is Low. Hence Output of Inverter is verified. L=1u W=1u W=1u L=1u B W=1u L=1u L=1u W=1u
B1 W=1u L=1u
Fig III.4.a: Schematic of 4:1 Multiplexer
Fig IV.1.b: Layout Result for CMOS Inverter
2) CMOS AND Gate
AND
v( OUT) 5.0
4.5
4.0 3.5 V(OUT) 3.0
2.5
2.0 1.5 1.0
0.5 Voltage (V)
0.0 0 50 100 150 200 Ti me (ns )
AND
5.0 v( A)
4.5 V(A)
4.0
3.5 3.0 2.5
2.0
1.5
1.0
0.5 Voltage (V) Voltage
0.0
0 50 100 150 200 Ti me (ns ) V(B) AND
Fig III.4.b: Layout of 4:1 Multiplexer 5.0 v( B) 4.5 4.0 3.5 3.0
2.5
2.0
4:1 MUX is implemented using three 2:1 MUX. A,B,C,and 1.5 1.0
0.5 Voltage (V)
0.0 D are the input bits and S1 & S2 are the control signal. Now 0 50 100 150 200 Ti me (ns ) depending upon both of these the output is obtained [12]. Fig IV.2.a: Schematic Result for CMOS AND Gate Proceedings of SPIT-IEEE Colloquium and Internatio nal Conference, Mumbai, India Vol. 2, 153
S A B Out 1 1 X A 1 0 X A 0 X 1 B 0 X 0 B Fig IV.3.c: Truth Table for CMOS 2:1 Multiplexer
In this simulation we see that with different control signal value [V(S)], we obtain different output. Explicitly, when V(S) = 1, V(A) is selected and when V(S) = 0, V(B) is selected [6].
Fig IV.2.a: Layout Result for CMOS AND Gate 4) CMOS 4:1 Multiplexer Here, we see that the output of the AND gate is High mux4to1
1.0 v(B1) whenever the inputs A & B are High. The output is Low when 0.5 0.0
-0.5
-1.0 either of the inputs is Low. Again the AND gate works as 0 50 100 150 200 V(D)=0v
Time (ns)
Voltage ( expected [8]. mux4to1
1.0 v(A1)
0.5
0.0 -0.5 V(C)=0v -1.0 3) CMOS 2:1 Multiplexer 0 50 100 150 200 Time (ns) Voltage ( mux4to1 mux2t01
5.5 v(B) v(B) 5.0 5.4 5.3
4.5 5.2
5.1
4.0 5.0
4.9
3.5 4.8 V(B)=5v 4.7
3.0 4.6
4.5
0 50 100 150 200 2.5 2.0 V(B) Time (ns) 1.5
1.0 Voltage ( 0.5 mux4to1
0.0 0 50 100 150 200 5.5 v(A) Voltage (V)
5.4 Time (ns) 5.3
5.2
5.1 mux2t01 5.0 4.9 V(A)=5v 4.8
4.7 v(A) 5.0 4.6
4.5
0 50 100 150 200 4.5 4.0 3.5 Time (ns)
3.0 Voltage ( 2.5 mux4to1 2.0 V(A) 1.5
5.0 v(S2)
1.0 4.5
4.0
3.5 0.5 3.0 V(S1) 2.5 0.0
2.0 0 50 100 150 200 1.5
1.0 Voltage (V)
0.5 Time (ns) 0.0 0 50 100 150 200 mux2t01 Time (ns)
v(IN) 5.0 Voltage ( 4.5 mux4to1 4.0 3.5 V(S2) 5.0 v(S1)
3.0 4.5
4.0
2.5 3.5
3.0
2.5 2.0 V(in) 2.0 1.5 1.5
1.0
0.5 1.0
0.0
0 50 100 150 200 0.5
0.0
0 50 100 150 200 Time (ns) Voltage (V)
Time (ns) Voltage ( V mux4to1 V(out) mux2t01
5.5 v(OUT)
v(OUT) 5.0 5.0
4.5
4.0 4.5
3.5
4.0 3.0
2.5
3.5 2.0
1.5
3.0 1.0
0.5
2.5 0.0
-0.5
2.0 0 50 100 150 200
1.5
1.0 V(out) Time (ns) 0.5
0.0
-0.5 Voltage (
-1.0
-1.5 0 50 100 150 200
Voltage (V) Fig IV.4.a: Schematic Result for CMOS 4:1 Multiplexer Time (ns) Fig IV.3.a: Schematic Result for CMOS 2:1 Multiplexer
Fig IV.3.b: Layout Result for CMOS 2:1 Multiplexer Fig IV.4.b: Layout Result for CMOS 4:1 Multiplexer
Proceedings of SPIT-IEEE Colloquium and Internatio nal Conference, Mumbai, India Vol. 2, 154
VIII. BIOGRAPHIES S1 S2 A B C D Out 0 0 1/0 X X X A Prasanna Palsodkar is working as a lecturer in 0 1 X 1/0 X X B Dept. of ECE, GHRCE, Nagpur. He completed his post graduation in Electronics with VLSI as his 1 0 X X 1/0 X C specialization from GHRCE in 2006.He is life member of ISTE, student member of IEEE. He has 1 1 X X X 1/0 D published one international paper in KES 2007, Table IV.4.b: Truth Table for 4:1 Multiplexer Italy.
In above simulation we can see that with different control signal V(S1),V(S2) value we obtain different output,i.e.when V(S1)=V(S2)=0, V(A) is selected and so on different values Yogesh Gudepkar is a final year student of Electronics Engineering at GHRCE Nagpur. are selected respectively [7].
V. APPLICATIONS
1) A barrel shifter is used in floating-point arithmetic hardware. 2) A barrel shifter is a combinational logic circuit with n data inputs,n data outputs, and a set of control inputs that Suparas Singhi is a final year student of Electronics Engineering at GHRCE Nagpur. specify how to shift the data between input and output [9]. 3) A barrel shifter that is part of a microprocessor CPU can typically specify the direction of shift (left or right), the type of shift (circular, arithmetic, or logical), and the amount of shift (typically 1 to n-1 bits, but sometimes 1 to n bits) [12]. 4) Barrel Shifter was used in processors till Pentium 3.The Athlon and K5 and Pentium-III uses Barrel Shifter [5].
VI. CONCLUSION
All of the above designed modules form an integral part of Siddhant Malani is a final year student of Electronics Engineering at the Barrel Shifter design. By using all these circuits, 4–bit and GHRCE,Nagpur
8–bit Barrel Shifter can be designed. The 2:1 MUX is designed for storing the falling bits and the 4:1 MUX is used for the arithmetic & logical shifting and rotating purposes. Priyanka Mandal is a final year student of Electronics Engineering at GHRCE,Nagpur VII. REFERENCE
[1] VLSI Design Techniques for Analog and Digital Circuit – R. Geiger, P. Allen & N. Strader, McGraw-Hill. [2] Handbook of Multilevel Metallization for Integrated Circuits – S. R. Wilson, C. J. Tracy, J. L. Freeman, William Andrew. [3] CMOS VLSI Design – N. H. E. Weste, D. Harris, Addison Wesley. [4] CMOS Digital Integrated Circuits: Analysis and Design – S. Kang, Y. Leblebici, McGraw-Hill. [5] Digital Integrated Circuits: A Design Perspective – J. M. Rabaey, A. Chandrakasan, B. Nikolic, Prentice Hall. [6] Basic VLSI Design – D.A. Pucknell, K Eshraghian, Prentice-Hall. [7] The Electronics HandBook – J. C. Whitaker, CRC Press. [8] Practical Low Power Digital VLSI Design – G. K. Yeap, KAP. [9] Low Power VLSI Design and Technology – G. K. Yeap, F. N. Najm, WSPC. [10] Integrated Circuit Design – B. Hochet, A. J. Acosta, M. J. Bellido, Springer. Methodologies, and Tools – D. Clein, Newnes. [11] Logic Design – W. Chen, CRC Press. [12] High Speed CMOS Design Styles – K. Bernstein, et al, Springer. [13] CMOS IC Layout: Concepts,– M. J. Madou, CRC Press.