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Versal ACAP System Software Developers Guide

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Versal ACAP System Software Developers Guide See all versions of this document Versal ACAP System Software Developers Guide UG1304 (v2020.2) March 1, 2021 Revision History Revision History The following table shows the revision history for this document. Section Revision Summary 03/01/2021 Version 2020.2 Chapter 3: Development Tools Added AI Engine Development Environment. Chapter 6: Software Design Paradigms Updated Virtualization with Hypervisor and Use of Hypervisors. 11/24/2020 Version 2020.2 PLM Boot and Configuration Updated JTAG information and added more PLM error codes. Added PLM Watch Dog Timer details for PLM Interface (XilPLMI). Updated Deferred Image Loading and Deferred Image Handoff details for XilLoader. Updated PLM Build Flags and Memory and Registers Reserved for PLM in PLM Usage. Chapter 9: Security Updated details of ECDSA-RSA hardware accelerator and AES-GCM hardware Crypto block. Chapter 10: Versal ACAP Platform Management Updated XPm_DevIoctl EEMI API. 07/16/2020 Version 2020.1 Initial release. N/A UG1304 (v2020.2) March 1, 2021Send Feedback www.xilinx.com Versal ACAP System Software Developers Guide 2 Table of Contents Revision History...............................................................................................................2 Chapter 1: Overview......................................................................................................6 Introduction to Versal ACAP.......................................................................................................6 Navigating Content by Design Process.................................................................................... 7 About This Guide......................................................................................................................... 8 Chapter 2: Programming View of Versal ACAP.............................................. 9 Hardware Overview.................................................................................................................. 10 Chapter 3: Development Tools.............................................................................. 19 Vivado Design Suite.................................................................................................................. 19 Vitis Software Platform............................................................................................................. 20 PetaLinux Tools..........................................................................................................................24 Device Tree Generator..............................................................................................................25 Open Source.............................................................................................................................. 26 Linux Software Development Using Yocto.............................................................................27 QEMU..........................................................................................................................................29 AI Engine Development Environment.................................................................................... 32 Chapter 4: Software Stack....................................................................................... 35 Bare-Metal Software Stack.......................................................................................................35 Linux Software Stack.................................................................................................................38 Third-Party Software Stack.......................................................................................................40 Chapter 5: Software Development Flow.......................................................... 41 Bare-Metal Application Development in the Vitis Environment .........................................42 Linux Application Development Using PetaLinux Tools.......................................................43 Linux Application Development Using the Vitis Software Platform....................................44 Chapter 6: Software Design Paradigms........................................................... 47 Frameworks for Multiprocessor Development......................................................................47 Symmetric Multiprocessing..................................................................................................... 48 UG1304 (v2020.2) March 1, 2021Send Feedback www.xilinx.com Versal ACAP System Software Developers Guide 3 Asymmetric Multiprocessing .................................................................................................. 50 Chapter 7: Boot and Configuration.................................................................... 55 Versal ACAP Boot Process........................................................................................................ 55 Boot Flow....................................................................................................................................61 Secondary Boot Process and Device Choices........................................................................ 64 Fallback Boot and MultiBoot....................................................................................................65 Programmable Device Image..................................................................................................67 Configuration Data Object....................................................................................................... 68 Boot Image (PDI) Creation.......................................................................................................68 Chapter 8: Platform Loader and Manager .................................................... 71 PLM Boot and Configuration................................................................................................... 71 PLM Software Details................................................................................................................75 PLM Interface (XilPLMI)............................................................................................................ 85 XilLoader.....................................................................................................................................95 XilPM........................................................................................................................................... 98 XilSecure..................................................................................................................................... 99 XilSEM....................................................................................................................................... 100 PLM Usage............................................................................................................................... 100 Services Flow............................................................................................................................103 Exception Handling.................................................................................................................103 Chapter 9: Security.....................................................................................................104 Security Features.....................................................................................................................104 Asymmetric Hardware Root-of-Trust (A-HWRoT) (Authentication Required)................. 107 Encryption................................................................................................................................ 108 Symmetric Hardware Root-of-Trust (S-HWRot) Boot Mode (Encryption Required)....... 109 Chapter 10: Versal ACAP Platform Management......................................110 Versal ACAP Platform Management Overview.................................................................... 111 Versal ACAP Power Domains................................................................................................. 111 Versal ACAP Platform Management Software Architecture.............................................. 114 Chapter 11: Target Development Platforms................................................161 Boards and Kits........................................................................................................................161 Appendix A: Libraries............................................................................................... 162 Appendix B: Additional Resources and Legal Notices........................... 163 UG1304 (v2020.2) March 1, 2021Send Feedback www.xilinx.com Versal ACAP System Software Developers Guide 4 Xilinx Resources.......................................................................................................................163 Documentation Navigator and Design Hubs...................................................................... 163 References................................................................................................................................163 Please Read: Important Legal Notices................................................................................. 165 UG1304 (v2020.2) March 1, 2021Send Feedback www.xilinx.com Versal ACAP System Software Developers Guide 5 Chapter 1: Overview Chapter 1 Overview Introduction to Versal ACAP Versal™ adaptive compute acceleration platforms (ACAPs) combine Scalar Engines, Adaptable Engines, and Intelligent Engines with leading-edge memory and interfacing technologies
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