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Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures

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Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures I Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures Richard Rashid, Avadis Tevanian, Michael Young, David Golub, Robert Baron, David Black, William Boloaky, and Jonathan Chew Department of Computer Science !iliii!i!i ¸ Carnegie Mellon University Pittsburgh, Pennsylvania 15213 Abstract Over the last two years CMU has been engaged in the development of a portable, multiprocessor operating system This paper describes the design and implementation of vir- called Mach. One of the goals of Mach has been to explore tual memory management within the CMU Mach Operating the relationship between hardware and software memory ar- System and the experiences gained by the Mach kernel group chitectures and to design a memory management system that in porting that system to a variety of architectures. As of this would be readily portable to multiprocessor computing en- writing, Maeh runs on more than half a dozen uniprocessors and multiprocessors including the VAX family of uniproces- gines as well as traditional uniprocessors. sors and multiprocessors, the IBM RT PC, the SUN 3, the Mach provides complete UNIX 4.3bsd compatibility while Encore MultiMax, the Sequent Balance 21000 and several significantly extending UNIX notions of virtual memory experimental computers. Although these systems vary con- management and inteerprocess communication [1]. Mach sup- siderably in the kind of hardware support for memory management they provide, the machine-dependent portion of ports: Mach virtual memory consists of a single code module and its * large, sparse virtual address spaces, related header file. This separation of software memory management from hardware support has been accomplished • copy-on-write virtual copy operations, without sacrificing system performance. In addition to im- proving portability, it makes possible a relatively unbiased • copy-on-write and read-write memory sharing examination of the pros and cons of various hardware between tasks, memory management schemes, especially as they apply to the support of multiprocessors. • memory mappedfiles and n user-provided backing store objects andpagers. 1. Introduction This has been accomplished without patterning Mach's in- While software designers are increasingly able to cope with ternal memory representation after any specific architecture. variations in instruction set architectures, operating system In fact, Math makes relatively few assumptions about avail- portability continues to suffer from a proliferation of memory able memory management hardware. The primary require- structures. UNIX systems have traditionally addressed the ment is an ability to handle and recover from page faults (for problem of VM portability by restricting the facilities some arbitrary page size). provided and basing implementations for new memory As of this writing, Math runs on more than half a dozen management architectures on versions already done for pre- uniprocessors and multiprocessors including the entire VAX vious systems. As a result, existing versions of UNIX, such family of uniprocessors and mulfiprocessors, the IBM RT PC, as Berkeley 4.3bsd, offer little in the way of virtual memory the SUN 3, the Encore MultiMax and the Sequent Balance management other than simple paging support. Versions of 21000. Implementations are in progress for several ex- Berkeley UNIX on non-VAX hardware, such as SunOS on perimental computers. Despite differences between supported the SUN 3 and ACIS 4.2 on the IBM RT PC, actually simu- architectures, the machine-dependent portion of Mach's vir- late internally the VAX memory mapping architecture -- in tual memory subsystem consists of a single code module and effect treating it as a machine-independent memory manage- its related header file. All information important to the ment specification. management of Mach virtual memory is maintained in machine-independent data structures and machine-dependent This xeseareh was sponsored by the Defense Advanced Research l:Xrojeels data structures contain only those mappings necessary to run- Agency (DOD), ARPA Order No. 4864, monitored by the Space and Naval ning the current mix of programs. Warfare Systems Command under contraeet N00039-85-C-1034. Permission to copy without fee all or part of this material is granted Mach's separation of software memory management from provided that the copies are not made or distributed for direct commercial hardware support has been accomplished without sacrificing advantage, the ACM copyright notice and the title of the publication and system performance. In several eases overall system perfor- Its date appear, and notice is given that copying Is by permission of the Association of Computing Machinery. To copy otherwise, or to republish, mance has measurably improved over existing UNIX im- requires a fee and/or specific permission. plementations. Moreover, this approach makes possible a 31 © 1987 ACM 0-89791-238-1/87/1000-0031 $00.75 I I relatively unbiased examination of the pros and cons of ferent classes of machines while providing a consistent inter- various hardware memory management schemes, especially face to all resources. The actual system running on any as they apply to the support of multiprocessors. This paper particular machine is thus more a function of its servers than describes the design and implementation of virtual memory its kernel. management within the CMU Mach Operating System and Traditionally, message based systems of this sort have the experiences gained by the Mach kernel group in porting operated at a distinct performance disadvantage to conven- that system to a variety of arChitectures. tionally implemented operating systems. The key to efficiency in Mach is the notion that virtual memory management can be 2. Mach Design integrated with a message-oriented communication facility. There are five basic Mach abstractions: This integration allows large amounts of data including whole 1. A task is an execution environment in which files and even whole address spaces to be sent in a single threads may run. It is the basic unit of resource message with the efficiency of simple memory remapping. allocation. A task includes a paged virtual ad- 2.1. Basle VM Operations dress space and protected access to system Each Mach task possesses a large address space that consists resources (such as processors, port capabilities of a series of mappings between ranges of memory addres- and virtual memory). A task address space con- sible to the task and memory objects. The size of a Mach sists of an ordered collection of mappings to address space is limited only by the addressing restrictions of memory objects (see below). The UNIX notion the underlying hardware. An RT PC task, for example, can of a process is, in Mach, represented by a task address a full 4 gigabytes of memory under Mach I while the with a single thread of control. VAX architecture allows at most 2 gigabytes of user address 2. A thread is the basic unit of CPU utilization. It space. A task can modify its address space in several ways, is roughly equivalent to an independent program including: counter operating within a task. All threads allocate a region of virtual memory on a page within a task share access to all task resources. boundary, 3. A port is a communication channel -- logically a ® deallocate a region ofvirtucd memory, queue for messages protected by the kernel. • set the protection status of a region of virtual Ports are the reference objects of the Mach memory, design. They are used in much the same way that object references could be used in an object • specify the inheritance of a region of virtual oriented system. Send and Receive are the fun- memory and damental primitive operations on ports. ® create and manage a memory object that can 4. A message is a typed collection of data objects then be mapped into the address space of another used in conmmnication between threads. Mes- task. sages may be of any size and may contain The only restriction imposed by Mach on the nature of the pointers and typed capabilities for ports. regions that may be specified for virtual memory operations is that they must be aligned on system page boundaries. The 5. A memory object is collection of data provided definition of page size is a boot time system parameter and and managed by a server which can be mapped can be any power of two multiple of the hardware page size. into the address space of a task. Table 2-1 fists the set of virtual memory operations that can Operations on objects other than messages are performed by be performed on a task. sending messages to ports. In this way, Mach permits system Both copy-on-write and read/write sharing of memory are services and resources to be managed by user-state tasks. For permitted between Mach tasks. Copy-on-write sharing be- example, the Mach kernel itself can be considered a task with tween unrelated tasks is typically the result of large message multiple threads of control. The kernel task acts as a server transfers. An entire address space may be sent in a single which in turn implements tasks, threads and memory objects. message with no actual data copy operations performed. The act of creating a task, a thread or a memory object, Read/write shared memory can be created by allocating a returns access rights to a port which represents the new object memory region and setting its inheritance attribute. Sub- and can be used to manipulate it. Incoming messages on such sequently created child tasks share the memory of their parent a port results in an operation performed on the object it according to its inheritance value. Inheritance may be represents. specified as shared, copy or none, and may be specified on a The indirection provided by message passing allows objects per-page basis. Pages specified as shared, are shared for read to be arbitrarily placed in the network (either within a mul- and write.
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