(19) &   

(11) EP 1 860 567 A1

(12) EUROPEAN PATENT APPLICATION

(43) Date of publication: (51) Int Cl.: 28.11.2007 Bulletin 2007/48 G06F 11/34 (2006.01) G06F 9/30 (2006.01)

(21) Application number: 06126643.3

(22) Date of filing: 20.12.2006

(84) Designated Contracting States: (72) Inventor: GREINER, Dan AT BE BG CH CY CZ DE DK EE ES FI FR GB GR Winchester, Hampshire SO21 2JN (GB) HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR (74) Representative: Williams, Julian David Designated Extension States: IBM United Kingdom Limited AL BA HR MK YU Intellectual Property Law Hursley Park (30) Priority: 19.05.2006 US 437220 Winchester Hampshire SO21 2JN (GB) (71) Applicant: International Business Machines Corporation Remarks: Armonk, NY 10504 (US) Amended claims in accordance with Rule 86 (2) EPC.

(54) Extract CPU facility

(57) An efficient facility for determining resource us- do not require a call to services. The age, such as a processor time used by tasks. The deter- facility includes an instruction that determines elapsed mination is performed on behalf of user applications that time and reports it to the user as a single unit of operation. EP 1 860 567 A1

Printed by Jouve, 75001 PARIS (FR) 1 EP 1 860 567 A1 2

Description vision of a method as claimed in claim 1. [0008] System and products corre- Technical Field sponding to the above-summarized method, as well as one or more instructions, are also described and claimed [0001] This invention relates, in general, to processing 5 herein. within a processing environment, and in particular, to a [0009] Additional features and advantages are real- facility to efficiently determine resource usage of tasks. ized through the techniques of the present invention. Oth- er embodiments and aspects of the invention are de- Background of the Invention scribed in detail herein and are considered a part of the 10 claimed invention. [0002] The determination of resource usage is critical for many aspects of processing, including code refine- Brief Description of the Drawings ment, billing, etc. One resource for which utilization is determined is processor time. In the z/Architecture, of- [0010] One or more aspects of the present invention fered by International Business Machines Corporation, 15 are particularly pointed out and distinctly claimed as ex- a timer is provided that measures elapsed central amples in the claims at the conclusion of the specification. processing unit (CPU) time and causes an interruption The foregoing and other objects, features, and advan- when a specified amount of time has elapsed. tages of the invention are apparent from the following [0003] This timer is set by a Set CPU Timer (SPT) con- detailed description taken in conjunction with the accom- trol instruction, and the contents of the timer are inspect- 20 panying drawings in which: ed via a Store CPU Time (STPT) control instruction. Both of these instructions are privileged instructions to ensure FIG. 1 depicts one embodiment of a processing en- the accuracy of the time, and as such are not usable by vironment incorporating and using one or more as- problem-state programs (i.e., user programs). pects of the present invention; [0004] In addition to the above, the z/OS® operating 25 system, offered by International Business Machines Cor- FIG. 2 depicts one embodiment of the logic associ- poration, also provides a service routine referred to as ated with determining resource usage, in accord- TIMEUSED, which is available to problem-state pro- ance with an aspect of the present invention; grams. A program or operation calls the service to deter- mine the amount of CPU time a piece of code (e.g., task) 30 FIG. 3 depicts one example of a format of an Extract has used. The TIMEUSED service routine computes the CPU Time instruction used in accordance with an elapsed time, adds the accumulated time, and returns aspect of the present invention; the value to the program. The calculations of the TIMEUSED routine must be performed while being dis- FIG. 4a depicts one embodiment of the fields of gen- abled for interruptions, since any interruption could ad- 35 eral register 0 used by the Extract CPU Time instruc- versely effect the results by manipulating the CPU timer tion of one aspect of the present invention; or the accumulator. [0005] The TIMEUSED service routine is linked to via FIG. 4b depicts one embodiment of the fields of gen- program call and program return instructions. This rou- eral register 1 employed by the Extract CPU Time tine disables for interruptions, obtains and releases a 40 instruction of one aspect of the present invention; CPU lock, establishes a recovery environment, calcu- lates the elapsed time, and re-enables after having com- FIG. 5 depicts one embodiment of the logic associ- pleted its work, all of which takes hundreds of CPU cy- ated with executing the Extract CPU Time instruc- cles. When attempting to measure a small fragment of tion, in accordance with an aspect of the present code, the overhead of the TIMEUSED service routine 45 invention; can severely perturb what is being measured. FIG. 6 is a pictorial representation of the operations Summary of the Invention of the Extract CPU Time instruction of one aspect of the present invention; and [0006] Based on the foregoing, a need exists for a fa- 50 cility to efficiently determine resource usage, such as FIG. 7 depicts one example of a computer program elapsed CPU time of a task. In particular, a need exists product incorporating one or more aspects of the for a facility that efficiently determines resource usage of present invention. tasks without calling operating system services. A need exists for the ability of a user to efficiently determine re- 55 Best Mode for Carrying Out the Invention source usage. [0007] The shortcomings of the prior art are overcome [0011] In accordance with an aspect of the present in- and additional advantages are provided through the pro- vention, a facility is provided to efficiently determine re-

2 3 EP 1 860 567 A1 4 source usage of tasks executing within a processing en- As a specific example, an instruction is provided to de- vironment. In one example, a facility is provided in which termine an amount of processor time used by a task. The a user (e.g., user code, user application, user program, instruction can be implemented in many architectures etc.) can accurately measure the processor time required and may be emulated. As examples, the instruction is to execute a particular code fragment (referred to herein 5 executed in hardware by a processor; or by emulation of as a task). This facility determines the elapsed processor an instruction set that includes this instruction, by soft- time without significant overhead that has skewed such ware executing on a processing unit having a different measurements, such as overhead associated with using native instruction set. In one particular example, the in- an operating system service to determine the elapsed struction is implemented in the z/Architecture, offered by time. 10 International Business Machines Corporation, and is re- [0012] One embodiment of a processing environment ferred to herein as an Extract CPU Time (ECTG) instruc- incorporating and using one or more aspects of the tion. present invention is described with reference to FIG. 1. [0018] An Extract CPU Time instruction 300 (FIG. 3) Processing environment 100 is, for instance, a multi- is a non-privileged instruction, and includes, for instance, processing environment including a plurality of proces- 15 an operation code 302a, 302b designating the Extract sors 102 (e.g., central processing units (CPUs)), a mem- CPU Time instruction; a general register 304, the con- ory 104 (e.g., main memory) and one or more input/output tents of which specify a third operand used by the instruc- (I/O) devices 106 coupled to one another via, for exam- tion; a base register 306, which may be any of sixteen ple, one or more buses 108 or other connections. general purpose registers of the processing unit and in- [0013] As one example, each processor 102 is a an 20 cludes a portion of an address of a first operand in storage IBM System Z™ server, offered by International Business used by the instruction; a displacement value 308, which Machines Corporation, Armonk, New York, and one or is, for instance, an unsigned 12 bit binary number added more of the processors execute an operating system, to the contents of register 306 to provide the address of such as z/OS®, also offered by International Business the first operand in storage; a base register 310, which Machines Corporation. (IBM and z/OS are registered 25 again is any of the sixteen general purpose registers in trademarks of International Business Machines Corpo- the processing unit and includes a portion of an address ration, Armonk, New York, USA. Other names used here- of a second operand in storage used by the instruction; in may be registered trademarks, trademarks or product and a displacement value 312, which is added to the names of International Business Machines Corporation contents of register 310 to provide the address of the or other companies.) 30 second operand in storage for the instruction. [0014] Processing within the processing environment [0019] In addition to the registers described above, the is facilitated by the provision of a facility that enables the Extract CPU Time instruction also implicitly uses two gen- determination of resource usage, such as elapsed proc- eral registers that do not have to be encoded in the in- essor (e.g., CPU) time, without requiring the call of an struction, but are used by the instruction. These registers operating system service or without using privileged in- 35 include general register 0 and general register 1. structions or operations. [0020] General register 0 (400, FIG. 4a) includes, for [0015] One embodiment of the logic associated with instance, the elapsed time since last dispatch of the task determining resource usage is described with reference 402. It is the difference resulting from subtracting the val- to FIG. 2. This logic is executed by a processing unit of ue of the current CPU timer from the first operand, the the processing environment, in response to, for instance, 40 contents of which include the value of the CPU timer at a request by a user application (e.g., non-privileged task dispatch. code). The resource usage is determined for a task ab- [0021] General register 1 (410; FIG. 4b) includes, for sent a call to an operating system service and without instance, a value of the task time accumulator when the using privileged operations, STEP 200. task was dispatched 412. This is the contents of the sec- [0016] Initially, a current value of a counter used to 45 ond operand of the instruction. track the resource for the task, such as time used, is [0022] Although examples of registers are described determined by reading the counter value, as instructed above, each of the registers may include more, less or by the logic, STEP 202. The determined value is then different information. Further, each may include addition- subtracted from a saved value, which is, for instance, the al data not necessarily needed in one or more aspects value of the counter when it was started, STEP 204. In 50 of the present invention. The specific location within the one example, the counter decrements as the resource registers for the information is implementation and/or ar- is used by the task and the current value of the counter chitecture dependent. is read, in response to the request. The result of the sub- [0023] One embodiment of the logic associated with traction represents the amount of resource used by the the Extract CPU Time instruction is described with refer- task for this time interval, which is defined by the begin- 55 ence to FIG. 5. As one example, this instruction is exe- ning and ending values of the counter, STEP 206. cuted by a processor of the processing environment on [0017] In one example, the operations used to deter- behalf of a non-privileged user application (e.g., in prob- mine resource usage are performed by an instruction. lem state) that requests the operation as it relates to a

3 5 EP 1 860 567 A1 6 particular task. The Extract CPU Time instruction is a (610) reference a second operand in storage 612, the non-privileged instruction that does not invoke an oper- contents of which are placed unchanged in general reg- ating system service. It does, however, assume in this ister 1 (614). Additionally, R3 (616) references a third embodiment, that the CPU timer (e.g., counter, register, operand in storage 618, the contents of which are placed 5 etc.) is set when a task is dispatched. In one example, unchanged in general register R3 (620). the timer is set by a Set CPU Timer (STP) instruction, [0029] In one embodiment, the above operations all which is a privileged instruction described in z/Architec- occur within the same unit of operation, without the pos- ture: Principles of Operation, IBM® Publication No. sibility of being interrupted. By performing these opera- SA22-7832-04, September 2005, which is incorporated tions atomically, the values retain their meanings. herein by reference in its entirety. It may also be set by 10 [0030] Described in detail above is a facility to efficient- any other means. The timer is set to a given value which ly determine resource usage without the overhead asso- represents a specified time slice for execution of the task ciated with costly operating system services and/or with- (e.g., 10-12 ms). out using privileged operations. In particular, an Extract [0024] In response to executing the Extract CPU Time CPU Time facility is described that enables the efficient instruction, the current value of the CPU timer is deter- 15 determination of the amount of CPU time consumed, mined, STEP 500. For instance, the timer decrements without the costly overhead of calling an operating sys- as the processor processes the task, and in response to tem service and/or without issuing Program Call and/or executing the Extract CPU Time instruction, the value of Program Return instructions. This facility enables an ap- the timer, at that time, is observed. This includes, for in- plication program to accurately measure the CPU time stance, reading the register that holds the timer. In one 20 required to execute a particular code fragment without embodiment, the value of the timer can be extracted at the significant overhead that has traditionally skewed any time, including prior to the end of the time slice pro- such measurements. The measurements are useful in vided for the task and without waiting for an interruption many aspects, including, but not limited to, fine tuning of of the timer. application code and billing. The facility advantageously [0025] The current value of the CPU timer is then sub- 25 enables an application program to efficiently determine tracted from the first operand of the instruction, STEP the amount of task time used at any given moment, and 502. The first operand represents the value of the CPU not just at the end of a time slice. This allows the program timer at the time the task was dispatched. For example, to effectively determine instruction timings in the micro- when a task is dispatched, the CPU timer is set to a cho- second or nanosecond range without having to wait until sen value (e.g., 10-12 ms) and that value is stored in 30 milliseconds have elapsed. storage (e.g., PSDATSAV). Thus, PSADTSAV - current [0031] One or more aspects of the present invention CPU Timer = elapsed processor time since last dispatch can be included in an article of manufacture (e.g., one or of the task. This value is placed in general register 0, more computer program products) having, for instance, STEP 504. computer usable media. The media has therein, for in- [0026] In addition to the above, additional information 35 stance, computer readable program code means or logic is also extracted, in one embodiment, STEP 506. As one (e.g., instructions, code, commands, etc.) to provide and example, the second operand of the instruction is placed facilitate the capabilities of the present invention. The unchanged in general register 1. The second operand article of manufacture can be included as a part of a com- includes, for instance, an address of a task control block puter system or sold separately. (e.g., TCBTTUSD) that maintains the previously used 40 [0032] One example of an article of manufacture or a amount of total CPU time for the task. By extracting and computer program product incorporating one or more as- placing this information in general register 1, the user pects of the present invention is described with reference application is able to determine the total amount of proc- to FIG. 7. A computer program product 700 includes, for essor time used thus far, by adding the results of general instance, one or more computer usable media 702 to register 0 and general register 1. 45 store computer readable program code means or logic [0027] Also, in one embodiment, information at the 704 thereon to provide and facilitate one or more aspects third operand location of the instruction replaces the con- of the present invention. The medium can be an elec- tents of general register R3. This information includes tronic, magnetic, optical, electromagnetic, infrared, or various types of information, including but not limited to, semiconductor system (or apparatus or device) or a prop- flags designating information important or desired for the 50 agation medium. Examples of a computer-readable me- task, a scaling factor usable in adjusting the processor dium include a semiconductor or solid state memory, time for billing purposes, as well as other types of infor- magnetic tape, a removable computer diskette, a random mation. access memory (RAM), a read-only memory (ROM), a [0028] A pictorial representation of the operations is rigid magnetic disk and an optical disk. Examples of op- 55 depicted in FIG. 6. B1D1 (600) reference a first operand tical disks include compact disk-read only memory (CD- in storage 602. Subtracted from the contents of the first ROM), compact disk-read/write (CD-R/W) and DVD. operand 604 is the current value of the CPU timer 606. [0033] A sequence of program instructions or a logical The difference is stored in general register 0 (608). B2D2 assembly of one or more interrelated modules defined

4 7 EP 1 860 567 A1 8 by one or more computer readable program code means ployed during actual execution of the program code, bulk or logic direct the performance of one or more aspects storage, and cache memory which provide temporary of the present invention. storage of at least some program code in order to reduce [0034] Although one or more examples have been pro- the number of times code must be retrieved from bulk vided herein, these are only examples. Many variations 5 storage during execution. are possible without departing from the spirit of the [0038] Input/Output or I/O devices (including, but not present invention. For instance, processing environ- limited to, keyboards, displays, pointing devices, etc.) ments other than the example provided herein may in- can be coupled to the system either directly or through clude and/or benefit from one or more aspects of the intervening I/O controllers. Network adapters may also present invention. As an example, one or more proces- 10 be coupled to the system to enable the data processing sors can be other than IBM System Z™ processors and/or system to become coupled to other data processing sys- execute operating systems other than z/OS®. Further, tems or remote printers or storage devices through inter- the environment need not be based on the z/Architecture, vening private or public networks. Modems, cable mo- but instead, can be based on other architectures, offered dems and Ethernet cards are just a few of the available by, for instance, Intel, Sun Microsystems, as well as oth- 15 types of network adapters. ers. Yet further, the instruction can include other registers [0039] As used herein, the term "operand" not only in- or entities other than registers to designate information. cludes and/or refers to operands of an instruction, but Further, different data and/or positioning within the reg- also other operands, as well as parameters or arguments isters and/or entities are possible. Still further, the timer passed between functions of programs, or any other data can be other than counters or registers. Any mechanism 20 that is passed between entities. Further, a task includes can be used to determine resource usage. The term "tim- any portion of code, including an entire application or er" is meant to include a broad spectrum of mechanisms, program or any portion thereof. including, but not limited to, counters and registers. Fur- [0040] The capabilities of one or more aspects of the ther, although in the embodiments herein, the timer dec- present invention can be implemented in software, rements, in other embodiments, it may increment and/or 25 firmware, hardware or some combination thereof. At least follow some pattern. Many other variations exist. one program storage device readable by a machine em- [0035] Moreover, an environment may include an em- bodying at least one program of instructions executable ulator (e.g., software or other emulation mechanisms), by the machine to perform the capabilities of the present in which a particular architecture or subset thereof is em- invention can be provided. ulated. In such an environment, one or more emulation 30 [0041] The flow diagrams depicted herein are just ex- functions of the emulator can implement one or more amples. There may be many variations to these diagrams aspects of the present invention, even though a computer or the steps (or operations) described therein without de- executing the emulator may have a different architecture parting from the spirit of the invention. For instance, the than the capabilities being emulated. As one example, steps may be performed in a differing order, or steps may in emulation mode, the specific instruction or operation 35 be added, deleted or modified. All of these variations are being emulated is decoded, and an appropriate emula- considered a part of the claimed invention. tion function is built to implement the individual instruction or operation. [0036] In an emulation environment, a host computer Claims includes, for instance, a memory to store instructions and 40 data; an instruction fetch unit to fetch instructions from 1. A method of determining time memory and to optionally, provide local buffering for the usage of tasks of a processing environment, said fetched instruction; an instruction decode unit to receive method comprising: the instruction fetch unit and to determine the type of instructions that have been fetched; and an instruction 45 selecting a task of the processing environment execution unit to execute the instructions. Execution may for which usage of central processing unit time include loading data into a register for memory; storing is to be determined; and data back to memory from a register; or performing some determining an amount of the central processing type of arithmetic or logical operation, as determined by unti time used by the task within a particular time the decode unit. In one example, each unit is implement- 50 interval, by ed in software. For instance, the operations being per- determining a current value of a timer set for the formed by the units are implemented as one or more task; and subroutines within emulator software. subtracting said current value from a saved val- [0037] Further, a data processing system suitable for ue to determine an amount of elapsed processor storing and/or executing program code is usable that in- 55 time used by the task during the particular time cludes at least one processor coupled directly or indirect- interval. ly to memory elements through a system bus. The mem- ory elements include, for instance, local memory em- 2. The method of claim 1, wherein said determining oc-

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curs at least at a time prior to an end of a time slice set for the task; provided for the task. subtracting (204) said current value from a saved value to determine an amount of 3. The method of claim 1, further comprising adding elapsed processor time used by the task the amount of elapsed processor time to an accu- 5 during the particular time interval; mulated value for the task to determine a total amount of processor time used by the task thus far. characterised by the further steps of

4. The method of claim 3, further comprising extracting adding the amount of elapsed processor time to the accumulated value, wherein the determining the 10 an accumulated value for the task to determine amount of elapsed processor time and the extracting a total amount of processor time used by the the accumulated value occur as a single unit of op- task thus far; and eration. extracting the accumulated value, wherein the determining the amount of elapsed processor 5. The method of claim 1, wherein said determining is 15 time and the extracting the accumulated value performed using an instruction. occur without interruption as a single unit of op- eration; 6. The method of claim 5, wherein said instruction en- ables extraction of additional information. wherein said determining a current value step and 20 said subtracting step use a non-privileged instruction 7. The method of claim 6, wherein the extraction of ad- and a plurality of general purpose registers (400, ditional information and the determining occur as a 410) are used for holding resource usage data, and single, uninterruptible unit of operation. said non-privileged instruction manipulates the re- source usage data of the general purpose registers 8. The method of claim 1, wherein the particular time 25 and is executed without interruption in a single unit interval is defined by a starting time of a timer asso- of operation. ciated with the task and an ending time of the timer. 2. The method of claim 1, wherein said determining 9. The method of claim 1, wherein said method further occurs at least at a time prior to an end of a time slice comprises extracting additional information relating 30 provided for the task. to the task, wherein the determining the amount of elapsed processor time and the extracting occur as 3. The method of claim 1, wherein said determining a single unit of operation. is performed using an instruction.

10. A system comprising means adapted for carrying out 35 4. The method of claim 3, wherein said instruction all the steps of the method according to any preced- enables extraction of additional information. ing method claim. 5. The method of claim 4, wherein the extraction of 11. A computer program comprising instructions for car- additional information and the determining occur as rying out all the steps of the method according to any 40 a single, uninterruptible unit of operation. preceding method claim, when said computer pro- gram is executed on a computer system. 6. The method of claim 1, wherein the particular time interval is defined by a starting time of a timer asso- ciated with the task and an ending time of the timer. Amended claims in accordance with Rule 86(2) EPC. 45 7. The method of claim 1, wherein said method fur- 1. A method of determining central processing unit ther comprises extracting additional information re- (CPU) time usage of tasks of a processing environ- lating to the task, wherein the determining the ment, said method comprising: amount of elapsed processor time and the extracting 50 occur as a single unit of operation. selecting a task of the processing environment for which usage of central processing unit time 8. A system comprising means adapted for carrying is to be determined; out all the steps of the method according to any pre- determining an amount of the central processing ceding method claim. unit time used by the task within a particular time 55 interval, by 9. A computer program comprising instructions for carrying out all the steps of the method according to determining (202) a current value of a timer any preceding method claim, when said computer

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