Power Line Modem with E-meter Platform Ti White Paper
Power Line Modem with E-meter Platform White Paper
February 4, 2004
ti
Copyright © 2004, Texas Instruments Incorporated
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Contents INTRODUCTION ...... 4
PLATFORM BACKGROUND ...... 5 POWER LINE MODEM APPLICATIONS...... 5 EXISTING POWER LINE MODULATION TECHNIQUES ...... 6 FSK ...... 6 X-10...... 6 BPSK...... 6 Broadband (HomePlug)...... 6 DESIGN GOALS ...... 6 AN INTRODUCTION TO OFDM...... 8 Advantages of OFDM ...... 8 Fundamentals of OFDM ...... 8 SIGNAL PATH OVERVIEW ...... 10 PACKET FORMAT ...... 10 TRANSMIT SEQUENCE...... 10 Transmit Overview...... 11 Preamble and Synchronization Generation ...... 11 Data Frame Generation...... 13 Addition of Cyclic Prefix...... 15 RECEIVE SEQUENCE ...... 17 Overview of Receive Operation ...... 17 Data Flow Description of Receive ...... 17 SIGNAL PROCESSING OVERVIEW ...... 20 SIGNAL SCHEME SELECTION – QPSK...... 20 Signal Scheme Selection...... 22 Comparing Binary and Quaternary Signaling...... 23 Channel Coding Error Rate Analysis...... 25 OFDM DETAIL ...... 26 Theoretical Advantage of OFDM...... 27 Advantage of OFDM with Multi-path Interference...... 28 PARITY CHECK BYTES CALCULATION ...... 29 DATA SCRAMBLING ...... 32 VITERBI ENCODING ...... 32 MODULATION MAPPING ...... 33 Advantages to Differential QPSK ...... 34 CREST FACTOR AND TRANSMIT TRUNCATION ...... 34 Study on Transmit Truncation vs. Received SNR ...... 35 Set Power/Truncation Algorithm ...... 36 VITERBI DECODING ...... 36 Choice of Distance Metric for DQPSK...... 38 Geometric Distance Metric Computation Simplification...... 39 FREQUENCY EQUALIZATION ...... 41 BER Simulation for Various Frequency Equalization Techniques ...... 41 AGC OPERATION ...... 43 PREAMBLE WAVEFORM AND DETECTION ...... 44 OFDM Frame Alignment ...... 44
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SYSTEM BLOCK DIAGRAM AND PARTS SELECTION...... 46 Metering Processor Selection ...... 47 DSP Selection...... 47 Codec Selection...... 48 Line Driver Selection ...... 48 MEASURED DATA ...... 49 Power Line Impedance Measurement...... 49 Conformance to CENELEC Mask...... 51 CONCLUSIONS...... 52
REFERENCES ...... 53
APPENDIX. COMPLETE VITERBI TRELLIS...... 54
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Introduction The “Power Line Modem with E-meter Platform” demonstrates communication over a power line using Orthogonal Frequency Division Multiplexing (OFDM) techniques. OFDM spreads the information over several frequencies, reducing sensitivity to impulsive noise, and is able to perform better in a multi-path environment, such as a power line.
This paper describes the market rationale and architectural design of the platform. Details of the hardware and software design can be found in the “Power Line Modem with E-meter Platform Hardware Description” and “Power Line Modem with E-meter Platform Software Architecture” documents. The intent is to give enough background to allow the platform to be used as a base for a power line modem design.
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Platform Background This section introduces the motivation for making this platform and describes the markets it is meant to address.
Power Line Modem Applications The power line modem application space can be segmented as shown in Figure 1. Performance Needs
AMR SCADA
Smart Appliances Voice
Data integrity Data HVAC Multimedia
1kbps 10kbps 100kbps 1Mbps Data rate
Figure 1 Segmentation of the Power Line Modem Markets This platform is intended to address applications requiring lower data rate and higher data integrity. These applications include: • Utility/Industrial o Automated meter reading (AMR) o Tariff and rate adjustments o Load management (Security Control and Data Acquisition) o HVAC (heating, ventilation, and air conditioning) • Residential o Smart homes Smart appliances (white goods) Security/monitoring o Voice – phone extension The distinct market of multimedia is not addressed by this platform.
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Existing Power Line Modulation Techniques Here is a list of many of the power line modulation techniques in use today. In the lower data rates, it is common to use narrowband modulation techniques. In the home broadband applications, the HomePlug specification (Reference 2) is used, which uses a spread spectrum technique.
FSK Frequency shift keying is used on units targeted at utility communication. In one implementation, the carrier frequencies are centered at around 132 kHz. There is the option of using a second backup frequency if the first one is corrupted.
X-10 This technique, aimed at home automation, is a zero-cross modulation technique.
BPSK One solution offers a binary phase-shift keying modulation technique. Since BPSK is a good signaling technique, this solution is better than an FSK scheme. There is an option with this solution, too, of using a second backup frequency if the first one is corrupted.
Broadband (HomePlug) HomePlug offers broadband capability over power lines. It uses orthogonal frequency division multiplexing (OFDM) over a frequency band of 4.5MHz to 20.7MHz. OFDM is described in greater detail later in this paper. Along with the OFDM, the HomePlug specification describes several additional signal processing techniques to extract more performance from the power line channel.
Design Goals The intent of this platform was to apply OFDM techniques to the lower data rate markets. One primary market is the increasing need for energy management, including measurement, control, and communication. For this reason, the platform was combined with an electronic meter (e- meter) so that load usage could be communicated as part of the demonstration.
The data rate required by these applications is low, from 300 bits per second to 30 kilobits per second.
If this type of application were to be deployed in Europe, the signaling would have to meet Europe’s CENELEC specifications. CENELEC standard EN50065 specifies the frequency band from 9 kHz to 94.5 kHz (the “A” band) for utility communications. This platform was designed to meet the requirements both within and outside this band.
In order to maximize the robustness of the power line communication, the signal processing was patterned significantly after that specified in the HomePlug specification. As was done in
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HomePlug, this platform uses OFDM modulation techniques to spread the information over a frequency band, allowing information transmitted on corrupted frequencies to be recovered through signal processing techniques.
OFDM modulation is used not only in high data rate power line communications, but also in many modern communication channels, including cable modems, ADSL modems, IEEE 802.11a, and digital television (in most countries except the U.S.).
This paper continues by describing the signal processing used in the platform, beginning with an introduction to OFDM.
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An Introduction to OFDM Orthogonal frequency division multiplexing (OFDM) is a technique for transmitting information between two points by spreading the data bits across multiple carrier frequencies, each of which is modulated and transmitted at the same time. An OFDM “frame” is a block of time over which the carriers are modulated with a given set of data bits. The frequencies used are selected so that they can be independently detected. Mathematically, the carriers are “orthogonal” to each other.
Advantages of OFDM The advantages of using OFDM in a power line communication system are two-fold. First, the use of several frequencies makes the system more robust to narrowband interference and/or signal drop-out. That is, by using several frequencies, the loss of a single frequency prevents some, but not all, of the information from making it to the receiver. With a single-frequency system, the transmitter and receiver would have to switch to a new frequency if the original frequency were corrupted for some reason. With OFDM, the missing bits can be recovered using error correction schemes, such as Reed-Solomon codes (Reference 3), increasing throughput since retransmission of the information would not be needed.
The second advantage is that OFDM works better in multi-path systems than single-frequency systems. Many times, a signal transmitted on a power line system can reach a receiver through multiple paths, so that the receiver sees the original signal and also time-delayed versions of that signal. Further, the uncontrolled impedance of power lines can create a highly under-damped system. In a single frequency system, the time of transmission of each bit of information must be long enough so that all the time-delayed versions of the signal and oscillations due to the under- damped network are able to get to the receiver before the next bit can be transmitted. This can limit the transmission rate of a single-frequency system.
In contrast, an OFDM system transmits several bits simultaneously. Similar to the single- frequency system, the transmission of each set of bits must be delayed so that the signal stabilizes at the receiver before the next set of bits can be transmitted. However, the time delay needed per bit is divided by the number of bits transmitted simultaneously. The result is that, if the signal-to-noise ratio of the line permits it, the data rate of the OFDM transmission can be increased over that of a single-frequency system.
Fundamentals of OFDM While the details of the OFDM implementation are given in the Signal Processing Overview section below, this section will give an introduction to its operation, enough to understand the overview of the transmit and receive operations given in the next section of the paper.
The process starts with a set of digital information that is to be transmitted in an OFDM frame. The information is to be transmitted over a set of frequencies in some way. There are a lot of ways to encode the digital information on each frequency in the set (“modulation schemes”), but the end result is a list of the amplitudes and phases that are to be transmitted at every frequency
February 4, 2004 8 Power Line Modem with E-meter Platform Ti White Paper in the set. This list is in the frequency domain. Before transmitting over the channel (the power line, in our case), this information must be converted to the time domain. The method to do this is by performing an inverse Fast Fourier Transform (FFT) to the amplitude/phase information that we want to transmit. Thus, any information that is to be transmitted must be put through an IFFT (inverse FFT) before being transmitted.
When data is received over the power line, it comes to the receiver in the time domain. In order to interpret the amplitude/phase information in it, it must be converted to the frequency domain using an FFT.
OFDM signal processing, then, consists of: 1. Taking the digital data to be transmitted and splitting it into data “frames.” 2. Modulating the data through some signal processing scheme to produce a set of amplitude/phase information to be transmitted. 3. Transforming the amplitude/phase information to the time domain using an IFFT. 4. Transmitting the signal over a (noisy) channel to the receiver. 5. Transforming the time domain signal at the receiver to amplitude/phase information using an FFT. 6. Detecting the digital data using the amplitude/phase information
Steps 1, 3, and 5 are additional steps required by OFDM over a single-frequency scheme. The overhead of the FFT and IFFT operations is not significant compared to, for example, the processing required by the Viterbi detection algorithm in the last step of the process.
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Signal Path Overview This section of the paper gives an overview of the format of the packet transmitted on the power line, as well as the sequence of operations during transmit and receive operations. While many of the details are deferred to the Signal Processing Overview section, the intent is to give a compact yet complete explanation of the packet being transmitted on the power line.
Packet Format A transmitted message consists of a data packet that is divided into OFDM frames (Figure 2). The data packet contains all of the information to train and synchronize the receiver to the transmitted data.
... P0 P1 P2 P3 P4 P5 M pad data0 data1 data2 data9
Preamble field Data field
Figure 2 Packet Format
The first few frames contain known data and are used to synchronize and train the receiver. These frames are known as the “preamble” field. The preamble field is split into two parts: the “P” frames (“preamble frames”) and the “M” frames (“sync frames”). The M frames are encoded differently from the P frames and are used as a synchronization mark to identify the start of the user data field. Details of the M- and P-frames are given in the Signal Processing Overview section of this paper.
The data field consists of a fixed number of frames. Each frame has a data part and a “cyclic prefix” part. The prefix (at the front of every frame) is called the “cyclic prefix” because it is constructed by repeating the last part of the data section of the frame. The purpose of the cyclic prefix is to allow a guard band between OFDM frames to minimize the effect of intersymbol interference. The length of the cyclic prefix is set according to the expected length of the channel impulse response.
To improve the detection performance, the data frames are grouped into “blocks” of three frames. Each of the data frames in a block transmits identical data, but each data bit is transmitted on a different frequency in each of the three frames. Performance is improved in two ways: first, each bit is transmitted for three times as long; secondly, each bit is transmitted on several frequencies, so that if a particular frequency is bad, the information may still get through on the other two frequencies used for that bit in the other frames in the block.
Transmit Sequence The generation of a data packet proceeds in three steps: (1) the generation of the preamble and synchronization frames, (2) the generation of the data frames, and (3) the addition of the cyclic
February 4, 2004 10 Power Line Modem with E-meter Platform Ti White Paper prefix to the data frames. This section will describe these steps at a high level, leaving the signal processing details to later.
Transmit Overview The overall transmit operation is depicted in Figure 3. As shown here, the transmit operation consists of building the preamble, the synchronization symbol, and the data frames separately, concatenating them, and driving them onto the power line. Build preamble append frames preamble 256 sample DAC power symbols IFFT + line
Build sync frame append synchronization 256 sample cyclic symbols IFFT prefix
256 sample IFFT Build data frames
Calculate Psudo fill Parity Check random subcarriers bytes sequence
Encode data: DQPSK Get user 2bit symbol xor modulation msg data + for each data append ECC scramble bit assign symbol phase
Figure 3 Overview of transmit operation The preamble and synchronization symbols are driven onto the power line first. The construction of the data frames consists of several steps. First, a parity check sequence is calculated for the message to be transmitted. The message and parity bytes are scrambled to prevent the signal from having a large crest factor. The resultant scrambled sequence is encoded to add redundancy for the Viterbi decode operation during the receive operation. The encoded sequence is encoded using differential quadrature phase shift keying (DQPSK), where each carrier represents a symbol. The sequence is inverse Fourier transformed to form a sequence to transmit on the line. The cyclic prefix is prepended to provide buffer against multi-path channel effects. Then the sequence is driven onto the power line.
The next sections detail each of the transmission steps.
Preamble and Synchronization Generation Figure 4 shows the generation of the preamble and synchronization parts of the waveform.
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Part I. Preamble and Sync FFT_LEN=256 FFT_LEN=256 Preamble Field complex Sync Field complex Data Pattern conjugate Data Pattern conjugate CARRIER_LEN CARRIER_LEN IFFT IFFT
Preamble start half Preambe end half Sync start half Sync end half
Transmitted Waveform (Part 1):
FFT_LEN FFT_LEN FFT_LEN FFT_LEN FFT_LEN
Pream Preamble Preamble Preamble Preamble Pream Preamble Preamble Preamble Preamble Preamble Preamble Preamble Sync Sync Sync End Start End Start End Start End Start End Start End Start End Start End Start WINDOW_LEN=16 Save beginning of WINDOW_LEN=16 sync for window between sync and multiply by raised cosine multiply start of sync by 1st data frame. This window at beginning of raised cosine window and is called the "postfix" preamble to limit add start of preamble by generation of unwanted (1-window) at sync harmonics transition …
Figure 4 Part 1 of Transmit First, the preamble and synchronization data is inverse Fourier transformed to the time-domain preamble start/stop and synchronization start/stop sequences shown. The preamble and synchronization data have a length of CARRIER_LEN1 bits. The top of Figure 4 shows an example of five different carriers, each carrier an inverse transform of one value in the frequency domain array, first shown separately and then added together (the bottom of each pair of waveforms in the figure). After being IFFT’d, the preamble start and stop sequences are FFT_LEN values long (with each value in each sequence being a complex number).
The preamble is then formed as shown in the second part of Figure 4. First, the start of the preamble is windowed to prevent leakage in the FFT operation during receive. (Windowing is merely multiplying the beginning of a frame by a sequence that starts at zero and ends at one, such as a raised cosine sequence. By multiplying the current frame by this sequence and by multiplying (1-window_sequence) by the beginning of the previous frame and adding the two waveforms at the beginning of each frame, we minimize abrupt transitions from occurring in the time domain sequence and hense minimize the generation of unwanted harmonics.) Windowing operations are indicated by the arcs in the diagram. The preamble frames, each of length
1 The lengths of the various fields are given as constants in the DSP software. The same names are used here.
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FFT_LEN, are repeated 6.5 times (starting with “preamble end” followed by six pairs of “preamble start” and “preamble end”).
Next, the synchronization frames are transmitted. To prevent leakage, the start of the synchronization frame is the sum of the front part of the preamble start frame, windowed down, added with the start of the synchronization start frame, windowed up. This ensures a smooth transition between the preamble and synchronization frames. The synchronization frame is transmitted 1.5 times.
Finally, the front part of the synchronization end frame (the “postfix”) is saved so that the same windowing trick can be done between the end of the synchronization frame and the beginning of the data frames.
Data Frame Generation The generation of the data frame is shown in Figure 5. It is desired to transmit NUM_USER_BYTES (128 bytes) worth of user data. First, two bytes are appended of parity information. These bytes will be used during receive to verify that the bytes were received properly. Then, because each transmitted frame holds multiple bits, pad bytes are added to make the length of the data buffer equate to the number of frames transmitted times the number of bits per frame (1080 total bits or 136 bytes).
The data is next put through a scrambler. The purpose of scrambling the data is to reduce the probability of transmitting a frame constructed of carriers which all have the same phase. Such a waveform will have a very high "crest factor." Crest factor is the ratio of peak amplitude to RMS amplitude and the higher the crest factor the more dynamic range is required to transmit and receive the packet signal.
The data is now divided into blocks of CARRIER_LEN bits. This is because each data frame transmits CARRIER_LEN bits at a time. In our case, CARRIER_LEN × NUM_DATA_BLOCKS is equal to the number of bits to be transmitted. Care must be taken to ensure that the last several bits to be transmitted are zeroes to allow the Viterbi detector to resolve properly during the receive operation.
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Part II. Data Frame Generation
Parity check bytes
2 6 NUM_USER_BYTES=128
User Data Pad DATA_BUFFER_LEN=136 bytes
scrambler Pad with zeroes at end to close 136x8=1088 bits, 1080 used out Viterbi
Number of bits=CARRIER_LEN x NUM_DATA_BLOCKS 0 = 60 x 18 = 1080
Note: differential encoding, rate 0.5 CARRIER_LEN=60 CARRIER_LEN customer bits gives 2 x CARRIER_LEN encoded bits, CARRIER_LEN but every pair becomes one phase, so get CARRIER_LEN phases.
phase Data Frame 0 … 59 Viterbi encode array IFFT without Cyclic Prefix output data frames
DATA_FRAMES_ phase Data Frame 15 … 59 0 … 14 Viterbi encode Still need PER_BLOCK = 3 array IFFT without Cyclic Prefix to add cyclic prefix … phase Data Frame 30 … 59 0 … 29 Viterbi encode array IFFT without Cyclic Prefix FFT_LEN FFT_LEN
SYMBOL_OFFSET DATA_FRAMES_PER_BLOCK x NUM_DATA_BLOCK = number of data frames
Figure 5 Part 2 of Transmit Each set of CARRIER_LEN bits is transmitted DATA_FRAMES_PER_BLOCK times. That is, the data is transmitted multiple times (across three frames) on a different frequency in each frame, to increase the chances that the bit will be seen at the receiver. In the first frame, bits 0 through 59 are transmitted across the sixty carriers. In the second frame, bits 15 through 59 are transmitted on the first 45 carriers, and then bits 0 through 14 are transmitted on the last 15 carriers. In the third frame, bits 30 through 59 are transmitted on the first 30 carriers, and the remainder of the bits on the last 30 carriers. The software symbol SYMBOL_OFFSET controls the placement of the bits in the three frames.
The data for each of the three data frames is generated by putting the scrambled user data through a convolutional encode algorithm. This coding, described in detail in the Signal Processing Overview section of this document, adds redundancy to the information being transmitted. During receive, a detector based on the Viterbi algorithm uses this redundancy to recover the data more accurately. The code used is a half-rate code; for every bit encoded, two bits are formed. The coding is also specialized to accommodate the differential nature of the coding used on each carrier.
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The result of the encoding is a list of CARRIER_LEN phase values, one for every frequency. Because we are using quadrature phase shift keying for each carrier, the two bits that were generated by the convolutional encode translate into a single phase value, so that, in the end, we end up with CARRIER_LEN phase values for the CARRIER_LEN frequencies to be transmitted per frame based on Carrier _LEN user data bits.
This list of values is placed into the proper bins of an array of FFT_LEN (256) values long. Specifically the complex phase values are placed in bins 30 through 90 and the complex conjugate of the phase values is placed in reverse order in bins 224 through 165. The phase information is inverse Fourier transformed to produce a real (as opposed to complex) waveform of the data frame to be transmitted.
However, the data frame isn’t ready to transmit yet. The cyclic prefix must be attached to the front of it next.
Addition of Cyclic Prefix Many communication channels introduce errors due to multi-path interference. That is, the receiver sees multiple copies of the transmitted signal, each arriving with a different delay and amplitude. This is true for power lines when used as a communication channel because of the many unterminated wires connected to each net. In order to accommodate this effect a guardband is inserted between each data frame that is longer than the worst delay expected. Since OFDM data frames are generated and detected using the FFT algorithm and since the FFT algorithm assumes that an N sample waveform is periodic, the best signal to insert as a guardband is a copy of the tail end of the current data frame. This guardband is called the "cyclic prefix."
In addition to preventing multi-path interference at the receiver, there is also the requirement not to generate frequency content outside of the allowed carrier frequency band. Such generation is called leakage and is due to the sharp transition in the transmit waveform that can occur between frames. By windowing the beginning of the cyclic prefix the transition can be smoothed and the generation of harmonics outside the carrier frequency band can be minimized. The windowed portion of the cyclic prefix consists of a raised cosine function times the beginning of the current cyclic prefix plus (1- raised cosine) times the beginning of the IFFT output sequence for the previous frame. The beginning of the previous IFFT sequence is used because of the periodic nature of the FFT algorithm. The next sample the FFT would expect to see after the last sample in the sequence is the first sample in that sequence.
Figure 6 illustrates the process.
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Part III. Addition of Cyclic Prefix
Inputs: Postfix from Data Frame Data Frame preamble 1 2
FFT_LEN=256 FFT_LEN WINDOW_LEN WINDOW_LEN WINDOW_LEN =16 CYCLIC_ CYCLIC_ PREFIX_ PREFIX_ Data Frame LEN=42 Data Frame LEN
WINDOW_LEN WINDOW_LEN
+ + from part I
= =
Output: Sync CP1 Data Frame 1 CP2 Data Frame 2 Start …
CP=cyclic prefix
CP1 = postfix from the preamble windowed down + cyclic prefix of Data Frame 1 windowed up CP2 = postfix from Data Frame 1 windowed down + cyclic prefix of Data Frame 2 windowed up
CPn = postfix from Data Frame n-1 windowed down + cyclic prefix of Data Frame n windowed up (n ≠ 1) Figure 6 Part 3 of Transmit Starting with the first Data Frame, a cyclic prefix (which is the last CYCLIC_PREFIX_LEN bits of the frame) is put in front of each data frame. This will prevent interference from delayed copies the signal previous to the data frame from corrupting the data detection. Instead it will be the cyclic prefix that is delayed and added to the signal that is FFT'd. Since the cyclic prefix contains the same amplitude and phase at each carrier frequency as the data frame, the effect of the addition of the multi-path interference signal will be a phase shift but not a loss of signal power. This phase shift is compensated for during the frequency equalization process. Additionally, to prevent the transmission of unwanted harmonics, a raised cosine window is applied to the beginning of the cyclic prefix. By placing the windowed transition between data frames at the start of the cyclic prefix the transition has minimal impact on data detection. The windowed transition consists of the postfix from the previous frame, which for the first data frame is the sync frame, and the beginning of the cyclic prefix. The postfix is multiples by a decreasing sample sequence while the front end of the cyclic prefix is multiplied by an increasing sequence. These two are added together to modify the front end of the cyclic prefix (CP1). This process is repeated for each data frame until the last frame, which is only includes the postfix.
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Receive Sequence The receive operation is described here at a high level. Details of many of the operations are described later in the paper.
Overview of Receive Operation An overview of the receive operation is shown in Figure 7.
AGC function if( CRC == 0 ) yes declare codec AGC Hold packet no good power VGA ADC 256 sample line FFT preamble det Calc parity check bytes
Receive Memory Buffer frame align Pass data User message on to data e-meter sync det de-scramble Pseudo xor random freq equ sequence
Viterbi Viterbi distance decode metric
Figure 7 Overview of Receive Operation The receive algorithm starts by transferring the ADC samples from the codec into the DSP. The codec’s programmable gain amplifier (PGA) is adjusted to maintain an approximately constant amplitude signal into the FFT using the AGC (automatic gain control) algorithm.
Repeated FFTs are taken of the input sequence until the preamble is detected. The receive algorithm determines the start of the frame using the frame align algorithm and then detects the exact start of the data with the synchronization detection algorithm. During the preamble, the channel’s response was characterized, and this characterization is used in the frequency equalization algorithm. The remaining steps are performed in the opposite order they were performed during the transmit operation: after the Viterbi decode determines the most likely data sequence, the sequence is descrambled to form the user message and parity check bytes. If the parity check bytes indicate the message was received successfully, then the user message is declared good.
Data Flow Description of Receive An overview of the receive operation’s data flow is shown in Figure 8.
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Receive Operation Data frame Data frame 1 Data frame 2 DATA_FRAME _BLOCK x NUM_DATA_BLOCK channel estimation done on preamble
Data Preamble Sync CP CP… CP
AGC State AGCIdle AGCPreamble AGCHold … AGCIdle
Frame Align
FFT and equalize based on channel estimate of preamble CYCLIC_PREFIX_LEN CARRIER_LEN FFT_LEN FFT_LEN ignore CP Data frame 3i -2 CP 0 … 59
+ SYMBOL_OFFSET
Data frame 3i -1 CP 15 … 59 0 … 14 +
Data frame 3i CP 30 … 59 0 … 29 =
Averaged phase 0 … 59 array block i Repeat for i=1 to NUM_DATA_BLOCK
……
CARRIER_LEN x NUM_DATA_BLOCKS Parity check bytes - verify parity to see if packet is OK.
Viterbi decode 2 6 NUM_USER_BYTES=128 Descramble
Scrambled Data User Data Pad DATA_BUFFER_LEN=136 bytes Figure 8 Receive Operation
While searching for a packet, the modem activates its automatic gain control function. This function adjusts the gain of the programmable gain amplifier in the codec based on the amplitude of the input signal. The algorithm reduces the gain quickly if a large signal is seen while allowing the gain to increase slowly with smaller signals. At the same time, the packet search algorithm begins to look for patterns that look like the preamble pattern. Because preamble frames consist of a known data pattern and are repeated, the search algorithm can look for this data pattern without needing to determine the absolute beginning of the packet. Once the presence of preamble frames, and therefore a data packet, is recognized, the programmable gain amplifier gain is held at this gain for the rest of the data packet.
The search algorithm now collects FFT data for successive preamble frames until an abrupt change in the phase modulated data pattern is found. This indicates that the synchronization frame has been reached. When that occurs, the collected and averaged FFT data is divided by the know frequency content of the transmitted preamble frame. The IFFT algorithm is then applied to this quotient. The time domain output of the IFFT represents the impulse response of
February 4, 2004 18 Power Line Modem with E-meter Platform Ti White Paper the communication channel and the sequence sample that has the largest absolute value corresponds to the start of the transmitted frames. This offset is added to the sample where the preamble was first detected to align the receiver to the transmitted frames. This process is called frame alignment.
If at any point in the search algorithm something occurs that doesn’t look right (e.g., not enough preamble with good phase characteristics is seen), then the search algorithm reverts to looking for the start of preamble.
Another operation that occurs while the preamble is being sensed is the calculation of the channel’s frequency response. This is called channel estimation. This is calculated by dividing the known preamble frequency response by the averaged received preamble frequency response. These complex quantities are multiplied with the corresponding detected data carrier value during data detection to correct for amplitude and phase errors introduced by the communication channel. This process is called frequency equalization.
Once the modem has achieved frame alignment and calculated the frequency equalization values, then each frame is read in sequence. Each frame is CYCLIC_PREFIX_LEN + FFT_LEN samples long, and consists of the cyclic prefix and the data frame. The cyclic prefix is first discarded, leaving a record FFT_LEN samples long. The record is FFT’d to produce a frequency domain version of the signal. Because the signal only used CARRIER_LEN carriers, only these carriers are stored.
The FFT’d values are equalized using the channel estimation values found in the preamble.
Because each data frame was repeated DATA_FRAMES_PER_BLOCK (=3) times, this number of frames are combined before entering the Viterbi algorithm decoder. The phases of the carriers in the three frames corresponding to each bit are averaged.
The averaged data is sent to the Viterbi decode that determines the most likely sequence of bits that produced the observed phases. The Viterbi performs a soft decision decoding on the data. The result is CARRIER_LEN bits for each block of three frames. These decoded bits are placed in the receive data buffer and the process is repeated for each data block to the end of the data packet.
Finally, the data in the receive data buffer must be descrambled to counteract the scrambling done during transmit. The buffer now contains NUM_USER_BYTES (128) user bytes and two parity check bytes. The parity check bytes are used to see if the data is valid. If so, the data is declared good.
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Signal Processing Overview This section fills in many of the details of the signal processing described at a high level in the previous sections. The section begins by describing the selection of the signal scheme used in the modem and then delves into the details of OFDM. Following that, details of the transmit and receive signal processing are considered in turn.
Signal scheme selection – QPSK The first step in choosing the signal processing scheme used for each carrier was to look at the theoretical operation of several schemes in white noise. Schemes considered included: • Coherent frequency shift keying (coherent FSK) • Non-coherent frequency shift keying (non-coherent FSK) • Coherent quadrature phase shift keying (coherent QPSK) • Non-coherent (differential) quadrature phase shift keying (DQPSK) • Binary phase shift keying (BPSK) • Non-coherent (differential) binary phase shift keying (DPSK) • Coherent 8-ary phase shift keying (coherence 8-PSK) • Differential 8-ary phase shift keying (D 8-PSK) • 64- Quadrature Amplitude Modulation (QAM)
“Coherent” schemes require an external clock; “differential” schemes use the phase of the previous bit to calculate the phase of the next bit, and so do not require an external clock.
The theoretical performances of the various schemes are listed in Table 1 and shown in Figure 9, which shows the log of the bit error rate as a function of the signal-to-noise ratio (SNR). The
SNR is defined as the signal power, Sav , divided by the noise power contained in a bandwidth of 1 , whereTb is the transmission time for a single bit. This time is equal to a frame time for Tb binary schemes. For quaternary, 8-ary, and 64-ary transmission schemes, the transmission time per bit is less than a frame time (since multiple bits are transmitted on each carrier each frame). The signal power is the energy per bit divided by the transmission time per bit: E = b S av Tb N Assuming a double-sided noise power spectral density of 0 (V2/Hz), the SNR is: 2 S E /T E SNR = av = b b = b 1 N N noisein ± 2 • 0 0 T b Tb 2 Since the SNR expression gives a power ratio, SNR in dB’s is expressed as: = SNRdb 10log10 (SNR)
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Error Rate Summary Define: • Tb = time per transmitted bit • A = amplitude (base to peak) of signaling sinusoid 2 • N0/2 = double-sided noise power spectral density (V /Hz) ∞ 1 − 2 1 y • Q(y) = ∫ e z / 2 dz = erfc( ) π y 2 2 2 ± SNR (= Eb N0 ) is the ratio of the power per bit and the noise power in a bandwidth of 1 Tb . SNR is defined as a ratio of powers, so SNR in dB is 10*log10(SNR/10) Scheme Parameter Coherent FSK Nonco- Coherent DQPSK∇@ BPSK DPSK Coherent 8-PSK D-8PSK 64-QAM ^ herent FSK QPSK∇ Filter BW 1 (1.5T ) 1 (1.5T ) 1 ( 3T ) 2 Tb 2Tb 1Tb 1Tb 2Tb 2Tb b b b E A2T A2T A2T A2T A2T A2T A2T A2T A2T A2T A2T A2T 7a 2 b b b b = s b = s b b b = s b = s (energy 2 2 2 4 2 4 2 2 2 6 2 6 per bit)
2 1 2 η 2 2 2 1 −A2T /( 2N ) 2 2 2 Peb (bit A Tb /( 4 ) b 0 0.228A T * 0.61A Tb e A Tb * 0.56 A Tb * A Tb e 2 0.44A Tb * Q b 2 2a error rate) Q 2 Q Q Q 2 Q Q N N N N 3 N N 0 3 N 0 0 0 0 0 0
* * (in ()1 − ()()()1 −SNR 2 2 Peb Q 1.21( SNR ) e SNR / 2 Q 2( SNR ) Q 1.12( SNR ) Q 2(SNR) e Q()0.88( SNR ) Q()0.46( SNR ) 2 2 2 3 3 Q ( SNR ) terms of 2 3 7 SNR) Table 1 Theoretical Performance of Signal Processing Schemes in White Noise * -- assuming the data has been grey coded ∇ = -- for QPSK schemes, Tb 0.5Ts , the symbol time @ -- Reference 5 assumes a clean phase reference derived from the previous symbol. This is how we implement the PLC modem. ^ -- 64-QAM: signal is the sum of a sine and cosine wave, each with amplitudes of one of {a,3a,5a,7a}.
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Error rates vs. SNR
0 D8PSK -1 Noncoherent FSK 64-QAM -2 -3 Coherent 8PSK -4 -5 Coherent QPSK and BPSK Coherent FSK
-6 DPSK DQPSK Log bit error rate error bit Log -7 -8 0 5 10 15 SNR (dB)
Figure 9 Error rate performance of various signaling schemes
Signal Scheme Selection Coherent QPSK and coherent BPSK give the best performance of the schemes considered followed by differential BPSK (DPSK), and then coherent FSK and differential QPSK (DQPSK). Using an 8PSK (or higher-order) scheme does not improve performance over the QPSK schemes
Competitive modem solutions use FSK and BPSK schemes. As can be seen by Figure 9, BPSK works very well, while FSK (and especially non-coherent FSK) is not a very good scheme to use.
For simplicity of implementation, our modem design was restricted to use a differential scheme. With a differential scheme, no external clock recovery circuit would be needed. It would seem from the error rate comparison above that DPSK (differential binary phase-shift coding) would be the correct choice. In an OFDM design, however, one can take advantage of the bandwidth efficiency of higher order schemes, such as DQPSK, to allow additional coding bits to be transmitted in the channel, improving the overall error rate performance. This will be explored more in detail below. It turns out that the coding gain of using additional bits is large enough to “pay” for the loss in performance of the DQPSK scheme when compared to the DPSK scheme. It turns out, too, that using a more bandwidth- efficient scheme results in a comparatively shorter bit time. In a differential system, it is best to keep the integration time (bit time) short to prevent any clock mismatch between the transmitter and receiver from degrading the error rate. Finally, selecting DQPSK would make it easier to migrate the code to support coherent QPSK (with additional hardware) if the best performance were desired.
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Comparing Binary and Quaternary Signaling Consider an OFDM system consisting of N carriers, each using (either differential or coherent) binary phase-shift keying (BPSK or DPSK). This system is illustrated in Figure 10. In this figure, the x-axis is time and the y-axis is frequency. The plot shows that the OFDM system uses a certain total bandwidth and that each bit is integrated over the same amount of time. As is shown below (see “Theoretical Advantage of OFDM”), the bit error rate of this system is the same as a single-frequency system of the same data rate and bandwidth.
Figure 10 BPSK system shown on a time/frequency plane
The overall data rate of the system, R, is the number of carriers, N, multiplied by the bit rate of each carrier. The integration time for each carrier is TbB, which is equivalent to the inverse of the bit rate.
The amplitude of each carrier is AB. The total power, PB, is computed as N times the power of each carrier.
Now, quaternary phase-shift keying is twice as bandwidth efficient as binary phase-shift keying (compare the required filter bandwidths in Table 1 above). So, one thing that could be done to reduce the bandwidth requirement on a system is to shift to QPSK. The result is shown in Figure 11.
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Figure 11 QPSK at the same data rate as the BPSK scheme
Here, the bandwidth is reduced by a factor of two compared to the bandwidth required for the BPSK scheme. There are now half as many carriers as before, and the amplitude of each carrier, AQ, can be increased compared to the amplitude of the carriers in the BPSK scheme while maintaining the same aggregate output power. The symbol integration time is now the same as the bit integration time in the BPSK scheme, so there is no disadvantage or advantage compared to the BPSK scheme in terms of clock drift over the integration period.
Finally, the SNR is the same as the DPSK/BPSK schemes, but since this modem is using differential encoding, there will be an error rate loss (as shown in Figure 9) between DQPSK and DPSK just due to using differential encoding (there would be no error rate loss if the modem used coherent encoding, since the error rates are the same between BPSK and QPSK). The end result is that the bandwidth has been reduced in half, but there is an increase in error rate in our differentially-encoded system.
The question naturally arises: since the bandwidth has been halved, is there some way to spend that freed-up bandwidth to improve the error rate?
The bandwidth of a quaternary system is half of the total data rate. To double the bandwidth (returning to the original bandwidth usage), the only alternative is to double the data rate. Consider spreading the carriers further apart to use the available bandwidth. The result is shown in Figure 12.
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Figure 12 Method to double the data rate in the same bandwidth as the original BPSK scheme
In Figure 12, the total bandwidth is the same as the original BPSK signaling. Because there are N/2 carriers, then the amplitude of each carrier, AD, is larger than in the original scheme. But, the integration time, TsD, is half of what is was in the original scheme. This is an advantage in differential signaling schemes without clock recovery, because the clock drift will be halved over the integration time of the detector. This is a key advantage to using a quaternary scheme.
Since the data rate has doubled, it’s no surprise that the SNR has degraded by 3dB. One could just stop here and just used the bandwidth advantage of quaternary schemes to double the data rate for the same bandwidth usage. Since a differential signaling scheme is being used, there would be some performance loss from using DQPSK compared to DPSK, as shown in Figure 9. But, this would give us a higher data rate in the same bandwidth, which could be important in some applications.
The alternative is to use the extra capacity to perform coding on the channel. This will give a coding gain that will improve the overall performance of the channel – better, it turns out, than the original BPSK scheme. Note, though, that there is a significant amount of performance to get back: first, 3dB were lost by doubling the data rate, and another 1.8 dB were lost because of using a differential quaternary scheme instead of the original differential binary signaling scheme. Fortunately, coding and maximum-likelihood detection will give these losses back, and more, as described next.
Channel Coding Error Rate Analysis This section considers the performance of a DQPSK system augmented with convolutional coding. This coding, described below, is a k=7, ½-rate, convolutional code.
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The coding scheme (using differential QPSK) was simulated and its error rate compared against the DQPSK, DPSK, QPSK, and BPSK coding schemes described above. The result is shown in Figure 13. The figure shows that the error rate of the coded system is slightly worse than DQPSK at very low SNRs, but crosses over coherent QPSK and BPSK (the best schemes in Figure 9) at about 6dB SNR. The boxes show that the simulation results of the BPSK as simulated match the theoretical plot. The convolutional encoder was run using exactly the same noise with error rate results shown with the triangles. Error rates vs. SNR
0 -1 -2 DQPSK -3 -4 Coherent QPSK -5 and BPSK -6 Coded -7 DQPSK DPSK Log bit error rate error bit Log -8 0 5 10 15 SNR (dB)
Figure 13 Comparison of Error Rates with Convolution Encoding
It is apparent that the coding can give significant error rate improvement at moderate SNR’s, allowing the PLC modem to use differential coding instead of coherent coding (which would require clock recovery circuitry).
Parenthetically, the error rate degradation of the coded DQPSK at poor SNR’s is due to the Viterbi detector’s errors coming in bursts. Many of these burst errors can be recovered using Reed-Solomon coding, assuming the data is permuted to spread the bursts over the interleaves of the Reed-Solomon code. Reed-Solomon coding was not implemented in our demonstration modem design.
OFDM detail Orthogonal frequency division multiplexing (OFDM) relies on the fact that it is possible to transmit several sinusoids of different frequencies and detect the sinusoids independently with no interference between the sinusoids transmitted. Mathematically, the selection of the various sinusoid frequencies is performed so that the sinusoids are orthogonal.
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Let the transmission frame be a specific time, T, in length. Let f0 be the inverse of the frame time. The sinusoids are chosen to be multiples of f0 in frequency.
ω = π For notational convenience, let 0 2 f0 .
ω ω + φ Consider two sinusoids chosen this way: cos( n 0t ) and cos( m 0t ), where phi is an arbitrary phase angle between the two cosine waves. These two sinusoids are orthogonal if (1) the integration of their product over a period T is zero when n ≠ m , and (2) the integration of their product over a period T is non-zero when n=m. (This means that, later on, when a Fourier transform is taken by multiplying by sinusoids of various frequencies, only the desired carrier gets selected). With our signals, this turns out to be true: T T ϖ − ϖ ϖ φ − ϖ − φ jn 0t + jn 0t jm 0t j + jm 0t j ϖ ϖ + φ = e e e e e e ∫∫cos( n 0t )cos( m 0t )dt dt 0 0 2 2 T = 1 ()()()+ ϖ + φ + − ϖ −φ ∫ cos n m 0t cos (n m) 0t dt 2 0 ≠ 0 if n m = T cosφ if n = m 2 So, the result of multiplying by a cosine wave is either zero, if the frequency is different, or proportional to the phase difference between the reference cosine wave and the phase-shifted cosine wave. This principal is used in the discrete Fourier transform to extract the phase information for each carrier when received. (Recall that each carrier was phase encoded using quadrature phase shift keying.)
In summary, the selection of the signals is to choose the length in time of a frame and make the carriers multiples of this fundamental frequency. In our design, the frame is chosen to be 1 ms long, so that the carriers are all multiples of 1 kHz. The carriers are then chosen to lie in a selected frequency band – in our case, selected to fall within the CENELEC A-band.
In OFDM, several carriers are transmitted at once. An amplitude and phase is selected for each carrier. The information, then, is naturally described in the frequency domain. Using an inverse discrete Fourier transform, the corresponding time sequence can be constructed. Computationally, an inverse fast Fourier transform, written in assembly code, is used.
On reception, the signal is discrete Fourier transformed (using an FFT) to find the phase of each carrier. Because of the orthogonality property of the signals, each carrier is detected independently. The detected phases are then put into the detection algorithm.
Theoretical Advantage of OFDM In theory, there is no inherent SNR advantage to using OFDM over a single-frequency modulation scheme. To see this, consider a coherent QPSK system operating at a single frequency compared with an OFDM system consisting of several QPSK channels. Suppose that there are M bits to be transmitted. In the single frequency system, the bit error rate is (assuming differential detection):
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0.56 A2T = s1 Peb Q 2N0 M Because there are M 2 symbols to be transmitted, the total transmission time is T . The other 2 s1 symbols in the equation are defined above.
In a comparable OFDM system, M 2carriers are transmitted, each carrying 2 bits (one symbol). The total time per symbol is the entire transmission time: M T = T . s2 2 s1 Assume that the total power is the same between the two schemes. Let a be the amplitude of the M 2carriers. Then: A2 a 2 = . M 2 Calculating the bit error rate: 2 M 2 0.56 A T 2 0.56a T s1 0.56 A T P = Q s2 = Q 2 = Q s1 . eb 2N M 2N 0 ()2N 0 2 0 So, the theoretical symbol error rate is the same whether OFDM is being used or not. There is no theoretical advantage of OFDM in white noise.
There are, however, advantages to using OFDM in a power line communication system. The real advantage is being able to spread the information over several frequencies to allow coding to regain lost information due to multi-path or frequency-specific interference. In the frequency-specific case, “bad” frequencies correspond to losing bits in a packet. If the bad frequencies are widely spaced the convolutional encode and Viterbi algorithm decode process will recover the bits. If there is a whole range of bad frequencies an outer (Reed-Solomon) code could be used to recover the bits not received correctly. The multi-path case is described in the next section.
Advantage of OFDM with Multi-path Interference Multi-path interference limits the data rate of a traditional system because data from the previous bit contaminates the present bit (Figure 14). In order to prevent this contamination from affecting the error rate, it’s necessary to slow the data rate down sufficiently that the interference from the previous bit is less than some fraction of a bit time. So, in a single frequency system, the data rate can be limited by the multi-path interference time.
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Tb
Previous Bit Present Bit
Previous Bit Delayed Present Bit Delayed
Figure 14 Illustration of Multi-path Interference
In an OFDM system, the guard band needs to be the same length. However, since several bits are being transmitted at the same time these bits all share the same guard band so the guard band overhead per bit is substantially less. So, the data transmission can be more efficient and the resultant data rate can be higher (Figure 15). In OFDM systems the guard band is called the cyclic prefix.
Tb
Previous Bits Present Bits
Previous Bits Delayed Present Bit Delayed
cyclic prefix time
Figure 15 The Cyclic Prefix for OFDM Signaling
Parity Check Bytes Calculation A 16-bit cyclic redundancy code (CRC) is appended to the user data to verify data integrity. The CRC detects if any of the bits are received in error.
The CRC-16 polynomial used is x16 + x15 + x2 + x0 . Conceptually, the user data bytes are serialized and passed through the CRC generation circuit (MSB’s first) shown in Figure 16. Also, two bytes of zeros are put through the shift register after the user data. The result is that the user data has been divided by the CRC polynomial, giving a sixteen bit remainder that is appended to the user data.
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Serial Data In
x15 + x14 x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 + x1 x0 +
Figure 16 Conceptual CRC Generation Circuit
In actuality, the CRC generation is done a byte at a time. This corresponds to shifting the data through the shift register eight times for each user byte.
Letting n be the time index and b be the input serial data, the output eight bit times later is: + = + ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ x0 ( n 8 ) b( n 7 ) x8 ( n ) x9 ( n ) x10 ( n ) x11 ( n ) x12 ( n ) x13 ( n ) x14 ( n ) x15 ( n ) + = + ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ x1( n 8 ) b( n 6 ) x9 ( n ) x10 ( n ) x11 ( n ) x12 ( n ) x13 ( n ) x14 ( n ) x15 ( n ) + = + ⊕ ⊕ x2 ( n 8 ) b( n 5 ) x8 ( n ) x9 ( n ) + = + ⊕ ⊕ x3 ( n 8 ) b( n 4 ) x9 ( n ) x10 ( n ) + = + ⊕ ⊕ x4 ( n 8 ) b( n 3 ) x10 ( n ) x11( n ) + = + ⊕ ⊕ x5 ( n 8 ) b( n 2 ) x11( n ) x12 ( n ) + = + ⊕ ⊕ x6 ( n 8 ) b( n 1) x12 ( n ) x13 ( n ) + = ⊕ ⊕ x7 ( n 8 ) b( n ) x13 ( n ) x14 ( n ) + = ⊕ ⊕ x8 ( n 8 ) x0 ( n ) x14 ( n ) x15 ( n ) + = ⊕ x9 ( n 8 ) x1 ( n ) x15 ( n ) + = x10 ( n 8 ) x2 ( n ) + = x11( n 8 ) x3 ( n ) + = x12 ( n 8 ) x4 ( n ) + = x13 ( n 8 ) x5 ( n ) + = x14 ( n 8 ) x6 ( n ) + = ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ x15 ( n 8 ) x7 ( n ) x8 ( n ) x9 ( n ) x10 ( n ) x11( n ) x12 ( n ) x13 ( n ) x14 ( n ) x15 ( n ) As described in Reference 7, these operations can be performed in a couple of steps (Figure 14) using ∆ ∆ a sixteen-bit shift register. First, the quantities 15 through 0 are calculated (actually, these are found by table lookup, as will be described in a few paragraphs). Then the next byte of user data, b(n..n+7), is shifted into the sixteen bit shift register. Finally, the shift register is XOR’d with the values ∆ ∆ 15 through 0 .
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x15(n) x8(n) x7(n) x0(n) b(n) b(n+7)
x7(n) x0(n) b(n) b(n+7)
⊕ ∆ ∆ 15 0
=
x15(n+8) x0(n+8)
Figure 17 Method to Calculate CRC
∆ ∆ The values 15 through 0 are found by rearranging the equations above. Basically, these values are what are required to get from the second row in Figure 17 to the last row. ∆ = + ⊕ = ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ 15 x15 ( n 8 ) x7 ( n ) x8 ( n ) x9 ( n ) x10 ( n ) x11( n ) x12 ( n ) x13 ( n ) x14 ( n ) x15 ( n ) ∆ = + ⊕ = 14 x14 ( n 8 ) x6 ( n ) 0 ∆ = + ⊕ = 13 x13 ( n 8 ) x5 ( n ) 0 ∆ = + ⊕ = 12 x12 ( n 8 ) x4 ( n ) 0 ∆ = + ⊕ = 11 x11( n 8 ) x3 ( n ) 0 ∆ = + ⊕ = 10 x10 ( n 8 ) x2 ( n ) 0 ∆ = + ⊕ = 9 x9 ( n 8 ) x1 ( n ) x15 ( n ) ∆ = + ⊕ = ⊕ 8 x8 ( n 8 ) x0 ( n ) x14 ( n ) x15 ( n ) ∆ = + ⊕ = ⊕ 7 x7 ( n 8 ) b( n ) x13 ( n ) x14 ( n ) ∆ = + ⊕ + = ⊕ 6 x6 ( n 8 ) b( n 1) x12 ( n ) x13 ( n ) ∆ = + ⊕ + = ⊕ 5 x5 ( n 8 ) b( n 2 ) x11( n ) x12 ( n ) ∆ = + ⊕ + = ⊕ 4 x4 ( n 8 ) b( n 3 ) x10 ( n ) x11( n ) ∆ = + ⊕ + = ⊕ 3 x3 ( n 8 ) b( n 4 ) x9 ( n ) x10 ( n ) ∆ = + ⊕ + = ⊕ 2 x2 ( n 8 ) b( n 5 ) x8 ( n ) x9 ( n ) ∆ = + ⊕ + = ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ 1 x1( n 8 ) b( n 6 ) x9 ( n ) x10 ( n ) x11 ( n ) x12 ( n ) x13 ( n ) x14 ( n ) x15 ( n ) ∆ = + ⊕ + = ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ 0 x0 ( n 8 ) b( n 7 ) x8 ( n ) x9 ( n ) x10 ( n ) x11 ( n ) x12 ( n ) x13 ( n ) x14 ( n ) x15 ( n )
Interestingly enough, all of these quantities are functions of x8 ( n ),L,x15 ( n ) , meaning that they can be pre-computed and placed in a table that can be indexed using these 8 bits. This table is computed
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once using the algorithm given in Reference 7 (which gives the same results as the equations here). Then the CRC is calculated using the algorithm illustrated in Figure 17 for every byte being transmitted.
When the packet is received, the data is put through the same algorithm. If there are no errors, then the calculated CRC will be zero.
Data scrambling The user message, consisting of NUM_USER_BYTES (128) bytes plus the two parity check bytes, is next scrambled by XOR-ing each bit with the output of a linear shift register (LSR) having the generator polynomial S()x = x 7 + x 4 +1. Conceptually, the scrambler operates as shown in Figure 18. The shift register elements are initialized to ones at the start of the message. The input data is serialized and XOR’d with the output of the LSR. Because S(x) is a primitive polynomial, the sequence repeats every 27-1 clocks. Input Data
+ + Output Data
Figure 18 Scrambler Block Diagram
The purpose of scrambling the data is to reduce the probability of transmitting a frame constructed of carriers which all have the same phase. Such a waveform will have a very high "crest factor." Crest factor is the ratio of peak amplitude to RMS amplitude and the higher the crest factor the more dynamic range is required to transmit and receive the packet signal.
In the actual software implementation, the data is not serialized. Instead, the LSR was run offline and the values with which the data is XOR’d stored in a table. Then the XOR operation is performed a word at a time.
Viterbi Encoding After the data is scrambled, the data is encoded using a rate ½, k=7, error correcting Hamming code (Reference 6). In this way, each user data bit is encoded into a 2-bit symbol that modulates one of the carriers (since the modem uses a quadrature encoding scheme that modulates two bits onto one carrier). Figure 19 shows the encoder.
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X output
input data D D D D D D
Y output
Figure 19 Viterbi Encoder The shift register is initialized to all zeroes at the start of each packet.
Modulation Mapping Every pair of bits of the encoded data is called a symbol and is assigned to a carrier in an OFDM frame. The bits select a modulation mapping based on differential quadrature phase shift keyed (DQPSK) modulation. In this implementation of DQPSK modulation, each 2-bit symbol (carrier phase) is based on the phase of the previous symbol (carrier phase). To accommodate the phase difference measurement performed by the receiver, the first symbol in each transmitted frame is the sum of the mapped phase for that symbol and the phase of the first symbol in the previous frame. Each subsequent symbol in the transmitted frame is the sum of its mapped phase and the phase of the previous symbol in that frame. Essentially, the phase of each carrier in a transmitted frame is the cumulative sum of the phase of the previous carriers. This "precodes" the phase so that the receiver can calculate the differential phase between carriers. This improves the receiver’s tolerance to timing errors relative to non-differential QPSK modulation.
With the phase encoded this way the original mapped phase is found by finding the difference in phase between adjacent symbols.
input phase relative to prev. constellation bits subcarrier (degrees) point 01 = 0+j1 00 0 1 11 = -1+j0 00 = 1+j0 01 90 j
10 -90 -j 10 = 0-j1 11 180 -1 Figure 20 Modulation Mapping
The pre-code algorithm is: • Let φ=0. • Loop: o Get the next two bits o Translate the bits to ∆φ using the table above
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o Compute φnew=φ+∆φ o Translate the new φ to a constellation point using the table above and output
o Let φ=φnew This table gives an example.
φ Input ∆φ φnew Constellation bits Point 0° 00 0° 0° 1 0° 10 -90° -90° -j -90° 11 180° 90° j 90° 01 90° 180° -1 180° 01 90° -90° -j -90° 00 0° -90° -j -90° 00 0° -90° -j Table 2 Example of Precoding
Advantages to Differential QPSK By detecting the differential phase, frame to frame, in the first symbol, frame to frame variations between the transmit and receive sample clocks are compensated for. Thus, the system does not require an external phase-locked loop for clock alignment.
By detecting the differential phase carrier to carrier in the rest of the frame, effects of phase distortion due to the channel are reduced, since adjacent carriers will have approximately the same phase response.
Crest Factor and Transmit Truncation The “crest factor” of a signal is defined as the highest peak of a signal divided by the RMS value of the signal. The crest factor of a sine wave is 2 .
Driving a signal with a high crest factor requires a higher voltage supply on the driver than driving a signal with a lower crest factor for the same output power. Because OFDM signals are composed as a sum of many sinusoids over a band of frequencies, they tend to resemble white noise, which has a crest factor of 3 or more. The actual crest factor of a signal is highly dependent on the data being transmitted. Because of this, techniques had to be built into the transmission algorithm to compensate for high crest factor signals. The algorithm truncates the peaks of the signal to keep the peak and RMS value of the signal within acceptable bounds.
This section will first consider the effects of truncation on the signal, showing minimal reduction in received SNR if the signal is truncated under extreme conditions. Then the algorithm used to scale/truncate the transmitted signal is described.
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Study on Transmit Truncation vs. Received SNR In this simulation, 10,000 frames were generated using random data. Each frame contained 85 2-bit symbols. The complex symbols and waveform for each frame were saved. The statistics for the crest factor of the 10,000 frames is shown in the following histogram.
1800 mean = 3.051 std = 349.515m 1600
1400
1200
1000
800
600
400
200
0 2 2.5 3 3.5 4 4.5 5 5.5
Figure 21 Distribution of OFDM Frame Crest Factors To estimate the expected bit error rate, truncation is applied to each waveform followed by the addition of white noise with an amplitude of RMS(waveform)/SNR. The waveforms are truncated at crest factors of 5.0 down to 2.0, in steps of 0.5. Phase Error vs SNR -0.6 trunc at CF=2.0 -0.8
-1 trunc at CF=2.5
-1.2
-1.4 trunc at CF=3.0 - 5.0 log rms phase err log
-1.6 6 8 10 12 14 16 18 20
0
-2 trunc at CF=2.0 -4 trunc at CF=2.5
-6 trunc at CF=3.0 - 5.0 log BERprobability log -8 6 8 10 12 14 16 18 20 SNR in dB
Figure 22 Bit error rate probability due to truncation
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Figure 22 shows that little bit error rate (BER) degradation is seen for truncations of greater than a crest factor of 3.0. Based on this analysis, the powerline modem truncates constructed waveforms at 3.0 times the RMS value of an untruncated waveform. (Note that except for small quantization errors, the RMS value of each transmit frame is constant before truncation.)
Set Power/Truncation Algorithm After the IFFT algorithm is used to generate the transmit waveform for a frame the RMS signal level of the signal is set and, if necessary, the peak values in the signal are clipped. Although the RMS signal level is also controlled by the values input to the IFFT routine, because of scaling performed by the IFFT library function, it is easier to set the RMS signal level after the IFFT routine. At this point the modem can provide fine control of the amplitude of the signal by multiplying by a gain factor TX_GAIN
At this point the modem can also test for and clip the signal at the level set by TX_PEAK_CLIP. This is useful in preventing the analog line driver from going into saturation since it takes the line driver amplifier a while to come out of saturation. That is, it's better to saturate the digital signal than the analog signal.
Viterbi Decoding The shift register in Figure 19 can be thought of as defining a state variable. Let the six binary values in the shift register at any time be thought of as a binary value with the LSB at the left. Each time a new bit of data is shifted into the shift register shown in Figure 19, the binary value gets multiplied by 2 (modulo 64) and then either one or zero gets added, depending on the input data bit. Said another way, for every state defined by the shift register outputs there are only two possible next state values. Or conversely, for every state value there are only two possible previous states. The Viterbi algorithm (VA) makes use of this fact and calculates the most likely sequence of states. For this reason the VA is called a maximum likelihood detector.
The progression of the state value as bits are shifted in can be visualized using a “trellis diagram.” The trellis basically shows time on the horizontal axis and the state on the vertical axis. Lines connect the legal state transitions. There are 64 states because the states can range from b’000000’ to b’111111’. Only certain state transitions (namely, from n to [2n mod 64] and [(2n+1) mod 64)] are allowed because of the shift register structure in Figure 19.
For every state transition, there is a defined X and Y output for an input data bit input W. The transitions between states are marked with a label, XY, that shows the output bits for the particular state transition. Figure 23 shows a part of the trellis. (A complete diagram of the trellis is shown in the Appendix.)
February 4, 2004 36 Power Line Modem with E-meter Platform Ti White Paper
Encoder State 63 11 11 11 00 00 00 62 01 01 01 10 10 10 61 00 00 00 11 11 11 60 10 10 10 01 01 01
00 00 00 11 11 11 33 10 10 10 01 01 01 32
31 10 10 10 01 01 01
30 00 00 00 11 11 11
10 10 10 01 01 01 3 00 00 10 11 11 01
2 01 01 01 10 10 10 1
11 11 11 0 00 00 00
Figure 23 Part of the Trellis. Outputs are Labeled To detect the data, a 64-state Viterbi detector is constructed that calculates path metrics for each state transition by comparing the received 2-bit symbol with the expected two bit symbol along each branch of the state trellis shown in the diagram. The error between the ideal 2-bit symbol and the received phase values is called the “path metric.”
In operation, the Viterbi algorithm calculates a path metric at each node in the trellis. For this code, there are 2 paths entering each node. The algorithm sums the path metric for each path and the path with the higher2 metric wins and the losing path is discarded. The data associated with the winning branch is then copied into the path memory for that node. This continues for each received 2-bit symbol until the end of the packet.
Because several bits of zeros were appended to the original data and encoded, the true path through the trellis will end up at the zero-state node. Therefore the correct data is that data accumulated in the zero state path memory.
2 Mathematically, the lower metric wins, but, as shown below, the actual path metric used is simplified to remove common terms, and a side effect of this is to invert the metric, so that the higher metric wins. February 4, 2004 37 Power Line Modem with E-meter Platform Ti White Paper
Choice of Distance Metric for DQPSK In a phase shift keying system, the natural choice for the error of a signal is the phase angle difference between the transmitted signal and the received signal. Computationally, however, other measures of the error are easier to implement. This section of the paper compares the ideal and implemented error measurement metrics and then shows a simplification in the computation of the error metric that is implemented that speeds the Viterbi Algorithm operation.
In quadrature phase shift keying, one of four signals are transmitted for each symbol: cos(ωt +α ), π π where α = 0, ,π ,− . The signal received is Acos(ωt +α +θ ), where A and θ are the amplitude 2 2 and angle errors, respectively. The transmitted and received signals can be shown on a phasor diagram, rotated by the angle α so that the transmitted phasor is 1+j0. (Acosθ, Asinθ) A θ D (0,0) (1,0)
Figure 24 Phasor Diagram of Transmitted and Received Signals
The angle distance metric, using squared error, and normalizing to give an error of one at 180 degrees, is: θ 2 β( A,θ ) = π 2 The error metric is normalized to give an error of one at 180 degrees because, at any node in the trellis, the Viterbi algorithm adds errors to the path metric for a signal and that signal offset by 180 degrees.
The geometric angle distance metric, normalized in the same way, is the distance D2 in Figure 24 divided by 4: 1 ∆( A,θ ) = ( A2 − 2Acosθ + 1) 4 Figure 25 shows a comparison between the two metrics.
February 4, 2004 38 Power Line Modem with E-meter Platform Ti White Paper
A=1.2 A=1.0 A=amplitude A=0.8
Geometric metrics Metric
Angle metric
Error Angle (degrees)
Figure 25 Comparison of Angle and Geometric Distance Metrics
The angle metric follows the traditional shape for squared error. The geometric metrics can be seen to be arguably better than the angle metrics, since they give more error into the path metrics more quickly as the error angle is increased. The geometric metrics are also monotonic, which is desirable, but level off slightly at extreme error angles. This leveling would only have an effect at extremely poor signal-to-noise ratios, where the error rate performance would already be unacceptable.
The geometric metric appears to be an effective distance metric for this system.
Geometric Distance Metric Computation Simplification In a DQPSK system, the distance metrics are computed in relation to the phase of the previous carrier. Let (cr,ci) denote the phase of the current carrier and (pr,pi) denote the phase of the previous carrier. The geometric distance metrics must be computed to the four constellation points offset 90 degrees from each other.
February 4, 2004 39 Power Line Modem with E-meter Platform Ti White Paper
• -pi,pr
+ cr,ci
• pr,pi • -pr,-pi
• pi,-pr
Figure 26 Calculation of Distance Metric
D 2 = ()()c − p 2 + c − p 2 = c 2 + p 2 − 2c p + c 2 + p 2 − 2c p 0 r r i i r r r r i i i i = ()2 + 2 + 2 + 2 − ()+ cr pr ci pi 2 cr pr ci pi D 2 = ()()c − ()− p 2 + ()c − p 2 = c 2 + p 2 + 2c p + c 2 + p 2 − 2c p 1 r i i r r i r i i r i r = ()2 + 2 + 2 + 2 − ()− + cr pr ci pi 2 cr pi ci pr D 2 = ()()c + p 2 + c + p 2 = c 2 + p 2 + 2c p + c 2 + p 2 + 2c p 2 r r i i r r r r i i i i = ()2 + 2 + 2 + 2 − ()− − cr pr ci pi 2 cr pr ci pi D 2 = ()()c − ()p 2 + ()c − − p 2 = c 2 + p 2 − 2c p + c 2 + p 2 + 2c p 3 r i i r r i r i i r i r = ()2 + 2 + 2 + 2 − ()− cr pr ci pi 2 cr pi ci pr
()2 + 2 + 2 + 2 Each of the four distance metrics computed have a common term of cr pr ci pi . Because the Viterbi needs only compare magnitudes of the errors, this common term can be removed. Then:
2 − ()2 + 2 + 2 + 2 = − ()+ D0 cr pr ci pi 2 cr pr ci pi 2 − ()2 + 2 + 2 + 2 = − ()− + D1 cr pr ci pi 2 cr pi ci pr 2 − ()2 + 2 + 2 + 2 = − ()− − D2 cr pr ci pi 2 cr pr ci pi 2 − ()2 + 2 + 2 + 2 = − ()− D3 cr pr ci pi 2 cr pi ci pr To simplify even more, skip the multiplication by -2. Also note that the first metric is the negative of the third metric and the second is the negative of the fourth. So, one needs only compute two quantities, d0 and d1, and use d0, d1, -d0, and –d1 in the Viterbi path metric calculation: = ()+ d0 cr pr ci pi = ()− + d1 cr pi ci pr Note that since the multiplication by -2 was removed, the minimum error corresponds to the maximum accumulated path metric. This is why the Viterbi Algorithm described above looked for the maximum accumulated metric value.
February 4, 2004 40 Power Line Modem with E-meter Platform Ti White Paper
Frequency equalization A power transmission line, whether it is outside on a power pole or within the walls of a building is not a perfect communication channel. It introduces attenuation and phase distortion to the original transmitted signal. The modem needs a mechanism to deal with this distortion. Fortunately the receiving modem knows what data pattern is being sent in the preamble portion of the data packet and can use this knowledge to calculate a correction for each carrier in the data frames. The process of calculating the effect of the power line as a communication channel is called channel estimation. The process of correcting the subsequently received data frames based on this measurement is called frequency equalization.
In the modem, frequency equalization consists of a defining a complex vector that is multiplied with the FFT output values for each data frame. To calculate the frequency equalization vector, the frequency responses (FFT output) of several frames of the preamble are averaged. Then the equalization vector is found by dividing the known, transmitted preamble frequency response by the averaged, received preamble frequency response. Because doing a complex divide is costly in terms of DSP processor MIPS, and because the modem uses DQPSK modulation, some alternatives to the complex divide can be considered.
BER Simulation for Various Frequency Equalization Techniques This section considers simplifications to the calculations used in the frequency equalization algorithm that might be considered. This algorithm is used on each carrier to compensate for the channel frequency response, using the characterizations measured during the channel estimation operation during the preamble.
A look at the complex math shows that the process of frequency equalization involves multiplying by a quotient where the numerator is a phase correcting part and the denominator is a amplitude correcting part.
p + jp p + jp r − jr feq = rk ik = rk ik rk ik k r + jr r + jr r − jr rk ik rk ik rk ik ()()r p + r p + j r p − r p = rk rk ik ik rk ik ik rk = phase correction part 2 + 2 rrk rik received signal power Since the modem uses DQPSK modulation, it is most interested in correcting the phase which is the numerator part of the frequency equalization quotient. The modem need only to correct the amplitude to the extent that there is sufficient dynamic range for the Viterbi to make accurate distance metric decisions. Thought of in this way, the denominator is a normalizing process.
Three types of frequency equalization were studied: 1. Normalizing each frequency equalization value by dividing by the average power in the preamble; 2. Normalizing by finding the closest power of two to the average preamble power, and then shifting each frequency equalization value; 3. Shifting each frequency equalization value by a fixed constant.
February 4, 2004 41 Power Line Modem with E-meter Platform Ti White Paper
The simulation was run for additive white noise amplitudes corresponding to an SNR (after channel response) of 12 dB down to 5 dB in 0.2 dB increments. For each SNR condition, 50 transmit waveforms were generated using random user data and 500 reads were attempted on that waveform.
The power line channel was simulated using a simple FIR filter. The tap weights of the filter were randomly picked as follows:
chanTapWeights = [ 1 0.01rn 0.05rn 0.13rn 0.10rn 0.05rn 0.02rn ]
where rn is a normal random variable. The results of the simulation are shown in Figure 27.
BER for PLC modem, 18-Sep-2003 b=div, g=bin, r=const 0
-2 Constant shift
-4 log BER -6 Division and binary division -8 5 6 7 8 9 10 11 12
Packet error rate 0
-1
-2 log BER -3
-4 5 6 7 8 9 10 11 12 SNR in dB
Figure 27 Error Rate Simulation of Various Equalization Calculation Methods The two active normalization methods clearly help compared to the fixed method. The full divide method is slightly better, but by less than 0.1 dB. Because the full divide was the best and didn’t use an inordinate amount of processing power, it was chosen for the PLC modem implementation.
Here is the range of channel responses that were generated by randomly picking the tap weights in the simulation:
February 4, 2004 42 Power Line Modem with E-meter Platform Ti White Paper
min, mean & max of channel taps 4
2
0 B
-2 resp in d -4
-6
-8 103 104 105 freq in Hz Figure 28 Channel Responses Used in Frequency Equalization Simulations
AGC operation The transmitted packet signal is attenuated and distorted by the transfer function of the power line. The first step in reconstructing the data is to amplify the signal so that its amplitude is within the dynamic range of the ADC in the modem codec. This function is provided by the automatic gain control (AGC) algorithm in the receiver.
The modem uses the Texas Instruments AFE1230 codec which includes a variable gain amplifier. It has a gain range from 0 to 21 dB in 3 dB steps. This gain is set through a register in the codec. To calculate the correct register the DSP monitors each received sample and calculates the correct gain setting, sending this value back to the codec along with transmit data for the codec DAC.
high threshold
AGC threshold
0
-AGC threshold
-high threshold
Figure 29 AGC Thresholds
February 4, 2004 43 Power Line Modem with E-meter Platform Ti White Paper
The AGC algorithm is an interrupt service routine (ISR) that periodically reads a block of received samples and updates the gain setting to be used to build the control portion of the transmit data sent to the codec DAC. During this routine the absolute value of each received sample is compared to two AGC thresholds: a normal threshold and a high threshold. If the absolute value of the sample is below both thresholds, the AGC control variable is incremented a small amount. If the absolute value of the sample is above the AGC threshold, the AGC control variable is decremented by an amount that is 7 times larger than the increment amount. If the absolute value of the sample is larger than the high threshold, the AGC control variable is decremented by an amount that is 23 times higher than the increment amount. In operation the algorithm holds the amplitude of the signal at a level so that the sum of the samples (area) below the normal threshold is 7 times larger than the sum of the samples (area) above the threshold. The high threshold allows the algorithm to quickly decrease the gain when a strong packet signal arrives.
A copy of the control variable is truncated to 3 bits and compared with the current VGA control register value. If the register value is to be updated, a hysteresis amount is added to the AGC control variable when increasing the register value and subtracted from the variable when decrementing the register. Then this 3 bit value is inserted into the transmit signal buffer and the processor DMA engine and McBSP port transfer the updated value to the AFE1230 codec.
Preamble waveform and detection
OFDM Frame Alignment In order for the FFT algorithm to detect the correct phase for each carrier, the modem needs to find the beginning of each transmitted frame. At the point where the modem has detected the presence of a data packet signal this is not yet known. To align the FFT routine in the receiver to the IFFT generated frames that were transmitted the modem goes through a process called frame alignment.
To do frame alignment the modem takes advantage of the fact that the preamble frames are a repeating known pattern. Because of this the modem can begin an FFT anywhere within the preamble portion of the packet waveform and average consecutive frames until the sync frame is detected. Averaging consists of finding the sum of the sine and cosine coefficients for each subcarrier. Since the preamble is a known repeating pattern, the modem can find the channel impulse response by dividing the averaged complex carrier response from the known preamble frequency content. Additionally, the preamble carriers are a constant amplitude, which allows the impulse response to be calculated by multiplying by the conjugate of the preamble response as follows: received resp r0 r1 rM tf ()k = = L preamble resp p p p 0 1 M r p* r p* r p* = 0 0 1 1 M M = 1 []* * * * * L * r0 p0 r1 p0 LrM pM p0 p0 p1 p1 pM pM C Since 1/C is known a-priori, no divide is necessary. Taking the IFFT of the channel transfer function gives the impulse response of the channel. The sample with the maximum value in the time domain impulse response corresponds to the beginning of the frame. This sample value is used to calculate
February 4, 2004 44 Power Line Modem with E-meter Platform Ti White Paper
the true beginning of the frames. Said another way, it is an offset from the first sample of the averaged FFTs to the beginning of the next frame. This offset is used in following processing functions. It cal also be used to calculate a phase correction for the averaged preamble frequency response values. Impulse Response
0 100 200 300 400 500 600 700 time in usec Figure 30 Impulse Response to Detect Start of Frame
Locating the Start of the First Data Frame Once the true start of the received preamble frames is found, and by keeping track of the number of frames that were averaged before we saw the sync frame, the modem can calculate the position of the signal sample in the receive buffer that represents the start of the first data frame. The modem code does this calculation, advances the working pointer for the FFT algorithm to that memory location and then waits for a frames worth of sample to fill the buffer. It knows then this has occurred by monitoring the DMA pointer.
February 4, 2004 45 Power Line Modem with E-meter Platform Ti White Paper
System Block Diagram and Parts Selection This section describes the overall hardware architecture of the design and details why key devices were chosen for the design.
Figure 31 shows the overall hardware block diagram.
OFDM Power Line Modem plus E-Meter
UCC 7V TPS TPS TPS TUSB USB
2809 79301 24V 77501 79433 3410
Off-Line 5V 3.3V 1.6V
TL16 MAX
C550 3221 RS-232
XFRM DSP
Codec
SN65
AFE1230 C5409A RS-485
TX HVD
THS6182 OFDM Modem 3082
E-Meter
0123.456 kW h
(LCD display)
SN65 V Sense
MSP430- HVD
FE427
I Sense 12 RS-485
µC N Hot Figure 31 Overall Block Diagram of Modem and Meter
The “e-meter” portion of the design measures power usage of devices attached to power connector on the modem box. When requested by another unit to transmit this information, the data is transferred across the RS-485 connection to the DSP in the modem portion of the design. The DSP formats the message to be transmitted and drives it onto the power line through the line driver and codec. The codec is involved in both transmit and receive operations. During transmit, it receives digital data from the DSP, filters it, converts it to an analog signal, and outputs it to the line driver. During receive, the codec receives the data from the line, amplifies it, filters it, digitizes it, and passes the data to the DSP for processing.
The key devices used in the design are the metering processor (MSP430FE427), the DSP (TMS320VC5409A), the codec (AFE1230), and the line driver (THS6182). The remainder of this section outlines the key features of each of these parts as it applies to this design.
February 4, 2004 46 Power Line Modem with E-meter Platform Ti White Paper
Metering Processor Selection The requirements on the processor used in the metering portion of the design is that it be able to efficiently measure voltage and current on the line and then efficiently compute power usage, power factor, and other values. Another requirement is that the meter be able to retain its reading through extended power outages and also when removed from service for an extended period of time.
The MSP430FE427 device, designed specifically for power metering systems, meets the requirements admirably. Its low power usage and integrated flash memory allows a meter to remain unpowered for extended periods of time. The ‘FE427 has built-in ADC’s that allow measurement of current and voltage on the power line. It also has a special purpose built-in computation engine that automates the calculation of power information based on current and voltage readings. Significantly, it has a built- in LCD controller that makes the addition of a display to the meter straightforward to design. Finally, the integrated UART allows communication between several meters and a communication device, such as a power line modem, if desired.
DSP Selection The TMS320C54x family was chosen for the design both its low power and ability to “gluelessly” connect to the codec through its McBSP interface and associated DMA engine. In addition, an assembler FFT routine was available, which was attractive since the OFDM algorithm uses FFTs extensively in data detection. Further, the ‘C54x processor offers specialized hardware that would allow the code to be made more efficient than what was implemented here; see Reference 1 for details. Finally, the DSP processor offers flexibility to tailor the processing to that needed by the application.
The ‘C5409A version of the processor was chosen because it has sufficient memory to hold the modem receive buffer (codec sample values held in data memory) and the firmware to implement both the modem and the PC communications logic needed to demonstrate the modem's performance (program memory). 24V
1.5k coupling power 3.3 transformer 1.5 : 1.0 line 3.3V 5V 0.1uF 1.5k THS6182 120p 2.0k 200 1.5u 1.0u AFE1230 12V 0.47u 4 wire serial CODEC 2.0k 1.5k interface 4 120p DAC output 0.1uF (tx/rxBaud) 3.3 (txData) 1.5k (RxData) (MClk) ADC input
10k 12.1k 2700p 15p 10k 12.1k 2700p
Figure 32 Analog Front End Circuit
February 4, 2004 47 Power Line Modem with E-meter Platform Ti White Paper
Codec Selection The codec performs several important functions in the transmission and reception of the data on the power line. During transmission, the codec is responsible for taking the digital waveform information from the DSP and converting it to the analog signal suitable for placing on the power line. The AFE1230 uses a 16-bit delta-sigma converter on the data from the DSP, followed by a digital transmit filter. The digital filter consists of two sections: a digital interpolation filter that up-samples the signal followed by a programmable analog low-pass filter. The low-pass filters remove quantization noise from the delta-sigma conversion. Because the digital section of the AFE1230 uses 3V while the analog section uses 5V, the device can be interfaced directly to the 3V DSP and the high-voltage line driver. Therefore, the AFE1230 meets the transmit requirements of the design.
During reception, the signal is taken from the power line and amplified through a programmable gain amplifier. The gain of the amplifier is continuously updated through the digital interface to the DSP. The analog signal is then put through a 16-bit delta-sigma converter, followed by a digital low-pass filter that removes quantization noise and down-samples the signal. The combination of PGA, direct interface to the DSP, and 16-bit ADC make the AFE1230’s receive side well suited for the power line modem application.
Line Driver Selection For a power line communication system, the line driver must be able to drive very low impedance loads with little distortion. Because of the high crest factor of OFDM signals, the driver also has to support a fairly high output voltage. Taken together, this means that the line driver must be a high power output capable device and it must be able to dissipate the heat generated.
The THS6182 line driver analog front end uses +/-12V supplies in this design. The driver itself supports higher voltage supplies, up to 30V, and can sink or source up to 1.0A, providing sufficient headroom to drive the low impedance line with the high crest factor OFDM signal. The part is available in both SOIC and PowerPADTM packages. Meters, which transmit only occasionally, could easily use the SOIC package, while concentrators that transmit more often may require the use of the PowerPADTM package.
The THS6182 also features multiple bias modes that allow the bias to be tuned to the impedance of the power line. The line driver also couples low noise onto the power line, disturbing the adjacent receiving codec less than a higher noise device would.
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Measured Data
Power Line Impedance Measurement Because of the high voltages present on a power line, some sort of network is required to measure the impedance of the line at the modem carrier frequencies. Figure 33 shows such a network.
Vm R C s N:1 2
i2 i1 vs L1 L2 ZL
Figure 33 Impedance Measurement Circuit
Calculation of Impedance ZL Express the transformer parameters in terms of the primary inductance and turns ratio: L L = 1 2 N 2 L M = K L L = 1 for K = 1 1 2 N = () Z L f s Then the mesh equations are: = + − vs i1 Rs i1 sL1 i2 sM = − + + + 1 0 i1 sM i2 sL2 i2 Z L i2 sC2 Solving the mesh equations for the currents i1 and i2, and then the measured voltage vm: = − vm vs i1Rs
Z ′ v s v = L s ⋅ where Z′ = Z N 2 (1) m R + Z′ R Z ′ L L s L s + s L ()+ ′ Rs Z L L1 If the vm equation is solved for the unknown line impedance ZL: v R s Z ()s = m s (2) L v − v N 2 v R s m s − m s − vs vm L1 So, by knowing vs and measuring vm with a spectrum analyzer the impedance seen on the power line can be calculated as a function of frequency. Figure 34 shows this measurement for a power outlet in our lab. Note that it varies substantially with frequency and goes as low as 2 ohms. In fact we have found that a laboratory setting is actually a very tough environment because the power supplies in lab
February 4, 2004 49 Power Line Modem with E-meter Platform Ti White Paper equipment typically have very good EMI filters on their inputs. These filters can present very low impedances to the modem. We also measured the line impedance in a couple of residential settings and found a far less severe environment.
Measured Power Line impedance 102
101 ohms
100 103 104 105 106 Frequency
Figure 34 Measured Impedance
February 4, 2004 50 Power Line Modem with E-meter Platform Ti White Paper
Conformance to CENELEC Mask The modem is designed to meet the requirements of the CENELEC EN50065 standard, which limits the amount of voltage that can be driven onto the power line. The modem uses the Utility A-Band, which ranges from 9 kHz to 95 kHz. The standard limits both the in-band signal (“transmit mask”) as well as the amount of signal outside the A-Band (“disturbance mask”). Figure 35 shows the measured output of the modem compared to the CENELEC output limit mask. This measurement was taken not using the standard load defined in the CENELEC specification, so it does not show an exact measurement to that specification. The plot shows that the modem meets the requirements of EN50065’s transmit mask, and meets the requirements of EN50065’s disturbance mask except in the 300 kHz region, where harmonics from the switching power supply encroach slightly above the mask limit by 2 dB. Some additional filtering on the switching power supply input would be needed to ensure complete compliance to the disturbance mask limits, assuming that the standard load defined by the specification would not change the measurements significantly.
Spectrum Analyzer Data Capture 140 CENELEC transmit mask 130
120
110 Modem output 100
90
80
Power Spectrum (dBuV) 70 CENELEC disturbance mask 60
50
40 10 100 500 Frequency (kHz)
Figure 35 Output spectrum from modem
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Conclusions With the “Power Line Modem with E-meter Platform,” we have demonstrated communication over a power line using Orthogonal Frequency Division Multiplexing (OFDM) techniques. This paper has described the architectural design of the platform, including the power line modem and the e-meter functions. It was shown how the TI TMS320VC5409A DSP, THS6182 line driver, and AFE1230 codec can be combined to provide a cost-effective power line communication modem solution. The addition of the MSP430FE427 e-metering processor provides a complete set of core devices to implement a complete automated meter reading system.
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References 1. H. Hendrix: “Viterbi Decoding Techniques for the TMS320C54x DSP Generation,” Texas Instruments Application Report SPRA071A, January 2002. 2. HomePlug Powerline Alliance: “HomePlug 1.0.1 Specification,” Dec. 2001 3. W.W. Peterson and E. J. Weldon: Error-Correcting Codes, MIT Press, Second Edition,1972. 4. J.G. Proakis: Digital Communications, McGraw Hill, Fourth Edition, 2001 as quoted in M. Fainberg: “A Performance Analysis of the IEEE 802.11b Local Area Network in the Presence of Bluetooth Personal Area Network,” M.S. Thesis, http://eeweb.poly.edu/dgoodman/fainberg.pdf. 5. K.S. Shanmugam: Digital and Analog Communication Systems, Wiley, 1979, pp. 402-427. 6. S.B. Wicker: Error Control Systems for Digital Communication and Storage, Prentice Hall, 1995. 7. R.N. Williams: “A Painless Guide to CRC Error Detection Algorithms,” http://www.piclist.com/techref/method/math/crcguide.html.
February 4, 2004 53 Power Line Modem with E-meter Platform Ti White Paper
Appendix. Complete Viterbi Trellis In the following diagram, each node represents either the present or next state with the transition shown between them. Each line between states is labeled with W/Z, where W is the input bit and Z is the output of the Viterbi encoder (Z=0, 1, 2, or 3).
32 1/0 1 36 1/3 9 40 1/0 17 44 1/3 25 0/3 0/0 0/3 0/0
1/3 1/0 1/3 1/0 0 0/0 0 4 0/3 8 8 0/0 16 12 0/3 24
33 1/2 3 37 1/1 11 41 1/2 19 45 1/1 27 0/1 0/2 0/1 0/2
1/1 1/2 1/1 1/2 1 0/2 2 5 0/1 10 9 0/2 18 13 0/1 26
34 1/3 5 38 1/0 13 42 1/3 21 46 1/0 29 0/0 0/3 0/0 0/3
1/0 1/3 1/0 1/3 2 0/3 4 6 0/0 12 10 0/3 20 14 0/0 28
35 1/1 7 39 1/2 15 43 1/1 23 47 1/2 31 0/2 0/1 0/2 0/1
1/2 1/1 1/2 1/1 3 0/1 6 7 0/2 14 11 0/1 22 15 0/2 30
48 1/1 33 52 1/2 41 56 1/1 49 60 1/2 57 0/2 0/1 0/2 0/1
1/2 1/1 1/2 1/1 16 0/1 32 20 0/2 40 24 0/1 48 28 0/2 56
49 1/3 35 53 1/0 43 57 1/3 51 61 1/0 59 0/0 0/3 0/0 0/3
1/0 1/3 1/0 1/3 17 0/3 34 21 0/0 42 25 0/3 50 29 0/0 58
50 1/2 37 54 1/1 45 58 1/2 53 62 1/1 61 0/1 0/2 0/1 0/2
1/1 1/2 1/1 1/2 18 0/2 36 22 0/1 44 26 0/2 52 30 0/1 60
51 1/0 39 55 1/3 47 59 1/0 55 63 1/3 63 0/3 0/0 0/3 0/0
1/3 1/0 1/3 1/0 19 0/0 38 23 0/3 46 27 0/0 54 31 0/3 62
Figure 36 Complete Trellis Transition Diagram
February 4, 2004 54 IMPORTANT NOTICE
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