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An Efficient Hardware Implementation of the Peak Cancellation Crest Factor Reduction Algorithm

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An Efficient Hardware Implementation of the Peak Cancellation Crest Factor Reduction Algorithm DEGREE PROJECT IN INFORMATION AND COMMUNICATION TECHNOLOGY, SECOND CYCLE, 30 CREDITS STOCKHOLM, SWEDEN 2016 An efficient Hardware implementation of the Peak Cancellation Crest Factor Reduction Algorithm MATTEO BERNINI KTH ROYAL INSTITUTE OF TECHNOLOGY SCHOOL OF INFORMATION AND COMMUNICATION TECHNOLOGY An efficient Hardware implementation of the Peak Cancellation Crest Factor Reduction Algorithm MATTEO BERNINI Master’s Thesis at KTH Information and Communication Technology Supervisor: Shafqat Ullah Examiner: Johnny Öberg TRITA-ICT-EX-2016:187 Abstract An important component of the cost of a radio base station comes from to the Power Am- plifier driving the array of antennas. The cost can be split in Capital and Operational expenditure, due to the high design and realization costs and low energy efficiency of the Power Amplifier respectively. Both these cost components are related to the Crest Factor of the input signal. In order to reduce both costs, it would be possible to lower the average power level of the transmitting signal, whereas in order to obtain a more efficient transmis- sion, a more energized signal would allow the receiver to better distinguish the message from the noise and interferences. These opposed needs motivate the research and development of solutions aiming at reducing the excursion of the signal without the need of sacrificing its average power level. One of the algorithms addressing this problem is the Peak Cancellation Crest Factor Reduction. This work documents the design of a hardware implementation of such method, targeting a possible future ASIC for Ericsson AB. SystemVerilog is the Hardware Description Language used for both the design and the verification of the project, together with a MATLAB model used for both exploring some design choices and to val- idate the design against the output of the simulation. The two main goals of the design have been the efficient hardware exploitation, aiming to a smaller area footprint on the inte- grated circuit, and the adoption of some innovative design solutions in the controlling part of the design, for example the managing of the cancelling pulse coefficients and the use of a time-division multiplexing strategy to further save area on the chip. For the contexts where both the solutions could compete, the proposed one shows better results in terms of area and delay compared to the current methods in use at Ericsson and also provides innovative suggestions and ideas for further improvements. Keywords: CFR, PC-CFR, PAPR Reduction, OFDM Sammanfattning En effektiv hårdvaruimplementation av Peak Cancellation-algoritmen för reduktion av toppfaktor En komponent som det är viktigt att ta hänsyn till när det kommer till en radiobasstations kostnad är förstärkaren som används för att driva antennerna. Kostnaden för förstärkaren kan delas upp i en initial kostnad relaterad till utveckling och tillverkning av kretsen, samt en löpande kostnad som är relaterad till kretsens energieffektivitet. Båda kostnaderna är kopplade till en egenskap hos förstärkarens insignal, vilken är kvoten mellan signalens maxi- mala effekt och dess medeleffekt, såkallad toppfaktor. För att reducera dessa kostnader så är det möjligt att minska signalens medeleffekt, men en hög medeleffekt förbättrar radioöver- föringen eftersom det är lättare för mottagaren att skilja en signal med hög energi från brus och interferens. Dessa två motsatta krav motiverar forskning och utveckling av lösningar för att minska signalens maximala värde utan att minska dess medeleffekt. En algoritm som kan användas för att minska signalens toppfaktor är Peak Cancellation. Den här rapporten presenterar design och hårdvaruimplementering av Peak Cancellation med avsikt att kunna användas av Ericsson AB i framtida integrerade kretsar. Det hårdvarubeskrivande språket SystemVerilog användes för både design och testning i projektet. MATLAB användes för att utforska designalternativ samt för att modellera algoritmen och jämföra utdata med hårdvaruimplementationen i simuleringar. De två huvudmålen med designen var att utnytt- ja hårdvaran effektivt för att nå en så liten kretsyta som möjligt och att använda en rad innovativa lösningar för kontrolldelen av designen. Exempel på innovativa designlösningar som användes är hur koefficienter för pulserna, som används för reducera toppar i signalen, hanteras och användning av tidsmultiplex för att ytterligare minska kretsytan. I använd- ningsscenarion där båda lösningarna kan konkurrera, visar den föreslagna lösningen bättre resultat när det kommer till kretsyta och latens än nuvarande lösningar som används av Ericsson. Ges också förslag på ytterligare framtida förbättringar av implementationen. Keywords: CFR, PC-CFR, PAPR Reduction, OFDM List of Acronyms and Abbreviations ACLR Adjacent Channel Leakage Ratio AM Amplitude Modulation ASIC Application Specific Integrated Circuit ASM Algorithmic State Machine BPSK Binary Phase Shift Keying CAF Clipping and Filtering Technique CapEx Capital Expenditure CCDF Complementary Cumulative Distribution Function CF Crest Factor CORDIC Coordinate Rotation Digital Computer CS Clip Stage EVM Error Vector Magnitude FDM Frequency Division Multiplexing FIR Finite Impulse Response FM Frequency Modulation FPGA Field Programmable Gate Array GSM Global System for Mobile communication (H)PA (High) Power Amplifier (I)DCT (Inverse) Discrete Cosine Transform IFFT Inverse Fast Fourier Transform I/Q In-phase / Quadrature signal LTE Long Term Evolution MSR Multi Standard Radio NS Noise Shaping OFDM Orthogonal Frequency Division Multiplexing OOB Out Of Band OpEx Operating Expenditure PA(P)R Peak to Average (Power) Ratio PC, PC-CFR Peak Cancellation Crest Factor Reduction PCU Peak Cancelling Unit PDF Probability Density Function PF Peak Filtering PM Phase Modulation PM Peak Manager PTS Partial Transmit Sequence PW Peak Windowing QPSK Quadrature Phase-Shift Keying RMS Root Mean Square RTL Register Transfer Level SLM SeLective Mapping SV SystemVerilog TC Turbo Clipping TDM Time Division Multiplexing TI Tone Injection TR Tone Reservation WCDMA Wideband Code Division Multiple Access Contents 1 Introduction 1 1.1 Background and statement of the problem . 2 1.2 Purpose of the design project . 4 2 Background and related work 7 2.1 Background . 7 2.1.1 Orthogonal Frequency Division Multiplexing (OFDM) . 7 2.1.2 Definitions: CF, PAPR, EVM and ACLR . 9 2.1.3 Overview of the main CFR methods . 11 2.2 Related Work . 18 3 The proposed implementation of the PC-CFR 21 3.1 General description of the PC-CFR algorithm . 21 3.2 Structural description of the proposed implementation . 26 3.2.1 The Clip Stage . 28 3.2.2 The Peak Manager . 31 4 Future work and suggested improvements 43 4.1 Programmable or dynamic CS–PCU mapping . 43 4.2 Bypassable PC-CFR module . 43 4.3 Clip Stages with different delay memories and cancelling pulses length 45 4.4 Truncation of cancelling pulses . 45 4.5 Variable length Peak Search Window . 46 4.6 Priority-based acceptance of peaks . 47 4.7 Generation of multiple cancelling pulses from the same time slot . 49 5 Results and conclusions 53 5.1 Comparative synthesis results . 53 5.2 Some input and model configuration exploration . 54 5.2.1 Observations . 57 Bibliography 61 Appendices 62 A The MATLAB golden model 63 Chapter 1 Introduction If the cost of a typical transmitting radio base station is analyzed, we discover that the Capital Expenditure (CapEx)1 and the Operating Expenditure (OpEx)2 relative to the radio cards alone cover roughly 50% of the total cost[1]. The radio cards house the Power Amplifier (PA) whose low efficiency is the main culprit for the OpEx part of the overall costs. In fact, only a small quota of the power consumed by the radio cards becomes transmitted power. Similar considerations are valid for the consumer electronics market: every mobile device, relying on wireless communications, suffers from the non-optimal efficiency of the PA causing a substantial negative effect on the battery lifetime. In many low-cost applications, this issue alone might prevent the whole system to be considered convenient or even possible to design. The efficiency of the PA is a function of the characteristics of the input signal, in particular of its Peak to Average Power Ratio (PAPR, or PAR) or Crest Factor (CF), which are the ratio between the powers or the magnitudes associated to the largest and the average values of the signal, respectively. In Figure 1.1, we can see a small segment of data in a typical scenario. The maximum values, that is the peaks (a more accurate definition of peaks will be given in 3.1, for now the intuitive comprehension is sufficient), are responsible for the high PAPR of a given signal. It is not surprising that the industry is striving to reduce this phenomenon, and thus the costs and inefficiencies, by investigating several alternatives. Basically the two most relevant ways to deal with the problem are: 1)introducing some changes in the signals to be transmitted (without of course compromising its informative content) in order to prevent the occurrence of high peaks, at the cost of an increased complexity of the transmitter and/or sacrificing some data rate for the transmission of side information needed on the receiver side for the reconstruction of the information, or 2)digitally processing the signal as it is (either in the time or frequency domain) in order to limit the occurrence and magnitude of the unavoidable peaks, at the cost of some introduced distortion. This thesis work focuses on the design, modeling and verification of an algo- 1Resources invested by a company to buy or upgrade fixed, physical, non-consumable assets. 2Day-to-day costs of operation. 1 CHAPTER 1. INTRODUCTION Figure 1.1: A segment of a typical signal amplitude showing high variability and, as a consequence, a high ratio between the maximum and average values. rithm belonging to the digital processing category, namely the Peak Cancellation Crest Factor Reduction (PC-CFR) and it is targeted to an Application Specific In- tegrated Circuit (ASIC). The thesis project was performed at Ericsson AB in Kista, Stockholm.
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