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SDR SDRAM Controller Reference Design SDR SDRAM Controller Reference Design FPGA-RD-02087-4.9 November 2019 SDR SDRAM Controller Reference Design Disclaimers Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice. © 2014-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-RD-02087-4.9 SDR SDRAM Controller Reference Design Contents 1. Introduction .................................................................................................................................................................. 4 2. Features ........................................................................................................................................................................ 5 3. Pin Descriptions ............................................................................................................................................................ 5 4. Functional Description .................................................................................................................................................. 6 5. Benefits of Using PLL .................................................................................................................................................... 7 6. SDRAM Initialization ..................................................................................................................................................... 7 7. Read/Write Cycle .......................................................................................................................................................... 9 8. Refresh Cycle .............................................................................................................................................................. 11 9. Data Path .................................................................................................................................................................... 11 10. Timing Diagrams ......................................................................................................................................................... 12 11. Implementation .......................................................................................................................................................... 14 Technical Support Assistance ............................................................................................................................................. 16 Revision History .................................................................................................................................................................. 17 Figures Figure 1.1. SDR SDRAM Controller System ........................................................................................................................... 4 Figure 4.1. Block Diagram ..................................................................................................................................................... 6 Figure 6.1. INIT_FSM State Diagram ..................................................................................................................................... 8 Figure 7.1. CMD_FSM State Diagram ................................................................................................................................... 9 Figure 9.1. Data Path Module ............................................................................................................................................. 12 Figure 10.1. Read Cycle Timing Diagram ............................................................................................................................ 13 Figure 10.2. Write Cycle Timing Diagram ........................................................................................................................... 13 Figure 11.1. Module Relationships ..................................................................................................................................... 15 Tables Table 3.1. Pin Descriptions ................................................................................................................................................... 5 Table 11.1. Performance and Resource Utilization ............................................................................................................ 14 © 2014-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-RD-02087-4.9 3 SDR SDRAM Controller Reference Design 1. Introduction Synchronous DRAM (SDRAM) has become a mainstream memory of choice in embedded system memory design due to its speed, burst access and pipeline features. For high-end applications using processors such as Motorola MPC 8260 or Intel StrongArm, the interface to the SDRAM is supported by the processor’s built-in peripheral module. However, for other applications, the system designer must design a controller to provide proper commands for SDRAM initialization, read/write accesses and memory refresh. In some cases, SDRAM is chosen because the previous generations of DRAM (FP and EDO) are either end-of-life or not recommended for new designs by the memory vendors. From the board design point of view, design using earlier generations of DRAM is much easier and more straightforward than using SDRAM unless the system bus master provides the SDRAM interface module as mentioned above. This SDRAM controller reference design, located between the SDRAM and the bus master, reduces the user’s effort to deal with the SDRAM command interface by providing a simple generic system interface to the bus master. Figure 1.1. shows the relationship of the controller between the bus master and SDRAM. The bus master can be either a microprocessor or a user’s proprietary module interface. In today's SDRAM market, there are two major types of SDRAM distinguished by their data transfer rates. The most common single data rate (SDR) SDRAM transfers data on the rising edge of the clock. The other is the double data rate (DDR) SDRAM which transfers data on both the rising and falling edge to double the data transfer throughput. Other than the data transfer phase, the different power-on initialization and mode register definitions, these two SDRAMs share the same command set and basic design concepts. This reference design is targeted for SDR SDRAM, however, due to the similarity of SDR and DDR SDRAM, this design can also be modified for a DDR SDRAM controller. For illustration purposes, the Micron SDR SDRAM MT48LC32M4A2 (8Meg x 4 x 4 banks) is chosen for this design. Also, this design has been verified by using Micron’s simulation model. It is highly recommended to download the simulation model from the SDRAM vendors for timing simulation when any modifications are made to this design. Figure 1.1. SDR SDRAM Controller System © 2014-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 4 FPGA-RD-02087-4.9 SDR SDRAM Controller Reference Design 2. Features Simplifies SDRAM command interface to standard system read/write interface. Internal state machine built for SDRAM power-on initialization. Read/write cycle access time optimized automatically according to the SDRAM timing specification and the mode it is configured to. Dedicated auto-refresh request input and acknowledge output for SDRAM refresh. Easily configurable to support different CAS latency and burst length. By taking advantage of the sysCLOCK™ PLL feature, a slower system clock can be used. The system interface clock does not need to be the same as the SDRAM clock. With the support of the sysIO™ feature available in all Lattice devices, the system interface can be in any I/O standards supported by the device. 3. Pin Descriptions Table 3.1. Pin Descriptions Pin Name Type Pin Description sys_R_Wn
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