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RM0312 Reference Manual Stm8tl5xxx Microcontroller Family

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RM0312 Reference Manual Stm8tl5xxx Microcontroller Family RM0312 Reference manual STM8TL5xxx microcontroller family Introduction This reference manual targets application developers. It provides complete information on how to use the STM8TL5xxx microcontroller family memory and peripherals. For ordering information, pin description, mechanical and electrical device characteristics, please refer to the datasheet. For information on the STM8 SWIM communication protocol and debug module, please refer to the user manual (UM0470). For more information related to the Flash memory, please refer to the STM8TL5xxx Flash memory programming manual (PM0212) . For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044). October 2013 DocID022352 Rev 3 1/275 www.st.com Contents RM0312 Contents 1 Memory and register map . 17 1.1 Register description abbreviations . 17 2 Central processing unit (CPU) . 18 2.1 Introduction . 18 2.2 CPU registers . 18 2.2.1 Description of CPU registers . 18 2.2.2 STM8 CPU register map . 22 2.3 Global configuration register (CFG_GCR) . 22 2.3.1 Activation level . 22 2.3.2 SWIM disable . 22 2.3.3 Description of global configuration register (CFG_GCR) . 23 2.3.4 Global configuration register map and reset values . 23 3 Single wire interface module (SWIM) and debug module (DM) . 24 3.1 Introduction . 24 3.2 Main features . 24 3.3 SWIM modes . 24 4 Flash program memory and data EEPROM . 25 4.1 Introduction . 25 4.2 Glossary . 25 4.3 Main Flash memory features . 25 4.4 Memory organization . 26 4.4.1 Proprietary code area (PCODE) . 27 4.4.2 User boot area (UBC) . 27 4.4.3 Data EEPROM (DATA) . 28 4.4.4 Main program area . 28 4.4.5 Option bytes . 28 4.5 Memory protection . 29 4.5.1 Readout protection . 29 4.5.2 Memory access security system (MASS) . 29 4.6 Memory programming . 31 2/275 DocID022352 Rev 3 RM0312 Contents 4.6.1 Byte programming . 31 4.6.2 Word programming . 31 4.6.3 Block programming . 32 4.7 ICP and IAP . 33 4.8 Flash registers . 36 4.8.1 Flash control register 1 (FLASH_CR1) . 36 4.8.2 Flash control register 2 (FLASH_CR2) . 37 4.8.3 Flash program memory unprotecting key register (FLASH_PUKR) . 37 4.8.4 Data EEPROM unprotection key register (FLASH_DUKR) . 38 4.8.5 Flash status register (FLASH_IAPSR) . 38 4.8.6 Flash register map and reset values . 39 5 Interrupt controller (ITC) . 40 5.1 ITC introduction . 40 5.2 Interrupt masking and processing flow . 40 5.2.1 Servicing pending interrupts . 41 5.2.2 Interrupt sources . 42 5.3 Interrupts and low power modes . 43 5.4 Activation level/low power mode control . 44 5.5 Concurrent and nested interrupt management . 44 5.5.1 Concurrent interrupt management mode . 45 5.5.2 Nested interrupt management mode . 45 5.6 External interrupts . 47 5.7 Interrupt instructions . 47 5.8 Interrupt mapping . 48 5.9 ITC and EXTI registers . 49 5.9.1 CPU condition code register interrupt bits (CCR) . 49 5.9.2 Software priority register x (ITC_SPRx) . 50 5.9.3 External interrupt control register 1 (EXTI_CR1) . 51 5.9.4 External interrupt control register 2 (EXTI_CR2) . 52 5.9.5 External interrupt control register 3 (EXTI_CR3) . 53 5.9.6 External interrupt status register 1 (EXTI_SR1) . 53 5.9.7 External interrupt status register 2 (EXTI_SR2) . 54 5.9.8 External interrupt port select register (EXTI_CONF) . 54 5.9.9 ITC and EXTI register map and reset values . 55 DocID022352 Rev 3 3/275 12 Contents RM0312 6 Power supply . 56 7 Reset (RST) and voltage detection . 57 7.1 “Reset state” and “under reset” definitions . 57 7.2 External reset (NRST pin) . 57 7.2.1 Asynchronous external reset description . 57 7.2.2 Configuring NRST/PA5 pin as general purpose output . 58 7.3 Internal reset . 58 7.3.1 Power-on reset (POR) . 58 7.3.2 Independent watchdog reset . 58 7.3.3 SWIM reset . 58 7.3.4 Illegal opcode reset . 58 7.4 RST registers . 59 7.4.1 Reset pin configuration register (RST_CR) . 59 7.4.2 Reset status register (RST_SR) . 59 7.5 RST register map and reset values . 60 8 Clock control (CLK) . 61 8.1 Master clock (HSI clock) . 62 8.1.1 Peripheral clock gating (PCG) . 62 8.2 LSI clock . 63 8.3 Configurable clock-output capability (CCO) . 63 8.4 CLK registers . 63 8.4.1 Clock divider register (CLK_CKDIVR) . 63 8.4.2 Peripheral clock gating register 1 (CLK_PCKENR1) . 64 8.4.3 Peripheral clock gating register 2 (CLK_PCKENR2) . 64 8.4.4 Configurable clock output register (CLK_CCOR) . 65 8.4.5 CLK register map and reset values . 66 9 Power management . 67 9.1 General considerations . ..
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